1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * Design Files: https://www.ti.com/lit/zip/SPRR466 6 * TRM: https://www.ti.com/lit/zip/spruj52 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/net/ti-dp83867.h> 12#include <dt-bindings/gpio/gpio.h> 13#include "k3-j784s4.dtsi" 14 15/ { 16 compatible = "ti,am69-sk", "ti,j784s4"; 17 model = "Texas Instruments AM69 SK"; 18 19 chosen { 20 stdout-path = "serial2:115200n8"; 21 }; 22 23 aliases { 24 serial0 = &wkup_uart0; 25 serial1 = &mcu_uart0; 26 serial2 = &main_uart8; 27 mmc0 = &main_sdhci0; 28 mmc1 = &main_sdhci1; 29 i2c0 = &wkup_i2c0; 30 i2c3 = &main_i2c0; 31 ethernet0 = &mcu_cpsw_port1; 32 }; 33 34 memory@80000000 { 35 device_type = "memory"; 36 bootph-all; 37 /* 32G RAM */ 38 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 39 <0x00000008 0x80000000 0x00000007 0x80000000>; 40 }; 41 42 reserved_memory: reserved-memory { 43 #address-cells = <2>; 44 #size-cells = <2>; 45 ranges; 46 47 secure_ddr: optee@9e800000 { 48 reg = <0x00 0x9e800000 0x00 0x01800000>; 49 no-map; 50 }; 51 52 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 53 compatible = "shared-dma-pool"; 54 reg = <0x00 0xa0000000 0x00 0x100000>; 55 no-map; 56 }; 57 58 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 59 compatible = "shared-dma-pool"; 60 reg = <0x00 0xa0100000 0x00 0xf00000>; 61 no-map; 62 }; 63 64 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 65 compatible = "shared-dma-pool"; 66 reg = <0x00 0xa1000000 0x00 0x100000>; 67 no-map; 68 }; 69 70 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 71 compatible = "shared-dma-pool"; 72 reg = <0x00 0xa1100000 0x00 0xf00000>; 73 no-map; 74 }; 75 76 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 77 compatible = "shared-dma-pool"; 78 reg = <0x00 0xa2000000 0x00 0x100000>; 79 no-map; 80 }; 81 82 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 83 compatible = "shared-dma-pool"; 84 reg = <0x00 0xa2100000 0x00 0xf00000>; 85 no-map; 86 }; 87 88 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 89 compatible = "shared-dma-pool"; 90 reg = <0x00 0xa3000000 0x00 0x100000>; 91 no-map; 92 }; 93 94 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 95 compatible = "shared-dma-pool"; 96 reg = <0x00 0xa3100000 0x00 0xf00000>; 97 no-map; 98 }; 99 100 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 101 compatible = "shared-dma-pool"; 102 reg = <0x00 0xa4000000 0x00 0x100000>; 103 no-map; 104 }; 105 106 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 107 compatible = "shared-dma-pool"; 108 reg = <0x00 0xa4100000 0x00 0xf00000>; 109 no-map; 110 }; 111 112 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 113 compatible = "shared-dma-pool"; 114 reg = <0x00 0xa5000000 0x00 0x100000>; 115 no-map; 116 }; 117 118 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 119 compatible = "shared-dma-pool"; 120 reg = <0x00 0xa5100000 0x00 0xf00000>; 121 no-map; 122 }; 123 124 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { 125 compatible = "shared-dma-pool"; 126 reg = <0x00 0xa6000000 0x00 0x100000>; 127 no-map; 128 }; 129 130 main_r5fss2_core0_memory_region: r5f-memory@a6100000 { 131 compatible = "shared-dma-pool"; 132 reg = <0x00 0xa6100000 0x00 0xf00000>; 133 no-map; 134 }; 135 136 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { 137 compatible = "shared-dma-pool"; 138 reg = <0x00 0xa7000000 0x00 0x100000>; 139 no-map; 140 }; 141 142 main_r5fss2_core1_memory_region: r5f-memory@a7100000 { 143 compatible = "shared-dma-pool"; 144 reg = <0x00 0xa7100000 0x00 0xf00000>; 145 no-map; 146 }; 147 148 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 149 compatible = "shared-dma-pool"; 150 reg = <0x00 0xa8000000 0x00 0x100000>; 151 no-map; 152 }; 153 154 c71_0_memory_region: c71-memory@a8100000 { 155 compatible = "shared-dma-pool"; 156 reg = <0x00 0xa8100000 0x00 0xf00000>; 157 no-map; 158 }; 159 160 c71_1_dma_memory_region: c71-dma-memory@a9000000 { 161 compatible = "shared-dma-pool"; 162 reg = <0x00 0xa9000000 0x00 0x100000>; 163 no-map; 164 }; 165 166 c71_1_memory_region: c71-memory@a9100000 { 167 compatible = "shared-dma-pool"; 168 reg = <0x00 0xa9100000 0x00 0xf00000>; 169 no-map; 170 }; 171 172 c71_2_dma_memory_region: c71-dma-memory@aa000000 { 173 compatible = "shared-dma-pool"; 174 reg = <0x00 0xaa000000 0x00 0x100000>; 175 no-map; 176 }; 177 178 c71_2_memory_region: c71-memory@aa100000 { 179 compatible = "shared-dma-pool"; 180 reg = <0x00 0xaa100000 0x00 0xf00000>; 181 no-map; 182 }; 183 184 c71_3_dma_memory_region: c71-dma-memory@ab000000 { 185 compatible = "shared-dma-pool"; 186 reg = <0x00 0xab000000 0x00 0x100000>; 187 no-map; 188 }; 189 190 c71_3_memory_region: c71-memory@ab100000 { 191 compatible = "shared-dma-pool"; 192 reg = <0x00 0xab100000 0x00 0xf00000>; 193 no-map; 194 }; 195 }; 196 197 vusb_main: regulator-vusb-main5v0 { 198 /* USB MAIN INPUT 5V DC */ 199 compatible = "regulator-fixed"; 200 regulator-name = "vusb-main5v0"; 201 regulator-min-microvolt = <5000000>; 202 regulator-max-microvolt = <5000000>; 203 regulator-always-on; 204 regulator-boot-on; 205 }; 206 207 vsys_5v0: regulator-vsys5v0 { 208 /* Output of LM61460 */ 209 compatible = "regulator-fixed"; 210 regulator-name = "vsys_5v0"; 211 regulator-min-microvolt = <5000000>; 212 regulator-max-microvolt = <5000000>; 213 vin-supply = <&vusb_main>; 214 regulator-always-on; 215 regulator-boot-on; 216 }; 217 218 vsys_3v3: regulator-vsys3v3 { 219 /* Output of LM5143 */ 220 compatible = "regulator-fixed"; 221 regulator-name = "vsys_3v3"; 222 regulator-min-microvolt = <3300000>; 223 regulator-max-microvolt = <3300000>; 224 vin-supply = <&vusb_main>; 225 regulator-always-on; 226 regulator-boot-on; 227 }; 228 229 vdd_mmc1: regulator-sd { 230 /* Output of TPS22918 */ 231 compatible = "regulator-fixed"; 232 regulator-name = "vdd_mmc1"; 233 regulator-min-microvolt = <3300000>; 234 regulator-max-microvolt = <3300000>; 235 regulator-boot-on; 236 enable-active-high; 237 vin-supply = <&vsys_3v3>; 238 gpio = <&exp1 2 GPIO_ACTIVE_HIGH>; 239 }; 240 241 vdd_sd_dv: regulator-tlv71033 { 242 /* Output of TLV71033 */ 243 compatible = "regulator-gpio"; 244 regulator-name = "tlv71033"; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&vdd_sd_dv_pins_default>; 247 regulator-min-microvolt = <1800000>; 248 regulator-max-microvolt = <3300000>; 249 regulator-boot-on; 250 vin-supply = <&vsys_5v0>; 251 gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; 252 states = <1800000 0x0>, 253 <3300000 0x1>; 254 }; 255 256 dp0_pwr_3v3: regulator-dp0-pwr { 257 compatible = "regulator-fixed"; 258 regulator-name = "dp0-pwr"; 259 regulator-min-microvolt = <3300000>; 260 regulator-max-microvolt = <3300000>; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&dp_pwr_en_pins_default>; 263 gpio = <&main_gpio0 4 0>; /* DP0_3V3 _EN */ 264 enable-active-high; 265 }; 266 267 dp0: connector-dp0 { 268 compatible = "dp-connector"; 269 label = "DP0"; 270 type = "full-size"; 271 dp-pwr-supply = <&dp0_pwr_3v3>; 272 273 port { 274 dp0_connector_in: endpoint { 275 remote-endpoint = <&dp0_out>; 276 }; 277 }; 278 }; 279 280 connector-hdmi { 281 compatible = "hdmi-connector"; 282 label = "hdmi"; 283 type = "a"; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&hdmi_hpd_pins_default>; 286 ddc-i2c-bus = <&mcu_i2c1>; 287 hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; /* HDMI_HPD */ 288 289 port { 290 hdmi_connector_in: endpoint { 291 remote-endpoint = <&tfp410_out>; 292 }; 293 }; 294 }; 295 296 bridge-dvi { 297 compatible = "ti,tfp410"; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&hdmi_pdn_pins_default>; 300 powerdown-gpios = <&wkup_gpio0 14 GPIO_ACTIVE_LOW>; /* HDMI_PDn */ 301 ti,deskew = <0>; 302 303 ports { 304 #address-cells = <1>; 305 #size-cells = <0>; 306 307 port@0 { 308 reg = <0>; 309 310 tfp410_in: endpoint { 311 remote-endpoint = <&dpi1_out0>; 312 pclk-sample = <1>; 313 }; 314 }; 315 316 port@1 { 317 reg = <1>; 318 319 tfp410_out: endpoint { 320 remote-endpoint = <&hdmi_connector_in>; 321 }; 322 }; 323 }; 324 }; 325 326 csi_mux: mux-controller { 327 compatible = "gpio-mux"; 328 #mux-state-cells = <1>; 329 mux-gpios = <&exp2 1 GPIO_ACTIVE_HIGH>; 330 idle-state = <0>; 331 }; 332 333 transceiver1: can-phy0 { 334 compatible = "ti,tcan1042"; 335 #phy-cells = <0>; 336 max-bitrate = <5000000>; 337 }; 338 339 transceiver2: can-phy1 { 340 compatible = "ti,tcan1042"; 341 #phy-cells = <0>; 342 max-bitrate = <5000000>; 343 }; 344 345 transceiver3: can-phy2 { 346 compatible = "ti,tcan1042"; 347 #phy-cells = <0>; 348 max-bitrate = <5000000>; 349 }; 350 351 transceiver4: can-phy3 { 352 compatible = "ti,tcan1042"; 353 #phy-cells = <0>; 354 max-bitrate = <5000000>; 355 }; 356 357}; 358 359&main_pmx0 { 360 bootph-all; 361 main_uart8_pins_default: main-uart8-default-pins { 362 bootph-all; 363 pinctrl-single,pins = < 364 J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ 365 J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ 366 >; 367 }; 368 369 main_i2c0_pins_default: main-i2c0-default-pins { 370 pinctrl-single,pins = < 371 J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ 372 J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ 373 >; 374 }; 375 376 main_i2c1_pins_default: main-i2c1-default-pins { 377 pinctrl-single,pins = < 378 J784S4_IOPAD(0x0ac, PIN_INPUT_PULLUP, 13) /* (AE34) MCASP0_AXR15.I2C1_SCL */ 379 J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 13) /* (AL33) MCASP1_AXR3.I2C1_SDA */ 380 >; 381 }; 382 383 main_mmc1_pins_default: main-mmc1-default-pins { 384 bootph-all; 385 pinctrl-single,pins = < 386 J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ 387 J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ 388 J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ 389 J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ 390 J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ 391 J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ 392 J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ 393 J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ 394 >; 395 }; 396 397 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 398 pinctrl-single,pins = < 399 J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */ 400 >; 401 }; 402 403 rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { 404 pinctrl-single,pins = < 405 J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ 406 J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */ 407 J784S4_IOPAD(0x0B4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */ 408 J784S4_IOPAD(0x0C0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */ 409 J784S4_IOPAD(0x00C, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */ 410 J784S4_IOPAD(0x0B8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */ 411 J784S4_IOPAD(0x090, PIN_INPUT, 7) /* (AC35) MCASP0_AXR8.GPIO0_36 */ 412 J784S4_IOPAD(0x0A8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */ 413 J784S4_IOPAD(0x0A4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */ 414 J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */ 415 J784S4_IOPAD(0x0CC, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */ 416 J784S4_IOPAD(0x08C, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */ 417 J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */ 418 J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ 419 >; 420 }; 421 422 dp0_pins_default: dp0-default-pins { 423 pinctrl-single,pins = < 424 J784S4_IOPAD(0x014, PIN_INPUT, 13) /* (AG33) MCAN14_TX.DP0_HPD */ 425 >; 426 }; 427 428 dp_pwr_en_pins_default: dp-pwr-en-default-pins { 429 pinctrl-single,pins = < 430 J784S4_IOPAD(0x010, PIN_INPUT, 7) /* (AH33) MCAN13_RX.GPIO0_4 */ 431 >; 432 }; 433 434 dss_vout0_pins_default: dss-vout0-default-pins { 435 pinctrl-single,pins = < 436 J784S4_IOPAD(0x074, PIN_OUTPUT, 2) /* (AC33) MCAN2_TX.VOUT0_DATA0 */ 437 J784S4_IOPAD(0x070, PIN_OUTPUT, 2) /* (AH38) MCAN1_RX.VOUT0_DATA1 */ 438 J784S4_IOPAD(0x07c, PIN_OUTPUT, 2) /* (AJ38) MCASP0_AXR3.VOUT0_DATA2 */ 439 J784S4_IOPAD(0x068, PIN_OUTPUT, 2) /* (AE38) MCAN0_RX.VOUT0_DATA3 */ 440 J784S4_IOPAD(0x064, PIN_OUTPUT, 2) /* (AF38) MCAN0_TX.VOUT0_DATA4 */ 441 J784S4_IOPAD(0x060, PIN_OUTPUT, 2) /* (AE36) MCASP2_AXR1.VOUT0_DATA5 */ 442 J784S4_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AC36) MCASP2_AXR0.VOUT0_DATA6 */ 443 J784S4_IOPAD(0x058, PIN_OUTPUT, 2) /* (AE37) MCASP2_AFSX.VOUT0_DATA7 */ 444 J784S4_IOPAD(0x054, PIN_OUTPUT, 2) /* (AD37) MCASP2_ACLKX.VOUT0_DATA8 */ 445 J784S4_IOPAD(0x050, PIN_OUTPUT, 2) /* (AC37) MCASP1_AXR2.VOUT0_DATA9 */ 446 J784S4_IOPAD(0x04c, PIN_OUTPUT, 2) /* (AC32) MCASP1_AXR1.VOUT0_DATA10 */ 447 J784S4_IOPAD(0x048, PIN_OUTPUT, 2) /* (AK33) MCASP0_AXR2.VOUT0_DATA11 */ 448 J784S4_IOPAD(0x044, PIN_OUTPUT, 2) /* (AG37) MCASP0_AXR1.VOUT0_DATA12 */ 449 J784S4_IOPAD(0x040, PIN_OUTPUT, 2) /* (AF37) MCASP0_AXR0.VOUT0_DATA13 */ 450 J784S4_IOPAD(0x03c, PIN_OUTPUT, 2) /* (AK38) MCASP0_AFSX.VOUT0_DATA14 */ 451 J784S4_IOPAD(0x038, PIN_OUTPUT, 2) /* (AK35) MCASP0_ACLKX.VOUT0_DATA15 */ 452 J784S4_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AJ32) EXT_REFCLK1.VOUT0_DATA16 */ 453 J784S4_IOPAD(0x030, PIN_OUTPUT, 2) /* (AK37) GPIO0_12.VOUT0_DATA17 */ 454 J784S4_IOPAD(0x02c, PIN_OUTPUT, 2) /* (AL32) GPIO0_11.VOUT0_DATA18 */ 455 J784S4_IOPAD(0x028, PIN_OUTPUT, 2) /* (AE33) MCAN16_RX.VOUT0_DATA19 */ 456 J784S4_IOPAD(0x024, PIN_OUTPUT, 2) /* (AH34) MCAN16_TX.VOUT0_DATA20 */ 457 J784S4_IOPAD(0x020, PIN_OUTPUT, 2) /* (AJ35) MCAN15_RX.VOUT0_DATA21 */ 458 J784S4_IOPAD(0x01c, PIN_OUTPUT, 2) /* (AG34) MCAN15_TX.VOUT0_DATA22 */ 459 J784S4_IOPAD(0x018, PIN_OUTPUT, 2) /* (AK36) MCAN14_RX.VOUT0_DATA23 */ 460 J784S4_IOPAD(0x084, PIN_OUTPUT, 2) /* (AG38) MCASP0_AXR5.VOUT0_DE */ 461 J784S4_IOPAD(0x080, PIN_OUTPUT, 2) /* (AK34) MCASP0_AXR4.VOUT0_HSYNC */ 462 J784S4_IOPAD(0x078, PIN_OUTPUT, 2) /* (AH37) MCAN2_RX.VOUT0_PCLK */ 463 J784S4_IOPAD(0x088, PIN_OUTPUT, 2) /* (AF36) MCASP0_AXR6.VOUT0_VSYNC */ 464 >; 465 }; 466 467 hdmi_hpd_pins_default: hdmi-hpd-default-pins { 468 pinctrl-single,pins = < 469 J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTN.GPIO0_0 */ 470 >; 471 }; 472 473 main_mcan6_pins_default: main-mcan6-default-pins { 474 pinctrl-single,pins = < 475 J784S4_IOPAD(0x098, PIN_INPUT, 0) /* (AH36) MCAN6_RX */ 476 J784S4_IOPAD(0x094, PIN_OUTPUT, 0) /* (AG35) MCAN6_TX */ 477 >; 478 }; 479 480 main_mcan7_pins_default: main-mcan7-default-pins { 481 pinctrl-single,pins = < 482 J784S4_IOPAD(0x0A0, PIN_INPUT, 0) /* (AD34) MCAN7_RX */ 483 J784S4_IOPAD(0x09C, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */ 484 >; 485 }; 486 487 main_usbss0_pins_default: main-usbss0-default-pins { 488 pinctrl-single,pins = < 489 J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ 490 >; 491 }; 492 493}; 494 495&wkup_pmx0 { 496 bootph-all; 497 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 498 pinctrl-single,pins = < 499 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ 500 J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ 501 J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ 502 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ 503 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ 504 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ 505 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ 506 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ 507 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ 508 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ 509 J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ 510 >; 511 }; 512}; 513 514&wkup_pmx2 { 515 bootph-all; 516 pmic_irq_pins_default: pmic-irq-default-pins { 517 pinctrl-single,pins = < 518 /* (AA37) MCU_ADC1_AIN4.WKUP_GPIO0_83 */ 519 J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 7) 520 >; 521 }; 522 523 wkup_uart0_pins_default: wkup-uart0-default-pins { 524 bootph-all; 525 pinctrl-single,pins = < 526 J784S4_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_UART0_CTSn */ 527 J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (L36) WKUP_UART0_RTSn */ 528 J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ 529 J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ 530 >; 531 }; 532 533 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 534 bootph-all; 535 pinctrl-single,pins = < 536 J784S4_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ 537 J784S4_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ 538 >; 539 }; 540 541 mcu_uart0_pins_default: mcu-uart0-default-pins { 542 bootph-all; 543 pinctrl-single,pins = < 544 J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ 545 J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ 546 >; 547 }; 548 549 mcu_i2c0_pins_default: mcu-i2c0-default-pins { 550 pinctrl-single,pins = < 551 J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT_PULLUP, 0) /* (M35) MCU_I2C0_SCL */ 552 J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT_PULLUP, 0) /* (G34) MCU_I2C0_SDA */ 553 >; 554 }; 555 556 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 557 pinctrl-single,pins = < 558 J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ 559 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ 560 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ 561 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ 562 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ 563 J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ 564 J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ 565 J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ 566 J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ 567 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ 568 J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ 569 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ 570 >; 571 }; 572 573 mcu_mdio_pins_default: mcu-mdio-default-pins { 574 pinctrl-single,pins = < 575 J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ 576 J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ 577 >; 578 }; 579 580 mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-default-pins { 581 pinctrl-single,pins = < 582 J784S4_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (N34) WKUP_GPIO0_66 */ 583 J784S4_WKUP_IOPAD(0x05c, PIN_INPUT, 7) /* (J34) WKUP_GPIO0_1 */ 584 J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ 585 J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (H38) WKUP_GPIO0_0 */ 586 J784S4_WKUP_IOPAD(0x0b8, PIN_INPUT, 7) /* (M37) WKUP_GPIO0_56 */ 587 J784S4_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (M36) WKUP_GPIO0_57 */ 588 J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (K37) WKUP_GPIO0_15 */ 589 J784S4_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (J36) WKUP_GPIO0_3 */ 590 J784S4_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (M34) WKUP_GPIO0_67 */ 591 >; 592 }; 593 594 mcu_i2c1_pins_default: mcu-i2c1-default-pins { 595 pinctrl-single,pins = < 596 /* (L35) WKUP_GPIO0_8.MCU_I2C1_SCL */ 597 J784S4_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0) 598 /* (L34) WKUP_GPIO0_9.MCU_I2C1_SDA */ 599 J784S4_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0) 600 >; 601 }; 602 603 hdmi_pdn_pins_default: hdmi-pdn-default-pins { 604 pinctrl-single,pins = < 605 J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 7) /* (H37) WKUP_GPIO0_14 */ 606 >; 607 }; 608 609 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 610 pinctrl-single,pins = < 611 J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ 612 J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ 613 >; 614 }; 615 616 mcu_mcan1_pins_default: mcu-mcan1-default-pins { 617 pinctrl-single,pins = < 618 J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ 619 J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0)/* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ 620 >; 621 }; 622 623}; 624 625&wkup_pmx3 { 626 mcu_rpi_hdr2_gpio0_pins_default: mcu-rpi-hdr2-gpio0-default-pins { 627 pinctrl-single,pins = < 628 J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO0_49 */ 629 >; 630 }; 631}; 632 633&mailbox0_cluster0 { 634 status = "okay"; 635 interrupts = <436>; 636 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 637 ti,mbox-rx = <0 0 0>; 638 ti,mbox-tx = <1 0 0>; 639 }; 640 641 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 642 ti,mbox-rx = <2 0 0>; 643 ti,mbox-tx = <3 0 0>; 644 }; 645}; 646 647&mailbox0_cluster1 { 648 status = "okay"; 649 interrupts = <432>; 650 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 651 ti,mbox-rx = <0 0 0>; 652 ti,mbox-tx = <1 0 0>; 653 }; 654 655 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 656 ti,mbox-rx = <2 0 0>; 657 ti,mbox-tx = <3 0 0>; 658 }; 659}; 660 661&mailbox0_cluster2 { 662 status = "okay"; 663 interrupts = <428>; 664 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 665 ti,mbox-rx = <0 0 0>; 666 ti,mbox-tx = <1 0 0>; 667 }; 668 669 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 670 ti,mbox-rx = <2 0 0>; 671 ti,mbox-tx = <3 0 0>; 672 }; 673}; 674 675&mailbox0_cluster3 { 676 status = "okay"; 677 interrupts = <424>; 678 mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { 679 ti,mbox-rx = <0 0 0>; 680 ti,mbox-tx = <1 0 0>; 681 }; 682 683 mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { 684 ti,mbox-rx = <2 0 0>; 685 ti,mbox-tx = <3 0 0>; 686 }; 687}; 688 689&mailbox0_cluster4 { 690 status = "okay"; 691 interrupts = <420>; 692 mbox_c71_0: mbox-c71-0 { 693 ti,mbox-rx = <0 0 0>; 694 ti,mbox-tx = <1 0 0>; 695 }; 696 697 mbox_c71_1: mbox-c71-1 { 698 ti,mbox-rx = <2 0 0>; 699 ti,mbox-tx = <3 0 0>; 700 }; 701}; 702 703&mailbox0_cluster5 { 704 status = "okay"; 705 interrupts = <416>; 706 mbox_c71_2: mbox-c71-2 { 707 ti,mbox-rx = <0 0 0>; 708 ti,mbox-tx = <1 0 0>; 709 }; 710 711 mbox_c71_3: mbox-c71-3 { 712 ti,mbox-rx = <2 0 0>; 713 ti,mbox-tx = <3 0 0>; 714 }; 715}; 716 717&wkup_uart0 { 718 /* Firmware usage */ 719 status = "reserved"; 720 pinctrl-names = "default"; 721 pinctrl-0 = <&wkup_uart0_pins_default>; 722}; 723 724&wkup_i2c0 { 725 bootph-all; 726 status = "okay"; 727 pinctrl-names = "default"; 728 pinctrl-0 = <&wkup_i2c0_pins_default>; 729 clock-frequency = <400000>; 730 731 eeprom@51 { 732 /* AT24C512C-MAHM-T */ 733 compatible = "atmel,24c512"; 734 reg = <0x51>; 735 }; 736 737 tps659413: pmic@48 { 738 compatible = "ti,tps6594-q1"; 739 reg = <0x48>; 740 system-power-controller; 741 pinctrl-names = "default"; 742 pinctrl-0 = <&pmic_irq_pins_default>; 743 interrupt-parent = <&wkup_gpio0>; 744 interrupts = <83 IRQ_TYPE_EDGE_FALLING>; 745 gpio-controller; 746 #gpio-cells = <2>; 747 ti,primary-pmic; 748 buck12-supply = <&vsys_3v3>; 749 buck3-supply = <&vsys_3v3>; 750 buck4-supply = <&vsys_3v3>; 751 buck5-supply = <&vsys_3v3>; 752 ldo1-supply = <&vsys_3v3>; 753 ldo2-supply = <&vsys_3v3>; 754 ldo3-supply = <&vsys_3v3>; 755 ldo4-supply = <&vsys_3v3>; 756 757 regulators { 758 bucka12: buck12 { 759 regulator-name = "vdd_ddr_1v1"; 760 regulator-min-microvolt = <1100000>; 761 regulator-max-microvolt = <1100000>; 762 regulator-boot-on; 763 regulator-always-on; 764 bootph-all; 765 }; 766 767 bucka3: buck3 { 768 regulator-name = "vdd_ram_0v85"; 769 regulator-min-microvolt = <850000>; 770 regulator-max-microvolt = <850000>; 771 regulator-boot-on; 772 regulator-always-on; 773 bootph-all; 774 }; 775 776 bucka4: buck4 { 777 regulator-name = "vdd_io_1v8"; 778 regulator-min-microvolt = <1800000>; 779 regulator-max-microvolt = <1800000>; 780 regulator-boot-on; 781 regulator-always-on; 782 bootph-all; 783 }; 784 785 bucka5: buck5 { 786 regulator-name = "vdd_mcu_0v85"; 787 regulator-min-microvolt = <850000>; 788 regulator-max-microvolt = <850000>; 789 regulator-boot-on; 790 regulator-always-on; 791 bootph-all; 792 }; 793 794 ldoa1: ldo1 { 795 regulator-name = "vdd_mcuio_1v8"; 796 regulator-min-microvolt = <1800000>; 797 regulator-max-microvolt = <1800000>; 798 regulator-boot-on; 799 regulator-always-on; 800 bootph-all; 801 }; 802 803 ldoa2: ldo2 { 804 regulator-name = "vdd_mcuio_3v3"; 805 regulator-min-microvolt = <3300000>; 806 regulator-max-microvolt = <3300000>; 807 regulator-boot-on; 808 regulator-always-on; 809 bootph-all; 810 }; 811 812 ldoa3: ldo3 { 813 regulator-name = "vds_dll_0v8"; 814 regulator-min-microvolt = <800000>; 815 regulator-max-microvolt = <800000>; 816 regulator-boot-on; 817 regulator-always-on; 818 bootph-all; 819 }; 820 821 ldoa4: ldo4 { 822 regulator-name = "vda_mcu_1v8"; 823 regulator-min-microvolt = <1800000>; 824 regulator-max-microvolt = <1800000>; 825 regulator-boot-on; 826 regulator-always-on; 827 bootph-all; 828 }; 829 }; 830 }; 831 832 tps62873a: regulator@40 { 833 compatible = "ti,tps62873"; 834 reg = <0x40>; 835 bootph-pre-ram; 836 regulator-name = "VDD_CPU_AVS"; 837 regulator-min-microvolt = <600000>; 838 regulator-max-microvolt = <900000>; 839 regulator-boot-on; 840 regulator-always-on; 841 }; 842 843 tps62873b: regulator@43 { 844 compatible = "ti,tps62873"; 845 reg = <0x43>; 846 regulator-name = "VDD_CORE_0V8"; 847 regulator-min-microvolt = <760000>; 848 regulator-max-microvolt = <840000>; 849 regulator-boot-on; 850 regulator-always-on; 851 }; 852}; 853 854&wkup_gpio0 { 855 status = "okay"; 856 pinctrl-names = "default"; 857 pinctrl-0 = <&mcu_rpi_hdr1_gpio0_pins_default>, <&mcu_rpi_hdr2_gpio0_pins_default>; 858}; 859 860&mcu_uart0 { 861 bootph-all; 862 status = "okay"; 863 pinctrl-names = "default"; 864 pinctrl-0 = <&mcu_uart0_pins_default>; 865}; 866 867&mcu_i2c0 { 868 status = "okay"; 869 pinctrl-names = "default"; 870 pinctrl-0 = <&mcu_i2c0_pins_default>; 871 clock-frequency = <400000>; 872}; 873 874&main_uart8 { 875 bootph-all; 876 status = "okay"; 877 pinctrl-names = "default"; 878 pinctrl-0 = <&main_uart8_pins_default>; 879}; 880 881&main_i2c0 { 882 status = "okay"; 883 pinctrl-names = "default"; 884 pinctrl-0 = <&main_i2c0_pins_default>; 885 clock-frequency = <400000>; 886 887 exp1: gpio@21 { 888 compatible = "ti,tca6416"; 889 reg = <0x21>; 890 gpio-controller; 891 #gpio-cells = <2>; 892 gpio-line-names = "BOARDID_EEPROM_WP", "CAN_STB", "GPIO_uSD_PWR_EN", 893 "IO_EXP_MCU_RGMII_RST#", "IO_EXP_PCIe0_4L_PERST#", 894 "IO_EXP_PCIe1_M.2_RTSz", "IO_EXP_PCIe3_M.2_RTSz", 895 "PM_INA_BUS_EN", "ENET1_EXP_PWRDN", "EXP1_ENET_RSTz", 896 "ENET1_I2CMUX_SEL", "PCIe0_CLKREQ#", "PCIe1_M.2_CLKREQ#", 897 "PCIe3_M2_CLKREQ#", "PCIe0_PRSNT2#_1", "PCIe0_PRSNT2#_2"; 898 }; 899}; 900 901&main_i2c1 { 902 pinctrl-names = "default"; 903 pinctrl-0 = <&main_i2c1_pins_default>; 904 clock-frequency = <400000>; 905 status = "okay"; 906 907 exp2: gpio@21 { 908 compatible = "ti,tca6408"; 909 reg = <0x21>; 910 gpio-controller; 911 #gpio-cells = <2>; 912 gpio-line-names = "CSI_VIO_SEL", "CSI_MUX_SEL_2", "CSI2_RSTz", 913 "IO_EXP_CAM0_GPIO1", "IO_EXP_CAM1_GPIO1"; 914 }; 915 916 i2c-mux@70 { 917 compatible = "nxp,pca9543"; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 reg = <0x70>; 921 922 cam0_i2c: i2c@0 { 923 #address-cells = <1>; 924 #size-cells = <0>; 925 reg = <0>; 926 }; 927 928 cam1_i2c: i2c@1 { 929 #address-cells = <1>; 930 #size-cells = <0>; 931 reg = <1>; 932 }; 933 934 }; 935}; 936 937&main_sdhci0 { 938 bootph-all; 939 /* eMMC */ 940 status = "okay"; 941 non-removable; 942 ti,driver-strength-ohm = <50>; 943 disable-wp; 944}; 945 946&main_sdhci1 { 947 bootph-all; 948 /* SD card */ 949 status = "okay"; 950 pinctrl-0 = <&main_mmc1_pins_default>; 951 pinctrl-names = "default"; 952 disable-wp; 953 vmmc-supply = <&vdd_mmc1>; 954 vqmmc-supply = <&vdd_sd_dv>; 955}; 956 957&main_gpio0 { 958 status = "okay"; 959 pinctrl-names = "default"; 960 pinctrl-0 = <&rpi_header_gpio0_pins_default>; 961}; 962 963&mcu_cpsw { 964 status = "okay"; 965 pinctrl-names = "default"; 966 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; 967}; 968 969&davinci_mdio { 970 mcu_phy0: ethernet-phy@0 { 971 reg = <0>; 972 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 973 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 974 ti,min-output-impedance; 975 }; 976}; 977 978&mcu_cpsw_port1 { 979 status = "okay"; 980 phy-mode = "rgmii-rxid"; 981 phy-handle = <&mcu_phy0>; 982}; 983 984&mcu_r5fss0_core0 { 985 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 986 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 987 <&mcu_r5fss0_core0_memory_region>; 988}; 989 990&mcu_r5fss0_core1 { 991 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 992 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 993 <&mcu_r5fss0_core1_memory_region>; 994}; 995 996&main_r5fss0 { 997 ti,cluster-mode = <0>; 998}; 999 1000&main_r5fss1 { 1001 ti,cluster-mode = <0>; 1002}; 1003 1004/* Timers are used by Remoteproc firmware */ 1005&main_timer0 { 1006 status = "reserved"; 1007}; 1008 1009&main_timer1 { 1010 status = "reserved"; 1011}; 1012 1013&main_timer2 { 1014 status = "reserved"; 1015}; 1016 1017&main_timer3 { 1018 status = "reserved"; 1019}; 1020 1021&main_timer4 { 1022 status = "reserved"; 1023}; 1024 1025&main_timer5 { 1026 status = "reserved"; 1027}; 1028 1029&main_timer6 { 1030 status = "reserved"; 1031}; 1032 1033&main_timer7 { 1034 status = "reserved"; 1035}; 1036 1037&main_timer8 { 1038 status = "reserved"; 1039}; 1040 1041&main_timer9 { 1042 status = "reserved"; 1043}; 1044 1045&main_r5fss2 { 1046 ti,cluster-mode = <0>; 1047}; 1048 1049&main_r5fss0_core0 { 1050 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 1051 memory-region = <&main_r5fss0_core0_dma_memory_region>, 1052 <&main_r5fss0_core0_memory_region>; 1053}; 1054 1055&main_r5fss0_core1 { 1056 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 1057 memory-region = <&main_r5fss0_core1_dma_memory_region>, 1058 <&main_r5fss0_core1_memory_region>; 1059}; 1060 1061&main_r5fss1_core0 { 1062 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 1063 memory-region = <&main_r5fss1_core0_dma_memory_region>, 1064 <&main_r5fss1_core0_memory_region>; 1065}; 1066 1067&main_r5fss1_core1 { 1068 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 1069 memory-region = <&main_r5fss1_core1_dma_memory_region>, 1070 <&main_r5fss1_core1_memory_region>; 1071}; 1072 1073&main_r5fss2_core0 { 1074 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; 1075 memory-region = <&main_r5fss2_core0_dma_memory_region>, 1076 <&main_r5fss2_core0_memory_region>; 1077}; 1078 1079&main_r5fss2_core1 { 1080 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; 1081 memory-region = <&main_r5fss2_core1_dma_memory_region>, 1082 <&main_r5fss2_core1_memory_region>; 1083}; 1084 1085&c71_0 { 1086 status = "okay"; 1087 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 1088 memory-region = <&c71_0_dma_memory_region>, 1089 <&c71_0_memory_region>; 1090}; 1091 1092&c71_1 { 1093 status = "okay"; 1094 mboxes = <&mailbox0_cluster4 &mbox_c71_1>; 1095 memory-region = <&c71_1_dma_memory_region>, 1096 <&c71_1_memory_region>; 1097}; 1098 1099&c71_2 { 1100 status = "okay"; 1101 mboxes = <&mailbox0_cluster5 &mbox_c71_2>; 1102 memory-region = <&c71_2_dma_memory_region>, 1103 <&c71_2_memory_region>; 1104}; 1105 1106&c71_3 { 1107 status = "okay"; 1108 mboxes = <&mailbox0_cluster5 &mbox_c71_3>; 1109 memory-region = <&c71_3_dma_memory_region>, 1110 <&c71_3_memory_region>; 1111}; 1112 1113&wkup_gpio_intr { 1114 status = "okay"; 1115}; 1116 1117&mcu_i2c1 { 1118 status = "okay"; 1119 pinctrl-names = "default"; 1120 pinctrl-0 = <&mcu_i2c1_pins_default>; 1121 clock-frequency = <100000>; 1122}; 1123 1124&serdes_refclk { 1125 status = "okay"; 1126 clock-frequency = <100000000>; 1127}; 1128 1129&dss { 1130 status = "okay"; 1131 pinctrl-names = "default"; 1132 pinctrl-0 = <&dss_vout0_pins_default>; 1133 assigned-clocks = <&k3_clks 218 2>, 1134 <&k3_clks 218 5>; 1135 assigned-clock-parents = <&k3_clks 218 3>, 1136 <&k3_clks 218 7>; 1137}; 1138 1139&serdes_wiz4 { 1140 status = "okay"; 1141}; 1142 1143&serdes4 { 1144 status = "okay"; 1145 serdes4_dp_link: phy@0 { 1146 reg = <0>; 1147 cdns,num-lanes = <4>; 1148 #phy-cells = <0>; 1149 cdns,phy-type = <PHY_TYPE_DP>; 1150 resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, 1151 <&serdes_wiz4 3>, <&serdes_wiz4 4>; 1152 }; 1153}; 1154 1155&mhdp { 1156 status = "okay"; 1157 pinctrl-names = "default"; 1158 pinctrl-0 = <&dp0_pins_default>; 1159 phys = <&serdes4_dp_link>; 1160 phy-names = "dpphy"; 1161}; 1162 1163&dss_ports { 1164 #address-cells = <1>; 1165 #size-cells = <0>; 1166 1167 /* DP */ 1168 port@0 { 1169 reg = <0>; 1170 1171 dpi0_out: endpoint { 1172 remote-endpoint = <&dp0_in>; 1173 }; 1174 }; 1175 1176 /* HDMI */ 1177 port@1 { 1178 reg = <1>; 1179 1180 dpi1_out0: endpoint { 1181 remote-endpoint = <&tfp410_in>; 1182 }; 1183 }; 1184}; 1185 1186&dp0_ports { 1187 1188 port@0 { 1189 reg = <0>; 1190 1191 dp0_in: endpoint { 1192 remote-endpoint = <&dpi0_out>; 1193 }; 1194 }; 1195 1196 port@4 { 1197 reg = <4>; 1198 1199 dp0_out: endpoint { 1200 remote-endpoint = <&dp0_connector_in>; 1201 }; 1202 }; 1203}; 1204 1205&mcu_mcan0 { 1206 status = "okay"; 1207 pinctrl-names = "default"; 1208 pinctrl-0 = <&mcu_mcan0_pins_default>; 1209 phys = <&transceiver1>; 1210}; 1211 1212&mcu_mcan1 { 1213 status = "okay"; 1214 pinctrl-names = "default"; 1215 pinctrl-0 = <&mcu_mcan1_pins_default>; 1216 phys = <&transceiver2>; 1217}; 1218 1219&main_mcan6 { 1220 status = "okay"; 1221 pinctrl-names = "default"; 1222 pinctrl-0 = <&main_mcan6_pins_default>; 1223 phys = <&transceiver3>; 1224}; 1225 1226&main_mcan7 { 1227 status = "okay"; 1228 pinctrl-names = "default"; 1229 pinctrl-0 = <&main_mcan7_pins_default>; 1230 phys = <&transceiver4>; 1231}; 1232 1233&ospi0 { 1234 status = "okay"; 1235 pinctrl-names = "default"; 1236 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 1237 1238 flash@0 { 1239 compatible = "jedec,spi-nor"; 1240 reg = <0x0>; 1241 spi-tx-bus-width = <8>; 1242 spi-rx-bus-width = <8>; 1243 spi-max-frequency = <25000000>; 1244 cdns,tshsl-ns = <60>; 1245 cdns,tsd2d-ns = <60>; 1246 cdns,tchsh-ns = <60>; 1247 cdns,tslch-ns = <60>; 1248 cdns,read-delay = <4>; 1249 1250 partitions { 1251 bootph-all; 1252 compatible = "fixed-partitions"; 1253 #address-cells = <1>; 1254 #size-cells = <1>; 1255 1256 partition@0 { 1257 label = "ospi.tiboot3"; 1258 reg = <0x0 0x100000>; 1259 }; 1260 1261 partition@100000 { 1262 label = "ospi.tispl"; 1263 reg = <0x100000 0x200000>; 1264 }; 1265 1266 partition@300000 { 1267 label = "ospi.u-boot"; 1268 reg = <0x300000 0x400000>; 1269 }; 1270 1271 partition@700000 { 1272 label = "ospi.env"; 1273 reg = <0x700000 0x40000>; 1274 }; 1275 1276 partition@740000 { 1277 label = "ospi.env.backup"; 1278 reg = <0x740000 0x40000>; 1279 }; 1280 1281 partition@800000 { 1282 label = "ospi.rootfs"; 1283 reg = <0x800000 0x37c0000>; 1284 }; 1285 1286 partition@3fc0000 { 1287 bootph-pre-ram; 1288 label = "ospi.phypattern"; 1289 reg = <0x3fc0000 0x40000>; 1290 }; 1291 }; 1292 }; 1293}; 1294 1295&serdes_ln_ctrl { 1296 idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>, 1297 <J784S4_SERDES0_LANE2_PCIE3_LANE0>, <J784S4_SERDES0_LANE3_USB>, 1298 <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>, 1299 <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>; 1300}; 1301 1302&serdes_wiz0 { 1303 status = "okay"; 1304}; 1305 1306&serdes0 { 1307 status = "okay"; 1308 1309 serdes0_pcie_link: phy@0 { 1310 reg = <0>; 1311 cdns,num-lanes = <3>; 1312 #phy-cells = <0>; 1313 cdns,phy-type = <PHY_TYPE_PCIE>; 1314 resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>, <&serdes_wiz0 3>; 1315 }; 1316 1317 serdes0_usb_link: phy@3 { 1318 reg = <3>; 1319 cdns,num-lanes = <1>; 1320 #phy-cells = <0>; 1321 cdns,phy-type = <PHY_TYPE_USB3>; 1322 resets = <&serdes_wiz0 4>; 1323 }; 1324}; 1325 1326&serdes_wiz1 { 1327 status = "okay"; 1328}; 1329 1330&serdes1 { 1331 status = "okay"; 1332 1333 serdes1_pcie_link: phy@0 { 1334 reg = <0>; 1335 cdns,num-lanes = <4>; 1336 #phy-cells = <0>; 1337 cdns,phy-type = <PHY_TYPE_PCIE>; 1338 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>, <&serdes_wiz1 3>, <&serdes_wiz1 4>; 1339 }; 1340}; 1341 1342&pcie0_rc { 1343 status = "okay"; 1344 reset-gpios = <&exp1 4 GPIO_ACTIVE_HIGH>; 1345 phys = <&serdes1_pcie_link>; 1346 phy-names = "pcie-phy"; 1347}; 1348 1349&pcie1_rc { 1350 status = "okay"; 1351 reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; 1352 phys = <&serdes0_pcie_link>; 1353 phy-names = "pcie-phy"; 1354 num-lanes = <2>; 1355}; 1356 1357&pcie3_rc { 1358 status = "okay"; 1359 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; 1360 phys = <&serdes0_pcie_link>; 1361 phy-names = "pcie-phy"; 1362 num-lanes = <1>; 1363}; 1364 1365&usb_serdes_mux { 1366 idle-states = <0>; /* USB0 to SERDES0 */ 1367}; 1368 1369&usbss0 { 1370 status = "okay"; 1371 pinctrl-0 = <&main_usbss0_pins_default>; 1372 pinctrl-names = "default"; 1373 ti,vbus-divider; 1374}; 1375 1376&usb0 { 1377 status = "okay"; 1378 dr_mode = "otg"; 1379 maximum-speed = "super-speed"; 1380 phys = <&serdes0_usb_link>; 1381 phy-names = "cdns3,usb3-phy"; 1382}; 1383