1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * IPQ9574 RDP433 board device tree source
4 *
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/gpio/gpio.h>
12#include "ipq9574-rdp-common.dtsi"
13
14/ {
15	model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
16	compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
17};
18
19&pcie1_phy {
20	status = "okay";
21};
22
23&pcie1 {
24	pinctrl-0 = <&pcie1_default>;
25	pinctrl-names = "default";
26
27	perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
28	wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
29	status = "okay";
30};
31
32&pcie2_phy {
33	status = "okay";
34};
35
36&pcie2 {
37	pinctrl-0 = <&pcie2_default>;
38	pinctrl-names = "default";
39
40	perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
41	wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
42	status = "okay";
43};
44
45&pcie3_phy {
46	status = "okay";
47};
48
49&pcie3 {
50	pinctrl-0 = <&pcie3_default>;
51	pinctrl-names = "default";
52
53	perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
54	wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
55	status = "okay";
56};
57
58&sdhc_1 {
59	pinctrl-0 = <&sdc_default_state>;
60	pinctrl-names = "default";
61	mmc-ddr-1_8v;
62	mmc-hs200-1_8v;
63	mmc-hs400-1_8v;
64	mmc-hs400-enhanced-strobe;
65	max-frequency = <384000000>;
66	bus-width = <8>;
67	status = "okay";
68};
69
70&tlmm {
71
72	pcie1_default: pcie1-default-state {
73		clkreq-n-pins {
74			pins = "gpio25";
75			function = "pcie1_clk";
76			drive-strength = <6>;
77			bias-pull-up;
78		};
79
80		perst-n-pins {
81			pins = "gpio26";
82			function = "gpio";
83			drive-strength = <8>;
84			bias-pull-down;
85			output-low;
86		};
87
88		wake-n-pins {
89			pins = "gpio27";
90			function = "pcie1_wake";
91			drive-strength = <6>;
92			bias-pull-up;
93		};
94	};
95
96	pcie2_default: pcie2-default-state {
97		clkreq-n-pins {
98			pins = "gpio28";
99			function = "pcie2_clk";
100			drive-strength = <6>;
101			bias-pull-up;
102		};
103
104		perst-n-pins {
105			pins = "gpio29";
106			function = "gpio";
107			drive-strength = <8>;
108			bias-pull-down;
109			output-low;
110		};
111
112		wake-n-pins {
113			pins = "gpio30";
114			function = "pcie2_wake";
115			drive-strength = <6>;
116			bias-pull-up;
117		};
118	};
119
120	pcie3_default: pcie3-default-state {
121		clkreq-n-pins {
122			pins = "gpio31";
123			function = "pcie3_clk";
124			drive-strength = <6>;
125			bias-pull-up;
126		};
127
128		perst-n-pins {
129			pins = "gpio32";
130			function = "gpio";
131			drive-strength = <8>;
132			bias-pull-up;
133			output-low;
134		};
135
136		wake-n-pins {
137			pins = "gpio33";
138			function = "pcie3_wake";
139			drive-strength = <6>;
140			bias-pull-up;
141		};
142	};
143
144	sdc_default_state: sdc-default-state {
145		clk-pins {
146			pins = "gpio5";
147			function = "sdc_clk";
148			drive-strength = <8>;
149			bias-disable;
150		};
151
152		cmd-pins {
153			pins = "gpio4";
154			function = "sdc_cmd";
155			drive-strength = <8>;
156			bias-pull-up;
157		};
158
159		data-pins {
160			pins = "gpio0", "gpio1", "gpio2",
161			       "gpio3", "gpio6", "gpio7",
162			       "gpio8", "gpio9";
163			function = "sdc_data";
164			drive-strength = <8>;
165			bias-pull-up;
166		};
167
168		rclk-pins {
169			pins = "gpio10";
170			function = "sdc_rclk";
171			drive-strength = <8>;
172			bias-pull-down;
173		};
174	};
175};
176