1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2021-2022 BayLibre, SAS.
4 * Authors:
5 * Fabien Parent <[email protected]>
6 * Bernhard Rosenkränzer <[email protected]>
7 * Alexandre Mergnat <[email protected]>
8 */
9
10/dts-v1/;
11
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/input/input.h>
14#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
15#include "mt8365.dtsi"
16#include "mt6357.dtsi"
17
18/ {
19	model = "MediaTek MT8365 Open Platform EVK";
20	compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
21
22	aliases {
23		serial0 = &uart0;
24		ethernet = &ethernet;
25	};
26
27	chosen {
28		stdout-path = "serial0:921600n8";
29	};
30
31	firmware {
32		optee {
33			compatible = "linaro,optee-tz";
34			method = "smc";
35		};
36	};
37
38	gpio-keys {
39		compatible = "gpio-keys";
40		pinctrl-names = "default";
41		pinctrl-0 = <&gpio_keys>;
42
43		key-volume-up {
44			gpios = <&pio 24 GPIO_ACTIVE_LOW>;
45			label = "volume_up";
46			linux,code = <KEY_VOLUMEUP>;
47			wakeup-source;
48			debounce-interval = <15>;
49		};
50	};
51
52	memory@40000000 {
53		device_type = "memory";
54		reg = <0 0x40000000 0 0xc0000000>;
55	};
56
57	usb_otg_vbus: regulator-0 {
58		compatible = "regulator-fixed";
59		regulator-name = "otg_vbus";
60		regulator-min-microvolt = <5000000>;
61		regulator-max-microvolt = <5000000>;
62		gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
63		enable-active-high;
64	};
65
66	reserved-memory {
67		#address-cells = <2>;
68		#size-cells = <2>;
69		ranges;
70
71		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
72		bl31_secmon_reserved: secmon@43000000 {
73			no-map;
74			reg = <0 0x43000000 0 0x30000>;
75		};
76
77		/* 12 MiB reserved for OP-TEE (BL32)
78		 * +-----------------------+ 0x43e0_0000
79		 * |      SHMEM 2MiB       |
80		 * +-----------------------+ 0x43c0_0000
81		 * |        | TA_RAM  8MiB |
82		 * + TZDRAM +--------------+ 0x4340_0000
83		 * |        | TEE_RAM 2MiB |
84		 * +-----------------------+ 0x4320_0000
85		 */
86		optee_reserved: optee@43200000 {
87			no-map;
88			reg = <0 0x43200000 0 0x00c00000>;
89		};
90	};
91
92	sound: sound {
93		compatible = "mediatek,mt8365-mt6357";
94		pinctrl-names = "default",
95				"dmic",
96				"miso_off",
97				"miso_on",
98				"mosi_off",
99				"mosi_on";
100		pinctrl-0 = <&aud_default_pins>;
101		pinctrl-1 = <&aud_dmic_pins>;
102		pinctrl-2 = <&aud_miso_off_pins>;
103		pinctrl-3 = <&aud_miso_on_pins>;
104		pinctrl-4 = <&aud_mosi_off_pins>;
105		pinctrl-5 = <&aud_mosi_on_pins>;
106		mediatek,platform = <&afe>;
107	};
108};
109
110&afe {
111	mediatek,dmic-mode = <1>;
112	status = "okay";
113};
114
115&cpu0 {
116	proc-supply = <&mt6357_vproc_reg>;
117	sram-supply = <&mt6357_vsram_proc_reg>;
118};
119
120&cpu1 {
121	proc-supply = <&mt6357_vproc_reg>;
122	sram-supply = <&mt6357_vsram_proc_reg>;
123};
124
125&cpu2 {
126	proc-supply = <&mt6357_vproc_reg>;
127	sram-supply = <&mt6357_vsram_proc_reg>;
128};
129
130&cpu3 {
131	proc-supply = <&mt6357_vproc_reg>;
132	sram-supply = <&mt6357_vsram_proc_reg>;
133};
134
135&ethernet {
136	pinctrl-0 = <&ethernet_pins>;
137	pinctrl-names = "default";
138	phy-handle = <&eth_phy>;
139	phy-mode = "rmii";
140	/*
141	 * Ethernet and HDMI (DSI0) are sharing pins.
142	 * Only one can be enabled at a time and require the physical switch
143	 * SW2101 to be set on LAN position
144	 * mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet
145	 */
146	status = "disabled";
147
148	mdio {
149		#address-cells = <1>;
150		#size-cells = <0>;
151
152		eth_phy: ethernet-phy@0 {
153			reg = <0>;
154		};
155	};
156};
157
158&i2c0 {
159	clock-frequency = <100000>;
160	pinctrl-0 = <&i2c0_pins>;
161	pinctrl-names = "default";
162	status = "okay";
163};
164
165&mmc0 {
166	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
167	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
168	bus-width = <8>;
169	cap-mmc-highspeed;
170	cap-mmc-hw-reset;
171	hs400-ds-delay = <0x12012>;
172	max-frequency = <200000000>;
173	mmc-hs200-1_8v;
174	mmc-hs400-1_8v;
175	no-sd;
176	no-sdio;
177	non-removable;
178	pinctrl-0 = <&mmc0_default_pins>;
179	pinctrl-1 = <&mmc0_uhs_pins>;
180	pinctrl-names = "default", "state_uhs";
181	vmmc-supply = <&mt6357_vemc_reg>;
182	vqmmc-supply = <&mt6357_vio18_reg>;
183	status = "okay";
184};
185
186&mmc1 {
187	bus-width = <4>;
188	cap-sd-highspeed;
189	cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
190	max-frequency = <200000000>;
191	pinctrl-0 = <&mmc1_default_pins>;
192	pinctrl-1 = <&mmc1_uhs_pins>;
193	pinctrl-names = "default", "state_uhs";
194	sd-uhs-sdr104;
195	sd-uhs-sdr50;
196	vmmc-supply = <&mt6357_vmch_reg>;
197	vqmmc-supply = <&mt6357_vmc_reg>;
198	status = "okay";
199};
200
201&mt6357_pmic {
202	interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
203	interrupt-controller;
204	#interrupt-cells = <2>;
205	mediatek,micbias0-microvolt = <1900000>;
206	mediatek,micbias1-microvolt = <1700000>;
207};
208
209&pio {
210	aud_default_pins: audiodefault-pins {
211		clk-dat-pins {
212			pinmux = <MT8365_PIN_72_CMDAT4__FUNC_I2S3_BCK>,
213				 <MT8365_PIN_73_CMDAT5__FUNC_I2S3_LRCK>,
214				 <MT8365_PIN_74_CMDAT6__FUNC_I2S3_MCK>,
215				 <MT8365_PIN_75_CMDAT7__FUNC_I2S3_DO>;
216		};
217	};
218
219	aud_dmic_pins: audiodmic-pins {
220		clk-dat-pins {
221			pinmux = <MT8365_PIN_117_DMIC0_CLK__FUNC_DMIC0_CLK>,
222				 <MT8365_PIN_118_DMIC0_DAT0__FUNC_DMIC0_DAT0>,
223				 <MT8365_PIN_119_DMIC0_DAT1__FUNC_DMIC0_DAT1>;
224		};
225	};
226
227	aud_miso_off_pins: misooff-pins {
228		clk-dat-pins {
229			pinmux = <MT8365_PIN_53_AUD_CLK_MISO__FUNC_GPIO53>,
230				 <MT8365_PIN_54_AUD_SYNC_MISO__FUNC_GPIO54>,
231				 <MT8365_PIN_55_AUD_DAT_MISO0__FUNC_GPIO55>,
232				 <MT8365_PIN_56_AUD_DAT_MISO1__FUNC_GPIO56>;
233			input-enable;
234			bias-pull-down;
235			drive-strength = <2>;
236		};
237	};
238
239	aud_miso_on_pins: misoon-pins {
240		clk-dat-pins {
241			pinmux = <MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MISO>,
242				 <MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MISO>,
243				 <MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MISO0>,
244				 <MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MISO1>;
245			drive-strength = <6>;
246		};
247	};
248
249	aud_mosi_off_pins: mosioff-pins {
250		clk-dat-pins {
251			pinmux = <MT8365_PIN_49_AUD_CLK_MOSI__FUNC_GPIO49>,
252				 <MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_GPIO50>,
253				 <MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_GPIO51>,
254				 <MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_GPIO52>;
255			input-enable;
256			bias-pull-down;
257			drive-strength = <2>;
258		};
259	};
260
261	aud_mosi_on_pins: mosion-pins {
262		clk-dat-pins {
263			pinmux = <MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI>,
264				 <MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MOSI>,
265				 <MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MOSI0>,
266				 <MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MOSI1>;
267			drive-strength = <6>;
268		};
269	};
270
271	ethernet_pins: ethernet-pins {
272		phy_reset_pins {
273			pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
274		};
275
276		rmii_pins {
277			pinmux = <MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0>,
278				 <MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1>,
279				 <MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2>,
280				 <MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3>,
281				 <MT8365_PIN_4_GPIO4__FUNC_EXT_TXC>,
282				 <MT8365_PIN_5_GPIO5__FUNC_EXT_RXER>,
283				 <MT8365_PIN_6_GPIO6__FUNC_EXT_RXC>,
284				 <MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV>,
285				 <MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0>,
286				 <MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1>,
287				 <MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2>,
288				 <MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3>,
289				 <MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN>,
290				 <MT8365_PIN_13_GPIO13__FUNC_EXT_COL>,
291				 <MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO>,
292				 <MT8365_PIN_15_GPIO15__FUNC_EXT_MDC>;
293		};
294	};
295
296	gpio_keys: gpio-keys-pins {
297		pins {
298			pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
299			bias-pull-up;
300			input-enable;
301		};
302	};
303
304	i2c0_pins: i2c0-pins {
305		pins {
306			pinmux = <MT8365_PIN_57_SDA0__FUNC_SDA0_0>,
307				 <MT8365_PIN_58_SCL0__FUNC_SCL0_0>;
308			bias-pull-up;
309		};
310	};
311
312	mmc0_default_pins: mmc0-default-pins {
313		clk-pins {
314			pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
315			bias-pull-down;
316		};
317
318		cmd-dat-pins {
319			pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
320				 <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
321				 <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
322				 <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
323				 <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
324				 <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
325				 <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
326				 <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
327				 <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
328			input-enable;
329			bias-pull-up;
330		};
331
332		rst-pins {
333			pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
334			bias-pull-up;
335		};
336	};
337
338	mmc0_uhs_pins: mmc0-uhs-pins {
339		clk-pins {
340			pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
341			drive-strength = <MTK_DRIVE_10mA>;
342			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
343		};
344
345		cmd-dat-pins {
346			pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
347				 <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
348				 <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
349				 <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
350				 <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
351				 <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
352				 <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
353				 <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
354				 <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
355			input-enable;
356			drive-strength = <MTK_DRIVE_10mA>;
357			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
358		};
359
360		ds-pins {
361			pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
362			drive-strength = <MTK_DRIVE_10mA>;
363			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
364		};
365
366		rst-pins {
367			pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
368			drive-strength = <MTK_DRIVE_10mA>;
369			bias-pull-up;
370		};
371	};
372
373	mmc1_default_pins: mmc1-default-pins {
374		cd-pins {
375			pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
376			bias-pull-up;
377		};
378
379		clk-pins {
380			pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
381			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
382		};
383
384		cmd-dat-pins {
385			pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
386				 <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
387				 <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
388				 <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
389				 <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
390			input-enable;
391			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
392		};
393	};
394
395	mmc1_uhs_pins: mmc1-uhs-pins {
396		clk-pins {
397			pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
398			drive-strength = <8>;
399			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
400		};
401
402		cmd-dat-pins {
403			pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
404				 <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
405				 <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
406				 <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
407				 <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
408			input-enable;
409			drive-strength = <6>;
410			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
411		};
412	};
413
414	uart0_pins: uart0-pins {
415		pins {
416			pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
417				 <MT8365_PIN_36_UTXD0__FUNC_UTXD0>;
418		};
419	};
420
421	uart1_pins: uart1-pins {
422		pins {
423			pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
424				 <MT8365_PIN_38_UTXD1__FUNC_UTXD1>;
425		};
426	};
427
428	uart2_pins: uart2-pins {
429		pins {
430			pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
431				 <MT8365_PIN_40_UTXD2__FUNC_UTXD2>;
432		};
433	};
434
435	usb_pins: usb-pins {
436		id-pins {
437			pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
438			input-enable;
439			bias-pull-up;
440		};
441
442		usb0-vbus-pins {
443			pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
444			output-high;
445		};
446
447		usb1-vbus-pins {
448			pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
449			output-high;
450		};
451	};
452
453	pwm_pins: pwm-pins {
454		pins {
455			pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
456				 <MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>;
457		};
458	};
459};
460
461&pwm {
462	pinctrl-0 = <&pwm_pins>;
463	pinctrl-names = "default";
464	status = "okay";
465};
466
467&ssusb {
468	dr_mode = "otg";
469	maximum-speed = "high-speed";
470	pinctrl-0 = <&usb_pins>;
471	pinctrl-names = "default";
472	usb-role-switch;
473	vusb33-supply = <&mt6357_vusb33_reg>;
474	status = "okay";
475
476	connector {
477		compatible = "gpio-usb-b-connector", "usb-b-connector";
478		id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
479		type = "micro";
480		vbus-supply = <&usb_otg_vbus>;
481	};
482};
483
484&usb_host {
485	vusb33-supply = <&mt6357_vusb33_reg>;
486	status = "okay";
487};
488
489&uart0 {
490	pinctrl-0 = <&uart0_pins>;
491	pinctrl-names = "default";
492	status = "okay";
493};
494
495&uart1 {
496	pinctrl-0 = <&uart1_pins>;
497	pinctrl-names = "default";
498	status = "okay";
499};
500
501&uart2 {
502	pinctrl-0 = <&uart2_pins>;
503	pinctrl-names = "default";
504	status = "okay";
505};
506