1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2024 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx93.dtsi" 10 11/ { 12 model = "NXP i.MX93 9x9 Quick Start Board"; 13 compatible = "fsl,imx93-9x9-qsb", "fsl,imx93"; 14 15 bt_sco_codec: bt-sco-codec { 16 #sound-dai-cells = <1>; 17 compatible = "linux,bt-sco"; 18 }; 19 20 chosen { 21 stdout-path = &lpuart1; 22 }; 23 24 reserved-memory { 25 #address-cells = <2>; 26 #size-cells = <2>; 27 ranges; 28 29 linux,cma { 30 compatible = "shared-dma-pool"; 31 reusable; 32 size = <0 0x10000000>; 33 linux,cma-default; 34 }; 35 36 vdev0vring0: vdev0vring0@a4000000 { 37 reg = <0 0xa4000000 0 0x8000>; 38 no-map; 39 }; 40 41 vdev0vring1: vdev0vring1@a4008000 { 42 reg = <0 0xa4008000 0 0x8000>; 43 no-map; 44 }; 45 46 vdev1vring0: vdev1vring0@a4010000 { 47 reg = <0 0xa4010000 0 0x8000>; 48 no-map; 49 }; 50 51 vdev1vring1: vdev1vring1@a4018000 { 52 reg = <0 0xa4018000 0 0x8000>; 53 no-map; 54 }; 55 56 rsc_table: rsc-table@2021e000 { 57 reg = <0 0x2021e000 0 0x1000>; 58 no-map; 59 }; 60 61 vdevbuffer: vdevbuffer@a4020000 { 62 compatible = "shared-dma-pool"; 63 reg = <0 0xa4020000 0 0x100000>; 64 no-map; 65 }; 66 67 }; 68 69 reg_vref_1v8: regulator-adc-vref { 70 compatible = "regulator-fixed"; 71 regulator-name = "VREF_1V8"; 72 regulator-min-microvolt = <1800000>; 73 regulator-max-microvolt = <1800000>; 74 }; 75 76 reg_audio_pwr: regulator-audio-pwr { 77 compatible = "regulator-fixed"; 78 regulator-name = "audio-pwr"; 79 regulator-min-microvolt = <3300000>; 80 regulator-max-microvolt = <3300000>; 81 gpio = <&pcal6524 16 GPIO_ACTIVE_HIGH>; 82 enable-active-high; 83 }; 84 85 reg_rpi_3v3: regulator-rpi { 86 compatible = "regulator-fixed"; 87 regulator-name = "VDD_RPI_3V3"; 88 regulator-min-microvolt = <3300000>; 89 regulator-max-microvolt = <3300000>; 90 gpio = <&pcal6524 21 GPIO_ACTIVE_HIGH>; 91 enable-active-high; 92 }; 93 94 reg_usdhc2_vmmc: regulator-usdhc2 { 95 compatible = "regulator-fixed"; 96 pinctrl-names = "default"; 97 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 98 regulator-name = "VSD_3V3"; 99 regulator-min-microvolt = <3300000>; 100 regulator-max-microvolt = <3300000>; 101 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 102 enable-active-high; 103 off-on-delay-us = <12000>; 104 }; 105 106 sound-bt-sco { 107 compatible = "simple-audio-card"; 108 simple-audio-card,name = "bt-sco-audio"; 109 simple-audio-card,format = "dsp_a"; 110 simple-audio-card,bitclock-inversion; 111 simple-audio-card,frame-master = <&btcpu>; 112 simple-audio-card,bitclock-master = <&btcpu>; 113 114 btcpu: simple-audio-card,cpu { 115 sound-dai = <&sai1>; 116 dai-tdm-slot-num = <2>; 117 dai-tdm-slot-width = <16>; 118 }; 119 120 simple-audio-card,codec { 121 sound-dai = <&bt_sco_codec 1>; 122 }; 123 }; 124 125 sound-micfil { 126 compatible = "fsl,imx-audio-card"; 127 model = "micfil-audio"; 128 129 pri-dai-link { 130 link-name = "micfil hifi"; 131 format = "i2s"; 132 133 cpu { 134 sound-dai = <&micfil>; 135 }; 136 }; 137 }; 138 139 sound-wm8962 { 140 compatible = "fsl,imx-audio-wm8962"; 141 model = "wm8962-audio"; 142 audio-cpu = <&sai3>; 143 audio-codec = <&wm8962>; 144 hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; 145 audio-routing = 146 "Headphone Jack", "HPOUTL", 147 "Headphone Jack", "HPOUTR", 148 "Ext Spk", "SPKOUTL", 149 "Ext Spk", "SPKOUTR", 150 "AMIC", "MICBIAS", 151 "IN3R", "AMIC", 152 "IN1R", "AMIC"; 153 }; 154}; 155 156&adc1 { 157 vref-supply = <®_vref_1v8>; 158 status = "okay"; 159}; 160 161&cm33 { 162 mbox-names = "tx", "rx", "rxdb"; 163 mboxes = <&mu1 0 1>, 164 <&mu1 1 1>, 165 <&mu1 3 1>; 166 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 167 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 168 status = "okay"; 169}; 170 171&eqos { 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pinctrl_eqos>; 174 phy-mode = "rgmii-id"; 175 phy-handle = <ðphy1>; 176 status = "okay"; 177 178 mdio { 179 compatible = "snps,dwmac-mdio"; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 clock-frequency = <5000000>; 183 184 ethphy1: ethernet-phy@1 { 185 compatible = "ethernet-phy-ieee802.3-c22"; 186 reg = <1>; 187 eee-broken-1000t; 188 reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; 189 reset-assert-us = <10000>; 190 reset-deassert-us = <80000>; 191 realtek,clkout-disable; 192 }; 193 }; 194}; 195 196&lpi2c1 { 197 clock-frequency = <400000>; 198 pinctrl-names = "default"; 199 pinctrl-0 = <&pinctrl_lpi2c1>; 200 status = "okay"; 201 202 wm8962: audio-codec@1a { 203 compatible = "wlf,wm8962"; 204 reg = <0x1a>; 205 clocks = <&clk IMX93_CLK_SAI3_GATE>; 206 DCVDD-supply = <®_audio_pwr>; 207 DBVDD-supply = <®_audio_pwr>; 208 AVDD-supply = <®_audio_pwr>; 209 CPVDD-supply = <®_audio_pwr>; 210 MICVDD-supply = <®_audio_pwr>; 211 PLLVDD-supply = <®_audio_pwr>; 212 SPKVDD1-supply = <®_audio_pwr>; 213 SPKVDD2-supply = <®_audio_pwr>; 214 gpio-cfg = < 215 0x0000 /* 0:Default */ 216 0x0000 /* 1:Default */ 217 0x0000 /* 2:FN_DMICCLK */ 218 0x0000 /* 3:Default */ 219 0x0000 /* 4:FN_DMICCDAT */ 220 0x0000 /* 5:Default */ 221 >; 222 }; 223 224 p3t1085: temperature-sensor@48 { 225 compatible = "nxp,p3t1085"; 226 reg = <0x48>; 227 }; 228 229 ptn5110: tcpc@50 { 230 compatible = "nxp,ptn5110", "tcpci"; 231 reg = <0x50>; 232 interrupt-parent = <&gpio3>; 233 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 234 235 typec1_con: connector { 236 compatible = "usb-c-connector"; 237 label = "USB-C"; 238 power-role = "dual"; 239 data-role = "dual"; 240 try-power-role = "sink"; 241 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 242 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 243 PDO_VAR(5000, 20000, 3000)>; 244 op-sink-microwatt = <15000000>; 245 self-powered; 246 247 ports { 248 #address-cells = <1>; 249 #size-cells = <0>; 250 251 port@0 { 252 reg = <0>; 253 254 typec1_dr_sw: endpoint { 255 remote-endpoint = <&usb1_drd_sw>; 256 }; 257 }; 258 }; 259 }; 260 }; 261 262 rtc@53 { 263 compatible = "nxp,pcf2131"; 264 reg = <0x53>; 265 interrupt-parent = <&pcal6524>; 266 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 267 }; 268}; 269 270&lpi2c2 { 271 clock-frequency = <400000>; 272 pinctrl-names = "default"; 273 pinctrl-0 = <&pinctrl_lpi2c2>; 274 status = "okay"; 275 276 pcal6524: gpio@22 { 277 compatible = "nxp,pcal6524"; 278 reg = <0x22>; 279 gpio-controller; 280 #gpio-cells = <2>; 281 interrupt-controller; 282 #interrupt-cells = <2>; 283 interrupt-parent = <&gpio3>; 284 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 285 pinctrl-names = "default"; 286 pinctrl-0 = <&pinctrl_pcal6524>; 287 288 exp-sel-hog { 289 gpio-hog; 290 gpios = <22 GPIO_ACTIVE_HIGH>; 291 output-low; 292 }; 293 294 mic-can-sel-hog { 295 gpio-hog; 296 gpios = <17 GPIO_ACTIVE_HIGH>; 297 output-low; 298 }; 299 }; 300 301 pmic@25 { 302 compatible = "nxp,pca9451a"; 303 reg = <0x25>; 304 interrupt-parent = <&pcal6524>; 305 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 306 307 regulators { 308 buck1: BUCK1 { 309 regulator-name = "BUCK1"; 310 regulator-min-microvolt = <650000>; 311 regulator-max-microvolt = <2237500>; 312 regulator-boot-on; 313 regulator-always-on; 314 regulator-ramp-delay = <3125>; 315 }; 316 317 buck2: BUCK2 { 318 regulator-name = "BUCK2"; 319 regulator-min-microvolt = <600000>; 320 regulator-max-microvolt = <2187500>; 321 regulator-boot-on; 322 regulator-always-on; 323 regulator-ramp-delay = <3125>; 324 }; 325 326 buck4: BUCK4 { 327 regulator-name = "BUCK4"; 328 regulator-min-microvolt = <600000>; 329 regulator-max-microvolt = <3400000>; 330 regulator-boot-on; 331 regulator-always-on; 332 }; 333 334 buck5: BUCK5 { 335 regulator-name = "BUCK5"; 336 regulator-min-microvolt = <600000>; 337 regulator-max-microvolt = <3400000>; 338 regulator-boot-on; 339 regulator-always-on; 340 }; 341 342 buck6: BUCK6 { 343 regulator-name = "BUCK6"; 344 regulator-min-microvolt = <600000>; 345 regulator-max-microvolt = <3400000>; 346 regulator-boot-on; 347 regulator-always-on; 348 }; 349 350 ldo1: LDO1 { 351 regulator-name = "LDO1"; 352 regulator-min-microvolt = <1600000>; 353 regulator-max-microvolt = <3300000>; 354 regulator-boot-on; 355 regulator-always-on; 356 }; 357 358 ldo4: LDO4 { 359 regulator-name = "LDO4"; 360 regulator-min-microvolt = <800000>; 361 regulator-max-microvolt = <3300000>; 362 regulator-boot-on; 363 regulator-always-on; 364 }; 365 366 ldo5: LDO5 { 367 regulator-name = "LDO5"; 368 regulator-min-microvolt = <1800000>; 369 regulator-max-microvolt = <3300000>; 370 regulator-boot-on; 371 regulator-always-on; 372 }; 373 }; 374 }; 375}; 376 377&lpuart1 { /* console */ 378 pinctrl-names = "default"; 379 pinctrl-0 = <&pinctrl_uart1>; 380 status = "okay"; 381}; 382 383&micfil { 384 pinctrl-names = "default"; 385 pinctrl-0 = <&pinctrl_pdm>; 386 assigned-clocks = <&clk IMX93_CLK_PDM>; 387 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 388 assigned-clock-rates = <49152000>; 389 status = "okay"; 390}; 391 392&mu1 { 393 status = "okay"; 394}; 395 396&mu2 { 397 status = "okay"; 398}; 399 400&sai1 { 401 pinctrl-names = "default"; 402 pinctrl-0 = <&pinctrl_sai1>; 403 assigned-clocks = <&clk IMX93_CLK_SAI1>; 404 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 405 assigned-clock-rates = <12288000>; 406 fsl,sai-mclk-direction-output; 407 status = "okay"; 408}; 409 410&sai3 { 411 pinctrl-names = "default"; 412 pinctrl-0 = <&pinctrl_sai3>; 413 assigned-clocks = <&clk IMX93_CLK_SAI3>; 414 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 415 assigned-clock-rates = <12288000>; 416 fsl,sai-mclk-direction-output; 417 fsl,sai-synchronous-rx; 418 status = "okay"; 419}; 420 421&usbotg1 { 422 dr_mode = "otg"; 423 hnp-disable; 424 srp-disable; 425 adp-disable; 426 usb-role-switch; 427 disable-over-current; 428 samsung,picophy-pre-emp-curr-control = <3>; 429 samsung,picophy-dc-vol-level-adjust = <7>; 430 status = "okay"; 431 432 port { 433 usb1_drd_sw: endpoint { 434 remote-endpoint = <&typec1_dr_sw>; 435 }; 436 }; 437}; 438 439&usdhc1 { 440 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 441 pinctrl-0 = <&pinctrl_usdhc1>; 442 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 443 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 444 bus-width = <8>; 445 non-removable; 446 status = "okay"; 447}; 448 449&usdhc2 { 450 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 451 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 452 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 453 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 454 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 455 vmmc-supply = <®_usdhc2_vmmc>; 456 bus-width = <4>; 457 no-mmc; 458 status = "okay"; 459}; 460 461&wdog3 { 462 pinctrl-names = "default"; 463 pinctrl-0 = <&pinctrl_wdog>; 464 fsl,ext-reset-output; 465 status = "okay"; 466}; 467 468&iomuxc { 469 pinctrl_eqos: eqosgrp { 470 fsl,pins = < 471 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e 472 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 473 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 474 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 475 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 476 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 477 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e 478 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 479 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 480 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e 481 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 482 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 483 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e 484 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 485 >; 486 }; 487 488 pinctrl_lpi2c1: lpi2c1grp { 489 fsl,pins = < 490 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 491 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 492 >; 493 }; 494 495 pinctrl_lpi2c2: lpi2c2grp { 496 fsl,pins = < 497 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 498 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 499 >; 500 }; 501 502 pinctrl_pcal6524: pcal6524grp { 503 fsl,pins = < 504 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e 505 >; 506 }; 507 508 pinctrl_pdm: pdmgrp { 509 fsl,pins = < 510 MX93_PAD_PDM_CLK__PDM_CLK 0x31e 511 MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e 512 MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e 513 >; 514 }; 515 516 pinctrl_uart1: uart1grp { 517 fsl,pins = < 518 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 519 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 520 >; 521 }; 522 523 pinctrl_uart5: uart5grp { 524 fsl,pins = < 525 MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 526 MX93_PAD_DAP_TDI__LPUART5_RX 0x31e 527 MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 528 MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 529 >; 530 }; 531 532 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 533 pinctrl_usdhc1: usdhc1grp { 534 fsl,pins = < 535 MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 536 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 537 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 538 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 539 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 540 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 541 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 542 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 543 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 544 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 545 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 546 >; 547 }; 548 549 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 550 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 551 fsl,pins = < 552 MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e 553 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e 554 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 555 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e 556 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e 557 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e 558 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e 559 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e 560 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e 561 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e 562 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 563 >; 564 }; 565 566 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 567 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 568 fsl,pins = < 569 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe 570 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe 571 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe 572 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe 573 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe 574 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe 575 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe 576 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe 577 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe 578 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe 579 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 580 >; 581 }; 582 583 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 584 fsl,pins = < 585 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 586 >; 587 }; 588 589 pinctrl_sai1: sai1grp { 590 fsl,pins = < 591 MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e 592 MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e 593 MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e 594 MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e 595 >; 596 }; 597 598 pinctrl_sai3: sai3grp { 599 fsl,pins = < 600 MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x31e 601 MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x31e 602 MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e 603 MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e 604 MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e 605 >; 606 }; 607 608 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 609 fsl,pins = < 610 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 611 >; 612 }; 613 614 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 615 pinctrl_usdhc2: usdhc2grp { 616 fsl,pins = < 617 MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 618 MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 619 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 620 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 621 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 622 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 623 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 624 >; 625 }; 626 627 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 628 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 629 fsl,pins = < 630 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e 631 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e 632 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 633 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 634 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e 635 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e 636 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 637 >; 638 }; 639 640 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 641 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 642 fsl,pins = < 643 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe 644 MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe 645 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe 646 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe 647 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe 648 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe 649 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 650 >; 651 }; 652 653 pinctrl_wdog: wdoggrp { 654 fsl,pins = < 655 MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e 656 >; 657 }; 658}; 659