1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2024 NXP
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/usb/pd.h>
9#include "imx93.dtsi"
10
11/ {
12	model = "NXP i.MX93 14X14 EVK board";
13	compatible = "fsl,imx93-14x14-evk", "fsl,imx93";
14
15	chosen {
16		stdout-path = &lpuart1;
17	};
18
19	reserved-memory {
20		#address-cells = <2>;
21		#size-cells = <2>;
22		ranges;
23
24		linux,cma {
25			compatible = "shared-dma-pool";
26			reusable;
27			alloc-ranges = <0 0x80000000 0 0x40000000>;
28			size = <0 0x10000000>;
29			linux,cma-default;
30		};
31
32		vdev0vring0: vdev0vring0@a4000000 {
33			reg = <0 0xa4000000 0 0x8000>;
34			no-map;
35		};
36
37		vdev0vring1: vdev0vring1@a4008000 {
38			reg = <0 0xa4008000 0 0x8000>;
39			no-map;
40		};
41
42		vdev1vring0: vdev1vring0@a4010000 {
43			reg = <0 0xa4010000 0 0x8000>;
44			no-map;
45		};
46
47		vdev1vring1: vdev1vring1@a4018000 {
48			reg = <0 0xa4018000 0 0x8000>;
49			no-map;
50		};
51
52		rsc_table: rsc-table@2021e000 {
53			reg = <0 0x2021e000 0 0x1000>;
54			no-map;
55		};
56
57		vdevbuffer: vdevbuffer@a4020000 {
58			compatible = "shared-dma-pool";
59			reg = <0 0xa4020000 0 0x100000>;
60			no-map;
61		};
62	};
63
64	reg_can1_stby: regulator-can1-stby {
65		compatible = "regulator-fixed";
66		regulator-name = "can1-stby";
67		regulator-min-microvolt = <3300000>;
68		regulator-max-microvolt = <3300000>;
69		gpio = <&pcal6524_2 10 GPIO_ACTIVE_HIGH>;
70		enable-active-high;
71		vin-supply = <&reg_can1_en>;
72	};
73
74	reg_can1_en: regulator-can1-en {
75		compatible = "regulator-fixed";
76		regulator-name = "can1-en";
77		regulator-min-microvolt = <3300000>;
78		regulator-max-microvolt = <3300000>;
79		gpio = <&pcal6524_2 12 GPIO_ACTIVE_HIGH>;
80		enable-active-high;
81	};
82
83	reg_can2_stby: regulator-can2-stby {
84		compatible = "regulator-fixed";
85		regulator-name = "can2-stby";
86		regulator-min-microvolt = <3300000>;
87		regulator-max-microvolt = <3300000>;
88		gpio = <&pcal6524_2 11 GPIO_ACTIVE_HIGH>;
89		enable-active-high;
90		vin-supply = <&reg_can2_en>;
91	};
92
93	reg_can2_en: regulator-can2-en {
94		compatible = "regulator-fixed";
95		regulator-name = "can2-en";
96		regulator-min-microvolt = <3300000>;
97		regulator-max-microvolt = <3300000>;
98		gpio = <&pcal6524_2 13 GPIO_ACTIVE_HIGH>;
99		enable-active-high;
100	};
101
102	reg_usdhc2_vmmc: regulator-usdhc2 {
103		compatible = "regulator-fixed";
104		pinctrl-names = "default";
105		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
106		regulator-name = "VSD_3V3";
107		regulator-min-microvolt = <3300000>;
108		regulator-max-microvolt = <3300000>;
109		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
110		enable-active-high;
111		off-on-delay-us = <12000>;
112	};
113
114	reg_vdd_12v: regulator-vdd-12v {
115		compatible = "regulator-fixed";
116		regulator-name = "reg_vdd_12v";
117		regulator-min-microvolt = <12000000>;
118		regulator-max-microvolt = <12000000>;
119		gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>;
120		enable-active-high;
121	};
122
123	reg_vref_1v8: regulator-adc-vref {
124		compatible = "regulator-fixed";
125		regulator-name = "vref_1v8";
126		regulator-min-microvolt = <1800000>;
127		regulator-max-microvolt = <1800000>;
128	};
129};
130
131&adc1 {
132	vref-supply = <&reg_vref_1v8>;
133	status = "okay";
134};
135
136&cm33 {
137	mbox-names = "tx", "rx", "rxdb";
138	mboxes = <&mu1 0 1>,
139		 <&mu1 1 1>,
140		 <&mu1 3 1>;
141	memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
142			<&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
143	status = "okay";
144};
145
146&fec {
147	pinctrl-names = "default";
148	pinctrl-0 = <&pinctrl_fec>;
149	phy-mode = "rgmii-id";
150	phy-handle = <&ethphy2>;
151	fsl,magic-packet;
152	status = "okay";
153
154	mdio {
155		#address-cells = <1>;
156		#size-cells = <0>;
157		clock-frequency = <5000000>;
158
159		ethphy2: ethernet-phy@2 {
160			compatible = "ethernet-phy-ieee802.3-c22";
161			reg = <2>;
162			eee-broken-1000t;
163			reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
164			reset-assert-us = <10000>;
165			reset-deassert-us = <80000>;
166			realtek,clkout-disable;
167		};
168	};
169};
170
171&flexcan1 {
172	pinctrl-names = "default";
173	pinctrl-0 = <&pinctrl_flexcan1>;
174	xceiver-supply = <&reg_can1_stby>;
175	status = "okay";
176};
177
178&flexcan2 {
179	pinctrl-names = "default";
180	pinctrl-0 = <&pinctrl_flexcan2>;
181	xceiver-supply = <&reg_can2_stby>;
182	status = "okay";
183};
184
185&lpi2c1 {
186	clock-frequency = <400000>;
187	pinctrl-names = "default";
188	pinctrl-0 = <&pinctrl_lpi2c1>;
189	status = "okay";
190
191	lsm6dsm@6a {
192		compatible = "st,lsm6dso";
193		reg = <0x6a>;
194	};
195};
196
197&lpi2c2 {
198	clock-frequency = <400000>;
199	pinctrl-names = "default";
200	pinctrl-0 = <&pinctrl_lpi2c2>;
201	status = "okay";
202
203	pcal6524_2: gpio@20 {
204		compatible = "nxp,pcal6524";
205		reg = <0x20>;
206		gpio-controller;
207		#gpio-cells = <2>;
208	};
209
210	pcal6524: gpio@22 {
211		compatible = "nxp,pcal6524";
212		pinctrl-names = "default";
213		pinctrl-0 = <&pinctrl_pcal6524>;
214		reg = <0x22>;
215		gpio-controller;
216		#gpio-cells = <2>;
217		interrupt-controller;
218		#interrupt-cells = <2>;
219		interrupt-parent = <&gpio3>;
220		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
221	};
222
223	pmic@25 {
224		compatible = "nxp,pca9452";
225		reg = <0x25>;
226		interrupt-parent = <&pcal6524>;
227		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
228
229		regulators {
230			buck1: BUCK1 {
231				regulator-name = "BUCK1";
232				regulator-min-microvolt = <610000>;
233				regulator-max-microvolt = <950000>;
234				regulator-boot-on;
235				regulator-always-on;
236				regulator-ramp-delay = <3125>;
237			};
238
239			buck2: BUCK2 {
240				regulator-name = "BUCK2";
241				regulator-min-microvolt = <600000>;
242				regulator-max-microvolt = <670000>;
243				regulator-boot-on;
244				regulator-always-on;
245				regulator-ramp-delay = <3125>;
246			};
247
248			buck4: BUCK4{
249				regulator-name = "BUCK4";
250				regulator-min-microvolt = <1620000>;
251				regulator-max-microvolt = <3400000>;
252				regulator-boot-on;
253				regulator-always-on;
254			};
255
256			buck5: BUCK5{
257				regulator-name = "BUCK5";
258				regulator-min-microvolt = <1620000>;
259				regulator-max-microvolt = <3400000>;
260				regulator-boot-on;
261				regulator-always-on;
262			};
263
264			buck6: BUCK6 {
265				regulator-name = "BUCK6";
266				regulator-min-microvolt = <1060000>;
267				regulator-max-microvolt = <1140000>;
268				regulator-boot-on;
269				regulator-always-on;
270			};
271
272			ldo1: LDO1 {
273				regulator-name = "LDO1";
274				regulator-min-microvolt = <1620000>;
275				regulator-max-microvolt = <1980000>;
276				regulator-boot-on;
277				regulator-always-on;
278			};
279
280			ldo3: LDO3 {
281				regulator-name = "LDO3";
282				regulator-min-microvolt = <1710000>;
283				regulator-max-microvolt = <1890000>;
284				regulator-boot-on;
285				regulator-always-on;
286			};
287
288			ldo4: LDO4 {
289				regulator-name = "LDO4";
290				regulator-min-microvolt = <800000>;
291				regulator-max-microvolt = <840000>;
292				regulator-boot-on;
293				regulator-always-on;
294			};
295
296			ldo5: LDO5 {
297				regulator-name = "LDO5";
298				regulator-min-microvolt = <1800000>;
299				regulator-max-microvolt = <3300000>;
300				regulator-boot-on;
301				regulator-always-on;
302			};
303		};
304	};
305};
306
307&lpi2c3 {
308	clock-frequency = <400000>;
309	pinctrl-names = "default";
310	pinctrl-0 = <&pinctrl_lpi2c3>;
311	status = "okay";
312};
313
314&lpuart1 { /* console */
315	pinctrl-names = "default";
316	pinctrl-0 = <&pinctrl_uart1>;
317	status = "okay";
318};
319
320&mu1 {
321	status = "okay";
322};
323
324&mu2 {
325	status = "okay";
326};
327
328&usbotg1 {
329	dr_mode = "otg";
330	hnp-disable;
331	srp-disable;
332	adp-disable;
333	disable-over-current;
334	samsung,picophy-pre-emp-curr-control = <3>;
335	samsung,picophy-dc-vol-level-adjust = <7>;
336	status = "okay";
337};
338
339&usbotg2 {
340	dr_mode = "host";
341	disable-over-current;
342	samsung,picophy-pre-emp-curr-control = <3>;
343	samsung,picophy-dc-vol-level-adjust = <7>;
344	status = "okay";
345};
346
347&usdhc1 {
348	pinctrl-names = "default", "state_100mhz", "state_200mhz";
349	pinctrl-0 = <&pinctrl_usdhc1>;
350	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
351	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
352	bus-width = <8>;
353	non-removable;
354	status = "okay";
355};
356
357&usdhc2 {
358	pinctrl-names = "default", "state_100mhz", "state_200mhz";
359	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
360	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
361	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
362	cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
363	vmmc-supply = <&reg_usdhc2_vmmc>;
364	bus-width = <4>;
365	no-mmc;
366	status = "okay";
367};
368
369&wdog3 {
370	pinctrl-names = "default";
371	pinctrl-0 = <&pinctrl_wdog>;
372	fsl,ext-reset-output;
373	status = "okay";
374};
375
376&iomuxc {
377	pinctrl_flexcan1: flexcan1grp {
378		fsl,pins = <
379			MX93_PAD_PDM_CLK__CAN1_TX		0x139e
380			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX	0x139e
381		>;
382	};
383
384	pinctrl_flexcan2: flexcan2grp {
385		fsl,pins = <
386			MX93_PAD_GPIO_IO25__CAN2_TX	0x139e
387			MX93_PAD_GPIO_IO27__CAN2_RX	0x139e
388		>;
389	};
390
391	pinctrl_lpi2c1: lpi2c1grp {
392		fsl,pins = <
393			MX93_PAD_I2C1_SCL__LPI2C1_SCL			0x40000b9e
394			MX93_PAD_I2C1_SDA__LPI2C1_SDA			0x40000b9e
395		>;
396	};
397
398	pinctrl_lpi2c2: lpi2c2grp {
399		fsl,pins = <
400			MX93_PAD_I2C2_SCL__LPI2C2_SCL			0x40000b9e
401			MX93_PAD_I2C2_SDA__LPI2C2_SDA			0x40000b9e
402		>;
403	};
404
405	pinctrl_lpi2c3: lpi2c3grp {
406		fsl,pins = <
407			MX93_PAD_GPIO_IO28__LPI2C3_SDA			0x40000b9e
408			MX93_PAD_GPIO_IO29__LPI2C3_SCL			0x40000b9e
409		>;
410	};
411
412	pinctrl_pcal6524: pcal6524grp {
413		fsl,pins = <
414			MX93_PAD_CCM_CLKO2__GPIO3_IO27			0x31e
415		>;
416	};
417
418	pinctrl_fec: fecgrp {
419		fsl,pins = <
420			MX93_PAD_ENET2_MDC__ENET1_MDC			0x57e
421			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x57e
422			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x57e
423			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x57e
424			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2		0x57e
425			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3		0x57e
426			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC		0x58e
427			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL	0x57e
428			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0		0x57e
429			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1		0x57e
430			MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2		0x57e
431			MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3		0x57e
432			MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC		0x58e
433			MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL	0x57e
434		>;
435	};
436
437	pinctrl_uart1: uart1grp {
438		fsl,pins = <
439			MX93_PAD_UART1_RXD__LPUART1_RX			0x31e
440			MX93_PAD_UART1_TXD__LPUART1_TX			0x31e
441		>;
442	};
443
444	pinctrl_uart5: uart5grp {
445		fsl,pins = <
446			MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX	0x31e
447			MX93_PAD_DAP_TDI__LPUART5_RX		0x31e
448			MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B	0x31e
449			MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B	0x31e
450		>;
451	};
452
453	/* need to config the SION for data and cmd pad, refer to ERR052021 */
454	pinctrl_usdhc1: usdhc1grp {
455		fsl,pins = <
456			MX93_PAD_SD1_CLK__USDHC1_CLK		0x1582
457			MX93_PAD_SD1_CMD__USDHC1_CMD		0x40001382
458			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x40001382
459			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x40001382
460			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x40001382
461			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x40001382
462			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x40001382
463			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x40001382
464			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x40001382
465			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x40001382
466			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x1582
467		>;
468	};
469
470	/* need to config the SION for data and cmd pad, refer to ERR052021 */
471	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
472		fsl,pins = <
473			MX93_PAD_SD1_CLK__USDHC1_CLK		0x158e
474			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000138e
475			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000138e
476			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x4000138e
477			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x4000138e
478			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x4000138e
479			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x4000138e
480			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x4000138e
481			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x4000138e
482			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x4000138e
483			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x158e
484		>;
485	};
486
487	/* need to config the SION for data and cmd pad, refer to ERR052021 */
488	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
489		fsl,pins = <
490			MX93_PAD_SD1_CLK__USDHC1_CLK		0x15fe
491			MX93_PAD_SD1_CMD__USDHC1_CMD		0x400013fe
492			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x400013fe
493			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x400013fe
494			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013fe
495			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x400013fe
496			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x400013fe
497			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x400013fe
498			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x400013fe
499			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x400013fe
500			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe
501		>;
502	};
503
504	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
505		fsl,pins = <
506			MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x31e
507		>;
508	};
509
510	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
511		fsl,pins = <
512			MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e
513		>;
514	};
515
516	/* need to config the SION for data and cmd pad, refer to ERR052021 */
517	pinctrl_usdhc2: usdhc2grp {
518		fsl,pins = <
519			MX93_PAD_SD2_CLK__USDHC2_CLK		0x1582
520			MX93_PAD_SD2_CMD__USDHC2_CMD		0x40001382
521			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x40001382
522			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x40001382
523			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x40001382
524			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x40001382
525			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
526		>;
527	};
528
529	/* need to config the SION for data and cmd pad, refer to ERR052021 */
530	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
531		fsl,pins = <
532			MX93_PAD_SD2_CLK__USDHC2_CLK		0x158e
533			MX93_PAD_SD2_CMD__USDHC2_CMD		0x4000138e
534			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x4000138e
535			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x4000138e
536			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x4000138e
537			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x4000138e
538			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
539		>;
540	};
541
542	/* need to config the SION for data and cmd pad, refer to ERR052021 */
543	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
544		fsl,pins = <
545			MX93_PAD_SD2_CLK__USDHC2_CLK		0x15fe
546			MX93_PAD_SD2_CMD__USDHC2_CMD		0x400013fe
547			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x400013fe
548			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x400013fe
549			MX93_PAD_SD2_DATA2__USDHC2_DATA2	0x400013fe
550			MX93_PAD_SD2_DATA3__USDHC2_DATA3	0x400013fe
551			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
552		>;
553	};
554
555	pinctrl_wdog: wdoggrp {
556		fsl,pins = <
557			MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY	0x31e
558		>;
559	};
560};
561