1// SPDX-License-Identifier: GPL-2.0 OR X11
2/*
3 * Device Tree Source for TQ-Systems TQMa7D board on MBa7 carrier board.
4 *
5 * Copyright (C) 2016 TQ-Systems GmbH
6 * Author: Markus Niebel <[email protected]>
7 * Copyright (C) 2019 Bruno Thomsen <[email protected]>
8 */
9
10/dts-v1/;
11
12#include "imx7d-tqma7.dtsi"
13#include "imx7-mba7.dtsi"
14
15/ {
16	model = "TQ-Systems TQMa7D board on MBa7 carrier board";
17	compatible = "tq,imx7d-mba7", "tq,imx7d-tqma7", "fsl,imx7d";
18};
19
20&fec2 {
21	pinctrl-names = "default";
22	pinctrl-0 = <&pinctrl_enet2>;
23	phy-mode = "rgmii-id";
24	phy-handle = <&ethphy2_0>;
25	fsl,magic-packet;
26	status = "okay";
27
28	mdio {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		ethphy2_0: ethernet-phy@0 {
33			compatible = "ethernet-phy-ieee802.3-c22";
34			reg = <0>;
35			pinctrl-names = "default";
36			pinctrl-0 = <&pinctrl_enet2_phy>;
37			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
38			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
39			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
40			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
41			reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
42			reset-assert-us = <1000>;
43			reset-deassert-us = <500>;
44			interrupt-parent = <&gpio2>;
45			interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
46		};
47	};
48};
49
50&gpio2 {
51	pcie-dis-hog {
52		gpio-hog;
53		gpios = <29 GPIO_ACTIVE_HIGH>;
54		output-high;
55		line-name = "pcie-dis";
56	};
57
58	pcie-rst-hog {
59		gpio-hog;
60		gpios = <12 GPIO_ACTIVE_HIGH>;
61		output-high;
62		line-name = "pcie-rst";
63	};
64};
65
66&iomuxc {
67	pinctrl-names = "default";
68	pinctrl-0 = <&pinctrl_hog_mba7_1>, <&pinctrl_hog_pcie>;
69
70	pinctrl_enet2: enet2grp {
71		fsl,pins =
72			<MX7D_PAD_SD2_CD_B__ENET2_MDIO			0x02>,
73			<MX7D_PAD_SD2_WP__ENET2_MDC			0x00>,
74			<MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC		0x71>,
75			<MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0		0x71>,
76			<MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1		0x71>,
77			<MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2		0x71>,
78			<MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3		0x71>,
79			<MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL		0x71>,
80			<MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC		0x79>,
81			<MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0		0x79>,
82			<MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1		0x79>,
83			<MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2		0x79>,
84			<MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3		0x79>,
85			<MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL	0x79>;
86	};
87
88	pinctrl_enet2_phy: enet2phygrp {
89		fsl,pins =
90			/* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
91			<MX7D_PAD_EPDC_BDR0__GPIO2_IO28		0x40000070>,
92			/* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
93			<MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31	0x40000078>;
94	};
95
96	pinctrl_hog_pcie: hogpciegrp {
97		fsl,pins =
98			/* #pcie_rst */
99			<MX7D_PAD_SD2_CLK__GPIO5_IO12			0x70>,
100			/* #pcie_dis */
101			<MX7D_PAD_EPDC_BDR1__GPIO2_IO29			0x70>;
102	};
103
104	pinctrl_pcie: pciegrp {
105		fsl,pins =
106			/* #pcie_wake */
107			<MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30		0x70>;
108	};
109};
110
111&iomuxc_lpsr {
112	pinctrl_usbotg2: usbotg2grp {
113		fsl,pins =
114			<MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC	0x5c>,
115			<MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7	0x59>;
116	};
117};
118
119&pcie {
120	pinctrl-names = "default";
121	pinctrl-0 = <&pinctrl_pcie>;
122	/* 1.5V logically from 3.3V */
123	/* probe deferral not supported */
124	/* pcie-bus-supply = <&reg_mpcie_1v5>; */
125	reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
126	status = "disabled";
127};
128
129&usbotg2 {
130	pinctrl-names = "default";
131	pinctrl-0 = <&pinctrl_usbotg2>;
132	vbus-supply = <&reg_usb_otg2_vbus>;
133	disable-over-current;
134	dr_mode = "host";
135	status = "okay";
136};
137