1// SPDX-License-Identifier: GPL-2.0 OR X11
2/*
3 * Device Tree Include file for TQ-Systems MBa7 carrier board.
4 *
5 * Copyright (C) 2016 TQ-Systems GmbH
6 * Author: Markus Niebel <[email protected]>
7 * Copyright (C) 2019 Bruno Thomsen <[email protected]>
8 *
9 * Note: This file does not include nodes for all peripheral devices.
10 * As device driver coverage increases additional nodes can be added.
11 */
12
13#include <dt-bindings/input/input.h>
14#include <dt-bindings/net/ti-dp83867.h>
15
16/ {
17	aliases {
18		mmc0 = &usdhc3;
19		mmc1 = &usdhc1;
20		/delete-property/ mmc2;
21		rtc0 = &ds1339;
22		rtc1 = &snvs_rtc;
23	};
24
25	beeper {
26		compatible = "gpio-beeper";
27		gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>;
28	};
29
30	chosen {
31		stdout-path = &uart6;
32	};
33
34	gpio_buttons: gpio-keys {
35		compatible = "gpio-keys";
36
37		/*
38		 * NOTE: These buttons are attached to a GPIO-expander.
39		 * Enabling wakeup-source, enables wakeup on all inputs.
40		 * If PE_GPIO[3..6] are used as inputs, they cause a
41		 * wakeup as well.
42		 */
43		button-0 {
44			/* #SWITCH_A */
45			label = "S11";
46			linux,code = <KEY_1>;
47			gpios = <&pca9555 13 GPIO_ACTIVE_LOW>;
48			wakeup-source;
49		};
50
51		button-1 {
52			/* #SWITCH_B */
53			label = "S12";
54			linux,code = <KEY_2>;
55			gpios = <&pca9555 14 GPIO_ACTIVE_LOW>;
56			wakeup-source;
57		};
58
59		button-2 {
60			/* #SWITCH_C */
61			label = "S13";
62			linux,code = <KEY_3>;
63			gpios = <&pca9555 15 GPIO_ACTIVE_LOW>;
64			wakeup-source;
65		};
66	};
67
68	gpio-leds {
69		compatible = "gpio-leds";
70
71		led1 {
72			label = "led1";
73			gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>;
74			linux,default-trigger = "default-on";
75		};
76
77		led2 {
78			label = "led2";
79			gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>;
80			linux,default-trigger = "heartbeat";
81		};
82	};
83
84	iio-hwmon {
85		compatible = "iio-hwmon";
86		io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>,
87			      <&adc2 0>, <&adc2 1>, <&adc2 2>, <&adc2 3>;
88	};
89
90	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
91		compatible = "regulator-fixed";
92		regulator-name = "VBUS_USBOTG1";
93		regulator-min-microvolt = <5000000>;
94		regulator-max-microvolt = <5000000>;
95		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
96		enable-active-high;
97	};
98
99	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
100		compatible = "regulator-fixed";
101		regulator-name = "VBUS_USBOTG2";
102		regulator-min-microvolt = <5000000>;
103		regulator-max-microvolt = <5000000>;
104		gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
105		enable-active-high;
106	};
107
108	reg_mpcie_1v5: regulator-mpcie-1v5 {
109		compatible = "regulator-fixed";
110		regulator-name = "VCC1V5_MPCIE";
111		regulator-min-microvolt = <1500000>;
112		regulator-max-microvolt = <1500000>;
113		gpio = <&pca9555 12 GPIO_ACTIVE_HIGH>;
114		enable-active-high;
115		regulator-always-on;
116		vin-supply = <&reg_mba_5v>;
117	};
118
119	reg_mpcie_3v3: regulator-mpcie-3v3 {
120		compatible = "regulator-fixed";
121		regulator-name = "VCC3V3_MPCIE";
122		regulator-min-microvolt = <3300000>;
123		regulator-max-microvolt = <3300000>;
124		gpio = <&pca9555 10 GPIO_ACTIVE_HIGH>;
125		enable-active-high;
126		regulator-always-on;
127		vin-supply = <&reg_mba_3v3>;
128	};
129
130	reg_mba_12v0: regulator-mba-12v0 {
131		compatible = "regulator-fixed";
132		regulator-name = "VCC12V0_MBA7";
133		regulator-min-microvolt = <12000000>;
134		regulator-max-microvolt = <12000000>;
135		gpio = <&pca9555 11 GPIO_ACTIVE_HIGH>;
136		enable-active-high;
137	};
138
139	reg_mba_5v: regulator-mba-5v {
140		compatible = "regulator-fixed";
141		regulator-name = "VCC5V";
142		regulator-min-microvolt = <5000000>;
143		regulator-max-microvolt = <5000000>;
144	};
145
146	reg_mba_3v3: regulator-mba-3v3 {
147		compatible = "regulator-fixed";
148		regulator-name = "VCC3V3";
149		regulator-min-microvolt = <3300000>;
150		regulator-max-microvolt = <3300000>;
151	};
152
153	reg_vref_1v8: regulator-vref-1v8 {
154		compatible = "regulator-fixed";
155		regulator-name = "VCC1V8_REF";
156		regulator-min-microvolt = <1800000>;
157		regulator-max-microvolt = <1800000>;
158		regulator-always-on;
159		vin-supply = <&sw2_reg>;
160	};
161
162	reg_audio_3v3: regulator-audio-3v3 {
163		compatible = "regulator-fixed";
164		regulator-name = "VCC3V3_AUDIO";
165		regulator-min-microvolt = <3300000>;
166		regulator-max-microvolt = <3300000>;
167		regulator-always-on;
168		vin-supply = <&reg_mba_3v3>;
169	};
170
171	sound {
172		compatible = "fsl,imx-audio-tlv320aic32x4";
173		model = "imx-audio-tlv320aic32x4";
174		ssi-controller = <&sai1>;
175		audio-codec = <&tlv320aic32x4>;
176		audio-routing =
177			"IN3_L", "Mic Jack",
178			"Mic Jack", "Mic Bias",
179			"IN1_L", "Line In Jack",
180			"IN1_R", "Line In Jack",
181			"Line Out Jack", "LOL",
182			"Line Out Jack", "LOR";
183	};
184};
185
186&adc1 {
187	vref-supply = <&reg_vref_1v8>;
188	status = "okay";
189};
190
191&adc2 {
192	vref-supply = <&reg_vref_1v8>;
193	status = "okay";
194};
195
196&ecspi1 {
197	pinctrl-names = "default";
198	pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_ss0>;
199	cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>,
200		   <&gpio4 2 GPIO_ACTIVE_LOW>, <&gpio4 19 GPIO_ACTIVE_LOW>;
201	status = "okay";
202};
203
204&ecspi2 {
205	pinctrl-names = "default";
206	pinctrl-0 = <&pinctrl_ecspi2>;
207	status = "okay";
208};
209
210&fec1 {
211	pinctrl-names = "default";
212	pinctrl-0 = <&pinctrl_enet1>;
213	phy-mode = "rgmii-id";
214	phy-handle = <&ethphy1_0>;
215	fsl,magic-packet;
216	status = "okay";
217
218	mdio {
219		#address-cells = <1>;
220		#size-cells = <0>;
221
222		ethphy1_0: ethernet-phy@0 {
223			compatible = "ethernet-phy-ieee802.3-c22";
224			reg = <0>;
225			pinctrl-names = "default";
226			pinctrl-0 = <&pinctrl_enet1_phy>;
227			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
228			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
229			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
230			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
231			reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
232			reset-assert-us = <1000>;
233			reset-deassert-us = <500>;
234			interrupt-parent = <&gpio1>;
235			interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
236		};
237	};
238};
239
240&flash0 {
241	partitions {
242		compatible = "fixed-partitions";
243		#address-cells = <1>;
244		#size-cells = <1>;
245
246		uboot@0 {
247			label = "U-Boot";
248			reg = <0x0 0xd0000>;
249		};
250
251		env1@d0000 {
252			label = "ENV1";
253			reg = <0xd0000 0x10000>;
254		};
255
256		env2@e0000 {
257			label = "ENV2";
258			reg = <0xe0000 0x10000>;
259		};
260
261		dtb@f0000 {
262			label = "DTB";
263			reg = <0xf0000 0x10000>;
264		};
265
266		linux@100000 {
267			label = "Linux";
268			reg = <0x100000 0x700000>;
269		};
270
271		rootfs@800000 {
272			label = "RootFS";
273			reg = <0x800000 0x3800000>;
274		};
275	};
276};
277
278&flexcan1 {
279	pinctrl-names = "default";
280	pinctrl-0 = <&pinctrl_flexcan1>;
281	status = "okay";
282};
283
284&flexcan2 {
285	pinctrl-names = "default";
286	pinctrl-0 = <&pinctrl_flexcan2>;
287	status = "okay";
288};
289
290&i2c1 {
291	lm75: temperature-sensor@49 {
292		compatible = "national,lm75a";
293		reg = <0x49>;
294		vs-supply = <&reg_mba_3v3>;
295	};
296};
297
298&i2c2 {
299	clock-frequency = <100000>;
300	pinctrl-names = "default", "gpio";
301	pinctrl-0 = <&pinctrl_i2c2>;
302	pinctrl-1 = <&pinctrl_i2c2_recovery>;
303	scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
304	sda-gpios = <&gpio4 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
305	status = "okay";
306
307	tlv320aic32x4: audio-codec@18 {
308		compatible = "ti,tlv320aic32x4";
309		reg = <0x18>;
310		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
311		clock-names = "mclk";
312		ldoin-supply = <&reg_audio_3v3>;
313		iov-supply = <&reg_audio_3v3>;
314	};
315
316	pca9555: gpio-expander@20 {
317		compatible = "nxp,pca9555";
318		reg = <0x20>;
319		pinctrl-names = "default";
320		pinctrl-0 = <&pinctrl_pca9555>;
321		gpio-controller;
322		#gpio-cells = <2>;
323		interrupt-parent = <&gpio7>;
324		interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
325		interrupt-controller;
326		#interrupt-cells = <2>;
327		vcc-supply = <&reg_mba_3v3>;
328	};
329};
330
331&i2c3 {
332	clock-frequency = <100000>;
333	pinctrl-names = "default", "gpio";
334	pinctrl-0 = <&pinctrl_i2c3>;
335	pinctrl-1 = <&pinctrl_i2c3_recovery>;
336	scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
337	sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
338	status = "okay";
339};
340
341&iomuxc {
342	pinctrl-names = "default";
343	pinctrl-0 = <&pinctrl_hog_mba7_1>;
344
345	pinctrl_ecspi1: ecspi1grp {
346		fsl,pins =
347			<MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO		0x7c>,
348			<MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI		0x74>,
349			<MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK		0x74>,
350			<MX7D_PAD_UART1_RX_DATA__GPIO4_IO0		0x74>,
351			<MX7D_PAD_UART1_TX_DATA__GPIO4_IO1		0x74>,
352			<MX7D_PAD_UART2_RX_DATA__GPIO4_IO2		0x74>;
353	};
354
355	pinctrl_ecspi1_ss0: ecspi1ss0grp {
356		fsl,pins = <
357			MX7D_PAD_ECSPI1_SS0__GPIO4_IO19			0x74
358		>;
359	};
360
361	pinctrl_ecspi2: ecspi2grp {
362		fsl,pins =
363			<MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO		0x7c>,
364			<MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI		0x74>,
365			<MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK		0x74>,
366			<MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0		0x74>;
367	};
368
369	pinctrl_enet1: enet1grp {
370		fsl,pins =
371			<MX7D_PAD_GPIO1_IO10__ENET1_MDIO			0x02>,
372			<MX7D_PAD_GPIO1_IO11__ENET1_MDC				0x00>,
373			<MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC		0x71>,
374			<MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0		0x71>,
375			<MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1		0x71>,
376			<MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2		0x71>,
377			<MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3		0x71>,
378			<MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x71>,
379			<MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC		0x79>,
380			<MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0		0x79>,
381			<MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1		0x79>,
382			<MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2		0x79>,
383			<MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3		0x79>,
384			<MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x79>;
385	};
386
387	pinctrl_enet1_phy: enet1phygrp {
388		fsl,pins =
389			/* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
390			<MX7D_PAD_ENET1_COL__GPIO7_IO15				0x40000070>,
391			/* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
392			<MX7D_PAD_GPIO1_IO09__GPIO1_IO9				0x40000078>;
393	};
394
395	pinctrl_flexcan1: flexcan1grp {
396		fsl,pins =
397			<MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX	0x5a>,
398			<MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX	0x52>;
399	};
400
401	pinctrl_flexcan2: flexcan2grp {
402		fsl,pins =
403			<MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX	0x5a>,
404			<MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX	0x52>;
405	};
406
407	pinctrl_hog_mba7_1: hogmba71grp {
408		fsl,pins =
409			/* Limitation: WDOG2_B / WDOG2_RESET not usable */
410			<MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13	0x4000007c>,
411			<MX7D_PAD_ENET1_CRS__GPIO7_IO14		0x40000074>,
412			/* #BOOT_EN */
413			<MX7D_PAD_UART2_TX_DATA__GPIO4_IO3	0x40000010>;
414	};
415
416	pinctrl_i2c2: i2c2grp {
417		fsl,pins =
418			<MX7D_PAD_I2C2_SCL__I2C2_SCL		0x40000078>,
419			<MX7D_PAD_I2C2_SDA__I2C2_SDA		0x40000078>;
420	};
421
422	pinctrl_i2c2_recovery: i2c2recoverygrp {
423		fsl,pins =
424			<MX7D_PAD_I2C2_SCL__GPIO4_IO10		0x40000078>,
425			<MX7D_PAD_I2C2_SDA__GPIO4_IO11		0x40000078>;
426	};
427
428	pinctrl_i2c3: i2c3grp {
429		fsl,pins =
430			<MX7D_PAD_I2C3_SCL__I2C3_SCL		0x40000078>,
431			<MX7D_PAD_I2C3_SDA__I2C3_SDA		0x40000078>;
432	};
433
434	pinctrl_i2c3_recovery: i2c3recoverygrp {
435		fsl,pins =
436			<MX7D_PAD_I2C3_SCL__GPIO4_IO12		0x40000078>,
437			<MX7D_PAD_I2C3_SDA__GPIO4_IO13		0x40000078>;
438	};
439
440	pinctrl_pca9555: pca95550grp {
441		fsl,pins =
442			<MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12	0x78>;
443	};
444
445	pinctrl_sai1: sai1grp {
446		fsl,pins =
447			<MX7D_PAD_SAI1_MCLK__SAI1_MCLK		0x11>,
448			<MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK	0x1c>,
449			<MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0	0x1c>,
450			<MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC	0x1c>,
451
452			<MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK	0x1c>,
453			<MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0	0x14>,
454			<MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC	0x14>;
455	};
456
457	pinctrl_uart3: uart3grp {
458		fsl,pins =
459			<MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX	0x7e>,
460			<MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX	0x76>,
461			<MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS	0x76>,
462			<MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS	0x7e>;
463	};
464
465	pinctrl_uart4: uart4grp {
466		fsl,pins =
467			<MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX	0x7e>,
468			<MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX	0x76>,
469			<MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS	0x76>,
470			<MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS	0x7e>;
471	};
472
473	pinctrl_uart5: uart5grp {
474		fsl,pins =
475			<MX7D_PAD_I2C4_SCL__UART5_DCE_RX	0x7e>,
476			<MX7D_PAD_I2C4_SDA__UART5_DCE_TX	0x76>;
477	};
478
479	pinctrl_uart6: uart6grp {
480		fsl,pins =
481			<MX7D_PAD_EPDC_DATA08__UART6_DCE_RX	0x7d>,
482			<MX7D_PAD_EPDC_DATA09__UART6_DCE_TX	0x75>,
483			<MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS	0x75>,
484			<MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS	0x7d>;
485	};
486
487	pinctrl_uart7: uart7grp {
488		fsl,pins =
489			<MX7D_PAD_EPDC_DATA12__UART7_DCE_RX	0x7e>,
490			<MX7D_PAD_EPDC_DATA13__UART7_DCE_TX	0x76>,
491			<MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS	0x76>,
492			/* Limitation: RTS is not connected */
493			<MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS	0x7e>;
494	};
495
496	pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
497		fsl,pins =
498			/* WP */
499			<MX7D_PAD_SD1_WP__GPIO5_IO1		0x7c>,
500			/* CD */
501			<MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x7c>,
502			/* VSELECT */
503			<MX7D_PAD_GPIO1_IO08__SD1_VSELECT	0x59>;
504	};
505
506	pinctrl_usdhc1: usdhc1grp {
507		fsl,pins =
508			<MX7D_PAD_SD1_CMD__SD1_CMD		0x5e>,
509			<MX7D_PAD_SD1_CLK__SD1_CLK		0x57>,
510			<MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5e>,
511			<MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5e>,
512			<MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5e>,
513			<MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5e>;
514	};
515
516	pinctrl_usdhc1_100mhz: usdhc1_100mhzgrp {
517		fsl,pins =
518			<MX7D_PAD_SD1_CMD__SD1_CMD		0x5a>,
519			<MX7D_PAD_SD1_CLK__SD1_CLK		0x57>,
520			<MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5a>,
521			<MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5a>,
522			<MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5a>,
523			<MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5a>;
524	};
525
526	pinctrl_usdhc1_200mhz: usdhc1_200mhzgrp {
527		fsl,pins =
528			<MX7D_PAD_SD1_CMD__SD1_CMD		0x5b>,
529			<MX7D_PAD_SD1_CLK__SD1_CLK		0x57>,
530			<MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5b>,
531			<MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5b>,
532			<MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5b>,
533			<MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5b>;
534	};
535};
536
537&iomuxc_lpsr {
538	pinctrl_pwm1: pwm1grp {
539		fsl,pins =
540			/* LCD_CONTRAST */
541			<MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT	0x50>;
542	};
543
544	pinctrl_usbotg1: usbotg1grp {
545		fsl,pins =
546			<MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC	0x5c>,
547			<MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5	0x59>;
548	};
549
550	pinctrl_wdog1: wdog1grp {
551		fsl,pins =
552			<MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B	0x30>;
553	};
554};
555
556&pwm1 {
557	pinctrl-names = "default";
558	pinctrl-0 = <&pinctrl_pwm1>;
559	status = "okay";
560};
561
562&sai1 {
563	pinctrl-names = "default";
564	pinctrl-0 = <&pinctrl_sai1>;
565	assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
566			  <&clks IMX7D_SAI1_ROOT_CLK>;
567	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
568	assigned-clock-rates = <0>, <36864000>;
569	status = "okay";
570};
571
572&snvs_pwrkey {
573	status = "okay";
574};
575
576&uart3 {
577	pinctrl-names = "default";
578	pinctrl-0 = <&pinctrl_uart3>;
579	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
580	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
581	status = "okay";
582};
583
584&uart4 {
585	pinctrl-names = "default";
586	pinctrl-0 = <&pinctrl_uart4>;
587	assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
588	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
589	status = "okay";
590};
591
592&uart5 {
593	pinctrl-names = "default";
594	pinctrl-0 = <&pinctrl_uart5>;
595	assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
596	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
597	status = "okay";
598};
599
600&uart6 {
601	pinctrl-names = "default";
602	pinctrl-0 = <&pinctrl_uart6>;
603	assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
604	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
605	status = "okay";
606};
607
608&uart7 {
609	pinctrl-names = "default";
610	pinctrl-0 = <&pinctrl_uart7>;
611	assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
612	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
613	uart-has-rtscts;
614	linux,rs485-enabled-at-boot-time;
615	rs485-rts-active-low;
616	rs485-rx-during-tx;
617	status = "okay";
618};
619
620&usbh {
621	disable-over-current;
622	status = "okay";
623};
624
625&usbotg1 {
626	pinctrl-names = "default";
627	pinctrl-0 = <&pinctrl_usbotg1>;
628	vbus-supply = <&reg_usb_otg1_vbus>;
629	srp-disable;
630	hnp-disable;
631	adp-disable;
632	over-current-active-low;
633	dr_mode = "otg";
634	status = "okay";
635};
636
637&usdhc1 {
638	pinctrl-names = "default", "state_100mhz", "state_200mhz";
639	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
640	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
641	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
642	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
643	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
644	vmmc-supply = <&reg_mba_3v3>;
645	bus-width = <4>;
646	no-1-8-v;
647	no-sdio;
648	no-mmc;
649	status = "okay";
650};
651
652&wdog1 {
653	pinctrl-names = "default";
654	pinctrl-0 = <&pinctrl_wdog1>;
655	fsl,ext-reset-output;
656};
657