1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 *  sama7d65.dtsi - Device Tree Include file for SAMA7D65 SoC
4 *
5 *  Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
6 *
7 *  Author: Ryan Wanner <[email protected]>
8 *
9 */
10
11#include <dt-bindings/clock/at91.h>
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/mfd/at91-usart.h>
16
17/ {
18	model = "Microchip SAMA7D65 family SoC";
19	compatible = "microchip,sama7d65";
20	#address-cells = <1>;
21	#size-cells = <1>;
22	interrupt-parent = <&gic>;
23
24	cpus {
25		#address-cells = <1>;
26		#size-cells = <0>;
27
28		cpu0: cpu@0 {
29			compatible = "arm,cortex-a7";
30			reg = <0x0>;
31			device_type = "cpu";
32			clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
33			clock-names = "cpu";
34		};
35	};
36
37	clocks {
38		main_xtal: clock-mainxtal {
39			compatible = "fixed-clock";
40			#clock-cells = <0>;
41		};
42
43		slow_xtal: clock-slowxtal {
44			compatible = "fixed-clock";
45			#clock-cells = <0>;
46		};
47	};
48
49	soc {
50		compatible = "simple-bus";
51		ranges;
52		#address-cells = <1>;
53		#size-cells = <1>;
54
55		pioa: pinctrl@e0014000 {
56			compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl";
57			reg = <0xe0014000 0x800>;
58			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
59				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
60				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
61				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
62				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
63			clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
64			interrupt-controller;
65			#interrupt-cells = <2>;
66			gpio-controller;
67			#gpio-cells = <2>;
68		};
69
70		pmc: clock-controller@e0018000 {
71			compatible = "microchip,sama7d65-pmc", "syscon";
72			reg = <0xe0018000 0x200>;
73			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
74			#clock-cells = <2>;
75			clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
76			clock-names = "td_slck", "md_slck", "main_xtal";
77		};
78
79		clk32k: clock-controller@e001d500 {
80			compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc";
81			reg = <0xe001d500 0x4>;
82			clocks = <&slow_xtal>;
83			#clock-cells = <1>;
84		};
85
86		sdmmc1: mmc@e1208000 {
87			compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci";
88			reg = <0xe1208000 0x400>;
89			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
90			clocks = <&pmc PMC_TYPE_PERIPHERAL 76>, <&pmc PMC_TYPE_GCK 76>;
91			clock-names = "hclock", "multclk";
92			assigned-clocks = <&pmc PMC_TYPE_GCK 76>;
93			assigned-clock-rates = <200000000>;
94			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK1>;
95			status = "disabled";
96		};
97
98		pit64b0: timer@e1800000 {
99			compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b";
100			reg = <0xe1800000 0x100>;
101			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
102			clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>;
103			clock-names = "pclk", "gclk";
104		};
105
106		pit64b1: timer@e1804000 {
107			compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b";
108			reg = <0xe1804000 0x100>;
109			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
110			clocks = <&pmc PMC_TYPE_PERIPHERAL 67>, <&pmc PMC_TYPE_GCK 67>;
111			clock-names = "pclk", "gclk";
112		};
113
114		flx6: flexcom@e2020000 {
115			compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom";
116			reg = <0xe2020000 0x200>;
117			ranges = <0x0 0xe2020000 0x800>;
118			#address-cells = <1>;
119			#size-cells = <1>;
120			clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
121			status = "disabled";
122
123			uart6: serial@200 {
124				compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart";
125				reg = <0x200 0x200>;
126				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
127				clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
128				clock-names = "usart";
129				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
130				atmel,fifo-size = <16>;
131				status = "disabled";
132			};
133		};
134
135		gic: interrupt-controller@e8c11000 {
136			compatible = "arm,cortex-a7-gic";
137			reg = <0xe8c11000 0x1000>,
138			      <0xe8c12000 0x2000>;
139			#interrupt-cells = <3>;
140			#address-cells = <0>;
141			interrupt-controller;
142		};
143	};
144};
145