1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ARM Ltd. Versatile Express
4 *
5 * CoreTile Express A5x2
6 * Cortex-A5 MPCore (V2P-CA5s)
7 *
8 * HBI-0225B
9 */
10
11/dts-v1/;
12#include "vexpress-v2m-rs1.dtsi"
13
14/ {
15	model = "V2P-CA5s";
16	arm,hbi = <0x225>;
17	arm,vexpress,site = <0xf>;
18	compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
19	interrupt-parent = <&gic>;
20	#address-cells = <1>;
21	#size-cells = <1>;
22
23	chosen { };
24
25	aliases {
26		serial0 = &v2m_serial0;
27		serial1 = &v2m_serial1;
28		serial2 = &v2m_serial2;
29		serial3 = &v2m_serial3;
30		i2c0 = &v2m_i2c_dvi;
31		i2c1 = &v2m_i2c_pcie;
32	};
33
34	cpus {
35		#address-cells = <1>;
36		#size-cells = <0>;
37
38		cpu@0 {
39			device_type = "cpu";
40			compatible = "arm,cortex-a5";
41			reg = <0>;
42			next-level-cache = <&L2>;
43		};
44
45		cpu@1 {
46			device_type = "cpu";
47			compatible = "arm,cortex-a5";
48			reg = <1>;
49			next-level-cache = <&L2>;
50		};
51	};
52
53	memory@80000000 {
54		device_type = "memory";
55		reg = <0x80000000 0x40000000>;
56	};
57
58	reserved-memory {
59		#address-cells = <1>;
60		#size-cells = <1>;
61		ranges;
62
63		/* Chipselect 2 is physically at 0x18000000 */
64		vram: vram@18000000 {
65			/* 8 MB of designated video RAM */
66			compatible = "shared-dma-pool";
67			reg = <0x18000000 0x00800000>;
68			no-map;
69		};
70	};
71
72	hdlcd@2a110000 {
73		compatible = "arm,hdlcd";
74		reg = <0x2a110000 0x1000>;
75		interrupts = <0 85 4>;
76		clocks = <&hdlcd_clk>;
77		clock-names = "pxlclk";
78	};
79
80	memory-controller@2a150000 {
81		compatible = "arm,pl341", "arm,primecell";
82		reg = <0x2a150000 0x1000>;
83		clocks = <&axi_clk>;
84		clock-names = "apb_pclk";
85	};
86
87	memory-controller@2a190000 {
88		compatible = "arm,pl354", "arm,primecell";
89		reg = <0x2a190000 0x1000>;
90		interrupts = <0 86 4>,
91			     <0 87 4>;
92		clocks = <&axi_clk>;
93		clock-names = "apb_pclk";
94	};
95
96	scu@2c000000 {
97		compatible = "arm,cortex-a5-scu";
98		reg = <0x2c000000 0x58>;
99	};
100
101	timer@2c000600 {
102		compatible = "arm,cortex-a5-twd-timer";
103		reg = <0x2c000600 0x20>;
104		interrupts = <1 13 0x304>;
105	};
106
107	timer@2c000200 {
108		compatible = "arm,cortex-a5-global-timer",
109		             "arm,cortex-a9-global-timer";
110		reg = <0x2c000200 0x20>;
111		interrupts = <1 11 0x304>;
112		clocks = <&cpu_clk>;
113	};
114
115	watchdog@2c000620 {
116		compatible = "arm,cortex-a5-twd-wdt";
117		reg = <0x2c000620 0x20>;
118		interrupts = <1 14 0x304>;
119	};
120
121	gic: interrupt-controller@2c001000 {
122		compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
123		#interrupt-cells = <3>;
124		#address-cells = <0>;
125		interrupt-controller;
126		reg = <0x2c001000 0x1000>,
127		      <0x2c000100 0x100>;
128	};
129
130	L2: cache-controller@2c0f0000 {
131		compatible = "arm,pl310-cache";
132		reg = <0x2c0f0000 0x1000>;
133		interrupts = <0 84 4>;
134		cache-level = <2>;
135		cache-unified;
136	};
137
138	pmu {
139		compatible = "arm,cortex-a5-pmu";
140		interrupts = <0 68 4>,
141			     <0 69 4>;
142	};
143
144	dcc {
145		compatible = "arm,vexpress,config-bus";
146		arm,vexpress,config-bridge = <&v2m_sysreg>;
147
148		cpu_clk: clock-controller-0 {
149			/* CPU and internal AXI reference clock */
150			compatible = "arm,vexpress-osc";
151			arm,vexpress-sysreg,func = <1 0>;
152			freq-range = <50000000 100000000>;
153			#clock-cells = <0>;
154			clock-output-names = "oscclk0";
155		};
156
157		axi_clk: clock-controller-1 {
158			/* Multiplexed AXI master clock */
159			compatible = "arm,vexpress-osc";
160			arm,vexpress-sysreg,func = <1 1>;
161			freq-range = <5000000 50000000>;
162			#clock-cells = <0>;
163			clock-output-names = "oscclk1";
164		};
165
166		clock-controller-2 {
167			/* DDR2 */
168			compatible = "arm,vexpress-osc";
169			arm,vexpress-sysreg,func = <1 2>;
170			freq-range = <80000000 120000000>;
171			#clock-cells = <0>;
172			clock-output-names = "oscclk2";
173		};
174
175		hdlcd_clk: clock-controller-3 {
176			/* HDLCD */
177			compatible = "arm,vexpress-osc";
178			arm,vexpress-sysreg,func = <1 3>;
179			freq-range = <23750000 165000000>;
180			#clock-cells = <0>;
181			clock-output-names = "oscclk3";
182		};
183
184		clock-controller-4 {
185			/* Test chip gate configuration */
186			compatible = "arm,vexpress-osc";
187			arm,vexpress-sysreg,func = <1 4>;
188			freq-range = <80000000 80000000>;
189			#clock-cells = <0>;
190			clock-output-names = "oscclk4";
191		};
192
193		smbclk: clock-controller-5 {
194			/* SMB clock */
195			compatible = "arm,vexpress-osc";
196			arm,vexpress-sysreg,func = <1 5>;
197			freq-range = <25000000 60000000>;
198			#clock-cells = <0>;
199			clock-output-names = "oscclk5";
200		};
201
202		temp-dcc {
203			/* DCC internal operating temperature */
204			compatible = "arm,vexpress-temp";
205			arm,vexpress-sysreg,func = <4 0>;
206			label = "DCC";
207		};
208	};
209
210	smb: bus@8000000 {
211		ranges = <0 0x8000000 0x18000000>;
212	};
213
214	site2: hsb@40000000 {
215		compatible = "simple-bus";
216		#address-cells = <1>;
217		#size-cells = <1>;
218		ranges = <0 0x40000000 0x40000000>;
219		#interrupt-cells = <1>;
220		interrupt-map-mask = <0 3>;
221		interrupt-map = <0 0 &gic 0 36 4>,
222				<0 1 &gic 0 37 4>,
223				<0 2 &gic 0 38 4>,
224				<0 3 &gic 0 39 4>;
225	};
226};
227