1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * linux/arch/alpha/kernel/core_marvel.c
4 *
5 * Code common to all Marvel based systems.
6 */
7
8 #define __EXTERN_INLINE inline
9 #include <asm/io.h>
10 #include <asm/core_marvel.h>
11 #undef __EXTERN_INLINE
12
13 #include <linux/types.h>
14 #include <linux/pci.h>
15 #include <linux/sched.h>
16 #include <linux/init.h>
17 #include <linux/vmalloc.h>
18 #include <linux/mc146818rtc.h>
19 #include <linux/rtc.h>
20 #include <linux/module.h>
21 #include <linux/memblock.h>
22
23 #include <asm/ptrace.h>
24 #include <asm/smp.h>
25 #include <asm/gct.h>
26 #include <asm/tlbflush.h>
27 #include <asm/vga.h>
28
29 #include "proto.h"
30 #include "pci_impl.h"
31
32
33 /*
34 * Debug helpers
35 */
36 #define DEBUG_CONFIG 0
37
38 #if DEBUG_CONFIG
39 # define DBG_CFG(args) printk args
40 #else
41 # define DBG_CFG(args)
42 #endif
43
44
45 /*
46 * Private data
47 */
48 static struct io7 *io7_head = NULL;
49
50
51 /*
52 * Helper functions
53 */
54 static unsigned long __attribute__ ((unused))
read_ev7_csr(int pe,unsigned long offset)55 read_ev7_csr(int pe, unsigned long offset)
56 {
57 ev7_csr *ev7csr = EV7_CSR_KERN(pe, offset);
58 unsigned long q;
59
60 mb();
61 q = ev7csr->csr;
62 mb();
63
64 return q;
65 }
66
67 static void __attribute__ ((unused))
write_ev7_csr(int pe,unsigned long offset,unsigned long q)68 write_ev7_csr(int pe, unsigned long offset, unsigned long q)
69 {
70 ev7_csr *ev7csr = EV7_CSR_KERN(pe, offset);
71
72 mb();
73 ev7csr->csr = q;
74 mb();
75 }
76
77 static char * __init
mk_resource_name(int pe,int port,char * str)78 mk_resource_name(int pe, int port, char *str)
79 {
80 char tmp[80];
81 char *name;
82
83 sprintf(tmp, "PCI %s PE %d PORT %d", str, pe, port);
84 name = memblock_alloc_or_panic(strlen(tmp) + 1, SMP_CACHE_BYTES);
85 strcpy(name, tmp);
86
87 return name;
88 }
89
90 inline struct io7 *
marvel_next_io7(struct io7 * prev)91 marvel_next_io7(struct io7 *prev)
92 {
93 return (prev ? prev->next : io7_head);
94 }
95
96 struct io7 *
marvel_find_io7(int pe)97 marvel_find_io7(int pe)
98 {
99 struct io7 *io7;
100
101 for (io7 = io7_head; io7 && io7->pe != pe; io7 = io7->next)
102 continue;
103
104 return io7;
105 }
106
107 static struct io7 * __init
alloc_io7(unsigned int pe)108 alloc_io7(unsigned int pe)
109 {
110 struct io7 *io7;
111 struct io7 *insp;
112 int h;
113
114 if (marvel_find_io7(pe)) {
115 printk(KERN_WARNING "IO7 at PE %d already allocated!\n", pe);
116 return NULL;
117 }
118
119 io7 = memblock_alloc_or_panic(sizeof(*io7), SMP_CACHE_BYTES);
120 io7->pe = pe;
121 raw_spin_lock_init(&io7->irq_lock);
122
123 for (h = 0; h < 4; h++) {
124 io7->ports[h].io7 = io7;
125 io7->ports[h].port = h;
126 io7->ports[h].enabled = 0; /* default to disabled */
127 }
128
129 /*
130 * Insert in pe sorted order.
131 */
132 if (NULL == io7_head) /* empty list */
133 io7_head = io7;
134 else if (io7_head->pe > io7->pe) { /* insert at head */
135 io7->next = io7_head;
136 io7_head = io7;
137 } else { /* insert at position */
138 for (insp = io7_head; insp; insp = insp->next) {
139 if (insp->pe == io7->pe) {
140 printk(KERN_ERR "Too many IO7s at PE %d\n",
141 io7->pe);
142 return NULL;
143 }
144
145 if (NULL == insp->next ||
146 insp->next->pe > io7->pe) { /* insert here */
147 io7->next = insp->next;
148 insp->next = io7;
149 break;
150 }
151 }
152
153 if (NULL == insp) { /* couldn't insert ?!? */
154 printk(KERN_WARNING "Failed to insert IO7 at PE %d "
155 " - adding at head of list\n", io7->pe);
156 io7->next = io7_head;
157 io7_head = io7;
158 }
159 }
160
161 return io7;
162 }
163
164 void
io7_clear_errors(struct io7 * io7)165 io7_clear_errors(struct io7 *io7)
166 {
167 io7_port7_csrs *p7csrs;
168 io7_ioport_csrs *csrs;
169 int port;
170
171
172 /*
173 * First the IO ports.
174 */
175 for (port = 0; port < 4; port++) {
176 csrs = IO7_CSRS_KERN(io7->pe, port);
177
178 csrs->POx_ERR_SUM.csr = -1UL;
179 csrs->POx_TLB_ERR.csr = -1UL;
180 csrs->POx_SPL_COMPLT.csr = -1UL;
181 csrs->POx_TRANS_SUM.csr = -1UL;
182 }
183
184 /*
185 * Then the common ones.
186 */
187 p7csrs = IO7_PORT7_CSRS_KERN(io7->pe);
188
189 p7csrs->PO7_ERROR_SUM.csr = -1UL;
190 p7csrs->PO7_UNCRR_SYM.csr = -1UL;
191 p7csrs->PO7_CRRCT_SYM.csr = -1UL;
192 }
193
194
195 /*
196 * IO7 PCI, PCI/X, AGP configuration.
197 */
198 static void __init
io7_init_hose(struct io7 * io7,int port)199 io7_init_hose(struct io7 *io7, int port)
200 {
201 static int hose_index = 0;
202
203 struct pci_controller *hose = alloc_pci_controller();
204 struct io7_port *io7_port = &io7->ports[port];
205 io7_ioport_csrs *csrs = IO7_CSRS_KERN(io7->pe, port);
206 int i;
207
208 hose->index = hose_index++; /* arbitrary */
209
210 /*
211 * We don't have an isa or legacy hose, but glibc expects to be
212 * able to use the bus == 0 / dev == 0 form of the iobase syscall
213 * to determine information about the i/o system. Since XFree86
214 * relies on glibc's determination to tell whether or not to use
215 * sparse access, we need to point the pci_isa_hose at a real hose
216 * so at least that determination is correct.
217 */
218 if (hose->index == 0)
219 pci_isa_hose = hose;
220
221 io7_port->csrs = csrs;
222 io7_port->hose = hose;
223 hose->sysdata = io7_port;
224
225 hose->io_space = alloc_resource();
226 hose->mem_space = alloc_resource();
227
228 /*
229 * Base addresses for userland consumption. Since these are going
230 * to be mapped, they are pure physical addresses.
231 */
232 hose->sparse_mem_base = hose->sparse_io_base = 0;
233 hose->dense_mem_base = IO7_MEM_PHYS(io7->pe, port);
234 hose->dense_io_base = IO7_IO_PHYS(io7->pe, port);
235
236 /*
237 * Base addresses and resource ranges for kernel consumption.
238 */
239 hose->config_space_base = (unsigned long)IO7_CONF_KERN(io7->pe, port);
240
241 hose->io_space->start = (unsigned long)IO7_IO_KERN(io7->pe, port);
242 hose->io_space->end = hose->io_space->start + IO7_IO_SPACE - 1;
243 hose->io_space->name = mk_resource_name(io7->pe, port, "IO");
244 hose->io_space->flags = IORESOURCE_IO;
245
246 hose->mem_space->start = (unsigned long)IO7_MEM_KERN(io7->pe, port);
247 hose->mem_space->end = hose->mem_space->start + IO7_MEM_SPACE - 1;
248 hose->mem_space->name = mk_resource_name(io7->pe, port, "MEM");
249 hose->mem_space->flags = IORESOURCE_MEM;
250
251 if (request_resource(&ioport_resource, hose->io_space) < 0)
252 printk(KERN_ERR "Failed to request IO on hose %d\n",
253 hose->index);
254 if (request_resource(&iomem_resource, hose->mem_space) < 0)
255 printk(KERN_ERR "Failed to request MEM on hose %d\n",
256 hose->index);
257
258 /*
259 * Save the existing DMA window settings for later restoration.
260 */
261 for (i = 0; i < 4; i++) {
262 io7_port->saved_wbase[i] = csrs->POx_WBASE[i].csr;
263 io7_port->saved_wmask[i] = csrs->POx_WMASK[i].csr;
264 io7_port->saved_tbase[i] = csrs->POx_TBASE[i].csr;
265 }
266
267 /*
268 * Set up the PCI to main memory translation windows.
269 *
270 * Window 0 is scatter-gather 8MB at 8MB
271 * Window 1 is direct access 1GB at 2GB
272 * Window 2 is scatter-gather (up-to) 1GB at 3GB
273 * Window 3 is disabled
274 */
275
276 /*
277 * TBIA before modifying windows.
278 */
279 marvel_pci_tbi(hose, 0, -1);
280
281 /*
282 * Set up window 0 for scatter-gather 8MB at 8MB.
283 */
284 hose->sg_isa = iommu_arena_new_node(0, hose, 0x00800000, 0x00800000, 0);
285 hose->sg_isa->align_entry = 8; /* cache line boundary */
286 csrs->POx_WBASE[0].csr =
287 hose->sg_isa->dma_base | wbase_m_ena | wbase_m_sg;
288 csrs->POx_WMASK[0].csr = (hose->sg_isa->size - 1) & wbase_m_addr;
289 csrs->POx_TBASE[0].csr = virt_to_phys(hose->sg_isa->ptes);
290
291 /*
292 * Set up window 1 for direct-mapped 1GB at 2GB.
293 */
294 csrs->POx_WBASE[1].csr = __direct_map_base | wbase_m_ena;
295 csrs->POx_WMASK[1].csr = (__direct_map_size - 1) & wbase_m_addr;
296 csrs->POx_TBASE[1].csr = 0;
297
298 /*
299 * Set up window 2 for scatter-gather (up-to) 1GB at 3GB.
300 */
301 hose->sg_pci = iommu_arena_new_node(0, hose, 0xc0000000, 0x40000000, 0);
302 hose->sg_pci->align_entry = 8; /* cache line boundary */
303 csrs->POx_WBASE[2].csr =
304 hose->sg_pci->dma_base | wbase_m_ena | wbase_m_sg;
305 csrs->POx_WMASK[2].csr = (hose->sg_pci->size - 1) & wbase_m_addr;
306 csrs->POx_TBASE[2].csr = virt_to_phys(hose->sg_pci->ptes);
307
308 /*
309 * Disable window 3.
310 */
311 csrs->POx_WBASE[3].csr = 0;
312
313 /*
314 * Make sure that the AGP Monster Window is disabled.
315 */
316 csrs->POx_CTRL.csr &= ~(1UL << 61);
317
318 #if 1
319 printk("FIXME: disabling master aborts\n");
320 csrs->POx_MSK_HEI.csr &= ~(3UL << 14);
321 #endif
322 /*
323 * TBIA after modifying windows.
324 */
325 marvel_pci_tbi(hose, 0, -1);
326 }
327
328 static void __init
marvel_init_io7(struct io7 * io7)329 marvel_init_io7(struct io7 *io7)
330 {
331 int i;
332
333 printk("Initializing IO7 at PID %d\n", io7->pe);
334
335 /*
336 * Get the Port 7 CSR pointer.
337 */
338 io7->csrs = IO7_PORT7_CSRS_KERN(io7->pe);
339
340 /*
341 * Init this IO7's hoses.
342 */
343 for (i = 0; i < IO7_NUM_PORTS; i++) {
344 io7_ioport_csrs *csrs = IO7_CSRS_KERN(io7->pe, i);
345 if (csrs->POx_CACHE_CTL.csr == 8) {
346 io7->ports[i].enabled = 1;
347 io7_init_hose(io7, i);
348 }
349 }
350 }
351
352 static void __init
marvel_io7_present(gct6_node * node)353 marvel_io7_present(gct6_node *node)
354 {
355 int pe;
356
357 if (node->type != GCT_TYPE_HOSE ||
358 node->subtype != GCT_SUBTYPE_IO_PORT_MODULE)
359 return;
360
361 pe = (node->id >> 8) & 0xff;
362 printk("Found an IO7 at PID %d\n", pe);
363
364 alloc_io7(pe);
365 }
366
367 static void __init
marvel_find_console_vga_hose(void)368 marvel_find_console_vga_hose(void)
369 {
370 #ifdef CONFIG_VGA_HOSE
371 u64 *pu64 = (u64 *)((u64)hwrpb + hwrpb->ctbt_offset);
372
373 if (pu64[7] == 3) { /* TERM_TYPE == graphics */
374 struct pci_controller *hose = NULL;
375 int h = (pu64[30] >> 24) & 0xff; /* TERM_OUT_LOC, hose # */
376 struct io7 *io7;
377 int pid, port;
378
379 /* FIXME - encoding is going to have to change for Marvel
380 * since hose will be able to overflow a byte...
381 * need to fix this decode when the console
382 * changes its encoding
383 */
384 printk("console graphics is on hose %d (console)\n", h);
385
386 /*
387 * The console's hose numbering is:
388 *
389 * hose<n:2>: PID
390 * hose<1:0>: PORT
391 *
392 * We need to find the hose at that pid and port
393 */
394 pid = h >> 2;
395 port = h & 3;
396 if ((io7 = marvel_find_io7(pid)))
397 hose = io7->ports[port].hose;
398
399 if (hose) {
400 printk("Console graphics on hose %d\n", hose->index);
401 pci_vga_hose = hose;
402 }
403 }
404 #endif
405 }
406
407 gct6_search_struct gct_wanted_node_list[] __initdata = {
408 { GCT_TYPE_HOSE, GCT_SUBTYPE_IO_PORT_MODULE, marvel_io7_present },
409 { 0, 0, NULL }
410 };
411
412 /*
413 * In case the GCT is not complete, let the user specify PIDs with IO7s
414 * at boot time. Syntax is 'io7=a,b,c,...,n' where a-n are the PIDs (decimal)
415 * where IO7s are connected
416 */
417 static int __init
marvel_specify_io7(char * str)418 marvel_specify_io7(char *str)
419 {
420 unsigned long pid;
421 struct io7 *io7;
422 char *pchar;
423
424 do {
425 pid = simple_strtoul(str, &pchar, 0);
426 if (pchar != str) {
427 printk("User-specified IO7 at PID %lu\n", pid);
428 io7 = alloc_io7(pid);
429 if (io7) marvel_init_io7(io7);
430 }
431
432 if (pchar == str) pchar++;
433 str = pchar;
434 } while(*str);
435
436 return 1;
437 }
438 __setup("io7=", marvel_specify_io7);
439
440 void __init
marvel_init_arch(void)441 marvel_init_arch(void)
442 {
443 struct io7 *io7;
444
445 /* With multiple PCI busses, we play with I/O as physical addrs. */
446 ioport_resource.end = ~0UL;
447
448 /* PCI DMA Direct Mapping is 1GB at 2GB. */
449 __direct_map_base = 0x80000000;
450 __direct_map_size = 0x40000000;
451
452 /* Parse the config tree. */
453 gct6_find_nodes(GCT_NODE_PTR(0), gct_wanted_node_list);
454
455 /* Init the io7s. */
456 for (io7 = NULL; NULL != (io7 = marvel_next_io7(io7)); )
457 marvel_init_io7(io7);
458
459 /* Check for graphic console location (if any). */
460 marvel_find_console_vga_hose();
461 }
462
463 void
marvel_kill_arch(int mode)464 marvel_kill_arch(int mode)
465 {
466 }
467
468
469 /*
470 * PCI Configuration Space access functions
471 *
472 * Configuration space addresses have the following format:
473 *
474 * |2 2 2 2|1 1 1 1|1 1 1 1|1 1
475 * |3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
476 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
477 * |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|R|R|
478 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
479 *
480 * n:24 reserved for hose base
481 * 23:16 bus number (8 bits = 128 possible buses)
482 * 15:11 Device number (5 bits)
483 * 10:8 function number
484 * 7:2 register number
485 *
486 * Notes:
487 * IO7 determines whether to use a type 0 or type 1 config cycle
488 * based on the bus number. Therefore the bus number must be set
489 * to 0 for the root bus on any hose.
490 *
491 * The function number selects which function of a multi-function device
492 * (e.g., SCSI and Ethernet).
493 *
494 */
495
496 static inline unsigned long
build_conf_addr(struct pci_controller * hose,u8 bus,unsigned int devfn,int where)497 build_conf_addr(struct pci_controller *hose, u8 bus,
498 unsigned int devfn, int where)
499 {
500 return (hose->config_space_base | (bus << 16) | (devfn << 8) | where);
501 }
502
503 static unsigned long
mk_conf_addr(struct pci_bus * pbus,unsigned int devfn,int where)504 mk_conf_addr(struct pci_bus *pbus, unsigned int devfn, int where)
505 {
506 struct pci_controller *hose = pbus->sysdata;
507 struct io7_port *io7_port;
508 unsigned long addr = 0;
509 u8 bus = pbus->number;
510
511 if (!hose)
512 return addr;
513
514 /* Check for enabled. */
515 io7_port = hose->sysdata;
516 if (!io7_port->enabled)
517 return addr;
518
519 if (!pbus->parent) { /* No parent means peer PCI bus. */
520 /* Don't support idsel > 20 on primary bus. */
521 if (devfn >= PCI_DEVFN(21, 0))
522 return addr;
523 bus = 0;
524 }
525
526 addr = build_conf_addr(hose, bus, devfn, where);
527
528 DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
529 return addr;
530 }
531
532 static int
marvel_read_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * value)533 marvel_read_config(struct pci_bus *bus, unsigned int devfn, int where,
534 int size, u32 *value)
535 {
536 unsigned long addr;
537
538 if (0 == (addr = mk_conf_addr(bus, devfn, where)))
539 return PCIBIOS_DEVICE_NOT_FOUND;
540
541 switch(size) {
542 case 1:
543 *value = __kernel_ldbu(*(vucp)addr);
544 break;
545 case 2:
546 *value = __kernel_ldwu(*(vusp)addr);
547 break;
548 case 4:
549 *value = *(vuip)addr;
550 break;
551 default:
552 return PCIBIOS_FUNC_NOT_SUPPORTED;
553 }
554
555 return PCIBIOS_SUCCESSFUL;
556 }
557
558 static int
marvel_write_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 value)559 marvel_write_config(struct pci_bus *bus, unsigned int devfn, int where,
560 int size, u32 value)
561 {
562 unsigned long addr;
563
564 if (0 == (addr = mk_conf_addr(bus, devfn, where)))
565 return PCIBIOS_DEVICE_NOT_FOUND;
566
567 switch (size) {
568 case 1:
569 __kernel_stb(value, *(vucp)addr);
570 mb();
571 __kernel_ldbu(*(vucp)addr);
572 break;
573 case 2:
574 __kernel_stw(value, *(vusp)addr);
575 mb();
576 __kernel_ldwu(*(vusp)addr);
577 break;
578 case 4:
579 *(vuip)addr = value;
580 mb();
581 *(vuip)addr;
582 break;
583 default:
584 return PCIBIOS_FUNC_NOT_SUPPORTED;
585 }
586
587 return PCIBIOS_SUCCESSFUL;
588 }
589
590 struct pci_ops marvel_pci_ops =
591 {
592 .read = marvel_read_config,
593 .write = marvel_write_config,
594 };
595
596
597 /*
598 * Other PCI helper functions.
599 */
600 void
marvel_pci_tbi(struct pci_controller * hose,dma_addr_t start,dma_addr_t end)601 marvel_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
602 {
603 io7_ioport_csrs *csrs = ((struct io7_port *)hose->sysdata)->csrs;
604
605 wmb();
606 csrs->POx_SG_TBIA.csr = 0;
607 mb();
608 csrs->POx_SG_TBIA.csr;
609 }
610
611
612
613 /*
614 * RTC Support
615 */
616 struct marvel_rtc_access_info {
617 unsigned long function;
618 unsigned long index;
619 unsigned long data;
620 };
621
622 static void
__marvel_access_rtc(void * info)623 __marvel_access_rtc(void *info)
624 {
625 struct marvel_rtc_access_info *rtc_access = info;
626
627 register unsigned long __r0 __asm__("$0");
628 register unsigned long __r16 __asm__("$16") = rtc_access->function;
629 register unsigned long __r17 __asm__("$17") = rtc_access->index;
630 register unsigned long __r18 __asm__("$18") = rtc_access->data;
631
632 __asm__ __volatile__(
633 "call_pal %4 # cserve rtc"
634 : "=r"(__r16), "=r"(__r17), "=r"(__r18), "=r"(__r0)
635 : "i"(PAL_cserve), "0"(__r16), "1"(__r17), "2"(__r18)
636 : "$1", "$22", "$23", "$24", "$25");
637
638 rtc_access->data = __r0;
639 }
640
641 static u8
__marvel_rtc_io(u8 b,unsigned long addr,int write)642 __marvel_rtc_io(u8 b, unsigned long addr, int write)
643 {
644 static u8 index = 0;
645
646 struct marvel_rtc_access_info rtc_access;
647 u8 ret = 0;
648
649 switch(addr) {
650 case 0x70: /* RTC_PORT(0) */
651 if (write) index = b;
652 ret = index;
653 break;
654
655 case 0x71: /* RTC_PORT(1) */
656 rtc_access.index = index;
657 rtc_access.data = bcd2bin(b);
658 rtc_access.function = 0x48 + !write; /* GET/PUT_TOY */
659
660 __marvel_access_rtc(&rtc_access);
661
662 ret = bin2bcd(rtc_access.data);
663 break;
664
665 default:
666 printk(KERN_WARNING "Illegal RTC port %lx\n", addr);
667 break;
668 }
669
670 return ret;
671 }
672
673
674 /*
675 * IO map support.
676 */
677 void __iomem *
marvel_ioremap(unsigned long addr,unsigned long size)678 marvel_ioremap(unsigned long addr, unsigned long size)
679 {
680 struct pci_controller *hose;
681 unsigned long baddr, last;
682 struct vm_struct *area;
683 unsigned long vaddr;
684 unsigned long *ptes;
685 unsigned long pfn;
686
687 /*
688 * Adjust the address.
689 */
690 FIXUP_MEMADDR_VGA(addr);
691
692 /*
693 * Find the hose.
694 */
695 for (hose = hose_head; hose; hose = hose->next) {
696 if ((addr >> 32) == (hose->mem_space->start >> 32))
697 break;
698 }
699 if (!hose)
700 return NULL;
701
702 /*
703 * We have the hose - calculate the bus limits.
704 */
705 baddr = addr - hose->mem_space->start;
706 last = baddr + size - 1;
707
708 /*
709 * Is it direct-mapped?
710 */
711 if ((baddr >= __direct_map_base) &&
712 ((baddr + size - 1) < __direct_map_base + __direct_map_size)) {
713 addr = IDENT_ADDR | (baddr - __direct_map_base);
714 return (void __iomem *) addr;
715 }
716
717 /*
718 * Check the scatter-gather arena.
719 */
720 if (hose->sg_pci &&
721 baddr >= (unsigned long)hose->sg_pci->dma_base &&
722 last < (unsigned long)hose->sg_pci->dma_base + hose->sg_pci->size) {
723
724 /*
725 * Adjust the limits (mappings must be page aligned)
726 */
727 baddr -= hose->sg_pci->dma_base;
728 last -= hose->sg_pci->dma_base;
729 baddr &= PAGE_MASK;
730 size = PAGE_ALIGN(last) - baddr;
731
732 /*
733 * Map it.
734 */
735 area = get_vm_area(size, VM_IOREMAP);
736 if (!area)
737 return NULL;
738
739 ptes = hose->sg_pci->ptes;
740 for (vaddr = (unsigned long)area->addr;
741 baddr <= last;
742 baddr += PAGE_SIZE, vaddr += PAGE_SIZE) {
743 pfn = ptes[baddr >> PAGE_SHIFT];
744 if (!(pfn & 1)) {
745 printk("ioremap failed... pte not valid...\n");
746 vfree(area->addr);
747 return NULL;
748 }
749 pfn >>= 1; /* make it a true pfn */
750
751 if (__alpha_remap_area_pages(vaddr,
752 pfn << PAGE_SHIFT,
753 PAGE_SIZE, 0)) {
754 printk("FAILED to map...\n");
755 vfree(area->addr);
756 return NULL;
757 }
758 }
759
760 flush_tlb_all();
761
762 vaddr = (unsigned long)area->addr + (addr & ~PAGE_MASK);
763
764 return (void __iomem *) vaddr;
765 }
766
767 /* Assume it was already a reasonable address */
768 vaddr = baddr + hose->mem_space->start;
769 return (void __iomem *) vaddr;
770 }
771
772 void
marvel_iounmap(volatile void __iomem * xaddr)773 marvel_iounmap(volatile void __iomem *xaddr)
774 {
775 unsigned long addr = (unsigned long) xaddr;
776 if (addr >= VMALLOC_START)
777 vfree((void *)(PAGE_MASK & addr));
778 }
779
780 int
marvel_is_mmio(const volatile void __iomem * xaddr)781 marvel_is_mmio(const volatile void __iomem *xaddr)
782 {
783 unsigned long addr = (unsigned long) xaddr;
784
785 if (addr >= VMALLOC_START)
786 return 1;
787 else
788 return (addr & 0xFF000000UL) == 0;
789 }
790
791 #define __marvel_is_port_kbd(a) (((a) == 0x60) || ((a) == 0x64))
792 #define __marvel_is_port_rtc(a) (((a) == 0x70) || ((a) == 0x71))
793
marvel_ioportmap(unsigned long addr)794 void __iomem *marvel_ioportmap (unsigned long addr)
795 {
796 FIXUP_IOADDR_VGA(addr);
797 return (void __iomem *)addr;
798 }
799
800 u8
marvel_ioread8(const void __iomem * xaddr)801 marvel_ioread8(const void __iomem *xaddr)
802 {
803 unsigned long addr = (unsigned long) xaddr;
804 if (__marvel_is_port_kbd(addr))
805 return 0;
806 else if (__marvel_is_port_rtc(addr))
807 return __marvel_rtc_io(0, addr, 0);
808 else if (marvel_is_ioaddr(addr))
809 return __kernel_ldbu(*(vucp)addr);
810 else
811 /* this should catch other legacy addresses
812 that would normally fail on MARVEL,
813 because there really is nothing there...
814 */
815 return ~0;
816 }
817
818 void
marvel_iowrite8(u8 b,void __iomem * xaddr)819 marvel_iowrite8(u8 b, void __iomem *xaddr)
820 {
821 unsigned long addr = (unsigned long) xaddr;
822 if (__marvel_is_port_kbd(addr))
823 return;
824 else if (__marvel_is_port_rtc(addr))
825 __marvel_rtc_io(b, addr, 1);
826 else if (marvel_is_ioaddr(addr))
827 __kernel_stb(b, *(vucp)addr);
828 }
829
830 #ifndef CONFIG_ALPHA_GENERIC
831 EXPORT_SYMBOL(marvel_ioremap);
832 EXPORT_SYMBOL(marvel_iounmap);
833 EXPORT_SYMBOL(marvel_is_mmio);
834 EXPORT_SYMBOL(marvel_ioportmap);
835 EXPORT_SYMBOL(marvel_ioread8);
836 EXPORT_SYMBOL(marvel_iowrite8);
837 #endif
838
839 /*
840 * AGP GART Support.
841 */
842 #include <linux/agp_backend.h>
843 #include <asm/agp_backend.h>
844 #include <linux/slab.h>
845 #include <linux/delay.h>
846
847 struct marvel_agp_aperture {
848 struct pci_iommu_arena *arena;
849 long pg_start;
850 long pg_count;
851 };
852
853 static int
marvel_agp_setup(alpha_agp_info * agp)854 marvel_agp_setup(alpha_agp_info *agp)
855 {
856 struct marvel_agp_aperture *aper;
857
858 if (!alpha_agpgart_size)
859 return -ENOMEM;
860
861 aper = kmalloc(sizeof(*aper), GFP_KERNEL);
862 if (aper == NULL) return -ENOMEM;
863
864 aper->arena = agp->hose->sg_pci;
865 aper->pg_count = alpha_agpgart_size / PAGE_SIZE;
866 aper->pg_start = iommu_reserve(aper->arena, aper->pg_count,
867 aper->pg_count - 1);
868
869 if (aper->pg_start < 0) {
870 printk(KERN_ERR "Failed to reserve AGP memory\n");
871 kfree(aper);
872 return -ENOMEM;
873 }
874
875 agp->aperture.bus_base =
876 aper->arena->dma_base + aper->pg_start * PAGE_SIZE;
877 agp->aperture.size = aper->pg_count * PAGE_SIZE;
878 agp->aperture.sysdata = aper;
879
880 return 0;
881 }
882
883 static void
marvel_agp_cleanup(alpha_agp_info * agp)884 marvel_agp_cleanup(alpha_agp_info *agp)
885 {
886 struct marvel_agp_aperture *aper = agp->aperture.sysdata;
887 int status;
888
889 status = iommu_release(aper->arena, aper->pg_start, aper->pg_count);
890 if (status == -EBUSY) {
891 printk(KERN_WARNING
892 "Attempted to release bound AGP memory - unbinding\n");
893 iommu_unbind(aper->arena, aper->pg_start, aper->pg_count);
894 status = iommu_release(aper->arena, aper->pg_start,
895 aper->pg_count);
896 }
897 if (status < 0)
898 printk(KERN_ERR "Failed to release AGP memory\n");
899
900 kfree(aper);
901 kfree(agp);
902 }
903
904 static int
marvel_agp_configure(alpha_agp_info * agp)905 marvel_agp_configure(alpha_agp_info *agp)
906 {
907 io7_ioport_csrs *csrs = ((struct io7_port *)agp->hose->sysdata)->csrs;
908 struct io7 *io7 = ((struct io7_port *)agp->hose->sysdata)->io7;
909 unsigned int new_rate = 0;
910 unsigned long agp_pll;
911
912 /*
913 * Check the requested mode against the PLL setting.
914 * The agpgart_be code has not programmed the card yet,
915 * so we can still tweak mode here.
916 */
917 agp_pll = io7->csrs->POx_RST[IO7_AGP_PORT].csr;
918 switch(IO7_PLL_RNGB(agp_pll)) {
919 case 0x4: /* 2x only */
920 /*
921 * The PLL is only programmed for 2x, so adjust the
922 * rate to 2x, if necessary.
923 */
924 if (agp->mode.bits.rate != 2)
925 new_rate = 2;
926 break;
927
928 case 0x6: /* 1x / 4x */
929 /*
930 * The PLL is programmed for 1x or 4x. Don't go faster
931 * than requested, so if the requested rate is 2x, use 1x.
932 */
933 if (agp->mode.bits.rate == 2)
934 new_rate = 1;
935 break;
936
937 default: /* ??????? */
938 /*
939 * Don't know what this PLL setting is, take the requested
940 * rate, but warn the user.
941 */
942 printk("%s: unknown PLL setting RNGB=%lx (PLL6_CTL=%016lx)\n",
943 __func__, IO7_PLL_RNGB(agp_pll), agp_pll);
944 break;
945 }
946
947 /*
948 * Set the new rate, if necessary.
949 */
950 if (new_rate) {
951 printk("Requested AGP Rate %dX not compatible "
952 "with PLL setting - using %dX\n",
953 agp->mode.bits.rate,
954 new_rate);
955
956 agp->mode.bits.rate = new_rate;
957 }
958
959 printk("Enabling AGP on hose %d: %dX%s RQ %d\n",
960 agp->hose->index, agp->mode.bits.rate,
961 agp->mode.bits.sba ? " - SBA" : "", agp->mode.bits.rq);
962
963 csrs->AGP_CMD.csr = agp->mode.lw;
964
965 return 0;
966 }
967
968 static int
marvel_agp_bind_memory(alpha_agp_info * agp,off_t pg_start,struct agp_memory * mem)969 marvel_agp_bind_memory(alpha_agp_info *agp, off_t pg_start, struct agp_memory *mem)
970 {
971 struct marvel_agp_aperture *aper = agp->aperture.sysdata;
972 return iommu_bind(aper->arena, aper->pg_start + pg_start,
973 mem->page_count, mem->pages);
974 }
975
976 static int
marvel_agp_unbind_memory(alpha_agp_info * agp,off_t pg_start,struct agp_memory * mem)977 marvel_agp_unbind_memory(alpha_agp_info *agp, off_t pg_start, struct agp_memory *mem)
978 {
979 struct marvel_agp_aperture *aper = agp->aperture.sysdata;
980 return iommu_unbind(aper->arena, aper->pg_start + pg_start,
981 mem->page_count);
982 }
983
984 static unsigned long
marvel_agp_translate(alpha_agp_info * agp,dma_addr_t addr)985 marvel_agp_translate(alpha_agp_info *agp, dma_addr_t addr)
986 {
987 struct marvel_agp_aperture *aper = agp->aperture.sysdata;
988 unsigned long baddr = addr - aper->arena->dma_base;
989 unsigned long pte;
990
991 if (addr < agp->aperture.bus_base ||
992 addr >= agp->aperture.bus_base + agp->aperture.size) {
993 printk("%s: addr out of range\n", __func__);
994 return -EINVAL;
995 }
996
997 pte = aper->arena->ptes[baddr >> PAGE_SHIFT];
998 if (!(pte & 1)) {
999 printk("%s: pte not valid\n", __func__);
1000 return -EINVAL;
1001 }
1002 return (pte >> 1) << PAGE_SHIFT;
1003 }
1004
1005 struct alpha_agp_ops marvel_agp_ops =
1006 {
1007 .setup = marvel_agp_setup,
1008 .cleanup = marvel_agp_cleanup,
1009 .configure = marvel_agp_configure,
1010 .bind = marvel_agp_bind_memory,
1011 .unbind = marvel_agp_unbind_memory,
1012 .translate = marvel_agp_translate
1013 };
1014
1015 alpha_agp_info *
marvel_agp_info(void)1016 marvel_agp_info(void)
1017 {
1018 struct pci_controller *hose;
1019 io7_ioport_csrs *csrs;
1020 alpha_agp_info *agp;
1021 struct io7 *io7;
1022
1023 /*
1024 * Find the first IO7 with an AGP card.
1025 *
1026 * FIXME -- there should be a better way (we want to be able to
1027 * specify and what if the agp card is not video???)
1028 */
1029 hose = NULL;
1030 for (io7 = NULL; (io7 = marvel_next_io7(io7)) != NULL; ) {
1031 struct pci_controller *h;
1032 vuip addr;
1033
1034 if (!io7->ports[IO7_AGP_PORT].enabled)
1035 continue;
1036
1037 h = io7->ports[IO7_AGP_PORT].hose;
1038 addr = (vuip)build_conf_addr(h, 0, PCI_DEVFN(5, 0), 0);
1039
1040 if (*addr != 0xffffffffu) {
1041 hose = h;
1042 break;
1043 }
1044 }
1045
1046 if (!hose || !hose->sg_pci)
1047 return NULL;
1048
1049 printk("MARVEL - using hose %d as AGP\n", hose->index);
1050
1051 /*
1052 * Get the csrs from the hose.
1053 */
1054 csrs = ((struct io7_port *)hose->sysdata)->csrs;
1055
1056 /*
1057 * Allocate the info structure.
1058 */
1059 agp = kmalloc(sizeof(*agp), GFP_KERNEL);
1060 if (!agp)
1061 return NULL;
1062
1063 /*
1064 * Fill it in.
1065 */
1066 agp->hose = hose;
1067 agp->private = NULL;
1068 agp->ops = &marvel_agp_ops;
1069
1070 /*
1071 * Aperture - not configured until ops.setup().
1072 */
1073 agp->aperture.bus_base = 0;
1074 agp->aperture.size = 0;
1075 agp->aperture.sysdata = NULL;
1076
1077 /*
1078 * Capabilities.
1079 *
1080 * NOTE: IO7 reports through AGP_STAT that it can support a read queue
1081 * depth of 17 (rq = 0x10). It actually only supports a depth of
1082 * 16 (rq = 0xf).
1083 */
1084 agp->capability.lw = csrs->AGP_STAT.csr;
1085 agp->capability.bits.rq = 0xf;
1086
1087 /*
1088 * Mode.
1089 */
1090 agp->mode.lw = csrs->AGP_CMD.csr;
1091
1092 return agp;
1093 }
1094