1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/watchdog/qcom-wdt.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer
8
9maintainers:
10  - Rajendra Nayak <[email protected]>
11
12properties:
13  $nodename:
14    pattern: "^(watchdog|timer)@[0-9a-f]+$"
15
16  compatible:
17    oneOf:
18      - items:
19          - enum:
20              - qcom,kpss-wdt-ipq4019
21              - qcom,apss-wdt-ipq5018
22              - qcom,apss-wdt-ipq5332
23              - qcom,apss-wdt-ipq5424
24              - qcom,apss-wdt-ipq9574
25              - qcom,apss-wdt-msm8226
26              - qcom,apss-wdt-msm8974
27              - qcom,apss-wdt-msm8994
28              - qcom,apss-wdt-qcm2290
29              - qcom,apss-wdt-qcs404
30              - qcom,apss-wdt-qcs615
31              - qcom,apss-wdt-qcs8300
32              - qcom,apss-wdt-sa8255p
33              - qcom,apss-wdt-sa8775p
34              - qcom,apss-wdt-sc7180
35              - qcom,apss-wdt-sc7280
36              - qcom,apss-wdt-sc8180x
37              - qcom,apss-wdt-sc8280xp
38              - qcom,apss-wdt-sdm845
39              - qcom,apss-wdt-sdx55
40              - qcom,apss-wdt-sdx65
41              - qcom,apss-wdt-sm6115
42              - qcom,apss-wdt-sm6350
43              - qcom,apss-wdt-sm8150
44              - qcom,apss-wdt-sm8250
45          - const: qcom,kpss-wdt
46      - const: qcom,kpss-wdt
47        deprecated: true
48      - items:
49          - const: qcom,scss-timer
50          - const: qcom,msm-timer
51      - items:
52          - enum:
53              - qcom,kpss-wdt-apq8064
54              - qcom,kpss-wdt-ipq8064
55              - qcom,kpss-wdt-mdm9615
56              - qcom,kpss-wdt-msm8960
57          - const: qcom,kpss-timer
58          - const: qcom,msm-timer
59
60  reg:
61    maxItems: 1
62
63  clocks:
64    maxItems: 1
65
66  clock-names:
67    items:
68      - const: sleep
69
70  clock-frequency:
71    description:
72      The frequency of the general purpose timer in Hz.
73
74  cpu-offset:
75    $ref: /schemas/types.yaml#/definitions/uint32
76    description:
77      Per-CPU offset used when the timer is accessed without the CPU remapping
78      facilities. The offset is cpu-offset + (0x10000 * cpu-nr).
79
80  interrupts:
81    minItems: 1
82    maxItems: 5
83
84required:
85  - compatible
86  - reg
87  - clocks
88
89allOf:
90  - $ref: watchdog.yaml#
91
92  - if:
93      properties:
94        compatible:
95          contains:
96            const: qcom,kpss-wdt
97    then:
98      properties:
99        clock-frequency: false
100        cpu-offset: false
101        interrupts:
102          minItems: 1
103          items:
104            - description: Bark
105            - description: Bite
106
107    else:
108      properties:
109        interrupts:
110          minItems: 3
111          items:
112            - description: Debug
113            - description: First general purpose timer
114            - description: Second general purpose timer
115            - description: First watchdog
116            - description: Second watchdog
117      required:
118        - clock-frequency
119
120unevaluatedProperties: false
121
122examples:
123  - |
124    #include <dt-bindings/interrupt-controller/arm-gic.h>
125
126    watchdog@17c10000 {
127        compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
128        reg = <0x17c10000 0x1000>;
129        clocks = <&sleep_clk>;
130        interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
131        timeout-sec = <10>;
132    };
133
134  - |
135    #include <dt-bindings/interrupt-controller/arm-gic.h>
136
137    watchdog@200a000 {
138        compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", "qcom,msm-timer";
139        interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
140                     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
141                     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
142                     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
143                     <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
144        reg = <0x0200a000 0x100>;
145        clock-frequency = <25000000>;
146        clocks = <&sleep_clk>;
147        clock-names = "sleep";
148        cpu-offset = <0x80000>;
149    };
150