1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Universal Flash Storage (UFS) Controller
8
9maintainers:
10  - Bjorn Andersson <[email protected]>
11  - Andy Gross <[email protected]>
12
13# Select only our matches, not all jedec,ufs-2.0
14select:
15  properties:
16    compatible:
17      contains:
18        const: qcom,ufshc
19  required:
20    - compatible
21
22properties:
23  compatible:
24    items:
25      - enum:
26          - qcom,msm8994-ufshc
27          - qcom,msm8996-ufshc
28          - qcom,msm8998-ufshc
29          - qcom,qcs615-ufshc
30          - qcom,qcs8300-ufshc
31          - qcom,sa8775p-ufshc
32          - qcom,sc7180-ufshc
33          - qcom,sc7280-ufshc
34          - qcom,sc8180x-ufshc
35          - qcom,sc8280xp-ufshc
36          - qcom,sdm845-ufshc
37          - qcom,sm6115-ufshc
38          - qcom,sm6125-ufshc
39          - qcom,sm6350-ufshc
40          - qcom,sm8150-ufshc
41          - qcom,sm8250-ufshc
42          - qcom,sm8350-ufshc
43          - qcom,sm8450-ufshc
44          - qcom,sm8550-ufshc
45          - qcom,sm8650-ufshc
46      - const: qcom,ufshc
47      - const: jedec,ufs-2.0
48
49  clocks:
50    minItems: 7
51    maxItems: 9
52
53  clock-names:
54    minItems: 7
55    maxItems: 9
56
57  dma-coherent: true
58
59  interconnects:
60    minItems: 2
61    maxItems: 2
62
63  interconnect-names:
64    items:
65      - const: ufs-ddr
66      - const: cpu-ufs
67
68  iommus:
69    minItems: 1
70    maxItems: 2
71
72  phys:
73    maxItems: 1
74
75  phy-names:
76    items:
77      - const: ufsphy
78
79  power-domains:
80    maxItems: 1
81
82  qcom,ice:
83    $ref: /schemas/types.yaml#/definitions/phandle
84    description: phandle to the Inline Crypto Engine node
85
86  reg:
87    minItems: 1
88    maxItems: 2
89
90  reg-names:
91    items:
92      - const: std
93      - const: ice
94
95  required-opps:
96    maxItems: 1
97
98  resets:
99    maxItems: 1
100
101  '#reset-cells':
102    const: 1
103
104  reset-names:
105    items:
106      - const: rst
107
108  reset-gpios:
109    maxItems: 1
110    description:
111      GPIO connected to the RESET pin of the UFS memory device.
112
113required:
114  - compatible
115  - reg
116
117allOf:
118  - $ref: ufs-common.yaml
119
120  - if:
121      properties:
122        compatible:
123          contains:
124            enum:
125              - qcom,sc7180-ufshc
126    then:
127      properties:
128        clocks:
129          minItems: 7
130          maxItems: 7
131        clock-names:
132          items:
133            - const: core_clk
134            - const: bus_aggr_clk
135            - const: iface_clk
136            - const: core_clk_unipro
137            - const: ref_clk
138            - const: tx_lane0_sync_clk
139            - const: rx_lane0_sync_clk
140        reg:
141          maxItems: 1
142        reg-names:
143          maxItems: 1
144
145  - if:
146      properties:
147        compatible:
148          contains:
149            enum:
150              - qcom,msm8998-ufshc
151              - qcom,qcs8300-ufshc
152              - qcom,sa8775p-ufshc
153              - qcom,sc7280-ufshc
154              - qcom,sc8180x-ufshc
155              - qcom,sc8280xp-ufshc
156              - qcom,sm8250-ufshc
157              - qcom,sm8350-ufshc
158              - qcom,sm8450-ufshc
159              - qcom,sm8550-ufshc
160              - qcom,sm8650-ufshc
161    then:
162      properties:
163        clocks:
164          minItems: 8
165          maxItems: 8
166        clock-names:
167          items:
168            - const: core_clk
169            - const: bus_aggr_clk
170            - const: iface_clk
171            - const: core_clk_unipro
172            - const: ref_clk
173            - const: tx_lane0_sync_clk
174            - const: rx_lane0_sync_clk
175            - const: rx_lane1_sync_clk
176        reg:
177          minItems: 1
178          maxItems: 1
179        reg-names:
180          maxItems: 1
181
182  - if:
183      properties:
184        compatible:
185          contains:
186            enum:
187              - qcom,sdm845-ufshc
188              - qcom,sm6350-ufshc
189              - qcom,sm8150-ufshc
190    then:
191      properties:
192        clocks:
193          minItems: 9
194          maxItems: 9
195        clock-names:
196          items:
197            - const: core_clk
198            - const: bus_aggr_clk
199            - const: iface_clk
200            - const: core_clk_unipro
201            - const: ref_clk
202            - const: tx_lane0_sync_clk
203            - const: rx_lane0_sync_clk
204            - const: rx_lane1_sync_clk
205            - const: ice_core_clk
206        reg:
207          minItems: 2
208          maxItems: 2
209        reg-names:
210          minItems: 2
211      required:
212        - reg-names
213
214  - if:
215      properties:
216        compatible:
217          contains:
218            enum:
219              - qcom,msm8996-ufshc
220    then:
221      properties:
222        clocks:
223          minItems: 9
224          maxItems: 9
225        clock-names:
226          items:
227            - const: core_clk
228            - const: bus_clk
229            - const: bus_aggr_clk
230            - const: iface_clk
231            - const: core_clk_unipro
232            - const: core_clk_ice
233            - const: ref_clk
234            - const: tx_lane0_sync_clk
235            - const: rx_lane0_sync_clk
236        reg:
237          minItems: 1
238          maxItems: 1
239        reg-names:
240          maxItems: 1
241
242  - if:
243      properties:
244        compatible:
245          contains:
246            enum:
247              - qcom,qcs615-ufshc
248              - qcom,sm6115-ufshc
249              - qcom,sm6125-ufshc
250    then:
251      properties:
252        clocks:
253          minItems: 8
254          maxItems: 8
255        clock-names:
256          items:
257            - const: core_clk
258            - const: bus_aggr_clk
259            - const: iface_clk
260            - const: core_clk_unipro
261            - const: ref_clk
262            - const: tx_lane0_sync_clk
263            - const: rx_lane0_sync_clk
264            - const: ice_core_clk
265        reg:
266          minItems: 2
267          maxItems: 2
268        reg-names:
269          minItems: 2
270      required:
271        - reg-names
272
273    # TODO: define clock bindings for qcom,msm8994-ufshc
274
275  - if:
276      required:
277        - qcom,ice
278    then:
279      properties:
280        reg:
281          maxItems: 1
282        clocks:
283          minItems: 7
284          maxItems: 8
285    else:
286      properties:
287        reg:
288          minItems: 1
289          maxItems: 2
290        clocks:
291          minItems: 7
292          maxItems: 9
293
294unevaluatedProperties: false
295
296examples:
297  - |
298    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
299    #include <dt-bindings/clock/qcom,rpmh.h>
300    #include <dt-bindings/gpio/gpio.h>
301    #include <dt-bindings/interconnect/qcom,sm8450.h>
302    #include <dt-bindings/interrupt-controller/arm-gic.h>
303
304    soc {
305        #address-cells = <2>;
306        #size-cells = <2>;
307
308        ufs@1d84000 {
309            compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
310                         "jedec,ufs-2.0";
311            reg = <0 0x01d84000 0 0x3000>;
312            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
313            phys = <&ufs_mem_phy_lanes>;
314            phy-names = "ufsphy";
315            lanes-per-direction = <2>;
316            #reset-cells = <1>;
317            resets = <&gcc GCC_UFS_PHY_BCR>;
318            reset-names = "rst";
319            reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
320
321            vcc-supply = <&vreg_l7b_2p5>;
322            vcc-max-microamp = <1100000>;
323            vccq-supply = <&vreg_l9b_1p2>;
324            vccq-max-microamp = <1200000>;
325
326            power-domains = <&gcc UFS_PHY_GDSC>;
327            iommus = <&apps_smmu 0xe0 0x0>;
328            interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
329                            <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
330            interconnect-names = "ufs-ddr", "cpu-ufs";
331
332            clock-names = "core_clk",
333                          "bus_aggr_clk",
334                          "iface_clk",
335                          "core_clk_unipro",
336                          "ref_clk",
337                          "tx_lane0_sync_clk",
338                          "rx_lane0_sync_clk",
339                          "rx_lane1_sync_clk";
340            clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
341                     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
342                     <&gcc GCC_UFS_PHY_AHB_CLK>,
343                     <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
344                     <&rpmhcc RPMH_CXO_CLK>,
345                     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
346                     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
347                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
348            freq-table-hz = <75000000 300000000>,
349                            <0 0>,
350                            <0 0>,
351                            <75000000 300000000>,
352                            <75000000 300000000>,
353                            <0 0>,
354                            <0 0>,
355                            <0 0>;
356            qcom,ice = <&ice>;
357        };
358    };
359