1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Cadence Quad SPI controller 8 9maintainers: 10 - Vaishnav Achath <[email protected]> 11 12allOf: 13 - $ref: spi-controller.yaml# 14 - if: 15 properties: 16 compatible: 17 contains: 18 const: xlnx,versal-ospi-1.0 19 then: 20 required: 21 - power-domains 22 - if: 23 properties: 24 compatible: 25 contains: 26 const: starfive,jh7110-qspi 27 then: 28 properties: 29 resets: 30 minItems: 2 31 maxItems: 3 32 33 reset-names: 34 minItems: 2 35 maxItems: 3 36 items: 37 enum: [ qspi, qspi-ocp, rstc_ref ] 38 39 else: 40 properties: 41 resets: 42 maxItems: 2 43 44 reset-names: 45 minItems: 1 46 maxItems: 2 47 items: 48 enum: [ qspi, qspi-ocp ] 49 - if: 50 properties: 51 compatible: 52 contains: 53 const: amd,pensando-elba-qspi 54 then: 55 properties: 56 cdns,fifo-depth: 57 enum: [ 128, 256, 1024 ] 58 default: 1024 59 else: 60 properties: 61 cdns,fifo-depth: 62 enum: [ 128, 256 ] 63 default: 128 64 65properties: 66 compatible: 67 oneOf: 68 - items: 69 - enum: 70 - amd,pensando-elba-qspi 71 - amd,versal2-ospi 72 - intel,lgm-qspi 73 - intel,socfpga-qspi 74 - mobileye,eyeq5-ospi 75 - starfive,jh7110-qspi 76 - ti,am654-ospi 77 - ti,k2g-qspi 78 - xlnx,versal-ospi-1.0 79 - const: cdns,qspi-nor 80 - const: cdns,qspi-nor 81 82 reg: 83 items: 84 - description: the controller register set 85 - description: the controller data area 86 87 interrupts: 88 maxItems: 1 89 90 clocks: 91 minItems: 1 92 maxItems: 3 93 94 clock-names: 95 oneOf: 96 - items: 97 - const: ref 98 - items: 99 - const: ref 100 - const: ahb 101 - const: apb 102 103 cdns,fifo-depth: 104 description: 105 Size of the data FIFO in words. 106 $ref: /schemas/types.yaml#/definitions/uint32 107 108 cdns,fifo-width: 109 $ref: /schemas/types.yaml#/definitions/uint32 110 description: 111 Bus width of the data FIFO in bytes. 112 default: 4 113 114 cdns,trigger-address: 115 $ref: /schemas/types.yaml#/definitions/uint32 116 description: 117 32-bit indirect AHB trigger address. 118 119 cdns,is-decoded-cs: 120 type: boolean 121 description: 122 Flag to indicate whether decoder is used to select different chip select 123 for different memory regions. 124 125 cdns,rclk-en: 126 type: boolean 127 description: 128 Flag to indicate that QSPI return clock is used to latch the read 129 data rather than the QSPI clock. Make sure that QSPI return clock 130 is populated on the board before using this property. 131 132 power-domains: 133 maxItems: 1 134 135 resets: 136 minItems: 2 137 maxItems: 3 138 139 reset-names: 140 minItems: 2 141 maxItems: 3 142 items: 143 enum: [ qspi, qspi-ocp, rstc_ref ] 144 145required: 146 - compatible 147 - reg 148 - interrupts 149 - clocks 150 - cdns,fifo-width 151 - cdns,trigger-address 152 - '#address-cells' 153 - '#size-cells' 154 155unevaluatedProperties: false 156 157examples: 158 - | 159 qspi: spi@ff705000 { 160 compatible = "cdns,qspi-nor"; 161 #address-cells = <1>; 162 #size-cells = <0>; 163 reg = <0xff705000 0x1000>, 164 <0xffa00000 0x1000>; 165 interrupts = <0 151 4>; 166 clocks = <&qspi_clk>; 167 cdns,fifo-depth = <128>; 168 cdns,fifo-width = <4>; 169 cdns,trigger-address = <0x00000000>; 170 resets = <&rst 0x1>, <&rst 0x2>; 171 reset-names = "qspi", "qspi-ocp"; 172 173 flash@0 { 174 compatible = "jedec,spi-nor"; 175 reg = <0x0>; 176 }; 177 }; 178