1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/sound/fsl,mqs.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NXP Medium Quality Sound (MQS) 8 9maintainers: 10 - Shengjiu Wang <[email protected]> 11 - Chancel Liu <[email protected]> 12 13description: | 14 Medium quality sound (MQS) is used to generate medium quality audio 15 via a standard GPIO in the pinmux, allowing the user to connect 16 stereo speakers or headphones to a power amplifier without an 17 additional DAC chip. 18 19properties: 20 compatible: 21 enum: 22 - fsl,imx6sx-mqs 23 - fsl,imx8qm-mqs 24 - fsl,imx8qxp-mqs 25 - fsl,imx93-mqs 26 - fsl,imx943-aonmix-mqs 27 - fsl,imx943-wakeupmix-mqs 28 - fsl,imx95-aonmix-mqs 29 - fsl,imx95-netcmix-mqs 30 31 clocks: 32 minItems: 1 33 maxItems: 2 34 35 clock-names: 36 minItems: 1 37 maxItems: 2 38 39 gpr: 40 $ref: /schemas/types.yaml#/definitions/phandle 41 description: The phandle to the General Purpose Register (GPR) node 42 43 reg: 44 maxItems: 1 45 46 power-domains: 47 maxItems: 1 48 49 resets: 50 maxItems: 1 51 52required: 53 - compatible 54 - clocks 55 - clock-names 56 57allOf: 58 - if: 59 properties: 60 compatible: 61 contains: 62 enum: 63 - fsl,imx8qm-mqs 64 - fsl,imx8qxp-mqs 65 then: 66 properties: 67 clocks: 68 items: 69 - description: Master clock 70 - description: Clock for register access 71 clock-names: 72 items: 73 - const: mclk 74 - const: core 75 required: 76 - reg 77 - power-domains 78 else: 79 properties: 80 clocks: 81 items: 82 - description: Master clock 83 clock-names: 84 items: 85 - const: mclk 86 required: 87 - gpr 88 89additionalProperties: false 90 91examples: 92 - | 93 #include <dt-bindings/clock/imx6sx-clock.h> 94 mqs0: mqs { 95 compatible = "fsl,imx6sx-mqs"; 96 gpr = <&gpr>; 97 clocks = <&clks IMX6SX_CLK_SAI1>; 98 clock-names = "mclk"; 99 }; 100 101 - | 102 #include <dt-bindings/firmware/imx/rsrc.h> 103 mqs1: mqs@59850000 { 104 compatible = "fsl,imx8qm-mqs"; 105 reg = <0x59850000 0x10000>; 106 clocks = <&mqs0_lpcg 0>, <&mqs0_lpcg 1>; 107 clock-names = "mclk", "core"; 108 power-domains = <&pd IMX_SC_R_MQS_0>; 109 }; 110