1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/renesas,scif.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas Serial Communication Interface with FIFO (SCIF)
8
9maintainers:
10  - Geert Uytterhoeven <[email protected]>
11
12properties:
13  compatible:
14    oneOf:
15      - items:
16          - enum:
17              - renesas,scif-r7s72100     # RZ/A1H
18          - const: renesas,scif           # generic SCIF compatible UART
19
20      - items:
21          - enum:
22              - renesas,scif-r7s9210      # RZ/A2
23
24      - items:
25          - enum:
26              - renesas,scif-r8a7778      # R-Car M1
27              - renesas,scif-r8a7779      # R-Car H1
28          - const: renesas,rcar-gen1-scif # R-Car Gen1
29          - const: renesas,scif           # generic SCIF compatible UART
30
31      - items:
32          - enum:
33              - renesas,scif-r8a7742      # RZ/G1H
34              - renesas,scif-r8a7743      # RZ/G1M
35              - renesas,scif-r8a7744      # RZ/G1N
36              - renesas,scif-r8a7745      # RZ/G1E
37              - renesas,scif-r8a77470     # RZ/G1C
38              - renesas,scif-r8a7790      # R-Car H2
39              - renesas,scif-r8a7791      # R-Car M2-W
40              - renesas,scif-r8a7792      # R-Car V2H
41              - renesas,scif-r8a7793      # R-Car M2-N
42              - renesas,scif-r8a7794      # R-Car E2
43          - const: renesas,rcar-gen2-scif # R-Car Gen2 and RZ/G1
44          - const: renesas,scif           # generic SCIF compatible UART
45
46      - items:
47          - enum:
48              - renesas,scif-r8a774a1     # RZ/G2M
49              - renesas,scif-r8a774a3     # RZ/G2M v3.0
50              - renesas,scif-r8a774b1     # RZ/G2N
51              - renesas,scif-r8a774c0     # RZ/G2E
52              - renesas,scif-r8a774e1     # RZ/G2H
53              - renesas,scif-r8a7795      # R-Car H3
54              - renesas,scif-r8a7796      # R-Car M3-W
55              - renesas,scif-r8a77961     # R-Car M3-W+
56              - renesas,scif-r8a77965     # R-Car M3-N
57              - renesas,scif-r8a77970     # R-Car V3M
58              - renesas,scif-r8a77980     # R-Car V3H
59              - renesas,scif-r8a77990     # R-Car E3
60              - renesas,scif-r8a77995     # R-Car D3
61          - const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2
62          - const: renesas,scif           # generic SCIF compatible UART
63
64      - items:
65          - enum:
66              - renesas,scif-r8a779a0     # R-Car V3U
67              - renesas,scif-r8a779f0     # R-Car S4-8
68              - renesas,scif-r8a779g0     # R-Car V4H
69              - renesas,scif-r8a779h0     # R-Car V4M
70          - const: renesas,rcar-gen4-scif # R-Car Gen4
71          - const: renesas,scif           # generic SCIF compatible UART
72
73      - items:
74          - enum:
75              - renesas,scif-r9a07g044      # RZ/G2{L,LC}
76
77      - items:
78          - enum:
79              - renesas,scif-r9a07g043      # RZ/G2UL and RZ/Five
80              - renesas,scif-r9a07g054      # RZ/V2L
81              - renesas,scif-r9a08g045      # RZ/G3S
82          - const: renesas,scif-r9a07g044   # RZ/G2{L,LC} fallback
83
84      - const: renesas,scif-r9a09g057       # RZ/V2H(P)
85
86      - items:
87          - enum:
88              - renesas,scif-r9a09g047      # RZ/G3E
89          - const: renesas,scif-r9a09g057   # RZ/V2H fallback
90
91  reg:
92    maxItems: 1
93
94  interrupts:
95    oneOf:
96      - items:
97          - description: A combined interrupt
98      - items:
99          - description: Error interrupt
100          - description: Receive buffer full interrupt
101          - description: Transmit buffer empty interrupt
102          - description: Break interrupt
103          - description: Data Ready interrupt
104          - description: Transmit End interrupt
105          - description: Transmit End/Data Ready interrupt
106          - description: Receive buffer full interrupt (EDGE trigger)
107          - description: Transmit buffer empty interrupt (EDGE trigger)
108        minItems: 4
109
110  interrupt-names:
111    minItems: 4
112    items:
113      - const: eri
114      - const: rxi
115      - const: txi
116      - const: bri
117      - const: dri
118      - const: tei
119      - const: tei-dri
120      - const: rxi-edge
121      - const: txi-edge
122
123  clocks:
124    minItems: 1
125    maxItems: 4
126
127  clock-names:
128    minItems: 1
129    maxItems: 4
130    items:
131      enum:
132        - fck # UART functional clock
133        - sck # optional external clock input
134        - brg_int # optional internal clock source for BRG frequency divider
135        - scif_clk # optional external clock source for BRG frequency divider
136
137  power-domains:
138    maxItems: 1
139
140  resets:
141    maxItems: 1
142
143  dmas:
144    minItems: 2
145    maxItems: 4
146    description:
147      Must contain a list of pairs of references to DMA specifiers, one for
148      transmission, and one for reception.
149
150  dma-names:
151    minItems: 2
152    maxItems: 4
153    items:
154      enum:
155        - tx
156        - rx
157
158required:
159  - compatible
160  - reg
161  - interrupts
162  - clocks
163  - clock-names
164  - power-domains
165
166allOf:
167  - $ref: serial.yaml#
168
169  - if:
170      properties:
171        compatible:
172          contains:
173            enum:
174              - renesas,rcar-gen2-scif
175              - renesas,rcar-gen3-scif
176              - renesas,rcar-gen4-scif
177              - renesas,scif-r9a07g044
178              - renesas,scif-r9a09g057
179    then:
180      required:
181        - resets
182
183  - if:
184      properties:
185        compatible:
186          contains:
187            enum:
188              - renesas,rcar-gen1-scif
189              - renesas,rcar-gen2-scif
190              - renesas,rcar-gen3-scif
191              - renesas,rcar-gen4-scif
192    then:
193      properties:
194        interrupts:
195          maxItems: 1
196
197        interrupt-names: false
198    else:
199      required:
200        - interrupt-names
201
202  - if:
203      properties:
204        compatible:
205          contains:
206            enum:
207              - renesas,scif-r7s72100
208    then:
209      properties:
210        interrupts:
211          minItems: 4
212          maxItems: 4
213
214        interrupt-names:
215          maxItems: 4
216
217  - if:
218      properties:
219        compatible:
220          contains:
221            enum:
222              - renesas,scif-r7s9210
223              - renesas,scif-r9a07g044
224    then:
225      properties:
226        interrupts:
227          minItems: 6
228          maxItems: 6
229
230        interrupt-names:
231          minItems: 6
232          maxItems: 6
233
234  - if:
235      properties:
236        compatible:
237          contains:
238            const: renesas,scif-r9a09g057
239    then:
240      properties:
241        clocks:
242          maxItems: 1
243
244        clock-names:
245          maxItems: 1
246
247        interrupts:
248          minItems: 9
249
250        interrupt-names:
251          minItems: 9
252
253unevaluatedProperties: false
254
255examples:
256  - |
257    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
258    #include <dt-bindings/interrupt-controller/arm-gic.h>
259    #include <dt-bindings/power/r8a7791-sysc.h>
260    aliases {
261        serial0 = &scif0;
262    };
263
264    scif0: serial@e6e60000 {
265        compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
266                     "renesas,scif";
267        reg = <0xe6e60000 64>;
268        interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
269        clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
270                 <&scif_clk>;
271        clock-names = "fck", "brg_int", "scif_clk";
272        dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>;
273        dma-names = "tx", "rx", "tx", "rx";
274        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
275        resets = <&cpg 721>;
276    };
277