1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mtd/nuvoton,ma35d1-nand.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Nuvoton MA35D1 NAND Flash Interface (NFI) Controller
8
9maintainers:
10  - Hui-Ping Chen <[email protected]>
11
12allOf:
13  - $ref: nand-controller.yaml#
14
15properties:
16  compatible:
17    enum:
18      - nuvoton,ma35d1-nand-controller
19
20  reg:
21    maxItems: 1
22
23  interrupts:
24    maxItems: 1
25
26  clocks:
27    maxItems: 1
28
29patternProperties:
30  "^nand@[a-f0-9]$":
31    type: object
32    $ref: raw-nand-chip.yaml
33    properties:
34      reg:
35        minimum: 0
36        maximum: 1
37
38      nand-ecc-step-size:
39        enum: [512, 1024]
40
41      nand-ecc-strength:
42        enum: [8, 12, 24]
43
44    required:
45      - reg
46
47    unevaluatedProperties: false
48
49required:
50  - compatible
51  - reg
52  - interrupts
53  - clocks
54
55unevaluatedProperties: false
56
57examples:
58  - |
59    #include <dt-bindings/interrupt-controller/arm-gic.h>
60    #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
61
62    soc {
63        #address-cells = <2>;
64        #size-cells = <2>;
65
66        nand-controller@401A0000 {
67            compatible = "nuvoton,ma35d1-nand-controller";
68            reg = <0x0 0x401A0000 0x0 0x1000>;
69            interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
70            clocks = <&clk NAND_GATE>;
71            #address-cells = <1>;
72            #size-cells = <0>;
73
74            nand@0 {
75                reg = <0>;
76                nand-on-flash-bbt;
77                nand-ecc-step-size = <512>;
78                nand-ecc-strength = <8>;
79
80                partitions {
81                    compatible = "fixed-partitions";
82                    #address-cells = <1>;
83                    #size-cells = <1>;
84
85                    uboot@0 {
86                        label = "nand-uboot";
87                        read-only;
88                        reg = <0x0 0x300000>;
89                    };
90                };
91            };
92        };
93    };
94
95...
96