1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/atmel,sama5d2-sdhci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Atmel SDHCI controller
8
9maintainers:
10  - Aubin Constans <[email protected]>
11  - Nicolas Ferre <[email protected]>
12
13description:
14  Bindings for the SDHCI controller found in Atmel/Microchip SoCs.
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - atmel,sama5d2-sdhci
21          - microchip,sam9x60-sdhci
22      - items:
23          - enum:
24              - microchip,sam9x7-sdhci
25              - microchip,sama7d65-sdhci
26              - microchip,sama7g5-sdhci
27          - const: microchip,sam9x60-sdhci
28
29  reg:
30    maxItems: 1
31
32  interrupts:
33    maxItems: 1
34
35  clocks:
36    items:
37      - description: hclock
38      - description: multclk
39      - description: baseclk
40    minItems: 2
41
42  clock-names:
43    items:
44      - const: hclock
45      - const: multclk
46      - const: baseclk
47    minItems: 2
48
49  microchip,sdcal-inverted:
50    type: boolean
51    description:
52      When present, polarity on the SDCAL SoC pin is inverted. The default
53      polarity for this signal is described in the datasheet. For instance on
54      SAMA5D2, the pin is usually tied to the GND with a resistor and a
55      capacitor (see "SDMMC I/O Calibration" chapter).
56
57required:
58  - compatible
59  - reg
60  - interrupts
61  - clocks
62  - clock-names
63
64allOf:
65  - $ref: sdhci-common.yaml#
66  - if:
67      properties:
68        compatible:
69          contains:
70            enum:
71              - atmel,sama5d2-sdhci
72    then:
73      properties:
74        clocks:
75          minItems: 3
76        clock-names:
77          minItems: 3
78
79unevaluatedProperties: false
80
81examples:
82  - |
83    #include <dt-bindings/interrupt-controller/irq.h>
84    #include <dt-bindings/clock/at91.h>
85    mmc@a0000000 {
86        compatible = "atmel,sama5d2-sdhci";
87        reg = <0xa0000000 0x300>;
88        interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
89        clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
90        clock-names = "hclock", "multclk", "baseclk";
91        assigned-clocks = <&sdmmc0_gclk>;
92        assigned-clock-rates = <480000000>;
93    };
94