1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/qcom,sm8250-camss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm CAMSS ISP
8
9maintainers:
10  - Robert Foss <[email protected]>
11
12description: |
13  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
14
15properties:
16  compatible:
17    const: qcom,sm8250-camss
18
19  clocks:
20    minItems: 37
21    maxItems: 37
22
23  clock-names:
24    items:
25      - const: cam_ahb_clk
26      - const: cam_hf_axi
27      - const: cam_sf_axi
28      - const: camnoc_axi
29      - const: camnoc_axi_src
30      - const: core_ahb
31      - const: cpas_ahb
32      - const: csiphy0
33      - const: csiphy0_timer
34      - const: csiphy1
35      - const: csiphy1_timer
36      - const: csiphy2
37      - const: csiphy2_timer
38      - const: csiphy3
39      - const: csiphy3_timer
40      - const: csiphy4
41      - const: csiphy4_timer
42      - const: csiphy5
43      - const: csiphy5_timer
44      - const: slow_ahb_src
45      - const: vfe0_ahb
46      - const: vfe0_axi
47      - const: vfe0
48      - const: vfe0_cphy_rx
49      - const: vfe0_csid
50      - const: vfe0_areg
51      - const: vfe1_ahb
52      - const: vfe1_axi
53      - const: vfe1
54      - const: vfe1_cphy_rx
55      - const: vfe1_csid
56      - const: vfe1_areg
57      - const: vfe_lite_ahb
58      - const: vfe_lite_axi
59      - const: vfe_lite
60      - const: vfe_lite_cphy_rx
61      - const: vfe_lite_csid
62
63  interrupts:
64    minItems: 14
65    maxItems: 14
66
67  interrupt-names:
68    items:
69      - const: csiphy0
70      - const: csiphy1
71      - const: csiphy2
72      - const: csiphy3
73      - const: csiphy4
74      - const: csiphy5
75      - const: csid0
76      - const: csid1
77      - const: csid2
78      - const: csid3
79      - const: vfe0
80      - const: vfe1
81      - const: vfe_lite0
82      - const: vfe_lite1
83
84  iommus:
85    minItems: 8
86    maxItems: 8
87
88  interconnects:
89    minItems: 4
90    maxItems: 4
91
92  interconnect-names:
93    items:
94      - const: cam_ahb
95      - const: cam_hf_0_mnoc
96      - const: cam_sf_0_mnoc
97      - const: cam_sf_icp_mnoc
98
99  power-domains:
100    items:
101      - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
102      - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
103      - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
104
105  ports:
106    $ref: /schemas/graph.yaml#/properties/ports
107
108    description:
109      CSI input ports.
110
111    properties:
112      port@0:
113        $ref: /schemas/graph.yaml#/$defs/port-base
114        unevaluatedProperties: false
115        description:
116          Input port for receiving CSI data.
117
118        properties:
119          endpoint:
120            $ref: video-interfaces.yaml#
121            unevaluatedProperties: false
122
123            properties:
124              clock-lanes:
125                maxItems: 1
126
127              data-lanes:
128                minItems: 1
129                maxItems: 4
130
131            required:
132              - clock-lanes
133              - data-lanes
134
135      port@1:
136        $ref: /schemas/graph.yaml#/$defs/port-base
137        unevaluatedProperties: false
138        description:
139          Input port for receiving CSI data.
140
141        properties:
142          endpoint:
143            $ref: video-interfaces.yaml#
144            unevaluatedProperties: false
145
146            properties:
147              clock-lanes:
148                maxItems: 1
149
150              data-lanes:
151                minItems: 1
152                maxItems: 4
153
154            required:
155              - clock-lanes
156              - data-lanes
157
158      port@2:
159        $ref: /schemas/graph.yaml#/$defs/port-base
160        unevaluatedProperties: false
161        description:
162          Input port for receiving CSI data.
163
164        properties:
165          endpoint:
166            $ref: video-interfaces.yaml#
167            unevaluatedProperties: false
168
169            properties:
170              clock-lanes:
171                maxItems: 1
172
173              data-lanes:
174                minItems: 1
175                maxItems: 4
176
177            required:
178              - clock-lanes
179              - data-lanes
180
181      port@3:
182        $ref: /schemas/graph.yaml#/$defs/port-base
183        unevaluatedProperties: false
184        description:
185          Input port for receiving CSI data.
186
187        properties:
188          endpoint:
189            $ref: video-interfaces.yaml#
190            unevaluatedProperties: false
191
192            properties:
193              clock-lanes:
194                maxItems: 1
195
196              data-lanes:
197                minItems: 1
198                maxItems: 4
199
200            required:
201              - clock-lanes
202              - data-lanes
203
204      port@4:
205        $ref: /schemas/graph.yaml#/$defs/port-base
206        unevaluatedProperties: false
207        description:
208          Input port for receiving CSI data.
209
210        properties:
211          endpoint:
212            $ref: video-interfaces.yaml#
213            unevaluatedProperties: false
214
215            properties:
216              clock-lanes:
217                maxItems: 1
218
219              data-lanes:
220                minItems: 1
221                maxItems: 4
222
223            required:
224              - clock-lanes
225              - data-lanes
226
227      port@5:
228        $ref: /schemas/graph.yaml#/$defs/port-base
229        unevaluatedProperties: false
230        description:
231          Input port for receiving CSI data.
232
233        properties:
234          endpoint:
235            $ref: video-interfaces.yaml#
236            unevaluatedProperties: false
237
238            properties:
239              clock-lanes:
240                maxItems: 1
241
242              data-lanes:
243                minItems: 1
244                maxItems: 4
245
246            required:
247              - clock-lanes
248              - data-lanes
249
250  reg:
251    minItems: 10
252    maxItems: 10
253
254  reg-names:
255    items:
256      - const: csiphy0
257      - const: csiphy1
258      - const: csiphy2
259      - const: csiphy3
260      - const: csiphy4
261      - const: csiphy5
262      - const: vfe0
263      - const: vfe1
264      - const: vfe_lite0
265      - const: vfe_lite1
266
267  vdda-phy-supply:
268    description:
269      Phandle to a regulator supply to PHY core block.
270
271  vdda-pll-supply:
272    description:
273      Phandle to 1.8V regulator supply to PHY refclk pll block.
274
275required:
276  - clock-names
277  - clocks
278  - compatible
279  - interconnects
280  - interconnect-names
281  - interrupts
282  - interrupt-names
283  - iommus
284  - power-domains
285  - reg
286  - reg-names
287  - vdda-phy-supply
288  - vdda-pll-supply
289
290additionalProperties: false
291
292examples:
293  - |
294    #include <dt-bindings/interrupt-controller/arm-gic.h>
295    #include <dt-bindings/clock/qcom,camcc-sm8250.h>
296    #include <dt-bindings/interconnect/qcom,sm8250.h>
297    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
298    #include <dt-bindings/power/qcom-rpmpd.h>
299
300    soc {
301        #address-cells = <2>;
302        #size-cells = <2>;
303
304        camss: camss@ac6a000 {
305            compatible = "qcom,sm8250-camss";
306
307            reg = <0 0xac6a000 0 0x2000>,
308                  <0 0xac6c000 0 0x2000>,
309                  <0 0xac6e000 0 0x1000>,
310                  <0 0xac70000 0 0x1000>,
311                  <0 0xac72000 0 0x1000>,
312                  <0 0xac74000 0 0x1000>,
313                  <0 0xacb4000 0 0xd000>,
314                  <0 0xacc3000 0 0xd000>,
315                  <0 0xacd9000 0 0x2200>,
316                  <0 0xacdb200 0 0x2200>;
317            reg-names = "csiphy0",
318                        "csiphy1",
319                        "csiphy2",
320                        "csiphy3",
321                        "csiphy4",
322                        "csiphy5",
323                        "vfe0",
324                        "vfe1",
325                        "vfe_lite0",
326                        "vfe_lite1";
327
328            vdda-phy-supply = <&vreg_l5a_0p88>;
329            vdda-pll-supply = <&vreg_l9a_1p2>;
330
331            interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
332                         <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
333                         <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
334                         <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
335                         <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
336                         <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
337                         <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
338                         <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
339                         <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
340                         <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
341                         <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
342                         <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
343                         <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
344                         <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
345            interrupt-names = "csiphy0",
346                              "csiphy1",
347                              "csiphy2",
348                              "csiphy3",
349                              "csiphy4",
350                              "csiphy5",
351                              "csid0",
352                              "csid1",
353                              "csid2",
354                              "csid3",
355                              "vfe0",
356                              "vfe1",
357                              "vfe_lite0",
358                              "vfe_lite1";
359
360            power-domains = <&camcc IFE_0_GDSC>,
361                            <&camcc IFE_1_GDSC>,
362                            <&camcc TITAN_TOP_GDSC>;
363
364            clocks = <&gcc GCC_CAMERA_AHB_CLK>,
365                     <&gcc GCC_CAMERA_HF_AXI_CLK>,
366                     <&gcc GCC_CAMERA_SF_AXI_CLK>,
367                     <&camcc CAM_CC_CAMNOC_AXI_CLK>,
368                     <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
369                     <&camcc CAM_CC_CORE_AHB_CLK>,
370                     <&camcc CAM_CC_CPAS_AHB_CLK>,
371                     <&camcc CAM_CC_CSIPHY0_CLK>,
372                     <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
373                     <&camcc CAM_CC_CSIPHY1_CLK>,
374                     <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
375                     <&camcc CAM_CC_CSIPHY2_CLK>,
376                     <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
377                     <&camcc CAM_CC_CSIPHY3_CLK>,
378                     <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
379                     <&camcc CAM_CC_CSIPHY4_CLK>,
380                     <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
381                     <&camcc CAM_CC_CSIPHY5_CLK>,
382                     <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
383                     <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
384                     <&camcc CAM_CC_IFE_0_AHB_CLK>,
385                     <&camcc CAM_CC_IFE_0_AXI_CLK>,
386                     <&camcc CAM_CC_IFE_0_CLK>,
387                     <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
388                     <&camcc CAM_CC_IFE_0_CSID_CLK>,
389                     <&camcc CAM_CC_IFE_0_AREG_CLK>,
390                     <&camcc CAM_CC_IFE_1_AHB_CLK>,
391                     <&camcc CAM_CC_IFE_1_AXI_CLK>,
392                     <&camcc CAM_CC_IFE_1_CLK>,
393                     <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
394                     <&camcc CAM_CC_IFE_1_CSID_CLK>,
395                     <&camcc CAM_CC_IFE_1_AREG_CLK>,
396                     <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
397                     <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
398                     <&camcc CAM_CC_IFE_LITE_CLK>,
399                     <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
400                     <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
401            clock-names = "cam_ahb_clk",
402                          "cam_hf_axi",
403                          "cam_sf_axi",
404                          "camnoc_axi",
405                          "camnoc_axi_src",
406                          "core_ahb",
407                          "cpas_ahb",
408                          "csiphy0",
409                          "csiphy0_timer",
410                          "csiphy1",
411                          "csiphy1_timer",
412                          "csiphy2",
413                          "csiphy2_timer",
414                          "csiphy3",
415                          "csiphy3_timer",
416                          "csiphy4",
417                          "csiphy4_timer",
418                          "csiphy5",
419                          "csiphy5_timer",
420                          "slow_ahb_src",
421                          "vfe0_ahb",
422                          "vfe0_axi",
423                          "vfe0",
424                          "vfe0_cphy_rx",
425                          "vfe0_csid",
426                          "vfe0_areg",
427                          "vfe1_ahb",
428                          "vfe1_axi",
429                          "vfe1",
430                          "vfe1_cphy_rx",
431                          "vfe1_csid",
432                          "vfe1_areg",
433                          "vfe_lite_ahb",
434                          "vfe_lite_axi",
435                          "vfe_lite",
436                          "vfe_lite_cphy_rx",
437                          "vfe_lite_csid";
438
439            iommus = <&apps_smmu 0x800 0x400>,
440                     <&apps_smmu 0x801 0x400>,
441                     <&apps_smmu 0x840 0x400>,
442                     <&apps_smmu 0x841 0x400>,
443                     <&apps_smmu 0xC00 0x400>,
444                     <&apps_smmu 0xC01 0x400>,
445                     <&apps_smmu 0xC40 0x400>,
446                     <&apps_smmu 0xC41 0x400>;
447
448            interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>,
449                            <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>,
450                            <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>,
451                            <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>;
452            interconnect-names = "cam_ahb",
453                                 "cam_hf_0_mnoc",
454                                 "cam_sf_0_mnoc",
455                                 "cam_sf_icp_mnoc";
456
457            ports {
458                #address-cells = <1>;
459                #size-cells = <0>;
460            };
461        };
462    };
463