1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/qcom,sdm845-camss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm CAMSS ISP
8
9maintainers:
10  - Robert Foss <[email protected]>
11
12description: |
13  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms
14
15properties:
16  compatible:
17    const: qcom,sdm845-camss
18
19  clocks:
20    minItems: 36
21    maxItems: 36
22
23  clock-names:
24    items:
25      - const: camnoc_axi
26      - const: cpas_ahb
27      - const: cphy_rx_src
28      - const: csi0
29      - const: csi0_src
30      - const: csi1
31      - const: csi1_src
32      - const: csi2
33      - const: csi2_src
34      - const: csiphy0
35      - const: csiphy0_timer
36      - const: csiphy0_timer_src
37      - const: csiphy1
38      - const: csiphy1_timer
39      - const: csiphy1_timer_src
40      - const: csiphy2
41      - const: csiphy2_timer
42      - const: csiphy2_timer_src
43      - const: csiphy3
44      - const: csiphy3_timer
45      - const: csiphy3_timer_src
46      - const: gcc_camera_ahb
47      - const: gcc_camera_axi
48      - const: slow_ahb_src
49      - const: soc_ahb
50      - const: vfe0_axi
51      - const: vfe0
52      - const: vfe0_cphy_rx
53      - const: vfe0_src
54      - const: vfe1_axi
55      - const: vfe1
56      - const: vfe1_cphy_rx
57      - const: vfe1_src
58      - const: vfe_lite
59      - const: vfe_lite_cphy_rx
60      - const: vfe_lite_src
61
62  interrupts:
63    minItems: 10
64    maxItems: 10
65
66  interrupt-names:
67    items:
68      - const: csid0
69      - const: csid1
70      - const: csid2
71      - const: csiphy0
72      - const: csiphy1
73      - const: csiphy2
74      - const: csiphy3
75      - const: vfe0
76      - const: vfe1
77      - const: vfe_lite
78
79  iommus:
80    maxItems: 4
81
82  power-domains:
83    items:
84      - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
85      - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
86      - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
87
88  ports:
89    $ref: /schemas/graph.yaml#/properties/ports
90
91    description:
92      CSI input ports.
93
94    properties:
95      port@0:
96        $ref: /schemas/graph.yaml#/$defs/port-base
97        unevaluatedProperties: false
98        description:
99          Input port for receiving CSI data.
100
101        properties:
102          endpoint:
103            $ref: video-interfaces.yaml#
104            unevaluatedProperties: false
105
106            properties:
107              data-lanes:
108                minItems: 1
109                maxItems: 4
110
111            required:
112              - data-lanes
113
114      port@1:
115        $ref: /schemas/graph.yaml#/$defs/port-base
116        unevaluatedProperties: false
117        description:
118          Input port for receiving CSI data.
119
120        properties:
121          endpoint:
122            $ref: video-interfaces.yaml#
123            unevaluatedProperties: false
124
125            properties:
126              data-lanes:
127                minItems: 1
128                maxItems: 4
129
130            required:
131              - data-lanes
132
133      port@2:
134        $ref: /schemas/graph.yaml#/$defs/port-base
135        unevaluatedProperties: false
136        description:
137          Input port for receiving CSI data.
138
139        properties:
140          endpoint:
141            $ref: video-interfaces.yaml#
142            unevaluatedProperties: false
143
144            properties:
145              data-lanes:
146                minItems: 1
147                maxItems: 4
148
149            required:
150              - data-lanes
151
152      port@3:
153        $ref: /schemas/graph.yaml#/$defs/port-base
154        unevaluatedProperties: false
155        description:
156          Input port for receiving CSI data.
157
158        properties:
159          endpoint:
160            $ref: video-interfaces.yaml#
161            unevaluatedProperties: false
162
163            properties:
164              data-lanes:
165                minItems: 1
166                maxItems: 4
167
168            required:
169              - data-lanes
170
171  reg:
172    minItems: 10
173    maxItems: 10
174
175  reg-names:
176    items:
177      - const: csid0
178      - const: csid1
179      - const: csid2
180      - const: csiphy0
181      - const: csiphy1
182      - const: csiphy2
183      - const: csiphy3
184      - const: vfe0
185      - const: vfe1
186      - const: vfe_lite
187
188  vdda-phy-supply:
189    description:
190      Phandle to a regulator supply to PHY core block.
191
192  vdda-pll-supply:
193    description:
194      Phandle to 1.8V regulator supply to PHY refclk pll block.
195
196required:
197  - clock-names
198  - clocks
199  - compatible
200  - interrupt-names
201  - interrupts
202  - iommus
203  - power-domains
204  - reg
205  - reg-names
206  - vdda-phy-supply
207  - vdda-pll-supply
208
209additionalProperties: false
210
211examples:
212  - |
213    #include <dt-bindings/interrupt-controller/arm-gic.h>
214    #include <dt-bindings/clock/qcom,camcc-sdm845.h>
215    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
216
217    soc {
218      #address-cells = <2>;
219      #size-cells = <2>;
220
221      camss: camss@acb3000 {
222        compatible = "qcom,sdm845-camss";
223
224        clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
225          <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
226          <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
227          <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
228          <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
229          <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
230          <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
231          <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
232          <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
233          <&clock_camcc CAM_CC_CSIPHY0_CLK>,
234          <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
235          <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
236          <&clock_camcc CAM_CC_CSIPHY1_CLK>,
237          <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
238          <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
239          <&clock_camcc CAM_CC_CSIPHY2_CLK>,
240          <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
241          <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
242          <&clock_camcc CAM_CC_CSIPHY3_CLK>,
243          <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
244          <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
245          <&gcc GCC_CAMERA_AHB_CLK>,
246          <&gcc GCC_CAMERA_AXI_CLK>,
247          <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
248          <&clock_camcc CAM_CC_SOC_AHB_CLK>,
249          <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
250          <&clock_camcc CAM_CC_IFE_0_CLK>,
251          <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
252          <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
253          <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
254          <&clock_camcc CAM_CC_IFE_1_CLK>,
255          <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
256          <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
257          <&clock_camcc CAM_CC_IFE_LITE_CLK>,
258          <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
259          <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
260
261        clock-names = "camnoc_axi",
262          "cpas_ahb",
263          "cphy_rx_src",
264          "csi0",
265          "csi0_src",
266          "csi1",
267          "csi1_src",
268          "csi2",
269          "csi2_src",
270          "csiphy0",
271          "csiphy0_timer",
272          "csiphy0_timer_src",
273          "csiphy1",
274          "csiphy1_timer",
275          "csiphy1_timer_src",
276          "csiphy2",
277          "csiphy2_timer",
278          "csiphy2_timer_src",
279          "csiphy3",
280          "csiphy3_timer",
281          "csiphy3_timer_src",
282          "gcc_camera_ahb",
283          "gcc_camera_axi",
284          "slow_ahb_src",
285          "soc_ahb",
286          "vfe0_axi",
287          "vfe0",
288          "vfe0_cphy_rx",
289          "vfe0_src",
290          "vfe1_axi",
291          "vfe1",
292          "vfe1_cphy_rx",
293          "vfe1_src",
294          "vfe_lite",
295          "vfe_lite_cphy_rx",
296          "vfe_lite_src";
297
298        interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
299          <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
300          <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
301          <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
302          <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
303          <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
304          <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
305          <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
306          <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
307          <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
308
309        interrupt-names = "csid0",
310          "csid1",
311          "csid2",
312          "csiphy0",
313          "csiphy1",
314          "csiphy2",
315          "csiphy3",
316          "vfe0",
317          "vfe1",
318          "vfe_lite";
319
320        iommus = <&apps_smmu 0x0808 0x0>,
321          <&apps_smmu 0x0810 0x8>,
322          <&apps_smmu 0x0c08 0x0>,
323          <&apps_smmu 0x0c10 0x8>;
324
325        power-domains = <&clock_camcc IFE_0_GDSC>,
326          <&clock_camcc IFE_1_GDSC>,
327          <&clock_camcc TITAN_TOP_GDSC>;
328
329        reg = <0 0xacb3000 0 0x1000>,
330          <0 0xacba000 0 0x1000>,
331          <0 0xacc8000 0 0x1000>,
332          <0 0xac65000 0 0x1000>,
333          <0 0xac66000 0 0x1000>,
334          <0 0xac67000 0 0x1000>,
335          <0 0xac68000 0 0x1000>,
336          <0 0xacaf000 0 0x4000>,
337          <0 0xacb6000 0 0x4000>,
338          <0 0xacc4000 0 0x4000>;
339
340        reg-names = "csid0",
341          "csid1",
342          "csid2",
343          "csiphy0",
344          "csiphy1",
345          "csiphy2",
346          "csiphy3",
347          "vfe0",
348          "vfe1",
349          "vfe_lite";
350
351        vdda-phy-supply = <&vreg_l1a_0p875>;
352        vdda-pll-supply = <&vreg_l26a_1p2>;
353
354        ports {
355          #address-cells = <1>;
356          #size-cells = <0>;
357        };
358      };
359    };
360