1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/media/qcom,sdm660-camss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm CAMSS ISP 8 9maintainers: 10 - Robert Foss <[email protected]> 11 - AngeloGioacchino Del Regno <[email protected]> 12 13description: | 14 The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms 15 16properties: 17 compatible: 18 const: qcom,sdm660-camss 19 20 clocks: 21 minItems: 42 22 maxItems: 42 23 24 clock-names: 25 items: 26 - const: ahb 27 - const: cphy_csid0 28 - const: cphy_csid1 29 - const: cphy_csid2 30 - const: cphy_csid3 31 - const: csi0_ahb 32 - const: csi0 33 - const: csi0_phy 34 - const: csi0_pix 35 - const: csi0_rdi 36 - const: csi1_ahb 37 - const: csi1 38 - const: csi1_phy 39 - const: csi1_pix 40 - const: csi1_rdi 41 - const: csi2_ahb 42 - const: csi2 43 - const: csi2_phy 44 - const: csi2_pix 45 - const: csi2_rdi 46 - const: csi3_ahb 47 - const: csi3 48 - const: csi3_phy 49 - const: csi3_pix 50 - const: csi3_rdi 51 - const: csiphy0_timer 52 - const: csiphy1_timer 53 - const: csiphy2_timer 54 - const: csiphy_ahb2crif 55 - const: csi_vfe0 56 - const: csi_vfe1 57 - const: ispif_ahb 58 - const: throttle_axi 59 - const: top_ahb 60 - const: vfe0_ahb 61 - const: vfe0 62 - const: vfe0_stream 63 - const: vfe1_ahb 64 - const: vfe1 65 - const: vfe1_stream 66 - const: vfe_ahb 67 - const: vfe_axi 68 69 interrupts: 70 minItems: 10 71 maxItems: 10 72 73 interrupt-names: 74 items: 75 - const: csid0 76 - const: csid1 77 - const: csid2 78 - const: csid3 79 - const: csiphy0 80 - const: csiphy1 81 - const: csiphy2 82 - const: ispif 83 - const: vfe0 84 - const: vfe1 85 86 interconnects: 87 maxItems: 1 88 89 interconnect-names: 90 items: 91 - const: vfe-mem 92 93 iommus: 94 maxItems: 4 95 96 power-domains: 97 items: 98 - description: VFE0 GDSC - Video Front End, Global Distributed Switch Controller. 99 - description: VFE1 GDSC - Video Front End, Global Distributed Switch Controller. 100 101 ports: 102 $ref: /schemas/graph.yaml#/properties/ports 103 104 description: 105 CSI input ports. 106 107 properties: 108 port@0: 109 $ref: /schemas/graph.yaml#/$defs/port-base 110 unevaluatedProperties: false 111 description: 112 Input port for receiving CSI data. 113 114 properties: 115 endpoint: 116 $ref: video-interfaces.yaml# 117 unevaluatedProperties: false 118 119 properties: 120 data-lanes: 121 minItems: 1 122 maxItems: 4 123 124 required: 125 - data-lanes 126 127 port@1: 128 $ref: /schemas/graph.yaml#/$defs/port-base 129 unevaluatedProperties: false 130 description: 131 Input port for receiving CSI data. 132 133 properties: 134 endpoint: 135 $ref: video-interfaces.yaml# 136 unevaluatedProperties: false 137 138 properties: 139 data-lanes: 140 minItems: 1 141 maxItems: 4 142 143 required: 144 - data-lanes 145 146 port@2: 147 $ref: /schemas/graph.yaml#/$defs/port-base 148 unevaluatedProperties: false 149 description: 150 Input port for receiving CSI data. 151 152 properties: 153 endpoint: 154 $ref: video-interfaces.yaml# 155 unevaluatedProperties: false 156 157 properties: 158 data-lanes: 159 minItems: 1 160 maxItems: 4 161 162 required: 163 - data-lanes 164 165 port@3: 166 $ref: /schemas/graph.yaml#/$defs/port-base 167 unevaluatedProperties: false 168 description: 169 Input port for receiving CSI data. 170 171 properties: 172 endpoint: 173 $ref: video-interfaces.yaml# 174 unevaluatedProperties: false 175 176 properties: 177 data-lanes: 178 minItems: 1 179 maxItems: 4 180 181 required: 182 - data-lanes 183 184 reg: 185 minItems: 14 186 maxItems: 14 187 188 reg-names: 189 items: 190 - const: csi_clk_mux 191 - const: csid0 192 - const: csid1 193 - const: csid2 194 - const: csid3 195 - const: csiphy0 196 - const: csiphy0_clk_mux 197 - const: csiphy1 198 - const: csiphy1_clk_mux 199 - const: csiphy2 200 - const: csiphy2_clk_mux 201 - const: ispif 202 - const: vfe0 203 - const: vfe1 204 205 vdda-supply: 206 description: 207 Definition of the regulator used as analog power supply. 208 209required: 210 - clock-names 211 - clocks 212 - compatible 213 - interrupt-names 214 - interrupts 215 - iommus 216 - power-domains 217 - reg 218 - reg-names 219 - vdda-supply 220 221additionalProperties: false 222 223examples: 224 - | 225 #include <dt-bindings/interrupt-controller/arm-gic.h> 226 #include <dt-bindings/clock/qcom,gcc-sdm660.h> 227 #include <dt-bindings/clock/qcom,mmcc-sdm660.h> 228 229 camss: camss@ca00020 { 230 compatible = "qcom,sdm660-camss"; 231 232 clocks = <&mmcc CAMSS_AHB_CLK>, 233 <&mmcc CAMSS_CPHY_CSID0_CLK>, 234 <&mmcc CAMSS_CPHY_CSID1_CLK>, 235 <&mmcc CAMSS_CPHY_CSID2_CLK>, 236 <&mmcc CAMSS_CPHY_CSID3_CLK>, 237 <&mmcc CAMSS_CSI0_AHB_CLK>, 238 <&mmcc CAMSS_CSI0_CLK>, 239 <&mmcc CAMSS_CPHY_CSID0_CLK>, 240 <&mmcc CAMSS_CSI0PIX_CLK>, 241 <&mmcc CAMSS_CSI0RDI_CLK>, 242 <&mmcc CAMSS_CSI1_AHB_CLK>, 243 <&mmcc CAMSS_CSI1_CLK>, 244 <&mmcc CAMSS_CPHY_CSID1_CLK>, 245 <&mmcc CAMSS_CSI1PIX_CLK>, 246 <&mmcc CAMSS_CSI1RDI_CLK>, 247 <&mmcc CAMSS_CSI2_AHB_CLK>, 248 <&mmcc CAMSS_CSI2_CLK>, 249 <&mmcc CAMSS_CPHY_CSID2_CLK>, 250 <&mmcc CAMSS_CSI2PIX_CLK>, 251 <&mmcc CAMSS_CSI2RDI_CLK>, 252 <&mmcc CAMSS_CSI3_AHB_CLK>, 253 <&mmcc CAMSS_CSI3_CLK>, 254 <&mmcc CAMSS_CPHY_CSID3_CLK>, 255 <&mmcc CAMSS_CSI3PIX_CLK>, 256 <&mmcc CAMSS_CSI3RDI_CLK>, 257 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 258 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 259 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 260 <&mmcc CSIPHY_AHB2CRIF_CLK>, 261 <&mmcc CAMSS_CSI_VFE0_CLK>, 262 <&mmcc CAMSS_CSI_VFE1_CLK>, 263 <&mmcc CAMSS_ISPIF_AHB_CLK>, 264 <&mmcc THROTTLE_CAMSS_AXI_CLK>, 265 <&mmcc CAMSS_TOP_AHB_CLK>, 266 <&mmcc CAMSS_VFE0_AHB_CLK>, 267 <&mmcc CAMSS_VFE0_CLK>, 268 <&mmcc CAMSS_VFE0_STREAM_CLK>, 269 <&mmcc CAMSS_VFE1_AHB_CLK>, 270 <&mmcc CAMSS_VFE1_CLK>, 271 <&mmcc CAMSS_VFE1_STREAM_CLK>, 272 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, 273 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>; 274 275 clock-names = "ahb", 276 "cphy_csid0", 277 "cphy_csid1", 278 "cphy_csid2", 279 "cphy_csid3", 280 "csi0_ahb", 281 "csi0", 282 "csi0_phy", 283 "csi0_pix", 284 "csi0_rdi", 285 "csi1_ahb", 286 "csi1", 287 "csi1_phy", 288 "csi1_pix", 289 "csi1_rdi", 290 "csi2_ahb", 291 "csi2", 292 "csi2_phy", 293 "csi2_pix", 294 "csi2_rdi", 295 "csi3_ahb", 296 "csi3", 297 "csi3_phy", 298 "csi3_pix", 299 "csi3_rdi", 300 "csiphy0_timer", 301 "csiphy1_timer", 302 "csiphy2_timer", 303 "csiphy_ahb2crif", 304 "csi_vfe0", 305 "csi_vfe1", 306 "ispif_ahb", 307 "throttle_axi", 308 "top_ahb", 309 "vfe0_ahb", 310 "vfe0", 311 "vfe0_stream", 312 "vfe1_ahb", 313 "vfe1", 314 "vfe1_stream", 315 "vfe_ahb", 316 "vfe_axi"; 317 318 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 319 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 320 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 321 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 322 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 323 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 324 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 325 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 326 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 327 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 328 329 interrupt-names = "csid0", 330 "csid1", 331 "csid2", 332 "csid3", 333 "csiphy0", 334 "csiphy1", 335 "csiphy2", 336 "ispif", 337 "vfe0", 338 "vfe1"; 339 340 iommus = <&mmss_smmu 0xc00>, 341 <&mmss_smmu 0xc01>, 342 <&mmss_smmu 0xc02>, 343 <&mmss_smmu 0xc03>; 344 345 power-domains = <&mmcc CAMSS_VFE0_GDSC>, 346 <&mmcc CAMSS_VFE1_GDSC>; 347 348 reg = <0x0ca00020 0x10>, 349 <0x0ca30000 0x100>, 350 <0x0ca30400 0x100>, 351 <0x0ca30800 0x100>, 352 <0x0ca30c00 0x100>, 353 <0x0c824000 0x1000>, 354 <0x0ca00120 0x4>, 355 <0x0c825000 0x1000>, 356 <0x0ca00124 0x4>, 357 <0x0c826000 0x1000>, 358 <0x0ca00128 0x4>, 359 <0x0ca31000 0x500>, 360 <0x0ca10000 0x1000>, 361 <0x0ca14000 0x1000>; 362 363 reg-names = "csi_clk_mux", 364 "csid0", 365 "csid1", 366 "csid2", 367 "csid3", 368 "csiphy0", 369 "csiphy0_clk_mux", 370 "csiphy1", 371 "csiphy1_clk_mux", 372 "csiphy2", 373 "csiphy2_clk_mux", 374 "ispif", 375 "vfe0", 376 "vfe1"; 377 378 vdda-supply = <®_2v8>; 379 380 ports { 381 #address-cells = <1>; 382 #size-cells = <0>; 383 }; 384 }; 385