1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/qcom,msm8996-camss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm CAMSS ISP
8
9maintainers:
10  - Robert Foss <[email protected]>
11  - Todor Tomov <[email protected]>
12
13description: |
14  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms
15
16properties:
17  compatible:
18    const: qcom,msm8996-camss
19
20  clocks:
21    minItems: 36
22    maxItems: 36
23
24  clock-names:
25    items:
26      - const: top_ahb
27      - const: ispif_ahb
28      - const: csiphy0_timer
29      - const: csiphy1_timer
30      - const: csiphy2_timer
31      - const: csi0_ahb
32      - const: csi0
33      - const: csi0_phy
34      - const: csi0_pix
35      - const: csi0_rdi
36      - const: csi1_ahb
37      - const: csi1
38      - const: csi1_phy
39      - const: csi1_pix
40      - const: csi1_rdi
41      - const: csi2_ahb
42      - const: csi2
43      - const: csi2_phy
44      - const: csi2_pix
45      - const: csi2_rdi
46      - const: csi3_ahb
47      - const: csi3
48      - const: csi3_phy
49      - const: csi3_pix
50      - const: csi3_rdi
51      - const: ahb
52      - const: vfe0
53      - const: csi_vfe0
54      - const: vfe0_ahb
55      - const: vfe0_stream
56      - const: vfe1
57      - const: csi_vfe1
58      - const: vfe1_ahb
59      - const: vfe1_stream
60      - const: vfe_ahb
61      - const: vfe_axi
62
63  interrupts:
64    minItems: 10
65    maxItems: 10
66
67  interrupt-names:
68    items:
69      - const: csiphy0
70      - const: csiphy1
71      - const: csiphy2
72      - const: csid0
73      - const: csid1
74      - const: csid2
75      - const: csid3
76      - const: ispif
77      - const: vfe0
78      - const: vfe1
79
80  iommus:
81    maxItems: 4
82
83  power-domains:
84    items:
85      - description: VFE0 GDSC - Video Front End, Global Distributed Switch Controller.
86      - description: VFE1 GDSC - Video Front End, Global Distributed Switch Controller.
87
88  ports:
89    $ref: /schemas/graph.yaml#/properties/ports
90
91    description:
92      CSI input ports.
93
94    properties:
95      port@0:
96        $ref: /schemas/graph.yaml#/$defs/port-base
97        unevaluatedProperties: false
98        description:
99          Input port for receiving CSI data.
100
101        properties:
102          endpoint:
103            $ref: video-interfaces.yaml#
104            unevaluatedProperties: false
105
106            properties:
107              data-lanes:
108                description:
109                  An array of physical data lanes indexes.
110                  Position of an entry determines the logical
111                  lane number, while the value of an entry
112                  indicates physical lane index. Lane swapping
113                  is supported. Physical lane indexes are;
114                  0, 1, 2, 3
115                minItems: 1
116                maxItems: 4
117
118            required:
119              - data-lanes
120
121      port@1:
122        $ref: /schemas/graph.yaml#/$defs/port-base
123        unevaluatedProperties: false
124        description:
125          Input port for receiving CSI data.
126
127        properties:
128          endpoint:
129            $ref: video-interfaces.yaml#
130            unevaluatedProperties: false
131
132            properties:
133              data-lanes:
134                minItems: 1
135                maxItems: 4
136
137            required:
138              - data-lanes
139
140      port@2:
141        $ref: /schemas/graph.yaml#/$defs/port-base
142        unevaluatedProperties: false
143        description:
144          Input port for receiving CSI data.
145
146        properties:
147          endpoint:
148            $ref: video-interfaces.yaml#
149            unevaluatedProperties: false
150
151            properties:
152              data-lanes:
153                minItems: 1
154                maxItems: 4
155
156            required:
157              - data-lanes
158
159      port@3:
160        $ref: /schemas/graph.yaml#/$defs/port-base
161        unevaluatedProperties: false
162        description:
163          Input port for receiving CSI data.
164
165        properties:
166          endpoint:
167            $ref: video-interfaces.yaml#
168            unevaluatedProperties: false
169
170            properties:
171              data-lanes:
172                minItems: 1
173                maxItems: 4
174
175            required:
176              - data-lanes
177
178  reg:
179    minItems: 14
180    maxItems: 14
181
182  reg-names:
183    items:
184      - const: csiphy0
185      - const: csiphy0_clk_mux
186      - const: csiphy1
187      - const: csiphy1_clk_mux
188      - const: csiphy2
189      - const: csiphy2_clk_mux
190      - const: csid0
191      - const: csid1
192      - const: csid2
193      - const: csid3
194      - const: ispif
195      - const: csi_clk_mux
196      - const: vfe0
197      - const: vfe1
198
199  vdda-supply:
200    description:
201      Definition of the regulator used as analog power supply.
202
203required:
204  - clock-names
205  - clocks
206  - compatible
207  - interrupt-names
208  - interrupts
209  - iommus
210  - power-domains
211  - reg
212  - reg-names
213  - vdda-supply
214
215additionalProperties: false
216
217examples:
218  - |
219    #include <dt-bindings/interrupt-controller/arm-gic.h>
220    #include <dt-bindings/clock/qcom,gcc-msm8996.h>
221    #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
222
223    camss: camss@a34000 {
224      compatible = "qcom,msm8996-camss";
225
226      clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
227        <&mmcc CAMSS_ISPIF_AHB_CLK>,
228        <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
229        <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
230        <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
231        <&mmcc CAMSS_CSI0_AHB_CLK>,
232        <&mmcc CAMSS_CSI0_CLK>,
233        <&mmcc CAMSS_CSI0PHY_CLK>,
234        <&mmcc CAMSS_CSI0PIX_CLK>,
235        <&mmcc CAMSS_CSI0RDI_CLK>,
236        <&mmcc CAMSS_CSI1_AHB_CLK>,
237        <&mmcc CAMSS_CSI1_CLK>,
238        <&mmcc CAMSS_CSI1PHY_CLK>,
239        <&mmcc CAMSS_CSI1PIX_CLK>,
240        <&mmcc CAMSS_CSI1RDI_CLK>,
241        <&mmcc CAMSS_CSI2_AHB_CLK>,
242        <&mmcc CAMSS_CSI2_CLK>,
243        <&mmcc CAMSS_CSI2PHY_CLK>,
244        <&mmcc CAMSS_CSI2PIX_CLK>,
245        <&mmcc CAMSS_CSI2RDI_CLK>,
246        <&mmcc CAMSS_CSI3_AHB_CLK>,
247        <&mmcc CAMSS_CSI3_CLK>,
248        <&mmcc CAMSS_CSI3PHY_CLK>,
249        <&mmcc CAMSS_CSI3PIX_CLK>,
250        <&mmcc CAMSS_CSI3RDI_CLK>,
251        <&mmcc CAMSS_AHB_CLK>,
252        <&mmcc CAMSS_VFE0_CLK>,
253        <&mmcc CAMSS_CSI_VFE0_CLK>,
254        <&mmcc CAMSS_VFE0_AHB_CLK>,
255        <&mmcc CAMSS_VFE0_STREAM_CLK>,
256        <&mmcc CAMSS_VFE1_CLK>,
257        <&mmcc CAMSS_CSI_VFE1_CLK>,
258        <&mmcc CAMSS_VFE1_AHB_CLK>,
259        <&mmcc CAMSS_VFE1_STREAM_CLK>,
260        <&mmcc CAMSS_VFE_AHB_CLK>,
261        <&mmcc CAMSS_VFE_AXI_CLK>;
262
263      clock-names = "top_ahb",
264        "ispif_ahb",
265        "csiphy0_timer",
266        "csiphy1_timer",
267        "csiphy2_timer",
268        "csi0_ahb",
269        "csi0",
270        "csi0_phy",
271        "csi0_pix",
272        "csi0_rdi",
273        "csi1_ahb",
274        "csi1",
275        "csi1_phy",
276        "csi1_pix",
277        "csi1_rdi",
278        "csi2_ahb",
279        "csi2",
280        "csi2_phy",
281        "csi2_pix",
282        "csi2_rdi",
283        "csi3_ahb",
284        "csi3",
285        "csi3_phy",
286        "csi3_pix",
287        "csi3_rdi",
288        "ahb",
289        "vfe0",
290        "csi_vfe0",
291        "vfe0_ahb",
292        "vfe0_stream",
293        "vfe1",
294        "csi_vfe1",
295        "vfe1_ahb",
296        "vfe1_stream",
297        "vfe_ahb",
298        "vfe_axi";
299
300      interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
301        <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
302        <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
303        <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
304        <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
305        <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
306        <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
307        <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
308        <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
309        <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
310
311      interrupt-names = "csiphy0",
312        "csiphy1",
313        "csiphy2",
314        "csid0",
315        "csid1",
316        "csid2",
317        "csid3",
318        "ispif",
319        "vfe0",
320        "vfe1";
321
322      iommus = <&vfe_smmu 0>,
323         <&vfe_smmu 1>,
324         <&vfe_smmu 2>,
325         <&vfe_smmu 3>;
326
327      power-domains = <&mmcc VFE0_GDSC>,
328        <&mmcc VFE1_GDSC>;
329
330      reg = <0x00a34000 0x1000>,
331        <0x00a00030 0x4>,
332        <0x00a35000 0x1000>,
333        <0x00a00038 0x4>,
334        <0x00a36000 0x1000>,
335        <0x00a00040 0x4>,
336        <0x00a30000 0x100>,
337        <0x00a30400 0x100>,
338        <0x00a30800 0x100>,
339        <0x00a30c00 0x100>,
340        <0x00a31000 0x500>,
341        <0x00a00020 0x10>,
342        <0x00a10000 0x1000>,
343        <0x00a14000 0x1000>;
344
345      reg-names = "csiphy0",
346        "csiphy0_clk_mux",
347        "csiphy1",
348        "csiphy1_clk_mux",
349        "csiphy2",
350        "csiphy2_clk_mux",
351        "csid0",
352        "csid1",
353        "csid2",
354        "csid3",
355        "ispif",
356        "csi_clk_mux",
357        "vfe0",
358        "vfe1";
359
360      vdda-supply = <&reg_2v8>;
361
362      ports {
363        #address-cells = <1>;
364        #size-cells = <0>;
365      };
366    };
367