1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/nxp,imx8-isi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: i.MX8 Image Sensing Interface
8
9maintainers:
10  - Laurent Pinchart <[email protected]>
11
12description: |
13  The Image Sensing Interface (ISI) combines image processing pipelines with
14  DMA engines to process and capture frames originating from a variety of
15  sources. The inputs to the ISI go through Pixel Link interfaces, and their
16  number and nature is SoC-dependent. They cover both capture interfaces (MIPI
17  CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
18
19properties:
20  compatible:
21    enum:
22      - fsl,imx8mn-isi
23      - fsl,imx8mp-isi
24      - fsl,imx8ulp-isi
25      - fsl,imx93-isi
26
27  reg:
28    maxItems: 1
29
30  clocks:
31    items:
32      - description: The AXI clock
33      - description: The APB clock
34      # TODO: Check if the per-channel ipg_proc_clk clocks need to be specified
35      # as well, in case some SoCs have the ability to control them separately.
36      # This may be the case of the i.MX8[DQ]X(P)
37
38  clock-names:
39    items:
40      - const: axi
41      - const: apb
42
43  fsl,blk-ctrl:
44    $ref: /schemas/types.yaml#/definitions/phandle
45    description:
46      A phandle referencing the block control that contains the CSIS to ISI
47      gasket.
48
49  interrupts:
50    description: Processing pipeline interrupts, one per pipeline
51    minItems: 1
52    maxItems: 2
53
54  power-domains:
55    maxItems: 1
56
57  ports:
58    $ref: /schemas/graph.yaml#/properties/ports
59    description: |
60      Ports represent the Pixel Link inputs to the ISI. Their number and
61      assignment are model-dependent. Each port shall have a single endpoint.
62
63required:
64  - compatible
65  - reg
66  - interrupts
67  - clocks
68  - clock-names
69  - fsl,blk-ctrl
70  - ports
71
72allOf:
73  - if:
74      properties:
75        compatible:
76          contains:
77            enum:
78              - fsl,imx8mn-isi
79              - fsl,imx8ulp-isi
80              - fsl,imx93-isi
81    then:
82      properties:
83        interrupts:
84          maxItems: 1
85        ports:
86          properties:
87            port@0:
88              description: MIPI CSI-2 RX
89            port@1: false
90          required:
91            - port@0
92
93  - if:
94      properties:
95        compatible:
96          contains:
97            const: fsl,imx8mp-isi
98    then:
99      properties:
100        interrupts:
101          maxItems: 2
102        ports:
103          properties:
104            port@0:
105              description: MIPI CSI-2 RX 0
106            port@1:
107              description: MIPI CSI-2 RX 1
108          required:
109            - port@0
110            - port@1
111
112additionalProperties: false
113
114examples:
115  - |
116    #include <dt-bindings/clock/imx8mn-clock.h>
117    #include <dt-bindings/interrupt-controller/arm-gic.h>
118    #include <dt-bindings/interrupt-controller/irq.h>
119    #include <dt-bindings/power/imx8mn-power.h>
120
121    isi@32e20000 {
122        compatible = "fsl,imx8mn-isi";
123        reg = <0x32e20000 0x100>;
124        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
125        clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
126                 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
127        clock-names = "axi", "apb";
128        fsl,blk-ctrl = <&disp_blk_ctrl>;
129        power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>;
130
131        ports {
132            #address-cells = <1>;
133            #size-cells = <0>;
134
135            port@0 {
136                reg = <0>;
137                isi_in: endpoint {
138                    remote-endpoint = <&mipi_csi_out>;
139                };
140            };
141        };
142    };
143
144  - |
145    #include <dt-bindings/clock/imx8mp-clock.h>
146    #include <dt-bindings/interrupt-controller/arm-gic.h>
147    #include <dt-bindings/interrupt-controller/irq.h>
148
149    isi@32e00000 {
150        compatible = "fsl,imx8mp-isi";
151        reg = <0x32e00000 0x4000>;
152        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
153                     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
154        clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
155                 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
156        clock-names = "axi", "apb";
157        fsl,blk-ctrl = <&media_blk_ctrl>;
158        power-domains = <&mediamix_pd>;
159
160        ports {
161            #address-cells = <1>;
162            #size-cells = <0>;
163
164            port@0 {
165                reg = <0>;
166                isi_in_0: endpoint {
167                    remote-endpoint = <&mipi_csi_0_out>;
168                };
169            };
170
171            port@1 {
172                reg = <1>;
173                isi_in_1: endpoint {
174                    remote-endpoint = <&mipi_csi_1_out>;
175                };
176            };
177        };
178    };
179...
180