1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek Video Decode Accelerator With Multi Hardware
8
9maintainers:
10  - Yunfei Dong <[email protected]>
11
12description: |
13  Mediatek Video Decode is the video decode hardware present in Mediatek
14  SoCs which supports high resolution decoding functionalities. Required
15  parent and child device node.
16
17  About the Decoder Hardware Block Diagram, please check below:
18
19    +------------------------------------------------+-------------------------------------+
20    |                                                |                                     |
21    |  input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output  |
22    |            ||             ||                   |                     ||              |
23    +------------||-------------||-------------------+---------------------||--------------+
24                 ||     lat     ||                   |               core workqueue  <parent>
25    -------------||-------------||-------------------|---------------------||---------------
26                 ||<------------||----------------HW index---------------->||        <child>
27                 \/             \/                                         \/
28               +-------------------------------------------------------------+
29               |                          enable/disable                     |
30               |                 clk     power    irq    iommu               |
31               |                   (lat/lat soc/core0/core1)                 |
32               +-------------------------------------------------------------+
33
34  As above, there are parent and child devices, child mean each hardware. The child device
35  controls the information of each hardware independent which include clk/power/irq.
36
37  There are two workqueues in parent device: lat workqueue and core workqueue. They are used
38  to lat and core hardware decoder. Lat workqueue need to get input bitstream and lat buffer,
39  then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode
40  done. Core workqueue need to get lat buffer and output buffer, then enable core to decode,
41  writing the result to output buffer, disable hardware when core decode done. These two
42  hardwares will decode each frame cyclically.
43
44  For the smi common may not the same for each hardware, can't combine all hardware in one node,
45  or leading to iommu fault when access dram data.
46
47  Lat soc is a hardware which is related with some larb(local arbiter) ports. For mt8195
48  platform, there are some ports like RDMA, UFO in lat soc larb, need to enable its power and
49  clock when lat start to work, don't have interrupt.
50
51  mt8195: lat soc HW + lat HW + core HW
52  mt8192: lat HW + core HW
53
54properties:
55  compatible:
56    enum:
57      - mediatek,mt8192-vcodec-dec
58      - mediatek,mt8186-vcodec-dec
59      - mediatek,mt8188-vcodec-dec
60      - mediatek,mt8195-vcodec-dec
61
62  reg:
63    minItems: 1
64    items:
65      - description: VDEC_SYS register space
66      - description: VDEC_RACING_CTRL register space
67
68  iommus:
69    minItems: 1
70    maxItems: 32
71    description: |
72      List of the hardware port in respective IOMMU block for current Socs.
73      Refer to bindings/iommu/mediatek,iommu.yaml.
74
75  mediatek,scp:
76    $ref: /schemas/types.yaml#/definitions/phandle
77    description: |
78      The node of system control processor (SCP), using
79      the remoteproc & rpmsg framework.
80
81  "#address-cells":
82    const: 2
83
84  "#size-cells":
85    const: 2
86
87  ranges: true
88
89# Required child node:
90patternProperties:
91  '^video-codec@[0-9a-f]+$':
92    type: object
93
94    properties:
95      compatible:
96        enum:
97          - mediatek,mtk-vcodec-core
98          - mediatek,mtk-vcodec-lat
99          - mediatek,mtk-vcodec-lat-soc
100
101      reg:
102        maxItems: 1
103        description: VDEC_MISC register space
104
105      interrupts:
106        maxItems: 1
107
108      iommus:
109        minItems: 1
110        maxItems: 32
111        description: |
112          List of the hardware port in respective IOMMU block for current Socs.
113          Refer to bindings/iommu/mediatek,iommu.yaml.
114
115      clocks:
116        minItems: 4
117        maxItems: 5
118
119      clock-names:
120        minItems: 4
121        maxItems: 5
122
123      assigned-clocks:
124        maxItems: 1
125
126      assigned-clock-parents:
127        maxItems: 1
128
129      power-domains:
130        maxItems: 1
131
132    required:
133      - compatible
134      - reg
135      - iommus
136      - clocks
137      - clock-names
138      - assigned-clocks
139      - assigned-clock-parents
140      - power-domains
141
142    additionalProperties: false
143
144required:
145  - compatible
146  - reg
147  - iommus
148  - mediatek,scp
149  - ranges
150
151if:
152  properties:
153    compatible:
154      contains:
155        enum:
156          - mediatek,mtk-vcodec-core
157          - mediatek,mtk-vcodec-lat
158
159then:
160  required:
161    - interrupts
162
163allOf:
164  - if:
165      properties:
166        compatible:
167          contains:
168            enum:
169              - mediatek,mt8192-vcodec-dec
170    then:
171      properties:
172        clock-names:
173          items:
174            - const: sel
175            - const: soc-vdec
176            - const: soc-lat
177            - const: vdec
178            - const: top
179
180  - if:
181      properties:
182        compatible:
183          contains:
184            enum:
185              - mediatek,mt8195-vcodec-dec
186    then:
187      properties:
188        clock-names:
189          items:
190            - const: sel
191            - const: vdec
192            - const: lat
193            - const: top
194
195additionalProperties: false
196
197examples:
198  - |
199    #include <dt-bindings/interrupt-controller/arm-gic.h>
200    #include <dt-bindings/memory/mt8192-larb-port.h>
201    #include <dt-bindings/interrupt-controller/irq.h>
202    #include <dt-bindings/clock/mt8192-clk.h>
203    #include <dt-bindings/power/mt8192-power.h>
204
205    bus@16000000 {
206        #address-cells = <2>;
207        #size-cells = <2>;
208        ranges = <0 0x16000000 0x16000000 0 0x40000>;
209
210        video-codec@16000000 {
211            compatible = "mediatek,mt8192-vcodec-dec";
212            mediatek,scp = <&scp>;
213            iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
214            #address-cells = <2>;
215            #size-cells = <2>;
216            ranges = <0 0 0 0x16000000 0 0x40000>;
217            reg = <0 0x16000000 0 0x1000>;		/* VDEC_SYS */
218            video-codec@10000 {
219                compatible = "mediatek,mtk-vcodec-lat";
220                reg = <0 0x10000 0 0x800>;
221                interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
222                iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
223                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
224                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
225                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
226                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
227                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
228                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
229                    <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
230                clocks = <&topckgen CLK_TOP_VDEC_SEL>,
231                    <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
232                    <&vdecsys_soc CLK_VDEC_SOC_LAT>,
233                    <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
234                    <&topckgen CLK_TOP_MAINPLL_D4>;
235                clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
236                assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
237                assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
238                power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
239            };
240
241            video-codec@25000 {
242                compatible = "mediatek,mtk-vcodec-core";
243                reg = <0 0x25000 0 0x1000>;
244                interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
245                iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
246                    <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
247                    <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
248                    <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
249                    <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
250                    <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
251                    <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
252                    <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
253                    <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
254                    <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
255                    <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
256                clocks = <&topckgen CLK_TOP_VDEC_SEL>,
257                    <&vdecsys CLK_VDEC_VDEC>,
258                    <&vdecsys CLK_VDEC_LAT>,
259                    <&vdecsys CLK_VDEC_LARB1>,
260                    <&topckgen CLK_TOP_MAINPLL_D4>;
261                clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
262                assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
263                assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
264                power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
265            };
266        };
267    };
268