1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/mediatek,vcodec-encoder.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek Video Encode Accelerator
8
9maintainers:
10  - Yunfei Dong <[email protected]>
11
12description: |+
13  Mediatek Video Encode is the video encode hardware present in Mediatek
14  SoCs which supports high resolution encoding functionalities.
15
16properties:
17  compatible:
18    oneOf:
19      - items:
20          - enum:
21              - mediatek,mt8173-vcodec-enc-vp8
22              - mediatek,mt8173-vcodec-enc
23              - mediatek,mt8183-vcodec-enc
24              - mediatek,mt8188-vcodec-enc
25              - mediatek,mt8192-vcodec-enc
26              - mediatek,mt8195-vcodec-enc
27      - items:
28          - const: mediatek,mt8186-vcodec-enc
29          - const: mediatek,mt8183-vcodec-enc
30  reg:
31    maxItems: 1
32
33  interrupts:
34    maxItems: 1
35
36  clocks:
37    minItems: 1
38    maxItems: 5
39
40  clock-names:
41    minItems: 1
42    maxItems: 5
43
44  assigned-clocks: true
45
46  assigned-clock-parents: true
47
48  iommus:
49    minItems: 1
50    maxItems: 32
51    description: |
52      List of the hardware port in respective IOMMU block for current Socs.
53      Refer to bindings/iommu/mediatek,iommu.yaml.
54
55  mediatek,vpu:
56    $ref: /schemas/types.yaml#/definitions/phandle
57    description:
58      Describes point to vpu.
59
60  mediatek,scp:
61    $ref: /schemas/types.yaml#/definitions/phandle
62    description:
63      Describes point to scp.
64
65  power-domains:
66    maxItems: 1
67
68  "#address-cells":
69    const: 2
70
71  "#size-cells":
72    const: 2
73
74required:
75  - compatible
76  - reg
77  - interrupts
78  - clocks
79  - clock-names
80  - iommus
81  - assigned-clocks
82  - assigned-clock-parents
83
84allOf:
85  - if:
86      properties:
87        compatible:
88          contains:
89            enum:
90              - mediatek,mt8183-vcodec-enc
91              - mediatek,mt8188-vcodec-enc
92              - mediatek,mt8192-vcodec-enc
93              - mediatek,mt8195-vcodec-enc
94
95    then:
96      required:
97        - mediatek,scp
98
99  - if:
100      properties:
101        compatible:
102          contains:
103            enum:
104              - mediatek,mt8173-vcodec-enc-vp8
105              - mediatek,mt8173-vcodec-enc
106
107    then:
108      required:
109        - mediatek,vpu
110
111  - if:
112      properties:
113        compatible:
114          enum:
115            - mediatek,mt8173-vcodec-enc-vp8
116
117    then:
118      properties:
119        clock:
120          items:
121            minItems: 1
122            maxItems: 1
123        clock-names:
124          items:
125            - const: venc_lt_sel
126    else:
127      properties:
128        clock:
129          items:
130            minItems: 1
131            maxItems: 1
132        clock-names:
133          items:
134            - const: venc_sel
135
136additionalProperties: false
137
138examples:
139  - |
140    #include <dt-bindings/interrupt-controller/arm-gic.h>
141    #include <dt-bindings/clock/mt8173-clk.h>
142    #include <dt-bindings/memory/mt8173-larb-port.h>
143    #include <dt-bindings/interrupt-controller/irq.h>
144
145    vcodec_enc_avc: vcodec@18002000 {
146      compatible = "mediatek,mt8173-vcodec-enc";
147      reg = <0x18002000 0x1000>;
148      interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
149      iommus = <&iommu M4U_PORT_VENC_RCPU>,
150             <&iommu M4U_PORT_VENC_REC>,
151             <&iommu M4U_PORT_VENC_BSDMA>,
152             <&iommu M4U_PORT_VENC_SV_COMV>,
153             <&iommu M4U_PORT_VENC_RD_COMV>,
154             <&iommu M4U_PORT_VENC_CUR_LUMA>,
155             <&iommu M4U_PORT_VENC_CUR_CHROMA>,
156             <&iommu M4U_PORT_VENC_REF_LUMA>,
157             <&iommu M4U_PORT_VENC_REF_CHROMA>,
158             <&iommu M4U_PORT_VENC_NBM_RDMA>,
159             <&iommu M4U_PORT_VENC_NBM_WDMA>;
160      mediatek,vpu = <&vpu>;
161      clocks = <&topckgen CLK_TOP_VENC_SEL>;
162      clock-names = "venc_sel";
163      assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
164      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
165    };
166
167    vcodec_enc_vp8: vcodec@19002000 {
168      compatible = "mediatek,mt8173-vcodec-enc-vp8";
169      reg =  <0x19002000 0x1000>;	/* VENC_LT_SYS */
170      interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
171      iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
172             <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
173             <&iommu M4U_PORT_VENC_BSDMA_SET2>,
174             <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
175             <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
176             <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
177             <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
178             <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
179             <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
180      mediatek,vpu = <&vpu>;
181      clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
182      clock-names = "venc_lt_sel";
183      assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
184      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
185    };
186