1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/dma/fsl,edma.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale enhanced Direct Memory Access(eDMA) Controller 8 9description: | 10 The eDMA channels have multiplex capability by programmable 11 memory-mapped registers. channels are split into two groups, called 12 DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed 13 by any channel of certain group, DMAMUX0 or DMAMUX1, but not both. 14 15maintainers: 16 - Peng Fan <[email protected]> 17 18properties: 19 compatible: 20 oneOf: 21 - enum: 22 - fsl,vf610-edma 23 - fsl,imx7ulp-edma 24 - fsl,imx8qm-edma 25 - fsl,imx8ulp-edma 26 - fsl,imx93-edma3 27 - fsl,imx93-edma4 28 - fsl,imx95-edma5 29 - nxp,s32g2-edma 30 - items: 31 - const: fsl,ls1028a-edma 32 - const: fsl,vf610-edma 33 - items: 34 - const: nxp,s32g3-edma 35 - const: nxp,s32g2-edma 36 37 reg: 38 minItems: 1 39 maxItems: 3 40 41 interrupts: 42 minItems: 1 43 maxItems: 64 44 45 interrupt-names: 46 minItems: 1 47 maxItems: 64 48 49 "#dma-cells": 50 description: | 51 Specifies the number of cells needed to encode an DMA channel. 52 53 Encode for cells number 2: 54 cell 0: index of dma channel mux instance. 55 cell 1: peripheral dma request id. 56 57 Encode for cells number 3: 58 cell 0: peripheral dma request id. 59 cell 1: dma channel priority. 60 cell 2: bitmask, defined at include/dt-bindings/dma/fsl-edma.h 61 enum: 62 - 2 63 - 3 64 65 dma-channels: 66 minimum: 1 67 maximum: 64 68 69 clocks: 70 minItems: 1 71 maxItems: 33 72 73 clock-names: 74 minItems: 1 75 maxItems: 33 76 77 power-domains: 78 description: 79 The number of power domains matches the number of channels, arranged 80 in ascending order according to their associated DMA channels. 81 minItems: 1 82 maxItems: 64 83 84 big-endian: 85 description: | 86 If present registers and hardware scatter/gather descriptors of the 87 eDMA are implemented in big endian mode, otherwise in little mode. 88 type: boolean 89 90required: 91 - "#dma-cells" 92 - compatible 93 - reg 94 - interrupts 95 - dma-channels 96 97allOf: 98 - $ref: dma-controller.yaml# 99 - if: 100 properties: 101 compatible: 102 contains: 103 enum: 104 - fsl,imx8qm-edma 105 - fsl,imx93-edma3 106 - fsl,imx93-edma4 107 - fsl,imx95-edma5 108 then: 109 properties: 110 "#dma-cells": 111 const: 3 112 # It is not necessary to write the interrupt name for each channel. 113 # instead, you can simply maintain the sequential IRQ numbers as 114 # defined for the DMA channels. 115 interrupt-names: false 116 clock-names: 117 items: 118 - const: dma 119 clocks: 120 maxItems: 1 121 122 - if: 123 properties: 124 compatible: 125 contains: 126 const: fsl,vf610-edma 127 then: 128 properties: 129 clocks: 130 minItems: 2 131 maxItems: 2 132 clock-names: 133 items: 134 - const: dmamux0 135 - const: dmamux1 136 interrupts: 137 minItems: 2 138 maxItems: 2 139 interrupt-names: 140 items: 141 - const: edma-tx 142 - const: edma-err 143 reg: 144 minItems: 2 145 maxItems: 3 146 "#dma-cells": 147 const: 2 148 dma-channels: 149 const: 32 150 151 - if: 152 properties: 153 compatible: 154 contains: 155 const: fsl,imx7ulp-edma 156 then: 157 properties: 158 clock: 159 minItems: 2 160 maxItems: 2 161 clock-names: 162 items: 163 - const: dma 164 - const: dmamux0 165 interrupts: 166 minItems: 2 167 maxItems: 17 168 reg: 169 minItems: 2 170 maxItems: 2 171 "#dma-cells": 172 const: 2 173 dma-channels: 174 const: 32 175 176 - if: 177 properties: 178 compatible: 179 contains: 180 const: fsl,imx8ulp-edma 181 then: 182 properties: 183 clocks: 184 minItems: 33 185 clock-names: 186 minItems: 33 187 items: 188 oneOf: 189 - const: dma 190 - pattern: "^ch(0[0-9]|[1-2][0-9]|3[01])$" 191 192 interrupt-names: false 193 interrupts: 194 minItems: 32 195 "#dma-cells": 196 const: 3 197 198 - if: 199 properties: 200 compatible: 201 contains: 202 enum: 203 - fsl,vf610-edma 204 - fsl,imx7ulp-edma 205 - fsl,imx93-edma3 206 - fsl,imx93-edma4 207 - fsl,imx95-edma5 208 - fsl,imx8ulp-edma 209 - fsl,ls1028a-edma 210 then: 211 required: 212 - clocks 213 214 - if: 215 properties: 216 compatible: 217 contains: 218 enum: 219 - fsl,imx8qm-adma 220 - fsl,imx8qm-edma 221 then: 222 required: 223 - power-domains 224 else: 225 properties: 226 power-domains: false 227 228 - if: 229 properties: 230 compatible: 231 contains: 232 const: nxp,s32g2-edma 233 then: 234 properties: 235 clocks: 236 minItems: 2 237 maxItems: 2 238 clock-names: 239 items: 240 - const: dmamux0 241 - const: dmamux1 242 interrupts: 243 minItems: 3 244 maxItems: 3 245 interrupt-names: 246 items: 247 - const: tx-0-15 248 - const: tx-16-31 249 - const: err 250 reg: 251 minItems: 3 252 maxItems: 3 253 "#dma-cells": 254 const: 2 255 dma-channels: 256 const: 32 257 258unevaluatedProperties: false 259 260examples: 261 - | 262 #include <dt-bindings/interrupt-controller/arm-gic.h> 263 #include <dt-bindings/clock/vf610-clock.h> 264 265 edma0: dma-controller@40018000 { 266 #dma-cells = <2>; 267 compatible = "fsl,vf610-edma"; 268 reg = <0x40018000 0x2000>, 269 <0x40024000 0x1000>, 270 <0x40025000 0x1000>; 271 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, 272 <0 9 IRQ_TYPE_LEVEL_HIGH>; 273 interrupt-names = "edma-tx", "edma-err"; 274 dma-channels = <32>; 275 clock-names = "dmamux0", "dmamux1"; 276 clocks = <&clks VF610_CLK_DMAMUX0>, <&clks VF610_CLK_DMAMUX1>; 277 }; 278 279 - | 280 #include <dt-bindings/interrupt-controller/arm-gic.h> 281 #include <dt-bindings/clock/imx7ulp-clock.h> 282 283 edma1: dma-controller@40080000 { 284 #dma-cells = <2>; 285 compatible = "fsl,imx7ulp-edma"; 286 reg = <0x40080000 0x2000>, 287 <0x40210000 0x1000>; 288 dma-channels = <32>; 289 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 305 /* last is eDMA2-ERR interrupt */ 306 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 307 clock-names = "dma", "dmamux0"; 308 clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>; 309 }; 310 311 - | 312 #include <dt-bindings/interrupt-controller/arm-gic.h> 313 #include <dt-bindings/firmware/imx/rsrc.h> 314 315 dma-controller@5a9f0000 { 316 compatible = "fsl,imx8qm-edma"; 317 reg = <0x5a9f0000 0x90000>; 318 #dma-cells = <3>; 319 dma-channels = <8>; 320 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>; 328 power-domains = <&pd IMX_SC_R_DMA_3_CH0>, 329 <&pd IMX_SC_R_DMA_3_CH1>, 330 <&pd IMX_SC_R_DMA_3_CH2>, 331 <&pd IMX_SC_R_DMA_3_CH3>, 332 <&pd IMX_SC_R_DMA_3_CH4>, 333 <&pd IMX_SC_R_DMA_3_CH5>, 334 <&pd IMX_SC_R_DMA_3_CH6>, 335 <&pd IMX_SC_R_DMA_3_CH7>; 336 }; 337