1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/atmel,sama5d4-dma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip AT91 Extensible Direct Memory Access Controller
8
9maintainers:
10  - Nicolas Ferre <[email protected]>
11  - Charan Pedumuru <[email protected]>
12
13description:
14  The DMA Controller (XDMAC) is a AHB-protocol central direct memory access
15  controller. It performs peripheral data transfer and memory move operations
16  over one or two bus ports through the unidirectional communication
17  channel. Each channel is fully programmable and provides both peripheral
18  or memory-to-memory transfers. The channel features are configurable at
19  implementation.
20
21allOf:
22  - $ref: dma-controller.yaml#
23
24properties:
25  compatible:
26    oneOf:
27      - enum:
28          - atmel,sama5d4-dma
29          - microchip,sama7g5-dma
30      - items:
31          - enum:
32              - microchip,sam9x60-dma
33              - microchip,sam9x7-dma
34          - const: atmel,sama5d4-dma
35
36  "#dma-cells":
37    description: |
38      Represents the number of integer cells in the `dmas` property of client
39      devices. The single cell specifies the channel configuration register:
40        - bit 13: SIF (Source Interface Identifier) for memory interface.
41        - bit 14: DIF (Destination Interface Identifier) for peripheral interface.
42        - bit 30-24: PERID (Peripheral Identifier).
43    const: 1
44
45  reg:
46    maxItems: 1
47
48  interrupts:
49    maxItems: 1
50
51  clocks:
52    maxItems: 1
53
54  clock-names:
55    const: dma_clk
56
57required:
58  - compatible
59  - reg
60  - interrupts
61  - clocks
62  - clock-names
63  - "#dma-cells"
64
65unevaluatedProperties: false
66
67examples:
68  - |
69    #include <dt-bindings/clock/at91.h>
70    #include <dt-bindings/dma/at91.h>
71    #include <dt-bindings/interrupt-controller/irq.h>
72    dma-controller@f0008000 {
73        compatible = "atmel,sama5d4-dma";
74        reg = <0xf0008000 0x1000>;
75        interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
76        #dma-cells = <1>;
77        clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
78        clock-names = "dma_clk";
79    };
80