1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display color processor
8
9maintainers:
10  - Chun-Kuang Hu <[email protected]>
11  - Philipp Zabel <[email protected]>
12
13description: |
14  Mediatek display color processor, namely COLOR, provides hue, luma and
15  saturation adjustments to get better picture quality and to have one panel
16  resemble the other in their output characteristics.
17  COLOR device node must be siblings to the central MMSYS_CONFIG node.
18  For a description of the MMSYS_CONFIG binding, see
19  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
20  for details.
21
22properties:
23  compatible:
24    oneOf:
25      - enum:
26          - mediatek,mt2701-disp-color
27          - mediatek,mt8167-disp-color
28          - mediatek,mt8173-disp-color
29          - mediatek,mt8195-mdp3-color
30      - items:
31          - enum:
32              - mediatek,mt7623-disp-color
33              - mediatek,mt2712-disp-color
34          - const: mediatek,mt2701-disp-color
35      - items:
36          - enum:
37              - mediatek,mt6795-disp-color
38              - mediatek,mt8183-disp-color
39              - mediatek,mt8186-disp-color
40              - mediatek,mt8188-disp-color
41              - mediatek,mt8192-disp-color
42              - mediatek,mt8195-disp-color
43              - mediatek,mt8365-disp-color
44          - const: mediatek,mt8173-disp-color
45  reg:
46    maxItems: 1
47
48  interrupts:
49    maxItems: 1
50
51  power-domains:
52    description: A phandle and PM domain specifier as defined by bindings of
53      the power controller specified by phandle. See
54      Documentation/devicetree/bindings/power/power-domain.yaml for details.
55
56  clocks:
57    items:
58      - description: COLOR Clock
59
60  mediatek,gce-client-reg:
61    description: The register of client driver can be configured by gce with
62      4 arguments defined in this property, such as phandle of gce, subsys id,
63      register offset and size. Each GCE subsys id is mapping to a client
64      defined in the header include/dt-bindings/gce/<chip>-gce.h.
65    $ref: /schemas/types.yaml#/definitions/phandle-array
66    maxItems: 1
67
68  ports:
69    $ref: /schemas/graph.yaml#/properties/ports
70    description:
71      Input and output ports can have multiple endpoints, each of those
72      connects to either the primary, secondary, etc, display pipeline.
73
74    properties:
75      port@0:
76        $ref: /schemas/graph.yaml#/properties/port
77        description: COLOR input port
78
79      port@1:
80        $ref: /schemas/graph.yaml#/properties/port
81        description:
82          COLOR output to the input of the next desired component in the
83          display pipeline, for example one of the available CCORR or AAL
84          blocks.
85
86    required:
87      - port@0
88      - port@1
89
90required:
91  - compatible
92  - reg
93  - interrupts
94  - power-domains
95  - clocks
96
97additionalProperties: false
98
99examples:
100  - |
101    #include <dt-bindings/interrupt-controller/arm-gic.h>
102    #include <dt-bindings/clock/mt8173-clk.h>
103    #include <dt-bindings/power/mt8173-power.h>
104    #include <dt-bindings/gce/mt8173-gce.h>
105
106    soc {
107        #address-cells = <2>;
108        #size-cells = <2>;
109
110        color0: color@14013000 {
111            compatible = "mediatek,mt8173-disp-color";
112            reg = <0 0x14013000 0 0x1000>;
113            interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
114            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
115            clocks = <&mmsys CLK_MM_DISP_COLOR0>;
116            mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
117        };
118    };
119