1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas R-Car MIPI DSI/CSI-2 Encoder
8
9maintainers:
10  - Laurent Pinchart <[email protected]>
11
12description: |
13  This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
14  R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up
15  to four data lanes.
16
17properties:
18  compatible:
19    enum:
20      - renesas,r8a779a0-dsi-csi2-tx    # for V3U
21      - renesas,r8a779g0-dsi-csi2-tx    # for V4H
22      - renesas,r8a779h0-dsi-csi2-tx    # for V4M
23
24  reg:
25    maxItems: 1
26
27  clocks:
28    items:
29      - description: Functional clock
30      - description: DSI (and CSI-2) functional clock
31      - description: PLL reference clock
32
33  clock-names:
34    items:
35      - const: fck
36      - const: dsi
37      - const: pll
38
39  power-domains:
40    maxItems: 1
41
42  resets:
43    maxItems: 1
44
45  ports:
46    $ref: /schemas/graph.yaml#/properties/ports
47
48    properties:
49      port@0:
50        $ref: /schemas/graph.yaml#/properties/port
51        description: Parallel input port
52
53      port@1:
54        $ref: /schemas/graph.yaml#/$defs/port-base
55        unevaluatedProperties: false
56        description: DSI/CSI-2 output port
57
58        properties:
59          endpoint:
60            $ref: /schemas/media/video-interfaces.yaml#
61            unevaluatedProperties: false
62
63            properties:
64              data-lanes:
65                minItems: 1
66                maxItems: 4
67
68            required:
69              - data-lanes
70
71    required:
72      - port@0
73      - port@1
74
75required:
76  - compatible
77  - reg
78  - clocks
79  - power-domains
80  - resets
81  - ports
82
83additionalProperties: false
84
85examples:
86  - |
87    #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
88    #include <dt-bindings/power/r8a779a0-sysc.h>
89
90    dsi0: dsi-encoder@fed80000 {
91        compatible = "renesas,r8a779a0-dsi-csi2-tx";
92        reg = <0xfed80000 0x10000>;
93        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
94        clocks = <&cpg CPG_MOD 415>,
95                 <&cpg CPG_CORE R8A779A0_CLK_DSI>,
96                 <&cpg CPG_CORE R8A779A0_CLK_CP>;
97        clock-names = "fck", "dsi", "pll";
98        resets = <&cpg 415>;
99
100        ports {
101            #address-cells = <1>;
102            #size-cells = <0>;
103
104            port@0 {
105                reg = <0>;
106                dsi0_in: endpoint {
107                    remote-endpoint = <&du_out_dsi0>;
108                };
109            };
110
111            port@1 {
112                reg = <1>;
113                dsi0_out: endpoint {
114                    data-lanes = <1 2>;
115                    remote-endpoint = <&sn65dsi86_in>;
116                };
117            };
118        };
119    };
120...
121