1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Graphics Clock & Reset Controller on SM8450
8
9maintainers:
10  - Konrad Dybcio <[email protected]>
11
12description: |
13  Qualcomm graphics clock control module provides the clocks, resets and power
14  domains on Qualcomm SoCs.
15
16  See also::
17    include/dt-bindings/clock/qcom,sar2130p-gpucc.h
18    include/dt-bindings/clock/qcom,sm4450-gpucc.h
19    include/dt-bindings/clock/qcom,sm8450-gpucc.h
20    include/dt-bindings/clock/qcom,sm8550-gpucc.h
21    include/dt-bindings/reset/qcom,sm8450-gpucc.h
22    include/dt-bindings/reset/qcom,sm8650-gpucc.h
23    include/dt-bindings/reset/qcom,x1e80100-gpucc.h
24
25properties:
26  compatible:
27    enum:
28      - qcom,sar2130p-gpucc
29      - qcom,sm4450-gpucc
30      - qcom,sm8450-gpucc
31      - qcom,sm8475-gpucc
32      - qcom,sm8550-gpucc
33      - qcom,sm8650-gpucc
34      - qcom,x1e80100-gpucc
35      - qcom,x1p42100-gpucc
36
37  clocks:
38    items:
39      - description: Board XO source
40      - description: GPLL0 main branch source
41      - description: GPLL0 div branch source
42
43required:
44  - compatible
45  - clocks
46  - '#power-domain-cells'
47
48allOf:
49  - $ref: qcom,gcc.yaml#
50
51unevaluatedProperties: false
52
53examples:
54  - |
55    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
56    #include <dt-bindings/clock/qcom,rpmh.h>
57
58    soc {
59        #address-cells = <2>;
60        #size-cells = <2>;
61
62        clock-controller@3d90000 {
63            compatible = "qcom,sm8450-gpucc";
64            reg = <0 0x03d90000 0 0xa000>;
65            clocks = <&rpmhcc RPMH_CXO_CLK>,
66                     <&gcc GCC_GPU_GPLL0_CLK_SRC>,
67                     <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
68            #clock-cells = <1>;
69            #reset-cells = <1>;
70            #power-domain-cells = <1>;
71        };
72    };
73...
74