1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Graphics Clock & Reset Controller 8 9maintainers: 10 - Taniya Das <[email protected]> 11 - Imran Shaik <[email protected]> 12 13description: | 14 Qualcomm graphics clock control module provides the clocks, resets and power 15 domains on Qualcomm SoCs. 16 17 See also:: 18 include/dt-bindings/clock/qcom,gpucc-sdm845.h 19 include/dt-bindings/clock/qcom,gpucc-sa8775p.h 20 include/dt-bindings/clock/qcom,gpucc-sc7180.h 21 include/dt-bindings/clock/qcom,gpucc-sc7280.h 22 include/dt-bindings/clock/qcom,gpucc-sc8280xp.h 23 include/dt-bindings/clock/qcom,gpucc-sm6350.h 24 include/dt-bindings/clock/qcom,gpucc-sm8150.h 25 include/dt-bindings/clock/qcom,gpucc-sm8250.h 26 include/dt-bindings/clock/qcom,gpucc-sm8350.h 27 include/dt-bindings/clock/qcom,qcs8300-gpucc.h 28 29properties: 30 compatible: 31 enum: 32 - qcom,qcs8300-gpucc 33 - qcom,sdm845-gpucc 34 - qcom,sa8775p-gpucc 35 - qcom,sc7180-gpucc 36 - qcom,sc7280-gpucc 37 - qcom,sc8180x-gpucc 38 - qcom,sc8280xp-gpucc 39 - qcom,sm6350-gpucc 40 - qcom,sm8150-gpucc 41 - qcom,sm8250-gpucc 42 - qcom,sm8350-gpucc 43 44 clocks: 45 items: 46 - description: Board XO source 47 - description: GPLL0 main branch source 48 - description: GPLL0 div branch source 49 50 clock-names: 51 items: 52 - const: bi_tcxo 53 - const: gcc_gpu_gpll0_clk_src 54 - const: gcc_gpu_gpll0_div_clk_src 55 56 power-domains: 57 maxItems: 1 58 59 vdd-gfx-supply: 60 description: Regulator supply for the VDD_GFX pads 61 62required: 63 - compatible 64 - clocks 65 - clock-names 66 - '#power-domain-cells' 67 68# Require that power-domains and vdd-gfx-supply are not both present 69not: 70 required: 71 - power-domains 72 - vdd-gfx-supply 73 74allOf: 75 - $ref: qcom,gcc.yaml# 76 77unevaluatedProperties: false 78 79examples: 80 - | 81 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 82 #include <dt-bindings/clock/qcom,rpmh.h> 83 clock-controller@5090000 { 84 compatible = "qcom,sdm845-gpucc"; 85 reg = <0x05090000 0x9000>; 86 clocks = <&rpmhcc RPMH_CXO_CLK>, 87 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 88 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 89 clock-names = "bi_tcxo", 90 "gcc_gpu_gpll0_clk_src", 91 "gcc_gpu_gpll0_div_clk_src"; 92 #clock-cells = <1>; 93 #reset-cells = <1>; 94 #power-domain-cells = <1>; 95 }; 96... 97