1===================================================================
2Marvell Odyssey DDR PMU Performance Monitoring Unit (PMU UNCORE)
3===================================================================
4
5Odyssey DRAM Subsystem supports eight counters for monitoring performance
6and software can program those counters to monitor any of the defined
7performance events. Supported performance events include those counted
8at the interface between the DDR controller and the PHY, interface between
9the DDR Controller and the CHI interconnect, or within the DDR Controller.
10
11Additionally DSS also supports two fixed performance event counters, one
12for ddr reads and the other for ddr writes.
13
14The counter will be operating in either manual or auto mode.
15
16The PMU driver exposes the available events and format options under sysfs::
17
18        /sys/bus/event_source/devices/mrvl_ddr_pmu_<>/events/
19        /sys/bus/event_source/devices/mrvl_ddr_pmu_<>/format/
20
21Examples::
22
23        $ perf list | grep ddr
24        mrvl_ddr_pmu_<>/ddr_act_bypass_access/   [Kernel PMU event]
25        mrvl_ddr_pmu_<>/ddr_bsm_alloc/           [Kernel PMU event]
26        mrvl_ddr_pmu_<>/ddr_bsm_starvation/      [Kernel PMU event]
27        mrvl_ddr_pmu_<>/ddr_cam_active_access/   [Kernel PMU event]
28        mrvl_ddr_pmu_<>/ddr_cam_mwr/             [Kernel PMU event]
29        mrvl_ddr_pmu_<>/ddr_cam_rd_active_access/ [Kernel PMU event]
30        mrvl_ddr_pmu_<>/ddr_cam_rd_or_wr_access/ [Kernel PMU event]
31        mrvl_ddr_pmu_<>/ddr_cam_read/            [Kernel PMU event]
32        mrvl_ddr_pmu_<>/ddr_cam_wr_access/       [Kernel PMU event]
33        mrvl_ddr_pmu_<>/ddr_cam_write/           [Kernel PMU event]
34        mrvl_ddr_pmu_<>/ddr_capar_error/         [Kernel PMU event]
35        mrvl_ddr_pmu_<>/ddr_crit_ref/            [Kernel PMU event]
36        mrvl_ddr_pmu_<>/ddr_ddr_reads/           [Kernel PMU event]
37        mrvl_ddr_pmu_<>/ddr_ddr_writes/          [Kernel PMU event]
38        mrvl_ddr_pmu_<>/ddr_dfi_cmd_is_retry/    [Kernel PMU event]
39        mrvl_ddr_pmu_<>/ddr_dfi_cycles/          [Kernel PMU event]
40        mrvl_ddr_pmu_<>/ddr_dfi_parity_poison/   [Kernel PMU event]
41        mrvl_ddr_pmu_<>/ddr_dfi_rd_data_access/  [Kernel PMU event]
42        mrvl_ddr_pmu_<>/ddr_dfi_wr_data_access/  [Kernel PMU event]
43        mrvl_ddr_pmu_<>/ddr_dqsosc_mpc/          [Kernel PMU event]
44        mrvl_ddr_pmu_<>/ddr_dqsosc_mrr/          [Kernel PMU event]
45        mrvl_ddr_pmu_<>/ddr_enter_mpsm/          [Kernel PMU event]
46        mrvl_ddr_pmu_<>/ddr_enter_powerdown/     [Kernel PMU event]
47        mrvl_ddr_pmu_<>/ddr_enter_selfref/       [Kernel PMU event]
48        mrvl_ddr_pmu_<>/ddr_hif_pri_rdaccess/    [Kernel PMU event]
49        mrvl_ddr_pmu_<>/ddr_hif_rd_access/       [Kernel PMU event]
50        mrvl_ddr_pmu_<>/ddr_hif_rd_or_wr_access/ [Kernel PMU event]
51        mrvl_ddr_pmu_<>/ddr_hif_rmw_access/      [Kernel PMU event]
52        mrvl_ddr_pmu_<>/ddr_hif_wr_access/       [Kernel PMU event]
53        mrvl_ddr_pmu_<>/ddr_hpri_sched_rd_crit_access/ [Kernel PMU event]
54        mrvl_ddr_pmu_<>/ddr_load_mode/           [Kernel PMU event]
55        mrvl_ddr_pmu_<>/ddr_lpri_sched_rd_crit_access/ [Kernel PMU event]
56        mrvl_ddr_pmu_<>/ddr_precharge/           [Kernel PMU event]
57        mrvl_ddr_pmu_<>/ddr_precharge_for_other/ [Kernel PMU event]
58        mrvl_ddr_pmu_<>/ddr_precharge_for_rdwr/  [Kernel PMU event]
59        mrvl_ddr_pmu_<>/ddr_raw_hazard/          [Kernel PMU event]
60        mrvl_ddr_pmu_<>/ddr_rd_bypass_access/    [Kernel PMU event]
61        mrvl_ddr_pmu_<>/ddr_rd_crc_error/        [Kernel PMU event]
62        mrvl_ddr_pmu_<>/ddr_rd_uc_ecc_error/     [Kernel PMU event]
63        mrvl_ddr_pmu_<>/ddr_rdwr_transitions/    [Kernel PMU event]
64        mrvl_ddr_pmu_<>/ddr_refresh/             [Kernel PMU event]
65        mrvl_ddr_pmu_<>/ddr_retry_fifo_full/     [Kernel PMU event]
66        mrvl_ddr_pmu_<>/ddr_spec_ref/            [Kernel PMU event]
67        mrvl_ddr_pmu_<>/ddr_tcr_mrr/             [Kernel PMU event]
68        mrvl_ddr_pmu_<>/ddr_war_hazard/          [Kernel PMU event]
69        mrvl_ddr_pmu_<>/ddr_waw_hazard/          [Kernel PMU event]
70        mrvl_ddr_pmu_<>/ddr_win_limit_reached_rd/ [Kernel PMU event]
71        mrvl_ddr_pmu_<>/ddr_win_limit_reached_wr/ [Kernel PMU event]
72        mrvl_ddr_pmu_<>/ddr_wr_crc_error/        [Kernel PMU event]
73        mrvl_ddr_pmu_<>/ddr_wr_trxn_crit_access/ [Kernel PMU event]
74        mrvl_ddr_pmu_<>/ddr_write_combine/       [Kernel PMU event]
75        mrvl_ddr_pmu_<>/ddr_zqcl/                [Kernel PMU event]
76        mrvl_ddr_pmu_<>/ddr_zqlatch/             [Kernel PMU event]
77        mrvl_ddr_pmu_<>/ddr_zqstart/             [Kernel PMU event]
78
79        $ perf stat -e ddr_cam_read,ddr_cam_write,ddr_cam_active_access,ddr_cam
80          rd_or_wr_access,ddr_cam_rd_active_access,ddr_cam_mwr <workload>
81