1 /**
2 ******************************************************************************
3 * File Name : hw_lpm.c
4 * Description : Hardware Low Power Mode source file for BLE
5 * middleWare.
6 ******************************************************************************
7 * This notice applies to any and all portions of this file
8 * that are not between comment pairs USER CODE BEGIN and
9 * USER CODE END. Other portions of this file, whether
10 * inserted by the user or by software development tools
11 * are owned by their respective copyright owners.
12 *
13 * Copyright (c) 2019 STMicroelectronics International N.V.
14 * All rights reserved.
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted, provided that the following conditions are met:
18 *
19 * 1. Redistribution of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials provided with the distribution.
24 * 3. Neither the name of STMicroelectronics nor the names of other
25 * contributors to this software may be used to endorse or promote products
26 * derived from this software without specific written permission.
27 * 4. This software, including modifications and/or derivative works of this
28 * software, must execute solely and exclusively on microcontroller or
29 * microprocessor devices manufactured by or for STMicroelectronics.
30 * 5. Redistribution and use of this software other than as permitted under
31 * this license is void and will automatically terminate your rights under
32 * this license.
33 *
34 * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
35 * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
37 * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
38 * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
39 * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
40 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
41 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
42 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
43 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
44 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
45 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
46 *
47 ******************************************************************************
48 */
49
50 /* Includes ------------------------------------------------------------------*/
51 #include "app_conf.h"
52 #include "hw_conf.h"
53
54 /* Private const -----------------------------------------------------------*/
55 const uint32_t HW_LPM_STOP_MODE[3] = {LL_PWR_MODE_STOP0, LL_PWR_MODE_STOP1, LL_PWR_MODE_STOP2};
56 const uint32_t HW_LPM_OFF_MODE[2] = {LL_PWR_MODE_STANDBY, LL_PWR_MODE_SHUTDOWN};
57
HW_LPM_SleepMode(void)58 void HW_LPM_SleepMode(void)
59 {
60 LL_LPM_EnableSleep(); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
61
62 /**
63 * This option is used to ensure that store operations are completed
64 */
65 #if defined ( __CC_ARM)
66 __force_stores();
67 #endif
68
69 __WFI();
70
71 return;
72 }
73
HW_LPM_StopMode(HW_LPM_StopModeConf_t configuration)74 void HW_LPM_StopMode(HW_LPM_StopModeConf_t configuration)
75 {
76 LL_PWR_SetPowerMode(HW_LPM_STOP_MODE[configuration]);
77
78 LL_LPM_EnableDeepSleep(); /**< Set SLEEPDEEP bit of Cortex System Control Register */
79
80 /**
81 * This option is used to ensure that store operations are completed
82 */
83 #if defined ( __CC_ARM)
84 __force_stores();
85 #endif
86
87 __WFI();
88
89 return;
90 }
91
HW_LPM_OffMode(HW_LPM_OffModeConf_t configuration)92 void HW_LPM_OffMode(HW_LPM_OffModeConf_t configuration)
93 {
94 /*
95 * There is no risk to clear all the WUF here because in the current implementation, this API is called
96 * in critical section. If an interrupt occurs while in that critical section before that point,
97 * the flag is set and will be cleared here but the system will not enter Off Mode
98 * because an interrupt is pending in the NVIC. The ISR will be executed when moving out
99 * of this critical section
100 */
101 LL_PWR_ClearFlag_WU();
102
103 LL_PWR_SetPowerMode(HW_LPM_OFF_MODE[configuration]);
104
105 LL_LPM_EnableDeepSleep(); /**< Set SLEEPDEEP bit of Cortex System Control Register */
106
107 /**
108 * This option is used to ensure that store operations are completed
109 */
110 #if defined ( __CC_ARM)
111 __force_stores();
112 #endif
113
114 __WFI();
115
116 return;
117 }
118
119 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
120