xref: /btstack/port/stm32-wb55xx-nucleo-freertos/Inc/app_conf.h (revision 0561b2d8d5dba972c7daa57d5e677f7a1327edfd)
1*0561b2d8STREFOU Felix /**
2*0561b2d8STREFOU Felix  ******************************************************************************
3*0561b2d8STREFOU Felix   * File Name          : app_conf.h
4*0561b2d8STREFOU Felix   * Description        : Application configuration file for STM32WPAN Middleware.
5*0561b2d8STREFOU Felix   *
6*0561b2d8STREFOU Felix  ******************************************************************************
7*0561b2d8STREFOU Felix   * @attention
8*0561b2d8STREFOU Felix   *
9*0561b2d8STREFOU Felix   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
10*0561b2d8STREFOU Felix   * All rights reserved.</center></h2>
11*0561b2d8STREFOU Felix   *
12*0561b2d8STREFOU Felix   * This software component is licensed by ST under Ultimate Liberty license
13*0561b2d8STREFOU Felix   * SLA0044, the "License"; You may not use this file except in compliance with
14*0561b2d8STREFOU Felix   * the License. You may obtain a copy of the License at:
15*0561b2d8STREFOU Felix   *                             www.st.com/SLA0044
16*0561b2d8STREFOU Felix   *
17*0561b2d8STREFOU Felix   ******************************************************************************
18*0561b2d8STREFOU Felix   */
19*0561b2d8STREFOU Felix 
20*0561b2d8STREFOU Felix /* Define to prevent recursive inclusion -------------------------------------*/
21*0561b2d8STREFOU Felix #ifndef APP_CONF_H
22*0561b2d8STREFOU Felix #define APP_CONF_H
23*0561b2d8STREFOU Felix 
24*0561b2d8STREFOU Felix #include "hw.h"
25*0561b2d8STREFOU Felix #include "hw_conf.h"
26*0561b2d8STREFOU Felix #include "hw_if.h"
27*0561b2d8STREFOU Felix 
28*0561b2d8STREFOU Felix /******************************************************************************
29*0561b2d8STREFOU Felix  * BLE Stack
30*0561b2d8STREFOU Felix  ******************************************************************************/
31*0561b2d8STREFOU Felix /**
32*0561b2d8STREFOU Felix  * Maximum number of simultaneous connections that the device will support.
33*0561b2d8STREFOU Felix  * Valid values are from 1 to 8
34*0561b2d8STREFOU Felix  */
35*0561b2d8STREFOU Felix #define CFG_BLE_NUM_LINK            8
36*0561b2d8STREFOU Felix 
37*0561b2d8STREFOU Felix /**
38*0561b2d8STREFOU Felix  * Maximum number of Services that can be stored in the GATT database.
39*0561b2d8STREFOU Felix  * Note that the GAP and GATT services are automatically added so this parameter should be 2 plus the number of user services
40*0561b2d8STREFOU Felix  */
41*0561b2d8STREFOU Felix #define CFG_BLE_NUM_GATT_SERVICES   8
42*0561b2d8STREFOU Felix 
43*0561b2d8STREFOU Felix /**
44*0561b2d8STREFOU Felix  * Maximum number of Attributes
45*0561b2d8STREFOU Felix  * (i.e. the number of characteristic + the number of characteristic values + the number of descriptors, excluding the services)
46*0561b2d8STREFOU Felix  * that can be stored in the GATT database.
47*0561b2d8STREFOU Felix  * Note that certain characteristics and relative descriptors are added automatically during device initialization
48*0561b2d8STREFOU Felix  * so this parameters should be 9 plus the number of user Attributes
49*0561b2d8STREFOU Felix  */
50*0561b2d8STREFOU Felix #define CFG_BLE_NUM_GATT_ATTRIBUTES 68
51*0561b2d8STREFOU Felix 
52*0561b2d8STREFOU Felix /**
53*0561b2d8STREFOU Felix  * Maximum supported ATT_MTU size
54*0561b2d8STREFOU Felix  */
55*0561b2d8STREFOU Felix #define CFG_BLE_MAX_ATT_MTU             (156)
56*0561b2d8STREFOU Felix 
57*0561b2d8STREFOU Felix /**
58*0561b2d8STREFOU Felix  * Size of the storage area for Attribute values
59*0561b2d8STREFOU Felix  *  This value depends on the number of attributes used by application. In particular the sum of the following quantities (in octets) should be made for each attribute:
60*0561b2d8STREFOU Felix  *  - attribute value length
61*0561b2d8STREFOU Felix  *  - 5, if UUID is 16 bit; 19, if UUID is 128 bit
62*0561b2d8STREFOU Felix  *  - 2, if server configuration descriptor is used
63*0561b2d8STREFOU Felix  *  - 2*DTM_NUM_LINK, if client configuration descriptor is used
64*0561b2d8STREFOU Felix  *  - 2, if extended properties is used
65*0561b2d8STREFOU Felix  *  The total amount of memory needed is the sum of the above quantities for each attribute.
66*0561b2d8STREFOU Felix  */
67*0561b2d8STREFOU Felix #define CFG_BLE_ATT_VALUE_ARRAY_SIZE    (1344)
68*0561b2d8STREFOU Felix 
69*0561b2d8STREFOU Felix /**
70*0561b2d8STREFOU Felix  * Prepare Write List size in terms of number of packet with ATT_MTU=23 bytes
71*0561b2d8STREFOU Felix  */
72*0561b2d8STREFOU Felix #define CFG_BLE_PREPARE_WRITE_LIST_SIZE         ( 0x3A )
73*0561b2d8STREFOU Felix 
74*0561b2d8STREFOU Felix /**
75*0561b2d8STREFOU Felix  * Number of allocated memory blocks
76*0561b2d8STREFOU Felix  */
77*0561b2d8STREFOU Felix #define CFG_BLE_MBLOCK_COUNT            ( 0x79 )
78*0561b2d8STREFOU Felix 
79*0561b2d8STREFOU Felix /**
80*0561b2d8STREFOU Felix  * Enable or disable the Extended Packet length feature. Valid values are 0 or 1.
81*0561b2d8STREFOU Felix  */
82*0561b2d8STREFOU Felix #define CFG_BLE_DATA_LENGTH_EXTENSION   1
83*0561b2d8STREFOU Felix 
84*0561b2d8STREFOU Felix /**
85*0561b2d8STREFOU Felix  * Sleep clock accuracy in Slave mode (ppm value)
86*0561b2d8STREFOU Felix  */
87*0561b2d8STREFOU Felix #define CFG_BLE_SLAVE_SCA   500
88*0561b2d8STREFOU Felix 
89*0561b2d8STREFOU Felix /**
90*0561b2d8STREFOU Felix  * Sleep clock accuracy in Master mode
91*0561b2d8STREFOU Felix  * 0 : 251 ppm to 500 ppm
92*0561b2d8STREFOU Felix  * 1 : 151 ppm to 250 ppm
93*0561b2d8STREFOU Felix  * 2 : 101 ppm to 150 ppm
94*0561b2d8STREFOU Felix  * 3 : 76 ppm to 100 ppm
95*0561b2d8STREFOU Felix  * 4 : 51 ppm to 75 ppm
96*0561b2d8STREFOU Felix  * 5 : 31 ppm to 50 ppm
97*0561b2d8STREFOU Felix  * 6 : 21 ppm to 30 ppm
98*0561b2d8STREFOU Felix  * 7 : 0 ppm to 20 ppm
99*0561b2d8STREFOU Felix  */
100*0561b2d8STREFOU Felix #define CFG_BLE_MASTER_SCA   0
101*0561b2d8STREFOU Felix 
102*0561b2d8STREFOU Felix /**
103*0561b2d8STREFOU Felix  *  Source for the 32 kHz slow speed clock
104*0561b2d8STREFOU Felix  *  1 : internal RO
105*0561b2d8STREFOU Felix  *  0 : external crystal ( no calibration )
106*0561b2d8STREFOU Felix  */
107*0561b2d8STREFOU Felix #define CFG_BLE_LSE_SOURCE  0
108*0561b2d8STREFOU Felix 
109*0561b2d8STREFOU Felix /**
110*0561b2d8STREFOU Felix  * Start up time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 us (~2.44 us)
111*0561b2d8STREFOU Felix  */
112*0561b2d8STREFOU Felix #define CFG_BLE_HSE_STARTUP_TIME  0x148
113*0561b2d8STREFOU Felix 
114*0561b2d8STREFOU Felix /**
115*0561b2d8STREFOU Felix  * Maximum duration of the connection event when the device is in Slave mode in units of 625/256 us (~2.44 us)
116*0561b2d8STREFOU Felix  */
117*0561b2d8STREFOU Felix #define CFG_BLE_MAX_CONN_EVENT_LENGTH  ( 0xFFFFFFFF )
118*0561b2d8STREFOU Felix 
119*0561b2d8STREFOU Felix /**
120*0561b2d8STREFOU Felix  * Viterbi Mode
121*0561b2d8STREFOU Felix  * 1 : enabled
122*0561b2d8STREFOU Felix  * 0 : disabled
123*0561b2d8STREFOU Felix  */
124*0561b2d8STREFOU Felix #define CFG_BLE_VITERBI_MODE  1
125*0561b2d8STREFOU Felix 
126*0561b2d8STREFOU Felix /**
127*0561b2d8STREFOU Felix  *  LL Only Mode
128*0561b2d8STREFOU Felix  *  1 : LL Only
129*0561b2d8STREFOU Felix  *  0 : LL + Host
130*0561b2d8STREFOU Felix  */
131*0561b2d8STREFOU Felix #define CFG_BLE_LL_ONLY  1
132*0561b2d8STREFOU Felix 
133*0561b2d8STREFOU Felix /******************************************************************************
134*0561b2d8STREFOU Felix  * Transport Layer
135*0561b2d8STREFOU Felix  ******************************************************************************/
136*0561b2d8STREFOU Felix /**
137*0561b2d8STREFOU Felix  * Queue length of BLE Event
138*0561b2d8STREFOU Felix  * This parameter defines the number of asynchronous events that can be stored in the HCI layer before
139*0561b2d8STREFOU Felix  * being reported to the application. When a command is sent to the BLE core coprocessor, the HCI layer
140*0561b2d8STREFOU Felix  * is waiting for the event with the Num_HCI_Command_Packets set to 1. The receive queue shall be large
141*0561b2d8STREFOU Felix  * enough to store all asynchronous events received in between.
142*0561b2d8STREFOU Felix  * When CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE is set to 27, this allow to store three 255 bytes long asynchronous events
143*0561b2d8STREFOU Felix  * between the HCI command and its event.
144*0561b2d8STREFOU Felix  * This parameter depends on the value given to CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE. When the queue size is to small,
145*0561b2d8STREFOU Felix  * the system may hang if the queue is full with asynchronous events and the HCI layer is still waiting
146*0561b2d8STREFOU Felix  * for a CC/CS event, In that case, the notification TL_BLE_HCI_ToNot() is called to indicate
147*0561b2d8STREFOU Felix  * to the application a HCI command did not receive its command event within 30s (Default HCI Timeout).
148*0561b2d8STREFOU Felix  */
149*0561b2d8STREFOU Felix #define CFG_TLBLE_EVT_QUEUE_LENGTH 5
150*0561b2d8STREFOU Felix 
151*0561b2d8STREFOU Felix /**
152*0561b2d8STREFOU Felix  * This parameter should be set to fit most events received by the HCI layer. It defines the buffer size of each element
153*0561b2d8STREFOU Felix  * allocated in the queue of received events and can be used to optimize the amount of RAM allocated by the Memory Manager.
154*0561b2d8STREFOU Felix  * It should not exceed 255 which is the maximum HCI packet payload size (a greater value is a lost of memory as it will
155*0561b2d8STREFOU Felix  * never be used)
156*0561b2d8STREFOU Felix  * It shall be at least 4 to receive the command status event in one frame.
157*0561b2d8STREFOU Felix  * The default value is set to 27 to allow receiving an event of MTU size in a single buffer. This value maybe reduced
158*0561b2d8STREFOU Felix  * further depending on the application.
159*0561b2d8STREFOU Felix  *
160*0561b2d8STREFOU Felix  */
161*0561b2d8STREFOU Felix #define CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE 255   /**< Set to 255 with the memory manager and the mailbox */
162*0561b2d8STREFOU Felix 
163*0561b2d8STREFOU Felix #define TL_BLE_EVENT_FRAME_SIZE ( TL_EVT_HDR_SIZE + CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE )
164*0561b2d8STREFOU Felix 
165*0561b2d8STREFOU Felix /******************************************************************************
166*0561b2d8STREFOU Felix  * UART interfaces
167*0561b2d8STREFOU Felix  ******************************************************************************/
168*0561b2d8STREFOU Felix 
169*0561b2d8STREFOU Felix /**
170*0561b2d8STREFOU Felix  * Select UART interfaces
171*0561b2d8STREFOU Felix  */
172*0561b2d8STREFOU Felix #define CFG_DEBUG_TRACE_UART    hw_uart1
173*0561b2d8STREFOU Felix #define CFG_CONSOLE_MENU
174*0561b2d8STREFOU Felix /******************************************************************************
175*0561b2d8STREFOU Felix  * USB interface
176*0561b2d8STREFOU Felix  ******************************************************************************/
177*0561b2d8STREFOU Felix 
178*0561b2d8STREFOU Felix /**
179*0561b2d8STREFOU Felix  * Enable/Disable USB interface
180*0561b2d8STREFOU Felix  */
181*0561b2d8STREFOU Felix #define CFG_USB_INTERFACE_ENABLE    0
182*0561b2d8STREFOU Felix 
183*0561b2d8STREFOU Felix /******************************************************************************
184*0561b2d8STREFOU Felix  * Low Power
185*0561b2d8STREFOU Felix  ******************************************************************************/
186*0561b2d8STREFOU Felix /**
187*0561b2d8STREFOU Felix  *  When set to 1, the low power mode is enable
188*0561b2d8STREFOU Felix  *  When set to 0, the device stays in RUN mode
189*0561b2d8STREFOU Felix  */
190*0561b2d8STREFOU Felix #define CFG_LPM_SUPPORTED    0
191*0561b2d8STREFOU Felix 
192*0561b2d8STREFOU Felix /******************************************************************************
193*0561b2d8STREFOU Felix  * Timer Server
194*0561b2d8STREFOU Felix  ******************************************************************************/
195*0561b2d8STREFOU Felix /**
196*0561b2d8STREFOU Felix  *  CFG_RTC_WUCKSEL_DIVIDER:  This sets the RTCCLK divider to the wakeup timer.
197*0561b2d8STREFOU Felix  *  The higher is the value, the better is the power consumption and the accuracy of the timerserver
198*0561b2d8STREFOU Felix  *  The lower is the value, the finest is the granularity
199*0561b2d8STREFOU Felix  *
200*0561b2d8STREFOU Felix  *  CFG_RTC_ASYNCH_PRESCALER: This sets the asynchronous prescaler of the RTC. It should as high as possible ( to ouput
201*0561b2d8STREFOU Felix  *  clock as low as possible) but the output clock should be equal or higher frequency compare to the clock feeding
202*0561b2d8STREFOU Felix  *  the wakeup timer. A lower clock speed would impact the accuracy of the timer server.
203*0561b2d8STREFOU Felix  *
204*0561b2d8STREFOU Felix  *  CFG_RTC_SYNCH_PRESCALER: This sets the synchronous prescaler of the RTC.
205*0561b2d8STREFOU Felix  *  When the 1Hz calendar clock is required, it shall be sets according to other settings
206*0561b2d8STREFOU Felix  *  When the 1Hz calendar clock is not needed, CFG_RTC_SYNCH_PRESCALER should be set to 0x7FFF (MAX VALUE)
207*0561b2d8STREFOU Felix  *
208*0561b2d8STREFOU Felix  *  CFG_RTCCLK_DIVIDER_CONF:
209*0561b2d8STREFOU Felix  *  Shall be set to either 0,2,4,8,16
210*0561b2d8STREFOU Felix  *  When set to either 2,4,8,16, the 1Hhz calendar is supported
211*0561b2d8STREFOU Felix  *  When set to 0, the user sets its own configuration
212*0561b2d8STREFOU Felix  *
213*0561b2d8STREFOU Felix  *  The following settings are computed with LSI as input to the RTC
214*0561b2d8STREFOU Felix  */
215*0561b2d8STREFOU Felix #define CFG_RTCCLK_DIVIDER_CONF 0
216*0561b2d8STREFOU Felix 
217*0561b2d8STREFOU Felix #if (CFG_RTCCLK_DIVIDER_CONF == 0)
218*0561b2d8STREFOU Felix /**
219*0561b2d8STREFOU Felix  * Custom configuration
220*0561b2d8STREFOU Felix  * It does not support 1Hz calendar
221*0561b2d8STREFOU Felix  * It divides the RTC CLK by 16
222*0561b2d8STREFOU Felix  */
223*0561b2d8STREFOU Felix #define CFG_RTCCLK_DIV  (16)
224*0561b2d8STREFOU Felix #define CFG_RTC_WUCKSEL_DIVIDER (0)
225*0561b2d8STREFOU Felix #define CFG_RTC_ASYNCH_PRESCALER (CFG_RTCCLK_DIV - 1)
226*0561b2d8STREFOU Felix #define CFG_RTC_SYNCH_PRESCALER (0x7FFF)
227*0561b2d8STREFOU Felix 
228*0561b2d8STREFOU Felix #else
229*0561b2d8STREFOU Felix 
230*0561b2d8STREFOU Felix #if (CFG_RTCCLK_DIVIDER_CONF == 2)
231*0561b2d8STREFOU Felix /**
232*0561b2d8STREFOU Felix  * It divides the RTC CLK by 2
233*0561b2d8STREFOU Felix  */
234*0561b2d8STREFOU Felix #define CFG_RTC_WUCKSEL_DIVIDER (3)
235*0561b2d8STREFOU Felix #endif
236*0561b2d8STREFOU Felix 
237*0561b2d8STREFOU Felix #if (CFG_RTCCLK_DIVIDER_CONF == 4)
238*0561b2d8STREFOU Felix /**
239*0561b2d8STREFOU Felix  * It divides the RTC CLK by 4
240*0561b2d8STREFOU Felix  */
241*0561b2d8STREFOU Felix #define CFG_RTC_WUCKSEL_DIVIDER (2)
242*0561b2d8STREFOU Felix #endif
243*0561b2d8STREFOU Felix 
244*0561b2d8STREFOU Felix #if (CFG_RTCCLK_DIVIDER_CONF == 8)
245*0561b2d8STREFOU Felix /**
246*0561b2d8STREFOU Felix  * It divides the RTC CLK by 8
247*0561b2d8STREFOU Felix  */
248*0561b2d8STREFOU Felix #define CFG_RTC_WUCKSEL_DIVIDER (1)
249*0561b2d8STREFOU Felix #endif
250*0561b2d8STREFOU Felix 
251*0561b2d8STREFOU Felix #if (CFG_RTCCLK_DIVIDER_CONF == 16)
252*0561b2d8STREFOU Felix /**
253*0561b2d8STREFOU Felix  * It divides the RTC CLK by 16
254*0561b2d8STREFOU Felix  */
255*0561b2d8STREFOU Felix #define CFG_RTC_WUCKSEL_DIVIDER (0)
256*0561b2d8STREFOU Felix #endif
257*0561b2d8STREFOU Felix 
258*0561b2d8STREFOU Felix #define CFG_RTCCLK_DIV              CFG_RTCCLK_DIVIDER_CONF
259*0561b2d8STREFOU Felix #define CFG_RTC_ASYNCH_PRESCALER    (CFG_RTCCLK_DIV - 1)
260*0561b2d8STREFOU Felix #define CFG_RTC_SYNCH_PRESCALER     (DIVR( LSE_VALUE, (CFG_RTC_ASYNCH_PRESCALER+1) ) - 1 )
261*0561b2d8STREFOU Felix 
262*0561b2d8STREFOU Felix #endif
263*0561b2d8STREFOU Felix 
264*0561b2d8STREFOU Felix /** tick timer value in us */
265*0561b2d8STREFOU Felix #define CFG_TS_TICK_VAL           DIVR( (CFG_RTCCLK_DIV * 1000000), LSE_VALUE )
266*0561b2d8STREFOU Felix 
267*0561b2d8STREFOU Felix /******************************************************************************
268*0561b2d8STREFOU Felix  * Debug
269*0561b2d8STREFOU Felix  ******************************************************************************/
270*0561b2d8STREFOU Felix /**
271*0561b2d8STREFOU Felix  * When set, this resets some hw resources to set the device in the same state than the power up
272*0561b2d8STREFOU Felix  * The FW resets only register that may prevent the FW to run properly
273*0561b2d8STREFOU Felix  *
274*0561b2d8STREFOU Felix  * This shall be set to 0 in a final product
275*0561b2d8STREFOU Felix  *
276*0561b2d8STREFOU Felix  */
277*0561b2d8STREFOU Felix #define CFG_HW_RESET_BY_FW         1
278*0561b2d8STREFOU Felix 
279*0561b2d8STREFOU Felix /**
280*0561b2d8STREFOU Felix  * keep debugger enabled while in any low power mode when set to 1
281*0561b2d8STREFOU Felix  * should be set to 0 in production
282*0561b2d8STREFOU Felix  */
283*0561b2d8STREFOU Felix #define CFG_DEBUGGER_SUPPORTED    0
284*0561b2d8STREFOU Felix 
285*0561b2d8STREFOU Felix /**
286*0561b2d8STREFOU Felix  * When set to 1, the traces are enabled in the BLE services
287*0561b2d8STREFOU Felix  */
288*0561b2d8STREFOU Felix #define CFG_DEBUG_BLE_TRACE     0
289*0561b2d8STREFOU Felix 
290*0561b2d8STREFOU Felix /**
291*0561b2d8STREFOU Felix  * Enable or Disable traces in application
292*0561b2d8STREFOU Felix  */
293*0561b2d8STREFOU Felix #define CFG_DEBUG_APP_TRACE     0
294*0561b2d8STREFOU Felix 
295*0561b2d8STREFOU Felix #if (CFG_DEBUG_APP_TRACE != 0)
296*0561b2d8STREFOU Felix #define APP_DBG_MSG                 PRINT_MESG_DBG
297*0561b2d8STREFOU Felix #else
298*0561b2d8STREFOU Felix #define APP_DBG_MSG                 PRINT_NO_MESG
299*0561b2d8STREFOU Felix #endif
300*0561b2d8STREFOU Felix 
301*0561b2d8STREFOU Felix #if ( (CFG_DEBUG_BLE_TRACE != 0) || (CFG_DEBUG_APP_TRACE != 0) )
302*0561b2d8STREFOU Felix #define CFG_DEBUG_TRACE             1
303*0561b2d8STREFOU Felix #endif
304*0561b2d8STREFOU Felix 
305*0561b2d8STREFOU Felix #if (CFG_DEBUG_TRACE != 0)
306*0561b2d8STREFOU Felix #undef CFG_LPM_SUPPORTED
307*0561b2d8STREFOU Felix #undef CFG_DEBUGGER_SUPPORTED
308*0561b2d8STREFOU Felix #define CFG_LPM_SUPPORTED         0
309*0561b2d8STREFOU Felix #define CFG_DEBUGGER_SUPPORTED      1
310*0561b2d8STREFOU Felix #endif
311*0561b2d8STREFOU Felix 
312*0561b2d8STREFOU Felix /**
313*0561b2d8STREFOU Felix  * When CFG_DEBUG_TRACE_FULL is set to 1, the trace are output with the API name, the file name and the line number
314*0561b2d8STREFOU Felix  * When CFG_DEBUG_TRACE_LIGHT is set to 1, only the debug message is output
315*0561b2d8STREFOU Felix  *
316*0561b2d8STREFOU Felix  * When both are set to 0, no trace are output
317*0561b2d8STREFOU Felix  * When both are set to 1,  CFG_DEBUG_TRACE_FULL is selected
318*0561b2d8STREFOU Felix  */
319*0561b2d8STREFOU Felix #define CFG_DEBUG_TRACE_LIGHT     1
320*0561b2d8STREFOU Felix #define CFG_DEBUG_TRACE_FULL      0
321*0561b2d8STREFOU Felix 
322*0561b2d8STREFOU Felix #if (( CFG_DEBUG_TRACE != 0 ) && ( CFG_DEBUG_TRACE_LIGHT == 0 ) && (CFG_DEBUG_TRACE_FULL == 0))
323*0561b2d8STREFOU Felix #undef CFG_DEBUG_TRACE_FULL
324*0561b2d8STREFOU Felix #undef CFG_DEBUG_TRACE_LIGHT
325*0561b2d8STREFOU Felix #define CFG_DEBUG_TRACE_FULL      0
326*0561b2d8STREFOU Felix #define CFG_DEBUG_TRACE_LIGHT     1
327*0561b2d8STREFOU Felix #endif
328*0561b2d8STREFOU Felix 
329*0561b2d8STREFOU Felix #if ( CFG_DEBUG_TRACE == 0 )
330*0561b2d8STREFOU Felix #undef CFG_DEBUG_TRACE_FULL
331*0561b2d8STREFOU Felix #undef CFG_DEBUG_TRACE_LIGHT
332*0561b2d8STREFOU Felix #define CFG_DEBUG_TRACE_FULL      0
333*0561b2d8STREFOU Felix #define CFG_DEBUG_TRACE_LIGHT     0
334*0561b2d8STREFOU Felix #endif
335*0561b2d8STREFOU Felix 
336*0561b2d8STREFOU Felix /**
337*0561b2d8STREFOU Felix  * When not set, the traces is looping on sending the trace over UART
338*0561b2d8STREFOU Felix  */
339*0561b2d8STREFOU Felix #define DBG_TRACE_USE_CIRCULAR_QUEUE 1
340*0561b2d8STREFOU Felix 
341*0561b2d8STREFOU Felix /**
342*0561b2d8STREFOU Felix  * max buffer Size to queue data traces and max data trace allowed.
343*0561b2d8STREFOU Felix  * Only Used if DBG_TRACE_USE_CIRCULAR_QUEUE is defined
344*0561b2d8STREFOU Felix  */
345*0561b2d8STREFOU Felix #define DBG_TRACE_MSG_QUEUE_SIZE 4096
346*0561b2d8STREFOU Felix #define MAX_DBG_TRACE_MSG_SIZE 1024
347*0561b2d8STREFOU Felix 
348*0561b2d8STREFOU Felix /******************************************************************************
349*0561b2d8STREFOU Felix  * OTP manager
350*0561b2d8STREFOU Felix  ******************************************************************************/
351*0561b2d8STREFOU Felix #define CFG_OTP_BASE_ADDRESS    OTP_AREA_BASE
352*0561b2d8STREFOU Felix 
353*0561b2d8STREFOU Felix #define CFG_OTP_END_ADRESS      OTP_AREA_END_ADDR
354*0561b2d8STREFOU Felix 
355*0561b2d8STREFOU Felix #endif /*APP_CONF_H */
356*0561b2d8STREFOU Felix 
357*0561b2d8STREFOU Felix /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/