1 /**
2 ******************************************************************************
3 * @file stm32wbxx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 @verbatim
33 ==============================================================================
34 ##### TIMER Generic features #####
35 ==============================================================================
36 [..] The Timer features include:
37 (#) 16-bit up, down, up/down auto-reload counter.
38 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
39 counter clock frequency either by any factor between 1 and 65536.
40 (#) Up to 4 independent channels for:
41 (++) Input Capture
42 (++) Output Compare
43 (++) PWM generation (Edge and Center-aligned Mode)
44 (++) One-pulse mode output
45 (#) Synchronization circuit to control the timer with external signals and to interconnect
46 several timers together.
47 (#) Supports incremental encoder for positioning purposes
48
49 ##### How to use this driver #####
50 ==============================================================================
51 [..]
52 (#) Initialize the TIM low level resources by implementing the following functions
53 depending on the selected feature:
54 (++) Time Base : HAL_TIM_Base_MspInit()
55 (++) Input Capture : HAL_TIM_IC_MspInit()
56 (++) Output Compare : HAL_TIM_OC_MspInit()
57 (++) PWM generation : HAL_TIM_PWM_MspInit()
58 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
59 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
60
61 (#) Initialize the TIM low level resources :
62 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
63 (##) TIM pins configuration
64 (+++) Enable the clock for the TIM GPIOs using the following function:
65 __HAL_RCC_GPIOx_CLK_ENABLE();
66 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
67
68 (#) The external Clock can be configured, if needed (the default clock is the
69 internal clock from the APBx), using the following function:
70 HAL_TIM_ConfigClockSource, the clock configuration should be done before
71 any start function.
72
73 (#) Configure the TIM in the desired functioning mode using one of the
74 Initialization function of this driver:
75 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
76 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
77 Output Compare signal.
78 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
79 PWM signal.
80 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
81 external signal.
82 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
83 in One Pulse Mode.
84 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
85
86 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
87 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
88 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
89 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
90 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
91 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
92 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
93
94 (#) The DMA Burst is managed with the two following functions:
95 HAL_TIM_DMABurst_WriteStart()
96 HAL_TIM_DMABurst_ReadStart()
97
98 *** Callback registration ***
99 =============================================
100
101 [..]
102 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
103 allows the user to configure dynamically the driver callbacks.
104
105 [..]
106 Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
107 @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
108 the Callback ID and a pointer to the user callback function.
109
110 [..]
111 Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
112 weak function.
113 @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
114 and the Callback ID.
115
116 [..]
117 These functions allow to register/unregister following callbacks:
118 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
119 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
120 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
121 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
122 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
123 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
124 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
125 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
126 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
127 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
128 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
129 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
130 (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
131 (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
132 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
133 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
134 (+) TriggerCallback : TIM Trigger Callback.
135 (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
136 (+) IC_CaptureCallback : TIM Input Capture Callback.
137 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
138 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
139 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
140 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
141 (+) ErrorCallback : TIM Error Callback.
142 (+) CommutationCallback : TIM Commutation Callback.
143 (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
144 (+) BreakCallback : TIM Break Callback.
145 (+) Break2Callback : TIM Break2 Callback.
146
147 [..]
148 By default, after the Init and when the state is HAL_TIM_STATE_RESET
149 all interrupt callbacks are set to the corresponding weak functions:
150 examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
151
152 [..]
153 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
154 functionalities in the Init / DeInit only when these callbacks are null
155 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
156 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
157
158 [..]
159 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
160 Exception done MspInit / MspDeInit that can be registered / unregistered
161 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
162 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
163 In that case first register the MspInit/MspDeInit user callbacks
164 using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
165
166 [..]
167 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
168 not defined, the callback registration feature is not available and all callbacks
169 are set to the corresponding weak functions.
170
171 @endverbatim
172 ******************************************************************************
173 * @attention
174 *
175 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
176 * All rights reserved.</center></h2>
177 *
178 * This software component is licensed by ST under BSD 3-Clause license,
179 * the "License"; You may not use this file except in compliance with the
180 * License. You may obtain a copy of the License at:
181 * opensource.org/licenses/BSD-3-Clause
182 *
183 ******************************************************************************
184 */
185
186 /* Includes ------------------------------------------------------------------*/
187 #include "stm32wbxx_hal.h"
188
189 /** @addtogroup STM32WBxx_HAL_Driver
190 * @{
191 */
192
193 /** @defgroup TIM TIM
194 * @brief TIM HAL module driver
195 * @{
196 */
197
198 #ifdef HAL_TIM_MODULE_ENABLED
199
200 /* Private typedef -----------------------------------------------------------*/
201 /* Private define ------------------------------------------------------------*/
202 /** @addtogroup TIM_Private_Constants
203 * @{
204 */
205 #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL
206 /**
207 * @}
208 */
209
210 /* Private macro -------------------------------------------------------------*/
211 /* Private variables ---------------------------------------------------------*/
212 /* Private function prototypes -----------------------------------------------*/
213 /** @addtogroup TIM_Private_Functions
214 * @{
215 */
216 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
217 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
218 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
219 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
220 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
221 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
222 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
223 uint32_t TIM_ICFilter);
224 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
225 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
226 uint32_t TIM_ICFilter);
227 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
228 uint32_t TIM_ICFilter);
229 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
230 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
231 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
232 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
233 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
234 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
235 TIM_SlaveConfigTypeDef *sSlaveConfig);
236 /**
237 * @}
238 */
239 /* Exported functions --------------------------------------------------------*/
240
241 /** @defgroup TIM_Exported_Functions TIM Exported Functions
242 * @{
243 */
244
245 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
246 * @brief Time Base functions
247 *
248 @verbatim
249 ==============================================================================
250 ##### Time Base functions #####
251 ==============================================================================
252 [..]
253 This section provides functions allowing to:
254 (+) Initialize and configure the TIM base.
255 (+) De-initialize the TIM base.
256 (+) Start the Time Base.
257 (+) Stop the Time Base.
258 (+) Start the Time Base and enable interrupt.
259 (+) Stop the Time Base and disable interrupt.
260 (+) Start the Time Base and enable DMA transfer.
261 (+) Stop the Time Base and disable DMA transfer.
262
263 @endverbatim
264 * @{
265 */
266 /**
267 * @brief Initializes the TIM Time base Unit according to the specified
268 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
269 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
270 * requires a timer reset to avoid unexpected direction
271 * due to DIR bit readonly in center aligned mode.
272 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
273 * @param htim TIM Base handle
274 * @retval HAL status
275 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)276 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
277 {
278 /* Check the TIM handle allocation */
279 if (htim == NULL)
280 {
281 return HAL_ERROR;
282 }
283
284 /* Check the parameters */
285 assert_param(IS_TIM_INSTANCE(htim->Instance));
286 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
287 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
288 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
289
290 if (htim->State == HAL_TIM_STATE_RESET)
291 {
292 /* Allocate lock resource and initialize it */
293 htim->Lock = HAL_UNLOCKED;
294
295 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
296 /* Reset interrupt callbacks to legacy weak callbacks */
297 TIM_ResetCallback(htim);
298
299 if (htim->Base_MspInitCallback == NULL)
300 {
301 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
302 }
303 /* Init the low level hardware : GPIO, CLOCK, NVIC */
304 htim->Base_MspInitCallback(htim);
305 #else
306 /* Init the low level hardware : GPIO, CLOCK, NVIC */
307 HAL_TIM_Base_MspInit(htim);
308 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
309 }
310
311 /* Set the TIM state */
312 htim->State = HAL_TIM_STATE_BUSY;
313
314 /* Set the Time Base configuration */
315 TIM_Base_SetConfig(htim->Instance, &htim->Init);
316
317 /* Initialize the TIM state*/
318 htim->State = HAL_TIM_STATE_READY;
319
320 return HAL_OK;
321 }
322
323 /**
324 * @brief DeInitializes the TIM Base peripheral
325 * @param htim TIM Base handle
326 * @retval HAL status
327 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)328 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
329 {
330 /* Check the parameters */
331 assert_param(IS_TIM_INSTANCE(htim->Instance));
332
333 htim->State = HAL_TIM_STATE_BUSY;
334
335 /* Disable the TIM Peripheral Clock */
336 __HAL_TIM_DISABLE(htim);
337
338 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
339 if (htim->Base_MspDeInitCallback == NULL)
340 {
341 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
342 }
343 /* DeInit the low level hardware */
344 htim->Base_MspDeInitCallback(htim);
345 #else
346 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
347 HAL_TIM_Base_MspDeInit(htim);
348 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
349
350 /* Change TIM state */
351 htim->State = HAL_TIM_STATE_RESET;
352
353 /* Release Lock */
354 __HAL_UNLOCK(htim);
355
356 return HAL_OK;
357 }
358
359 /**
360 * @brief Initializes the TIM Base MSP.
361 * @param htim TIM Base handle
362 * @retval None
363 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)364 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
365 {
366 /* Prevent unused argument(s) compilation warning */
367 UNUSED(htim);
368
369 /* NOTE : This function should not be modified, when the callback is needed,
370 the HAL_TIM_Base_MspInit could be implemented in the user file
371 */
372 }
373
374 /**
375 * @brief DeInitializes TIM Base MSP.
376 * @param htim TIM Base handle
377 * @retval None
378 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)379 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
380 {
381 /* Prevent unused argument(s) compilation warning */
382 UNUSED(htim);
383
384 /* NOTE : This function should not be modified, when the callback is needed,
385 the HAL_TIM_Base_MspDeInit could be implemented in the user file
386 */
387 }
388
389
390 /**
391 * @brief Starts the TIM Base generation.
392 * @param htim TIM Base handle
393 * @retval HAL status
394 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)395 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
396 {
397 uint32_t tmpsmcr;
398
399 /* Check the parameters */
400 assert_param(IS_TIM_INSTANCE(htim->Instance));
401
402 /* Set the TIM state */
403 htim->State = HAL_TIM_STATE_BUSY;
404
405 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
406 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
407 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
408 {
409 __HAL_TIM_ENABLE(htim);
410 }
411
412 /* Change the TIM state*/
413 htim->State = HAL_TIM_STATE_READY;
414
415 /* Return function status */
416 return HAL_OK;
417 }
418
419 /**
420 * @brief Stops the TIM Base generation.
421 * @param htim TIM Base handle
422 * @retval HAL status
423 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)424 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
425 {
426 /* Check the parameters */
427 assert_param(IS_TIM_INSTANCE(htim->Instance));
428
429 /* Set the TIM state */
430 htim->State = HAL_TIM_STATE_BUSY;
431
432 /* Disable the Peripheral */
433 __HAL_TIM_DISABLE(htim);
434
435 /* Change the TIM state*/
436 htim->State = HAL_TIM_STATE_READY;
437
438 /* Return function status */
439 return HAL_OK;
440 }
441
442 /**
443 * @brief Starts the TIM Base generation in interrupt mode.
444 * @param htim TIM Base handle
445 * @retval HAL status
446 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)447 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
448 {
449 uint32_t tmpsmcr;
450
451 /* Check the parameters */
452 assert_param(IS_TIM_INSTANCE(htim->Instance));
453
454 /* Enable the TIM Update interrupt */
455 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
456
457 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
458 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
459 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
460 {
461 __HAL_TIM_ENABLE(htim);
462 }
463
464 /* Return function status */
465 return HAL_OK;
466 }
467
468 /**
469 * @brief Stops the TIM Base generation in interrupt mode.
470 * @param htim TIM Base handle
471 * @retval HAL status
472 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)473 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
474 {
475 /* Check the parameters */
476 assert_param(IS_TIM_INSTANCE(htim->Instance));
477 /* Disable the TIM Update interrupt */
478 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
479
480 /* Disable the Peripheral */
481 __HAL_TIM_DISABLE(htim);
482
483 /* Return function status */
484 return HAL_OK;
485 }
486
487 /**
488 * @brief Starts the TIM Base generation in DMA mode.
489 * @param htim TIM Base handle
490 * @param pData The source Buffer address.
491 * @param Length The length of data to be transferred from memory to peripheral.
492 * @retval HAL status
493 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,uint32_t * pData,uint16_t Length)494 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
495 {
496 uint32_t tmpsmcr;
497
498 /* Check the parameters */
499 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
500
501 if (htim->State == HAL_TIM_STATE_BUSY)
502 {
503 return HAL_BUSY;
504 }
505 else if (htim->State == HAL_TIM_STATE_READY)
506 {
507 if ((pData == NULL) && (Length > 0U))
508 {
509 return HAL_ERROR;
510 }
511 else
512 {
513 htim->State = HAL_TIM_STATE_BUSY;
514 }
515 }
516 else
517 {
518 /* nothing to do */
519 }
520
521 /* Set the DMA Period elapsed callbacks */
522 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
523 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
524
525 /* Set the DMA error callback */
526 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
527
528 /* Enable the DMA channel */
529 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
530 {
531 return HAL_ERROR;
532 }
533
534 /* Enable the TIM Update DMA request */
535 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
536
537 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
538 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
539 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
540 {
541 __HAL_TIM_ENABLE(htim);
542 }
543
544 /* Return function status */
545 return HAL_OK;
546 }
547
548 /**
549 * @brief Stops the TIM Base generation in DMA mode.
550 * @param htim TIM Base handle
551 * @retval HAL status
552 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)553 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
554 {
555 /* Check the parameters */
556 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
557
558 /* Disable the TIM Update DMA request */
559 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
560
561 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
562
563 /* Disable the Peripheral */
564 __HAL_TIM_DISABLE(htim);
565
566 /* Change the htim state */
567 htim->State = HAL_TIM_STATE_READY;
568
569 /* Return function status */
570 return HAL_OK;
571 }
572
573 /**
574 * @}
575 */
576
577 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
578 * @brief TIM Output Compare functions
579 *
580 @verbatim
581 ==============================================================================
582 ##### TIM Output Compare functions #####
583 ==============================================================================
584 [..]
585 This section provides functions allowing to:
586 (+) Initialize and configure the TIM Output Compare.
587 (+) De-initialize the TIM Output Compare.
588 (+) Start the TIM Output Compare.
589 (+) Stop the TIM Output Compare.
590 (+) Start the TIM Output Compare and enable interrupt.
591 (+) Stop the TIM Output Compare and disable interrupt.
592 (+) Start the TIM Output Compare and enable DMA transfer.
593 (+) Stop the TIM Output Compare and disable DMA transfer.
594
595 @endverbatim
596 * @{
597 */
598 /**
599 * @brief Initializes the TIM Output Compare according to the specified
600 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
601 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
602 * requires a timer reset to avoid unexpected direction
603 * due to DIR bit readonly in center aligned mode.
604 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
605 * @param htim TIM Output Compare handle
606 * @retval HAL status
607 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)608 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
609 {
610 /* Check the TIM handle allocation */
611 if (htim == NULL)
612 {
613 return HAL_ERROR;
614 }
615
616 /* Check the parameters */
617 assert_param(IS_TIM_INSTANCE(htim->Instance));
618 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
619 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
620 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
621
622 if (htim->State == HAL_TIM_STATE_RESET)
623 {
624 /* Allocate lock resource and initialize it */
625 htim->Lock = HAL_UNLOCKED;
626
627 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
628 /* Reset interrupt callbacks to legacy weak callbacks */
629 TIM_ResetCallback(htim);
630
631 if (htim->OC_MspInitCallback == NULL)
632 {
633 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
634 }
635 /* Init the low level hardware : GPIO, CLOCK, NVIC */
636 htim->OC_MspInitCallback(htim);
637 #else
638 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
639 HAL_TIM_OC_MspInit(htim);
640 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
641 }
642
643 /* Set the TIM state */
644 htim->State = HAL_TIM_STATE_BUSY;
645
646 /* Init the base time for the Output Compare */
647 TIM_Base_SetConfig(htim->Instance, &htim->Init);
648
649 /* Initialize the TIM state*/
650 htim->State = HAL_TIM_STATE_READY;
651
652 return HAL_OK;
653 }
654
655 /**
656 * @brief DeInitializes the TIM peripheral
657 * @param htim TIM Output Compare handle
658 * @retval HAL status
659 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)660 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
661 {
662 /* Check the parameters */
663 assert_param(IS_TIM_INSTANCE(htim->Instance));
664
665 htim->State = HAL_TIM_STATE_BUSY;
666
667 /* Disable the TIM Peripheral Clock */
668 __HAL_TIM_DISABLE(htim);
669
670 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
671 if (htim->OC_MspDeInitCallback == NULL)
672 {
673 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
674 }
675 /* DeInit the low level hardware */
676 htim->OC_MspDeInitCallback(htim);
677 #else
678 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
679 HAL_TIM_OC_MspDeInit(htim);
680 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
681
682 /* Change TIM state */
683 htim->State = HAL_TIM_STATE_RESET;
684
685 /* Release Lock */
686 __HAL_UNLOCK(htim);
687
688 return HAL_OK;
689 }
690
691 /**
692 * @brief Initializes the TIM Output Compare MSP.
693 * @param htim TIM Output Compare handle
694 * @retval None
695 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)696 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
697 {
698 /* Prevent unused argument(s) compilation warning */
699 UNUSED(htim);
700
701 /* NOTE : This function should not be modified, when the callback is needed,
702 the HAL_TIM_OC_MspInit could be implemented in the user file
703 */
704 }
705
706 /**
707 * @brief DeInitializes TIM Output Compare MSP.
708 * @param htim TIM Output Compare handle
709 * @retval None
710 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)711 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
712 {
713 /* Prevent unused argument(s) compilation warning */
714 UNUSED(htim);
715
716 /* NOTE : This function should not be modified, when the callback is needed,
717 the HAL_TIM_OC_MspDeInit could be implemented in the user file
718 */
719 }
720
721 /**
722 * @brief Starts the TIM Output Compare signal generation.
723 * @param htim TIM Output Compare handle
724 * @param Channel TIM Channel to be enabled
725 * This parameter can be one of the following values:
726 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
727 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
728 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
729 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
730 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
731 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
732 * @retval HAL status
733 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)734 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
735 {
736 uint32_t tmpsmcr;
737
738 /* Check the parameters */
739 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
740
741 /* Enable the Output compare channel */
742 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
743
744 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
745 {
746 /* Enable the main output */
747 __HAL_TIM_MOE_ENABLE(htim);
748 }
749
750 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
751 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
752 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
753 {
754 __HAL_TIM_ENABLE(htim);
755 }
756
757 /* Return function status */
758 return HAL_OK;
759 }
760
761 /**
762 * @brief Stops the TIM Output Compare signal generation.
763 * @param htim TIM Output Compare handle
764 * @param Channel TIM Channel to be disabled
765 * This parameter can be one of the following values:
766 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
767 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
768 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
769 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
770 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
771 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
772 * @retval HAL status
773 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)774 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
775 {
776 /* Check the parameters */
777 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
778
779 /* Disable the Output compare channel */
780 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
781
782 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
783 {
784 /* Disable the Main Output */
785 __HAL_TIM_MOE_DISABLE(htim);
786 }
787
788 /* Disable the Peripheral */
789 __HAL_TIM_DISABLE(htim);
790
791 /* Return function status */
792 return HAL_OK;
793 }
794
795 /**
796 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
797 * @param htim TIM Output Compare handle
798 * @param Channel TIM Channel to be enabled
799 * This parameter can be one of the following values:
800 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
801 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
802 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
803 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
804 * @retval HAL status
805 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)806 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
807 {
808 uint32_t tmpsmcr;
809
810 /* Check the parameters */
811 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
812
813 switch (Channel)
814 {
815 case TIM_CHANNEL_1:
816 {
817 /* Enable the TIM Capture/Compare 1 interrupt */
818 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
819 break;
820 }
821
822 case TIM_CHANNEL_2:
823 {
824 /* Enable the TIM Capture/Compare 2 interrupt */
825 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
826 break;
827 }
828
829 case TIM_CHANNEL_3:
830 {
831 /* Enable the TIM Capture/Compare 3 interrupt */
832 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
833 break;
834 }
835
836 case TIM_CHANNEL_4:
837 {
838 /* Enable the TIM Capture/Compare 4 interrupt */
839 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
840 break;
841 }
842
843 default:
844 break;
845 }
846
847 /* Enable the Output compare channel */
848 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
849
850 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
851 {
852 /* Enable the main output */
853 __HAL_TIM_MOE_ENABLE(htim);
854 }
855
856 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
857 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
858 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
859 {
860 __HAL_TIM_ENABLE(htim);
861 }
862
863 /* Return function status */
864 return HAL_OK;
865 }
866
867 /**
868 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
869 * @param htim TIM Output Compare handle
870 * @param Channel TIM Channel to be disabled
871 * This parameter can be one of the following values:
872 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
873 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
874 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
875 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
876 * @retval HAL status
877 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)878 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
879 {
880 /* Check the parameters */
881 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
882
883 switch (Channel)
884 {
885 case TIM_CHANNEL_1:
886 {
887 /* Disable the TIM Capture/Compare 1 interrupt */
888 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
889 break;
890 }
891
892 case TIM_CHANNEL_2:
893 {
894 /* Disable the TIM Capture/Compare 2 interrupt */
895 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
896 break;
897 }
898
899 case TIM_CHANNEL_3:
900 {
901 /* Disable the TIM Capture/Compare 3 interrupt */
902 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
903 break;
904 }
905
906 case TIM_CHANNEL_4:
907 {
908 /* Disable the TIM Capture/Compare 4 interrupt */
909 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
910 break;
911 }
912
913 default:
914 break;
915 }
916
917 /* Disable the Output compare channel */
918 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
919
920 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
921 {
922 /* Disable the Main Output */
923 __HAL_TIM_MOE_DISABLE(htim);
924 }
925
926 /* Disable the Peripheral */
927 __HAL_TIM_DISABLE(htim);
928
929 /* Return function status */
930 return HAL_OK;
931 }
932
933 /**
934 * @brief Starts the TIM Output Compare signal generation in DMA mode.
935 * @param htim TIM Output Compare handle
936 * @param Channel TIM Channel to be enabled
937 * This parameter can be one of the following values:
938 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
939 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
940 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
941 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
942 * @param pData The source Buffer address.
943 * @param Length The length of data to be transferred from memory to TIM peripheral
944 * @retval HAL status
945 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)946 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
947 {
948 uint32_t tmpsmcr;
949
950 /* Check the parameters */
951 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
952
953 if (htim->State == HAL_TIM_STATE_BUSY)
954 {
955 return HAL_BUSY;
956 }
957 else if (htim->State == HAL_TIM_STATE_READY)
958 {
959 if ((pData == NULL) && (Length > 0U))
960 {
961 return HAL_ERROR;
962 }
963 else
964 {
965 htim->State = HAL_TIM_STATE_BUSY;
966 }
967 }
968 else
969 {
970 /* nothing to do */
971 }
972
973 switch (Channel)
974 {
975 case TIM_CHANNEL_1:
976 {
977 /* Set the DMA compare callbacks */
978 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
979 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
980
981 /* Set the DMA error callback */
982 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
983
984 /* Enable the DMA channel */
985 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
986 {
987 return HAL_ERROR;
988 }
989
990 /* Enable the TIM Capture/Compare 1 DMA request */
991 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
992 break;
993 }
994
995 case TIM_CHANNEL_2:
996 {
997 /* Set the DMA compare callbacks */
998 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
999 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1000
1001 /* Set the DMA error callback */
1002 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1003
1004 /* Enable the DMA channel */
1005 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
1006 {
1007 return HAL_ERROR;
1008 }
1009
1010 /* Enable the TIM Capture/Compare 2 DMA request */
1011 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1012 break;
1013 }
1014
1015 case TIM_CHANNEL_3:
1016 {
1017 /* Set the DMA compare callbacks */
1018 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1019 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1020
1021 /* Set the DMA error callback */
1022 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1023
1024 /* Enable the DMA channel */
1025 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
1026 {
1027 return HAL_ERROR;
1028 }
1029 /* Enable the TIM Capture/Compare 3 DMA request */
1030 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1031 break;
1032 }
1033
1034 case TIM_CHANNEL_4:
1035 {
1036 /* Set the DMA compare callbacks */
1037 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1038 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1039
1040 /* Set the DMA error callback */
1041 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1042
1043 /* Enable the DMA channel */
1044 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
1045 {
1046 return HAL_ERROR;
1047 }
1048 /* Enable the TIM Capture/Compare 4 DMA request */
1049 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1050 break;
1051 }
1052
1053 default:
1054 break;
1055 }
1056
1057 /* Enable the Output compare channel */
1058 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1059
1060 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1061 {
1062 /* Enable the main output */
1063 __HAL_TIM_MOE_ENABLE(htim);
1064 }
1065
1066 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1067 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1068 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1069 {
1070 __HAL_TIM_ENABLE(htim);
1071 }
1072
1073 /* Return function status */
1074 return HAL_OK;
1075 }
1076
1077 /**
1078 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1079 * @param htim TIM Output Compare handle
1080 * @param Channel TIM Channel to be disabled
1081 * This parameter can be one of the following values:
1082 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1083 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1084 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1085 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1086 * @retval HAL status
1087 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1088 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1089 {
1090 /* Check the parameters */
1091 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1092
1093 switch (Channel)
1094 {
1095 case TIM_CHANNEL_1:
1096 {
1097 /* Disable the TIM Capture/Compare 1 DMA request */
1098 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1099 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1100 break;
1101 }
1102
1103 case TIM_CHANNEL_2:
1104 {
1105 /* Disable the TIM Capture/Compare 2 DMA request */
1106 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1107 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1108 break;
1109 }
1110
1111 case TIM_CHANNEL_3:
1112 {
1113 /* Disable the TIM Capture/Compare 3 DMA request */
1114 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1115 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1116 break;
1117 }
1118
1119 case TIM_CHANNEL_4:
1120 {
1121 /* Disable the TIM Capture/Compare 4 interrupt */
1122 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1123 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1124 break;
1125 }
1126
1127 default:
1128 break;
1129 }
1130
1131 /* Disable the Output compare channel */
1132 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1133
1134 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1135 {
1136 /* Disable the Main Output */
1137 __HAL_TIM_MOE_DISABLE(htim);
1138 }
1139
1140 /* Disable the Peripheral */
1141 __HAL_TIM_DISABLE(htim);
1142
1143 /* Change the htim state */
1144 htim->State = HAL_TIM_STATE_READY;
1145
1146 /* Return function status */
1147 return HAL_OK;
1148 }
1149
1150 /**
1151 * @}
1152 */
1153
1154 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1155 * @brief TIM PWM functions
1156 *
1157 @verbatim
1158 ==============================================================================
1159 ##### TIM PWM functions #####
1160 ==============================================================================
1161 [..]
1162 This section provides functions allowing to:
1163 (+) Initialize and configure the TIM PWM.
1164 (+) De-initialize the TIM PWM.
1165 (+) Start the TIM PWM.
1166 (+) Stop the TIM PWM.
1167 (+) Start the TIM PWM and enable interrupt.
1168 (+) Stop the TIM PWM and disable interrupt.
1169 (+) Start the TIM PWM and enable DMA transfer.
1170 (+) Stop the TIM PWM and disable DMA transfer.
1171
1172 @endverbatim
1173 * @{
1174 */
1175 /**
1176 * @brief Initializes the TIM PWM Time Base according to the specified
1177 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1178 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1179 * requires a timer reset to avoid unexpected direction
1180 * due to DIR bit readonly in center aligned mode.
1181 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1182 * @param htim TIM PWM handle
1183 * @retval HAL status
1184 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1185 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1186 {
1187 /* Check the TIM handle allocation */
1188 if (htim == NULL)
1189 {
1190 return HAL_ERROR;
1191 }
1192
1193 /* Check the parameters */
1194 assert_param(IS_TIM_INSTANCE(htim->Instance));
1195 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1196 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1197 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1198
1199 if (htim->State == HAL_TIM_STATE_RESET)
1200 {
1201 /* Allocate lock resource and initialize it */
1202 htim->Lock = HAL_UNLOCKED;
1203
1204 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1205 /* Reset interrupt callbacks to legacy weak callbacks */
1206 TIM_ResetCallback(htim);
1207
1208 if (htim->PWM_MspInitCallback == NULL)
1209 {
1210 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1211 }
1212 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1213 htim->PWM_MspInitCallback(htim);
1214 #else
1215 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1216 HAL_TIM_PWM_MspInit(htim);
1217 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1218 }
1219
1220 /* Set the TIM state */
1221 htim->State = HAL_TIM_STATE_BUSY;
1222
1223 /* Init the base time for the PWM */
1224 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1225
1226 /* Initialize the TIM state*/
1227 htim->State = HAL_TIM_STATE_READY;
1228
1229 return HAL_OK;
1230 }
1231
1232 /**
1233 * @brief DeInitializes the TIM peripheral
1234 * @param htim TIM PWM handle
1235 * @retval HAL status
1236 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1237 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1238 {
1239 /* Check the parameters */
1240 assert_param(IS_TIM_INSTANCE(htim->Instance));
1241
1242 htim->State = HAL_TIM_STATE_BUSY;
1243
1244 /* Disable the TIM Peripheral Clock */
1245 __HAL_TIM_DISABLE(htim);
1246
1247 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1248 if (htim->PWM_MspDeInitCallback == NULL)
1249 {
1250 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1251 }
1252 /* DeInit the low level hardware */
1253 htim->PWM_MspDeInitCallback(htim);
1254 #else
1255 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1256 HAL_TIM_PWM_MspDeInit(htim);
1257 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1258
1259 /* Change TIM state */
1260 htim->State = HAL_TIM_STATE_RESET;
1261
1262 /* Release Lock */
1263 __HAL_UNLOCK(htim);
1264
1265 return HAL_OK;
1266 }
1267
1268 /**
1269 * @brief Initializes the TIM PWM MSP.
1270 * @param htim TIM PWM handle
1271 * @retval None
1272 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1273 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1274 {
1275 /* Prevent unused argument(s) compilation warning */
1276 UNUSED(htim);
1277
1278 /* NOTE : This function should not be modified, when the callback is needed,
1279 the HAL_TIM_PWM_MspInit could be implemented in the user file
1280 */
1281 }
1282
1283 /**
1284 * @brief DeInitializes TIM PWM MSP.
1285 * @param htim TIM PWM handle
1286 * @retval None
1287 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1288 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1289 {
1290 /* Prevent unused argument(s) compilation warning */
1291 UNUSED(htim);
1292
1293 /* NOTE : This function should not be modified, when the callback is needed,
1294 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1295 */
1296 }
1297
1298 /**
1299 * @brief Starts the PWM signal generation.
1300 * @param htim TIM handle
1301 * @param Channel TIM Channels to be enabled
1302 * This parameter can be one of the following values:
1303 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1304 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1305 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1306 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1307 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1308 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1309 * @retval HAL status
1310 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1311 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1312 {
1313 uint32_t tmpsmcr;
1314
1315 /* Check the parameters */
1316 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1317
1318 /* Enable the Capture compare channel */
1319 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1320
1321 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1322 {
1323 /* Enable the main output */
1324 __HAL_TIM_MOE_ENABLE(htim);
1325 }
1326
1327 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1328 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1329 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1330 {
1331 __HAL_TIM_ENABLE(htim);
1332 }
1333
1334 /* Return function status */
1335 return HAL_OK;
1336 }
1337
1338 /**
1339 * @brief Stops the PWM signal generation.
1340 * @param htim TIM PWM handle
1341 * @param Channel TIM Channels to be disabled
1342 * This parameter can be one of the following values:
1343 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1344 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1345 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1346 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1347 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1348 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1349 * @retval HAL status
1350 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1351 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1352 {
1353 /* Check the parameters */
1354 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1355
1356 /* Disable the Capture compare channel */
1357 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1358
1359 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1360 {
1361 /* Disable the Main Output */
1362 __HAL_TIM_MOE_DISABLE(htim);
1363 }
1364
1365 /* Disable the Peripheral */
1366 __HAL_TIM_DISABLE(htim);
1367
1368 /* Change the htim state */
1369 htim->State = HAL_TIM_STATE_READY;
1370
1371 /* Return function status */
1372 return HAL_OK;
1373 }
1374
1375 /**
1376 * @brief Starts the PWM signal generation in interrupt mode.
1377 * @param htim TIM PWM handle
1378 * @param Channel TIM Channel to be enabled
1379 * This parameter can be one of the following values:
1380 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1381 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1382 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1383 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1384 * @retval HAL status
1385 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1386 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1387 {
1388 uint32_t tmpsmcr;
1389 /* Check the parameters */
1390 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1391
1392 switch (Channel)
1393 {
1394 case TIM_CHANNEL_1:
1395 {
1396 /* Enable the TIM Capture/Compare 1 interrupt */
1397 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1398 break;
1399 }
1400
1401 case TIM_CHANNEL_2:
1402 {
1403 /* Enable the TIM Capture/Compare 2 interrupt */
1404 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1405 break;
1406 }
1407
1408 case TIM_CHANNEL_3:
1409 {
1410 /* Enable the TIM Capture/Compare 3 interrupt */
1411 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1412 break;
1413 }
1414
1415 case TIM_CHANNEL_4:
1416 {
1417 /* Enable the TIM Capture/Compare 4 interrupt */
1418 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1419 break;
1420 }
1421
1422 default:
1423 break;
1424 }
1425
1426 /* Enable the Capture compare channel */
1427 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1428
1429 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1430 {
1431 /* Enable the main output */
1432 __HAL_TIM_MOE_ENABLE(htim);
1433 }
1434
1435 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1436 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1437 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1438 {
1439 __HAL_TIM_ENABLE(htim);
1440 }
1441
1442 /* Return function status */
1443 return HAL_OK;
1444 }
1445
1446 /**
1447 * @brief Stops the PWM signal generation in interrupt mode.
1448 * @param htim TIM PWM handle
1449 * @param Channel TIM Channels to be disabled
1450 * This parameter can be one of the following values:
1451 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1452 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1453 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1454 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1455 * @retval HAL status
1456 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1457 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1458 {
1459 /* Check the parameters */
1460 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1461
1462 switch (Channel)
1463 {
1464 case TIM_CHANNEL_1:
1465 {
1466 /* Disable the TIM Capture/Compare 1 interrupt */
1467 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1468 break;
1469 }
1470
1471 case TIM_CHANNEL_2:
1472 {
1473 /* Disable the TIM Capture/Compare 2 interrupt */
1474 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1475 break;
1476 }
1477
1478 case TIM_CHANNEL_3:
1479 {
1480 /* Disable the TIM Capture/Compare 3 interrupt */
1481 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1482 break;
1483 }
1484
1485 case TIM_CHANNEL_4:
1486 {
1487 /* Disable the TIM Capture/Compare 4 interrupt */
1488 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1489 break;
1490 }
1491
1492 default:
1493 break;
1494 }
1495
1496 /* Disable the Capture compare channel */
1497 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1498
1499 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1500 {
1501 /* Disable the Main Output */
1502 __HAL_TIM_MOE_DISABLE(htim);
1503 }
1504
1505 /* Disable the Peripheral */
1506 __HAL_TIM_DISABLE(htim);
1507
1508 /* Return function status */
1509 return HAL_OK;
1510 }
1511
1512 /**
1513 * @brief Starts the TIM PWM signal generation in DMA mode.
1514 * @param htim TIM PWM handle
1515 * @param Channel TIM Channels to be enabled
1516 * This parameter can be one of the following values:
1517 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1518 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1519 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1520 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1521 * @param pData The source Buffer address.
1522 * @param Length The length of data to be transferred from memory to TIM peripheral
1523 * @retval HAL status
1524 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)1525 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1526 {
1527 uint32_t tmpsmcr;
1528
1529 /* Check the parameters */
1530 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1531
1532 if (htim->State == HAL_TIM_STATE_BUSY)
1533 {
1534 return HAL_BUSY;
1535 }
1536 else if (htim->State == HAL_TIM_STATE_READY)
1537 {
1538 if ((pData == NULL) && (Length > 0U))
1539 {
1540 return HAL_ERROR;
1541 }
1542 else
1543 {
1544 htim->State = HAL_TIM_STATE_BUSY;
1545 }
1546 }
1547 else
1548 {
1549 /* nothing to do */
1550 }
1551
1552 switch (Channel)
1553 {
1554 case TIM_CHANNEL_1:
1555 {
1556 /* Set the DMA compare callbacks */
1557 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1558 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1559
1560 /* Set the DMA error callback */
1561 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1562
1563 /* Enable the DMA channel */
1564 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
1565 {
1566 return HAL_ERROR;
1567 }
1568
1569 /* Enable the TIM Capture/Compare 1 DMA request */
1570 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1571 break;
1572 }
1573
1574 case TIM_CHANNEL_2:
1575 {
1576 /* Set the DMA compare callbacks */
1577 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1578 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1579
1580 /* Set the DMA error callback */
1581 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1582
1583 /* Enable the DMA channel */
1584 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
1585 {
1586 return HAL_ERROR;
1587 }
1588 /* Enable the TIM Capture/Compare 2 DMA request */
1589 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1590 break;
1591 }
1592
1593 case TIM_CHANNEL_3:
1594 {
1595 /* Set the DMA compare callbacks */
1596 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1597 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1598
1599 /* Set the DMA error callback */
1600 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1601
1602 /* Enable the DMA channel */
1603 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
1604 {
1605 return HAL_ERROR;
1606 }
1607 /* Enable the TIM Output Capture/Compare 3 request */
1608 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1609 break;
1610 }
1611
1612 case TIM_CHANNEL_4:
1613 {
1614 /* Set the DMA compare callbacks */
1615 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1616 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1617
1618 /* Set the DMA error callback */
1619 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1620
1621 /* Enable the DMA channel */
1622 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
1623 {
1624 return HAL_ERROR;
1625 }
1626 /* Enable the TIM Capture/Compare 4 DMA request */
1627 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1628 break;
1629 }
1630
1631 default:
1632 break;
1633 }
1634
1635 /* Enable the Capture compare channel */
1636 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1637
1638 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1639 {
1640 /* Enable the main output */
1641 __HAL_TIM_MOE_ENABLE(htim);
1642 }
1643
1644 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1645 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1646 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1647 {
1648 __HAL_TIM_ENABLE(htim);
1649 }
1650
1651 /* Return function status */
1652 return HAL_OK;
1653 }
1654
1655 /**
1656 * @brief Stops the TIM PWM signal generation in DMA mode.
1657 * @param htim TIM PWM handle
1658 * @param Channel TIM Channels to be disabled
1659 * This parameter can be one of the following values:
1660 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1661 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1662 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1663 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1664 * @retval HAL status
1665 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1666 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1667 {
1668 /* Check the parameters */
1669 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1670
1671 switch (Channel)
1672 {
1673 case TIM_CHANNEL_1:
1674 {
1675 /* Disable the TIM Capture/Compare 1 DMA request */
1676 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1677 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1678 break;
1679 }
1680
1681 case TIM_CHANNEL_2:
1682 {
1683 /* Disable the TIM Capture/Compare 2 DMA request */
1684 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1685 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1686 break;
1687 }
1688
1689 case TIM_CHANNEL_3:
1690 {
1691 /* Disable the TIM Capture/Compare 3 DMA request */
1692 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1693 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1694 break;
1695 }
1696
1697 case TIM_CHANNEL_4:
1698 {
1699 /* Disable the TIM Capture/Compare 4 interrupt */
1700 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1701 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1702 break;
1703 }
1704
1705 default:
1706 break;
1707 }
1708
1709 /* Disable the Capture compare channel */
1710 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1711
1712 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1713 {
1714 /* Disable the Main Output */
1715 __HAL_TIM_MOE_DISABLE(htim);
1716 }
1717
1718 /* Disable the Peripheral */
1719 __HAL_TIM_DISABLE(htim);
1720
1721 /* Change the htim state */
1722 htim->State = HAL_TIM_STATE_READY;
1723
1724 /* Return function status */
1725 return HAL_OK;
1726 }
1727
1728 /**
1729 * @}
1730 */
1731
1732 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1733 * @brief TIM Input Capture functions
1734 *
1735 @verbatim
1736 ==============================================================================
1737 ##### TIM Input Capture functions #####
1738 ==============================================================================
1739 [..]
1740 This section provides functions allowing to:
1741 (+) Initialize and configure the TIM Input Capture.
1742 (+) De-initialize the TIM Input Capture.
1743 (+) Start the TIM Input Capture.
1744 (+) Stop the TIM Input Capture.
1745 (+) Start the TIM Input Capture and enable interrupt.
1746 (+) Stop the TIM Input Capture and disable interrupt.
1747 (+) Start the TIM Input Capture and enable DMA transfer.
1748 (+) Stop the TIM Input Capture and disable DMA transfer.
1749
1750 @endverbatim
1751 * @{
1752 */
1753 /**
1754 * @brief Initializes the TIM Input Capture Time base according to the specified
1755 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1756 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1757 * requires a timer reset to avoid unexpected direction
1758 * due to DIR bit readonly in center aligned mode.
1759 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1760 * @param htim TIM Input Capture handle
1761 * @retval HAL status
1762 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)1763 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1764 {
1765 /* Check the TIM handle allocation */
1766 if (htim == NULL)
1767 {
1768 return HAL_ERROR;
1769 }
1770
1771 /* Check the parameters */
1772 assert_param(IS_TIM_INSTANCE(htim->Instance));
1773 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1774 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1775 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1776
1777 if (htim->State == HAL_TIM_STATE_RESET)
1778 {
1779 /* Allocate lock resource and initialize it */
1780 htim->Lock = HAL_UNLOCKED;
1781
1782 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1783 /* Reset interrupt callbacks to legacy weak callbacks */
1784 TIM_ResetCallback(htim);
1785
1786 if (htim->IC_MspInitCallback == NULL)
1787 {
1788 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
1789 }
1790 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1791 htim->IC_MspInitCallback(htim);
1792 #else
1793 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1794 HAL_TIM_IC_MspInit(htim);
1795 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1796 }
1797
1798 /* Set the TIM state */
1799 htim->State = HAL_TIM_STATE_BUSY;
1800
1801 /* Init the base time for the input capture */
1802 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1803
1804 /* Initialize the TIM state*/
1805 htim->State = HAL_TIM_STATE_READY;
1806
1807 return HAL_OK;
1808 }
1809
1810 /**
1811 * @brief DeInitializes the TIM peripheral
1812 * @param htim TIM Input Capture handle
1813 * @retval HAL status
1814 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)1815 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
1816 {
1817 /* Check the parameters */
1818 assert_param(IS_TIM_INSTANCE(htim->Instance));
1819
1820 htim->State = HAL_TIM_STATE_BUSY;
1821
1822 /* Disable the TIM Peripheral Clock */
1823 __HAL_TIM_DISABLE(htim);
1824
1825 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1826 if (htim->IC_MspDeInitCallback == NULL)
1827 {
1828 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
1829 }
1830 /* DeInit the low level hardware */
1831 htim->IC_MspDeInitCallback(htim);
1832 #else
1833 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1834 HAL_TIM_IC_MspDeInit(htim);
1835 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1836
1837 /* Change TIM state */
1838 htim->State = HAL_TIM_STATE_RESET;
1839
1840 /* Release Lock */
1841 __HAL_UNLOCK(htim);
1842
1843 return HAL_OK;
1844 }
1845
1846 /**
1847 * @brief Initializes the TIM Input Capture MSP.
1848 * @param htim TIM Input Capture handle
1849 * @retval None
1850 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)1851 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
1852 {
1853 /* Prevent unused argument(s) compilation warning */
1854 UNUSED(htim);
1855
1856 /* NOTE : This function should not be modified, when the callback is needed,
1857 the HAL_TIM_IC_MspInit could be implemented in the user file
1858 */
1859 }
1860
1861 /**
1862 * @brief DeInitializes TIM Input Capture MSP.
1863 * @param htim TIM handle
1864 * @retval None
1865 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)1866 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
1867 {
1868 /* Prevent unused argument(s) compilation warning */
1869 UNUSED(htim);
1870
1871 /* NOTE : This function should not be modified, when the callback is needed,
1872 the HAL_TIM_IC_MspDeInit could be implemented in the user file
1873 */
1874 }
1875
1876 /**
1877 * @brief Starts the TIM Input Capture measurement.
1878 * @param htim TIM Input Capture handle
1879 * @param Channel TIM Channels to be enabled
1880 * This parameter can be one of the following values:
1881 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1882 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1883 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1884 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1885 * @retval HAL status
1886 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1887 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1888 {
1889 uint32_t tmpsmcr;
1890
1891 /* Check the parameters */
1892 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1893
1894 /* Enable the Input Capture channel */
1895 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1896
1897 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1898 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1899 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1900 {
1901 __HAL_TIM_ENABLE(htim);
1902 }
1903
1904 /* Return function status */
1905 return HAL_OK;
1906 }
1907
1908 /**
1909 * @brief Stops the TIM Input Capture measurement.
1910 * @param htim TIM Input Capture handle
1911 * @param Channel TIM Channels to be disabled
1912 * This parameter can be one of the following values:
1913 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1914 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1915 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1916 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1917 * @retval HAL status
1918 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1919 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1920 {
1921 /* Check the parameters */
1922 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1923
1924 /* Disable the Input Capture channel */
1925 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1926
1927 /* Disable the Peripheral */
1928 __HAL_TIM_DISABLE(htim);
1929
1930 /* Return function status */
1931 return HAL_OK;
1932 }
1933
1934 /**
1935 * @brief Starts the TIM Input Capture measurement in interrupt mode.
1936 * @param htim TIM Input Capture handle
1937 * @param Channel TIM Channels to be enabled
1938 * This parameter can be one of the following values:
1939 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1940 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1941 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1942 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1943 * @retval HAL status
1944 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1945 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1946 {
1947 uint32_t tmpsmcr;
1948
1949 /* Check the parameters */
1950 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1951
1952 switch (Channel)
1953 {
1954 case TIM_CHANNEL_1:
1955 {
1956 /* Enable the TIM Capture/Compare 1 interrupt */
1957 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1958 break;
1959 }
1960
1961 case TIM_CHANNEL_2:
1962 {
1963 /* Enable the TIM Capture/Compare 2 interrupt */
1964 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1965 break;
1966 }
1967
1968 case TIM_CHANNEL_3:
1969 {
1970 /* Enable the TIM Capture/Compare 3 interrupt */
1971 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1972 break;
1973 }
1974
1975 case TIM_CHANNEL_4:
1976 {
1977 /* Enable the TIM Capture/Compare 4 interrupt */
1978 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1979 break;
1980 }
1981
1982 default:
1983 break;
1984 }
1985 /* Enable the Input Capture channel */
1986 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1987
1988 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1989 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1990 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1991 {
1992 __HAL_TIM_ENABLE(htim);
1993 }
1994
1995 /* Return function status */
1996 return HAL_OK;
1997 }
1998
1999 /**
2000 * @brief Stops the TIM Input Capture measurement in interrupt mode.
2001 * @param htim TIM Input Capture handle
2002 * @param Channel TIM Channels to be disabled
2003 * This parameter can be one of the following values:
2004 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2005 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2006 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2007 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2008 * @retval HAL status
2009 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2010 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2011 {
2012 /* Check the parameters */
2013 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2014
2015 switch (Channel)
2016 {
2017 case TIM_CHANNEL_1:
2018 {
2019 /* Disable the TIM Capture/Compare 1 interrupt */
2020 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2021 break;
2022 }
2023
2024 case TIM_CHANNEL_2:
2025 {
2026 /* Disable the TIM Capture/Compare 2 interrupt */
2027 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2028 break;
2029 }
2030
2031 case TIM_CHANNEL_3:
2032 {
2033 /* Disable the TIM Capture/Compare 3 interrupt */
2034 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2035 break;
2036 }
2037
2038 case TIM_CHANNEL_4:
2039 {
2040 /* Disable the TIM Capture/Compare 4 interrupt */
2041 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2042 break;
2043 }
2044
2045 default:
2046 break;
2047 }
2048
2049 /* Disable the Input Capture channel */
2050 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2051
2052 /* Disable the Peripheral */
2053 __HAL_TIM_DISABLE(htim);
2054
2055 /* Return function status */
2056 return HAL_OK;
2057 }
2058
2059 /**
2060 * @brief Starts the TIM Input Capture measurement in DMA mode.
2061 * @param htim TIM Input Capture handle
2062 * @param Channel TIM Channels to be enabled
2063 * This parameter can be one of the following values:
2064 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2065 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2066 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2067 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2068 * @param pData The destination Buffer address.
2069 * @param Length The length of data to be transferred from TIM peripheral to memory.
2070 * @retval HAL status
2071 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2072 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2073 {
2074 uint32_t tmpsmcr;
2075
2076 /* Check the parameters */
2077 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2078 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2079
2080 if (htim->State == HAL_TIM_STATE_BUSY)
2081 {
2082 return HAL_BUSY;
2083 }
2084 else if (htim->State == HAL_TIM_STATE_READY)
2085 {
2086 if ((pData == NULL) && (Length > 0U))
2087 {
2088 return HAL_ERROR;
2089 }
2090 else
2091 {
2092 htim->State = HAL_TIM_STATE_BUSY;
2093 }
2094 }
2095 else
2096 {
2097 /* nothing to do */
2098 }
2099
2100 switch (Channel)
2101 {
2102 case TIM_CHANNEL_1:
2103 {
2104 /* Set the DMA capture callbacks */
2105 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2106 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2107
2108 /* Set the DMA error callback */
2109 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2110
2111 /* Enable the DMA channel */
2112 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
2113 {
2114 return HAL_ERROR;
2115 }
2116 /* Enable the TIM Capture/Compare 1 DMA request */
2117 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2118 break;
2119 }
2120
2121 case TIM_CHANNEL_2:
2122 {
2123 /* Set the DMA capture callbacks */
2124 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2125 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2126
2127 /* Set the DMA error callback */
2128 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2129
2130 /* Enable the DMA channel */
2131 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
2132 {
2133 return HAL_ERROR;
2134 }
2135 /* Enable the TIM Capture/Compare 2 DMA request */
2136 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2137 break;
2138 }
2139
2140 case TIM_CHANNEL_3:
2141 {
2142 /* Set the DMA capture callbacks */
2143 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2144 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2145
2146 /* Set the DMA error callback */
2147 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2148
2149 /* Enable the DMA channel */
2150 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
2151 {
2152 return HAL_ERROR;
2153 }
2154 /* Enable the TIM Capture/Compare 3 DMA request */
2155 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2156 break;
2157 }
2158
2159 case TIM_CHANNEL_4:
2160 {
2161 /* Set the DMA capture callbacks */
2162 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2163 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2164
2165 /* Set the DMA error callback */
2166 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2167
2168 /* Enable the DMA channel */
2169 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
2170 {
2171 return HAL_ERROR;
2172 }
2173 /* Enable the TIM Capture/Compare 4 DMA request */
2174 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2175 break;
2176 }
2177
2178 default:
2179 break;
2180 }
2181
2182 /* Enable the Input Capture channel */
2183 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2184
2185 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2186 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2187 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2188 {
2189 __HAL_TIM_ENABLE(htim);
2190 }
2191
2192 /* Return function status */
2193 return HAL_OK;
2194 }
2195
2196 /**
2197 * @brief Stops the TIM Input Capture measurement in DMA mode.
2198 * @param htim TIM Input Capture handle
2199 * @param Channel TIM Channels to be disabled
2200 * This parameter can be one of the following values:
2201 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2202 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2203 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2204 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2205 * @retval HAL status
2206 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2207 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2208 {
2209 /* Check the parameters */
2210 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2211 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2212
2213 switch (Channel)
2214 {
2215 case TIM_CHANNEL_1:
2216 {
2217 /* Disable the TIM Capture/Compare 1 DMA request */
2218 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2219 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2220 break;
2221 }
2222
2223 case TIM_CHANNEL_2:
2224 {
2225 /* Disable the TIM Capture/Compare 2 DMA request */
2226 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2227 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2228 break;
2229 }
2230
2231 case TIM_CHANNEL_3:
2232 {
2233 /* Disable the TIM Capture/Compare 3 DMA request */
2234 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2235 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2236 break;
2237 }
2238
2239 case TIM_CHANNEL_4:
2240 {
2241 /* Disable the TIM Capture/Compare 4 DMA request */
2242 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2243 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2244 break;
2245 }
2246
2247 default:
2248 break;
2249 }
2250
2251 /* Disable the Input Capture channel */
2252 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2253
2254 /* Disable the Peripheral */
2255 __HAL_TIM_DISABLE(htim);
2256
2257 /* Change the htim state */
2258 htim->State = HAL_TIM_STATE_READY;
2259
2260 /* Return function status */
2261 return HAL_OK;
2262 }
2263 /**
2264 * @}
2265 */
2266
2267 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2268 * @brief TIM One Pulse functions
2269 *
2270 @verbatim
2271 ==============================================================================
2272 ##### TIM One Pulse functions #####
2273 ==============================================================================
2274 [..]
2275 This section provides functions allowing to:
2276 (+) Initialize and configure the TIM One Pulse.
2277 (+) De-initialize the TIM One Pulse.
2278 (+) Start the TIM One Pulse.
2279 (+) Stop the TIM One Pulse.
2280 (+) Start the TIM One Pulse and enable interrupt.
2281 (+) Stop the TIM One Pulse and disable interrupt.
2282 (+) Start the TIM One Pulse and enable DMA transfer.
2283 (+) Stop the TIM One Pulse and disable DMA transfer.
2284
2285 @endverbatim
2286 * @{
2287 */
2288 /**
2289 * @brief Initializes the TIM One Pulse Time Base according to the specified
2290 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2291 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2292 * requires a timer reset to avoid unexpected direction
2293 * due to DIR bit readonly in center aligned mode.
2294 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2295 * @param htim TIM One Pulse handle
2296 * @param OnePulseMode Select the One pulse mode.
2297 * This parameter can be one of the following values:
2298 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2299 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2300 * @retval HAL status
2301 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2302 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2303 {
2304 /* Check the TIM handle allocation */
2305 if (htim == NULL)
2306 {
2307 return HAL_ERROR;
2308 }
2309
2310 /* Check the parameters */
2311 assert_param(IS_TIM_INSTANCE(htim->Instance));
2312 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2313 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2314 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2315 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2316
2317 if (htim->State == HAL_TIM_STATE_RESET)
2318 {
2319 /* Allocate lock resource and initialize it */
2320 htim->Lock = HAL_UNLOCKED;
2321
2322 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2323 /* Reset interrupt callbacks to legacy weak callbacks */
2324 TIM_ResetCallback(htim);
2325
2326 if (htim->OnePulse_MspInitCallback == NULL)
2327 {
2328 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2329 }
2330 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2331 htim->OnePulse_MspInitCallback(htim);
2332 #else
2333 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2334 HAL_TIM_OnePulse_MspInit(htim);
2335 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2336 }
2337
2338 /* Set the TIM state */
2339 htim->State = HAL_TIM_STATE_BUSY;
2340
2341 /* Configure the Time base in the One Pulse Mode */
2342 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2343
2344 /* Reset the OPM Bit */
2345 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2346
2347 /* Configure the OPM Mode */
2348 htim->Instance->CR1 |= OnePulseMode;
2349
2350 /* Initialize the TIM state*/
2351 htim->State = HAL_TIM_STATE_READY;
2352
2353 return HAL_OK;
2354 }
2355
2356 /**
2357 * @brief DeInitializes the TIM One Pulse
2358 * @param htim TIM One Pulse handle
2359 * @retval HAL status
2360 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2361 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2362 {
2363 /* Check the parameters */
2364 assert_param(IS_TIM_INSTANCE(htim->Instance));
2365
2366 htim->State = HAL_TIM_STATE_BUSY;
2367
2368 /* Disable the TIM Peripheral Clock */
2369 __HAL_TIM_DISABLE(htim);
2370
2371 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2372 if (htim->OnePulse_MspDeInitCallback == NULL)
2373 {
2374 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2375 }
2376 /* DeInit the low level hardware */
2377 htim->OnePulse_MspDeInitCallback(htim);
2378 #else
2379 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2380 HAL_TIM_OnePulse_MspDeInit(htim);
2381 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2382
2383 /* Change TIM state */
2384 htim->State = HAL_TIM_STATE_RESET;
2385
2386 /* Release Lock */
2387 __HAL_UNLOCK(htim);
2388
2389 return HAL_OK;
2390 }
2391
2392 /**
2393 * @brief Initializes the TIM One Pulse MSP.
2394 * @param htim TIM One Pulse handle
2395 * @retval None
2396 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2397 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2398 {
2399 /* Prevent unused argument(s) compilation warning */
2400 UNUSED(htim);
2401
2402 /* NOTE : This function should not be modified, when the callback is needed,
2403 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2404 */
2405 }
2406
2407 /**
2408 * @brief DeInitializes TIM One Pulse MSP.
2409 * @param htim TIM One Pulse handle
2410 * @retval None
2411 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2412 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2413 {
2414 /* Prevent unused argument(s) compilation warning */
2415 UNUSED(htim);
2416
2417 /* NOTE : This function should not be modified, when the callback is needed,
2418 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2419 */
2420 }
2421
2422 /**
2423 * @brief Starts the TIM One Pulse signal generation.
2424 * @param htim TIM One Pulse handle
2425 * @param OutputChannel TIM Channels to be enabled
2426 * This parameter can be one of the following values:
2427 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2428 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2429 * @retval HAL status
2430 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2431 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2432 {
2433 /* Prevent unused argument(s) compilation warning */
2434 UNUSED(OutputChannel);
2435
2436 /* Enable the Capture compare and the Input Capture channels
2437 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2438 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2439 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2440 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2441
2442 No need to enable the counter, it's enabled automatically by hardware
2443 (the counter starts in response to a stimulus and generate a pulse */
2444
2445 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2446 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2447
2448 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2449 {
2450 /* Enable the main output */
2451 __HAL_TIM_MOE_ENABLE(htim);
2452 }
2453
2454 /* Return function status */
2455 return HAL_OK;
2456 }
2457
2458 /**
2459 * @brief Stops the TIM One Pulse signal generation.
2460 * @param htim TIM One Pulse handle
2461 * @param OutputChannel TIM Channels to be disable
2462 * This parameter can be one of the following values:
2463 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2464 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2465 * @retval HAL status
2466 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2467 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2468 {
2469 /* Prevent unused argument(s) compilation warning */
2470 UNUSED(OutputChannel);
2471
2472 /* Disable the Capture compare and the Input Capture channels
2473 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2474 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2475 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2476 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2477
2478 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2479 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2480
2481 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2482 {
2483 /* Disable the Main Output */
2484 __HAL_TIM_MOE_DISABLE(htim);
2485 }
2486
2487 /* Disable the Peripheral */
2488 __HAL_TIM_DISABLE(htim);
2489
2490 /* Return function status */
2491 return HAL_OK;
2492 }
2493
2494 /**
2495 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2496 * @param htim TIM One Pulse handle
2497 * @param OutputChannel TIM Channels to be enabled
2498 * This parameter can be one of the following values:
2499 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2500 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2501 * @retval HAL status
2502 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2503 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2504 {
2505 /* Prevent unused argument(s) compilation warning */
2506 UNUSED(OutputChannel);
2507
2508 /* Enable the Capture compare and the Input Capture channels
2509 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2510 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2511 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2512 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2513
2514 No need to enable the counter, it's enabled automatically by hardware
2515 (the counter starts in response to a stimulus and generate a pulse */
2516
2517 /* Enable the TIM Capture/Compare 1 interrupt */
2518 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2519
2520 /* Enable the TIM Capture/Compare 2 interrupt */
2521 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2522
2523 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2524 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2525
2526 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2527 {
2528 /* Enable the main output */
2529 __HAL_TIM_MOE_ENABLE(htim);
2530 }
2531
2532 /* Return function status */
2533 return HAL_OK;
2534 }
2535
2536 /**
2537 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2538 * @param htim TIM One Pulse handle
2539 * @param OutputChannel TIM Channels to be enabled
2540 * This parameter can be one of the following values:
2541 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2542 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2543 * @retval HAL status
2544 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2545 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2546 {
2547 /* Prevent unused argument(s) compilation warning */
2548 UNUSED(OutputChannel);
2549
2550 /* Disable the TIM Capture/Compare 1 interrupt */
2551 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2552
2553 /* Disable the TIM Capture/Compare 2 interrupt */
2554 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2555
2556 /* Disable the Capture compare and the Input Capture channels
2557 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2558 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2559 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2560 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2561 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2562 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2563
2564 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2565 {
2566 /* Disable the Main Output */
2567 __HAL_TIM_MOE_DISABLE(htim);
2568 }
2569
2570 /* Disable the Peripheral */
2571 __HAL_TIM_DISABLE(htim);
2572
2573 /* Return function status */
2574 return HAL_OK;
2575 }
2576
2577 /**
2578 * @}
2579 */
2580
2581 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
2582 * @brief TIM Encoder functions
2583 *
2584 @verbatim
2585 ==============================================================================
2586 ##### TIM Encoder functions #####
2587 ==============================================================================
2588 [..]
2589 This section provides functions allowing to:
2590 (+) Initialize and configure the TIM Encoder.
2591 (+) De-initialize the TIM Encoder.
2592 (+) Start the TIM Encoder.
2593 (+) Stop the TIM Encoder.
2594 (+) Start the TIM Encoder and enable interrupt.
2595 (+) Stop the TIM Encoder and disable interrupt.
2596 (+) Start the TIM Encoder and enable DMA transfer.
2597 (+) Stop the TIM Encoder and disable DMA transfer.
2598
2599 @endverbatim
2600 * @{
2601 */
2602 /**
2603 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
2604 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2605 * requires a timer reset to avoid unexpected direction
2606 * due to DIR bit readonly in center aligned mode.
2607 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
2608 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
2609 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
2610 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
2611 * @param htim TIM Encoder Interface handle
2612 * @param sConfig TIM Encoder Interface configuration structure
2613 * @retval HAL status
2614 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,TIM_Encoder_InitTypeDef * sConfig)2615 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
2616 {
2617 uint32_t tmpsmcr;
2618 uint32_t tmpccmr1;
2619 uint32_t tmpccer;
2620
2621 /* Check the TIM handle allocation */
2622 if (htim == NULL)
2623 {
2624 return HAL_ERROR;
2625 }
2626
2627 /* Check the parameters */
2628 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2629 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2630 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2631 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2632 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
2633 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
2634 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
2635 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
2636 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
2637 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
2638 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
2639 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
2640 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
2641
2642 if (htim->State == HAL_TIM_STATE_RESET)
2643 {
2644 /* Allocate lock resource and initialize it */
2645 htim->Lock = HAL_UNLOCKED;
2646
2647 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2648 /* Reset interrupt callbacks to legacy weak callbacks */
2649 TIM_ResetCallback(htim);
2650
2651 if (htim->Encoder_MspInitCallback == NULL)
2652 {
2653 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
2654 }
2655 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2656 htim->Encoder_MspInitCallback(htim);
2657 #else
2658 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2659 HAL_TIM_Encoder_MspInit(htim);
2660 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2661 }
2662
2663 /* Set the TIM state */
2664 htim->State = HAL_TIM_STATE_BUSY;
2665
2666 /* Reset the SMS and ECE bits */
2667 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
2668
2669 /* Configure the Time base in the Encoder Mode */
2670 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2671
2672 /* Get the TIMx SMCR register value */
2673 tmpsmcr = htim->Instance->SMCR;
2674
2675 /* Get the TIMx CCMR1 register value */
2676 tmpccmr1 = htim->Instance->CCMR1;
2677
2678 /* Get the TIMx CCER register value */
2679 tmpccer = htim->Instance->CCER;
2680
2681 /* Set the encoder Mode */
2682 tmpsmcr |= sConfig->EncoderMode;
2683
2684 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
2685 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
2686 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
2687
2688 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
2689 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
2690 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
2691 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
2692 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
2693
2694 /* Set the TI1 and the TI2 Polarities */
2695 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
2696 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
2697 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
2698
2699 /* Write to TIMx SMCR */
2700 htim->Instance->SMCR = tmpsmcr;
2701
2702 /* Write to TIMx CCMR1 */
2703 htim->Instance->CCMR1 = tmpccmr1;
2704
2705 /* Write to TIMx CCER */
2706 htim->Instance->CCER = tmpccer;
2707
2708 /* Initialize the TIM state*/
2709 htim->State = HAL_TIM_STATE_READY;
2710
2711 return HAL_OK;
2712 }
2713
2714
2715 /**
2716 * @brief DeInitializes the TIM Encoder interface
2717 * @param htim TIM Encoder Interface handle
2718 * @retval HAL status
2719 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)2720 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
2721 {
2722 /* Check the parameters */
2723 assert_param(IS_TIM_INSTANCE(htim->Instance));
2724
2725 htim->State = HAL_TIM_STATE_BUSY;
2726
2727 /* Disable the TIM Peripheral Clock */
2728 __HAL_TIM_DISABLE(htim);
2729
2730 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2731 if (htim->Encoder_MspDeInitCallback == NULL)
2732 {
2733 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
2734 }
2735 /* DeInit the low level hardware */
2736 htim->Encoder_MspDeInitCallback(htim);
2737 #else
2738 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2739 HAL_TIM_Encoder_MspDeInit(htim);
2740 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2741
2742 /* Change TIM state */
2743 htim->State = HAL_TIM_STATE_RESET;
2744
2745 /* Release Lock */
2746 __HAL_UNLOCK(htim);
2747
2748 return HAL_OK;
2749 }
2750
2751 /**
2752 * @brief Initializes the TIM Encoder Interface MSP.
2753 * @param htim TIM Encoder Interface handle
2754 * @retval None
2755 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)2756 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
2757 {
2758 /* Prevent unused argument(s) compilation warning */
2759 UNUSED(htim);
2760
2761 /* NOTE : This function should not be modified, when the callback is needed,
2762 the HAL_TIM_Encoder_MspInit could be implemented in the user file
2763 */
2764 }
2765
2766 /**
2767 * @brief DeInitializes TIM Encoder Interface MSP.
2768 * @param htim TIM Encoder Interface handle
2769 * @retval None
2770 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)2771 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
2772 {
2773 /* Prevent unused argument(s) compilation warning */
2774 UNUSED(htim);
2775
2776 /* NOTE : This function should not be modified, when the callback is needed,
2777 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
2778 */
2779 }
2780
2781 /**
2782 * @brief Starts the TIM Encoder Interface.
2783 * @param htim TIM Encoder Interface handle
2784 * @param Channel TIM Channels to be enabled
2785 * This parameter can be one of the following values:
2786 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2787 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2788 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2789 * @retval HAL status
2790 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2791 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2792 {
2793 /* Check the parameters */
2794 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2795
2796 /* Enable the encoder interface channels */
2797 switch (Channel)
2798 {
2799 case TIM_CHANNEL_1:
2800 {
2801 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2802 break;
2803 }
2804
2805 case TIM_CHANNEL_2:
2806 {
2807 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2808 break;
2809 }
2810
2811 default :
2812 {
2813 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2814 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2815 break;
2816 }
2817 }
2818 /* Enable the Peripheral */
2819 __HAL_TIM_ENABLE(htim);
2820
2821 /* Return function status */
2822 return HAL_OK;
2823 }
2824
2825 /**
2826 * @brief Stops the TIM Encoder Interface.
2827 * @param htim TIM Encoder Interface handle
2828 * @param Channel TIM Channels to be disabled
2829 * This parameter can be one of the following values:
2830 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2831 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2832 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2833 * @retval HAL status
2834 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2835 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2836 {
2837 /* Check the parameters */
2838 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2839
2840 /* Disable the Input Capture channels 1 and 2
2841 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2842 switch (Channel)
2843 {
2844 case TIM_CHANNEL_1:
2845 {
2846 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2847 break;
2848 }
2849
2850 case TIM_CHANNEL_2:
2851 {
2852 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2853 break;
2854 }
2855
2856 default :
2857 {
2858 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2859 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2860 break;
2861 }
2862 }
2863
2864 /* Disable the Peripheral */
2865 __HAL_TIM_DISABLE(htim);
2866
2867 /* Return function status */
2868 return HAL_OK;
2869 }
2870
2871 /**
2872 * @brief Starts the TIM Encoder Interface in interrupt mode.
2873 * @param htim TIM Encoder Interface handle
2874 * @param Channel TIM Channels to be enabled
2875 * This parameter can be one of the following values:
2876 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2877 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2878 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2879 * @retval HAL status
2880 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2881 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2882 {
2883 /* Check the parameters */
2884 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2885
2886 /* Enable the encoder interface channels */
2887 /* Enable the capture compare Interrupts 1 and/or 2 */
2888 switch (Channel)
2889 {
2890 case TIM_CHANNEL_1:
2891 {
2892 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2893 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2894 break;
2895 }
2896
2897 case TIM_CHANNEL_2:
2898 {
2899 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2900 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2901 break;
2902 }
2903
2904 default :
2905 {
2906 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2907 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2908 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2909 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2910 break;
2911 }
2912 }
2913
2914 /* Enable the Peripheral */
2915 __HAL_TIM_ENABLE(htim);
2916
2917 /* Return function status */
2918 return HAL_OK;
2919 }
2920
2921 /**
2922 * @brief Stops the TIM Encoder Interface in interrupt mode.
2923 * @param htim TIM Encoder Interface handle
2924 * @param Channel TIM Channels to be disabled
2925 * This parameter can be one of the following values:
2926 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2927 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2928 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2929 * @retval HAL status
2930 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2931 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2932 {
2933 /* Check the parameters */
2934 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2935
2936 /* Disable the Input Capture channels 1 and 2
2937 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2938 if (Channel == TIM_CHANNEL_1)
2939 {
2940 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2941
2942 /* Disable the capture compare Interrupts 1 */
2943 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2944 }
2945 else if (Channel == TIM_CHANNEL_2)
2946 {
2947 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2948
2949 /* Disable the capture compare Interrupts 2 */
2950 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2951 }
2952 else
2953 {
2954 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2955 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2956
2957 /* Disable the capture compare Interrupts 1 and 2 */
2958 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2959 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2960 }
2961
2962 /* Disable the Peripheral */
2963 __HAL_TIM_DISABLE(htim);
2964
2965 /* Change the htim state */
2966 htim->State = HAL_TIM_STATE_READY;
2967
2968 /* Return function status */
2969 return HAL_OK;
2970 }
2971
2972 /**
2973 * @brief Starts the TIM Encoder Interface in DMA mode.
2974 * @param htim TIM Encoder Interface handle
2975 * @param Channel TIM Channels to be enabled
2976 * This parameter can be one of the following values:
2977 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2978 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2979 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2980 * @param pData1 The destination Buffer address for IC1.
2981 * @param pData2 The destination Buffer address for IC2.
2982 * @param Length The length of data to be transferred from TIM peripheral to memory.
2983 * @retval HAL status
2984 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)2985 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
2986 uint32_t *pData2, uint16_t Length)
2987 {
2988 /* Check the parameters */
2989 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2990
2991 if (htim->State == HAL_TIM_STATE_BUSY)
2992 {
2993 return HAL_BUSY;
2994 }
2995 else if (htim->State == HAL_TIM_STATE_READY)
2996 {
2997 if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
2998 {
2999 return HAL_ERROR;
3000 }
3001 else
3002 {
3003 htim->State = HAL_TIM_STATE_BUSY;
3004 }
3005 }
3006 else
3007 {
3008 /* nothing to do */
3009 }
3010
3011 switch (Channel)
3012 {
3013 case TIM_CHANNEL_1:
3014 {
3015 /* Set the DMA capture callbacks */
3016 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3017 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3018
3019 /* Set the DMA error callback */
3020 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3021
3022 /* Enable the DMA channel */
3023 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
3024 {
3025 return HAL_ERROR;
3026 }
3027 /* Enable the TIM Input Capture DMA request */
3028 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3029
3030 /* Enable the Peripheral */
3031 __HAL_TIM_ENABLE(htim);
3032
3033 /* Enable the Capture compare channel */
3034 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3035 break;
3036 }
3037
3038 case TIM_CHANNEL_2:
3039 {
3040 /* Set the DMA capture callbacks */
3041 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3042 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3043
3044 /* Set the DMA error callback */
3045 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3046 /* Enable the DMA channel */
3047 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
3048 {
3049 return HAL_ERROR;
3050 }
3051 /* Enable the TIM Input Capture DMA request */
3052 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3053
3054 /* Enable the Peripheral */
3055 __HAL_TIM_ENABLE(htim);
3056
3057 /* Enable the Capture compare channel */
3058 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3059 break;
3060 }
3061
3062 case TIM_CHANNEL_ALL:
3063 {
3064 /* Set the DMA capture callbacks */
3065 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3066 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3067
3068 /* Set the DMA error callback */
3069 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3070
3071 /* Enable the DMA channel */
3072 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
3073 {
3074 return HAL_ERROR;
3075 }
3076
3077 /* Set the DMA capture callbacks */
3078 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3079 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3080
3081 /* Set the DMA error callback */
3082 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3083
3084 /* Enable the DMA channel */
3085 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
3086 {
3087 return HAL_ERROR;
3088 }
3089 /* Enable the Peripheral */
3090 __HAL_TIM_ENABLE(htim);
3091
3092 /* Enable the Capture compare channel */
3093 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3094 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3095
3096 /* Enable the TIM Input Capture DMA request */
3097 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3098 /* Enable the TIM Input Capture DMA request */
3099 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3100 break;
3101 }
3102
3103 default:
3104 break;
3105 }
3106 /* Return function status */
3107 return HAL_OK;
3108 }
3109
3110 /**
3111 * @brief Stops the TIM Encoder Interface in DMA mode.
3112 * @param htim TIM Encoder Interface handle
3113 * @param Channel TIM Channels to be enabled
3114 * This parameter can be one of the following values:
3115 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3116 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3117 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3118 * @retval HAL status
3119 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3120 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3121 {
3122 /* Check the parameters */
3123 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
3124
3125 /* Disable the Input Capture channels 1 and 2
3126 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3127 if (Channel == TIM_CHANNEL_1)
3128 {
3129 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3130
3131 /* Disable the capture compare DMA Request 1 */
3132 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3133 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3134 }
3135 else if (Channel == TIM_CHANNEL_2)
3136 {
3137 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3138
3139 /* Disable the capture compare DMA Request 2 */
3140 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3141 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3142 }
3143 else
3144 {
3145 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3146 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3147
3148 /* Disable the capture compare DMA Request 1 and 2 */
3149 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3150 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3151 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3152 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3153 }
3154
3155 /* Disable the Peripheral */
3156 __HAL_TIM_DISABLE(htim);
3157
3158 /* Change the htim state */
3159 htim->State = HAL_TIM_STATE_READY;
3160
3161 /* Return function status */
3162 return HAL_OK;
3163 }
3164
3165 /**
3166 * @}
3167 */
3168 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3169 * @brief TIM IRQ handler management
3170 *
3171 @verbatim
3172 ==============================================================================
3173 ##### IRQ handler management #####
3174 ==============================================================================
3175 [..]
3176 This section provides Timer IRQ handler function.
3177
3178 @endverbatim
3179 * @{
3180 */
3181 /**
3182 * @brief This function handles TIM interrupts requests.
3183 * @param htim TIM handle
3184 * @retval None
3185 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3186 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3187 {
3188 /* Capture compare 1 event */
3189 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
3190 {
3191 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
3192 {
3193 {
3194 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
3195 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3196
3197 /* Input capture event */
3198 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3199 {
3200 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3201 htim->IC_CaptureCallback(htim);
3202 #else
3203 HAL_TIM_IC_CaptureCallback(htim);
3204 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3205 }
3206 /* Output compare event */
3207 else
3208 {
3209 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3210 htim->OC_DelayElapsedCallback(htim);
3211 htim->PWM_PulseFinishedCallback(htim);
3212 #else
3213 HAL_TIM_OC_DelayElapsedCallback(htim);
3214 HAL_TIM_PWM_PulseFinishedCallback(htim);
3215 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3216 }
3217 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3218 }
3219 }
3220 }
3221 /* Capture compare 2 event */
3222 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
3223 {
3224 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
3225 {
3226 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
3227 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3228 /* Input capture event */
3229 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3230 {
3231 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3232 htim->IC_CaptureCallback(htim);
3233 #else
3234 HAL_TIM_IC_CaptureCallback(htim);
3235 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3236 }
3237 /* Output compare event */
3238 else
3239 {
3240 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3241 htim->OC_DelayElapsedCallback(htim);
3242 htim->PWM_PulseFinishedCallback(htim);
3243 #else
3244 HAL_TIM_OC_DelayElapsedCallback(htim);
3245 HAL_TIM_PWM_PulseFinishedCallback(htim);
3246 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3247 }
3248 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3249 }
3250 }
3251 /* Capture compare 3 event */
3252 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
3253 {
3254 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
3255 {
3256 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
3257 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3258 /* Input capture event */
3259 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3260 {
3261 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3262 htim->IC_CaptureCallback(htim);
3263 #else
3264 HAL_TIM_IC_CaptureCallback(htim);
3265 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3266 }
3267 /* Output compare event */
3268 else
3269 {
3270 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3271 htim->OC_DelayElapsedCallback(htim);
3272 htim->PWM_PulseFinishedCallback(htim);
3273 #else
3274 HAL_TIM_OC_DelayElapsedCallback(htim);
3275 HAL_TIM_PWM_PulseFinishedCallback(htim);
3276 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3277 }
3278 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3279 }
3280 }
3281 /* Capture compare 4 event */
3282 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
3283 {
3284 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
3285 {
3286 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
3287 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3288 /* Input capture event */
3289 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3290 {
3291 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3292 htim->IC_CaptureCallback(htim);
3293 #else
3294 HAL_TIM_IC_CaptureCallback(htim);
3295 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3296 }
3297 /* Output compare event */
3298 else
3299 {
3300 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3301 htim->OC_DelayElapsedCallback(htim);
3302 htim->PWM_PulseFinishedCallback(htim);
3303 #else
3304 HAL_TIM_OC_DelayElapsedCallback(htim);
3305 HAL_TIM_PWM_PulseFinishedCallback(htim);
3306 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3307 }
3308 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3309 }
3310 }
3311 /* TIM Update event */
3312 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
3313 {
3314 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
3315 {
3316 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
3317 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3318 htim->PeriodElapsedCallback(htim);
3319 #else
3320 HAL_TIM_PeriodElapsedCallback(htim);
3321 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3322 }
3323 }
3324 /* TIM Break input event */
3325 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
3326 {
3327 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
3328 {
3329 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
3330 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3331 htim->BreakCallback(htim);
3332 #else
3333 HAL_TIMEx_BreakCallback(htim);
3334 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3335 }
3336 }
3337 /* TIM Break2 input event */
3338 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
3339 {
3340 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
3341 {
3342 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
3343 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3344 htim->Break2Callback(htim);
3345 #else
3346 HAL_TIMEx_Break2Callback(htim);
3347 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3348 }
3349 }
3350 /* TIM Trigger detection event */
3351 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
3352 {
3353 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
3354 {
3355 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
3356 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3357 htim->TriggerCallback(htim);
3358 #else
3359 HAL_TIM_TriggerCallback(htim);
3360 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3361 }
3362 }
3363 /* TIM commutation event */
3364 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
3365 {
3366 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
3367 {
3368 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
3369 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3370 htim->CommutationCallback(htim);
3371 #else
3372 HAL_TIMEx_CommutCallback(htim);
3373 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3374 }
3375 }
3376 }
3377
3378 /**
3379 * @}
3380 */
3381
3382 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
3383 * @brief TIM Peripheral Control functions
3384 *
3385 @verbatim
3386 ==============================================================================
3387 ##### Peripheral Control functions #####
3388 ==============================================================================
3389 [..]
3390 This section provides functions allowing to:
3391 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
3392 (+) Configure External Clock source.
3393 (+) Configure Complementary channels, break features and dead time.
3394 (+) Configure Master and the Slave synchronization.
3395 (+) Configure the DMA Burst Mode.
3396
3397 @endverbatim
3398 * @{
3399 */
3400
3401 /**
3402 * @brief Initializes the TIM Output Compare Channels according to the specified
3403 * parameters in the TIM_OC_InitTypeDef.
3404 * @param htim TIM Output Compare handle
3405 * @param sConfig TIM Output Compare configuration structure
3406 * @param Channel TIM Channels to configure
3407 * This parameter can be one of the following values:
3408 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3409 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3410 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3411 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3412 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
3413 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
3414 * @retval HAL status
3415 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OC_InitTypeDef * sConfig,uint32_t Channel)3416 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
3417 TIM_OC_InitTypeDef *sConfig,
3418 uint32_t Channel)
3419 {
3420 /* Check the parameters */
3421 assert_param(IS_TIM_CHANNELS(Channel));
3422 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
3423 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3424
3425 /* Process Locked */
3426 __HAL_LOCK(htim);
3427
3428 htim->State = HAL_TIM_STATE_BUSY;
3429
3430 switch (Channel)
3431 {
3432 case TIM_CHANNEL_1:
3433 {
3434 /* Check the parameters */
3435 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3436
3437 /* Configure the TIM Channel 1 in Output Compare */
3438 TIM_OC1_SetConfig(htim->Instance, sConfig);
3439 break;
3440 }
3441
3442 case TIM_CHANNEL_2:
3443 {
3444 /* Check the parameters */
3445 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3446
3447 /* Configure the TIM Channel 2 in Output Compare */
3448 TIM_OC2_SetConfig(htim->Instance, sConfig);
3449 break;
3450 }
3451
3452 case TIM_CHANNEL_3:
3453 {
3454 /* Check the parameters */
3455 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3456
3457 /* Configure the TIM Channel 3 in Output Compare */
3458 TIM_OC3_SetConfig(htim->Instance, sConfig);
3459 break;
3460 }
3461
3462 case TIM_CHANNEL_4:
3463 {
3464 /* Check the parameters */
3465 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3466
3467 /* Configure the TIM Channel 4 in Output Compare */
3468 TIM_OC4_SetConfig(htim->Instance, sConfig);
3469 break;
3470 }
3471
3472 case TIM_CHANNEL_5:
3473 {
3474 /* Check the parameters */
3475 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
3476
3477 /* Configure the TIM Channel 5 in Output Compare */
3478 TIM_OC5_SetConfig(htim->Instance, sConfig);
3479 break;
3480 }
3481
3482 case TIM_CHANNEL_6:
3483 {
3484 /* Check the parameters */
3485 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
3486
3487 /* Configure the TIM Channel 6 in Output Compare */
3488 TIM_OC6_SetConfig(htim->Instance, sConfig);
3489 break;
3490 }
3491
3492 default:
3493 break;
3494 }
3495
3496 htim->State = HAL_TIM_STATE_READY;
3497
3498 __HAL_UNLOCK(htim);
3499
3500 return HAL_OK;
3501 }
3502
3503 /**
3504 * @brief Initializes the TIM Input Capture Channels according to the specified
3505 * parameters in the TIM_IC_InitTypeDef.
3506 * @param htim TIM IC handle
3507 * @param sConfig TIM Input Capture configuration structure
3508 * @param Channel TIM Channel to configure
3509 * This parameter can be one of the following values:
3510 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3511 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3512 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3513 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3514 * @retval HAL status
3515 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,TIM_IC_InitTypeDef * sConfig,uint32_t Channel)3516 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
3517 {
3518 /* Check the parameters */
3519 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3520 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
3521 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
3522 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
3523 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
3524
3525 /* Process Locked */
3526 __HAL_LOCK(htim);
3527
3528 htim->State = HAL_TIM_STATE_BUSY;
3529
3530 if (Channel == TIM_CHANNEL_1)
3531 {
3532 /* TI1 Configuration */
3533 TIM_TI1_SetConfig(htim->Instance,
3534 sConfig->ICPolarity,
3535 sConfig->ICSelection,
3536 sConfig->ICFilter);
3537
3538 /* Reset the IC1PSC Bits */
3539 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3540
3541 /* Set the IC1PSC value */
3542 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
3543 }
3544 else if (Channel == TIM_CHANNEL_2)
3545 {
3546 /* TI2 Configuration */
3547 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3548
3549 TIM_TI2_SetConfig(htim->Instance,
3550 sConfig->ICPolarity,
3551 sConfig->ICSelection,
3552 sConfig->ICFilter);
3553
3554 /* Reset the IC2PSC Bits */
3555 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3556
3557 /* Set the IC2PSC value */
3558 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
3559 }
3560 else if (Channel == TIM_CHANNEL_3)
3561 {
3562 /* TI3 Configuration */
3563 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3564
3565 TIM_TI3_SetConfig(htim->Instance,
3566 sConfig->ICPolarity,
3567 sConfig->ICSelection,
3568 sConfig->ICFilter);
3569
3570 /* Reset the IC3PSC Bits */
3571 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
3572
3573 /* Set the IC3PSC value */
3574 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
3575 }
3576 else
3577 {
3578 /* TI4 Configuration */
3579 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3580
3581 TIM_TI4_SetConfig(htim->Instance,
3582 sConfig->ICPolarity,
3583 sConfig->ICSelection,
3584 sConfig->ICFilter);
3585
3586 /* Reset the IC4PSC Bits */
3587 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
3588
3589 /* Set the IC4PSC value */
3590 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
3591 }
3592
3593 htim->State = HAL_TIM_STATE_READY;
3594
3595 __HAL_UNLOCK(htim);
3596
3597 return HAL_OK;
3598 }
3599
3600 /**
3601 * @brief Initializes the TIM PWM channels according to the specified
3602 * parameters in the TIM_OC_InitTypeDef.
3603 * @param htim TIM PWM handle
3604 * @param sConfig TIM PWM configuration structure
3605 * @param Channel TIM Channels to be configured
3606 * This parameter can be one of the following values:
3607 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3608 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3609 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3610 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3611 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
3612 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
3613 * @retval HAL status
3614 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OC_InitTypeDef * sConfig,uint32_t Channel)3615 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
3616 TIM_OC_InitTypeDef *sConfig,
3617 uint32_t Channel)
3618 {
3619 /* Check the parameters */
3620 assert_param(IS_TIM_CHANNELS(Channel));
3621 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
3622 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3623 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
3624
3625 /* Process Locked */
3626 __HAL_LOCK(htim);
3627
3628 htim->State = HAL_TIM_STATE_BUSY;
3629
3630 switch (Channel)
3631 {
3632 case TIM_CHANNEL_1:
3633 {
3634 /* Check the parameters */
3635 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3636
3637 /* Configure the Channel 1 in PWM mode */
3638 TIM_OC1_SetConfig(htim->Instance, sConfig);
3639
3640 /* Set the Preload enable bit for channel1 */
3641 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
3642
3643 /* Configure the Output Fast mode */
3644 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
3645 htim->Instance->CCMR1 |= sConfig->OCFastMode;
3646 break;
3647 }
3648
3649 case TIM_CHANNEL_2:
3650 {
3651 /* Check the parameters */
3652 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3653
3654 /* Configure the Channel 2 in PWM mode */
3655 TIM_OC2_SetConfig(htim->Instance, sConfig);
3656
3657 /* Set the Preload enable bit for channel2 */
3658 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
3659
3660 /* Configure the Output Fast mode */
3661 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
3662 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
3663 break;
3664 }
3665
3666 case TIM_CHANNEL_3:
3667 {
3668 /* Check the parameters */
3669 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3670
3671 /* Configure the Channel 3 in PWM mode */
3672 TIM_OC3_SetConfig(htim->Instance, sConfig);
3673
3674 /* Set the Preload enable bit for channel3 */
3675 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
3676
3677 /* Configure the Output Fast mode */
3678 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
3679 htim->Instance->CCMR2 |= sConfig->OCFastMode;
3680 break;
3681 }
3682
3683 case TIM_CHANNEL_4:
3684 {
3685 /* Check the parameters */
3686 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3687
3688 /* Configure the Channel 4 in PWM mode */
3689 TIM_OC4_SetConfig(htim->Instance, sConfig);
3690
3691 /* Set the Preload enable bit for channel4 */
3692 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
3693
3694 /* Configure the Output Fast mode */
3695 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
3696 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
3697 break;
3698 }
3699
3700 case TIM_CHANNEL_5:
3701 {
3702 /* Check the parameters */
3703 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
3704
3705 /* Configure the Channel 5 in PWM mode */
3706 TIM_OC5_SetConfig(htim->Instance, sConfig);
3707
3708 /* Set the Preload enable bit for channel5*/
3709 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
3710
3711 /* Configure the Output Fast mode */
3712 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
3713 htim->Instance->CCMR3 |= sConfig->OCFastMode;
3714 break;
3715 }
3716
3717 case TIM_CHANNEL_6:
3718 {
3719 /* Check the parameters */
3720 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
3721
3722 /* Configure the Channel 6 in PWM mode */
3723 TIM_OC6_SetConfig(htim->Instance, sConfig);
3724
3725 /* Set the Preload enable bit for channel6 */
3726 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
3727
3728 /* Configure the Output Fast mode */
3729 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
3730 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
3731 break;
3732 }
3733
3734 default:
3735 break;
3736 }
3737
3738 htim->State = HAL_TIM_STATE_READY;
3739
3740 __HAL_UNLOCK(htim);
3741
3742 return HAL_OK;
3743 }
3744
3745 /**
3746 * @brief Initializes the TIM One Pulse Channels according to the specified
3747 * parameters in the TIM_OnePulse_InitTypeDef.
3748 * @param htim TIM One Pulse handle
3749 * @param sConfig TIM One Pulse configuration structure
3750 * @param OutputChannel TIM output channel to configure
3751 * This parameter can be one of the following values:
3752 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3753 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3754 * @param InputChannel TIM input Channel to configure
3755 * This parameter can be one of the following values:
3756 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3757 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3758 * @note To output a waveform with a minimum delay user can enable the fast
3759 * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
3760 * output is forced in response to the edge detection on TIx input,
3761 * without taking in account the comparison.
3762 * @retval HAL status
3763 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)3764 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
3765 uint32_t OutputChannel, uint32_t InputChannel)
3766 {
3767 TIM_OC_InitTypeDef temp1;
3768
3769 /* Check the parameters */
3770 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
3771 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
3772
3773 if (OutputChannel != InputChannel)
3774 {
3775 /* Process Locked */
3776 __HAL_LOCK(htim);
3777
3778 htim->State = HAL_TIM_STATE_BUSY;
3779
3780 /* Extract the Output compare configuration from sConfig structure */
3781 temp1.OCMode = sConfig->OCMode;
3782 temp1.Pulse = sConfig->Pulse;
3783 temp1.OCPolarity = sConfig->OCPolarity;
3784 temp1.OCNPolarity = sConfig->OCNPolarity;
3785 temp1.OCIdleState = sConfig->OCIdleState;
3786 temp1.OCNIdleState = sConfig->OCNIdleState;
3787
3788 switch (OutputChannel)
3789 {
3790 case TIM_CHANNEL_1:
3791 {
3792 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3793
3794 TIM_OC1_SetConfig(htim->Instance, &temp1);
3795 break;
3796 }
3797 case TIM_CHANNEL_2:
3798 {
3799 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3800
3801 TIM_OC2_SetConfig(htim->Instance, &temp1);
3802 break;
3803 }
3804 default:
3805 break;
3806 }
3807
3808 switch (InputChannel)
3809 {
3810 case TIM_CHANNEL_1:
3811 {
3812 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3813
3814 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
3815 sConfig->ICSelection, sConfig->ICFilter);
3816
3817 /* Reset the IC1PSC Bits */
3818 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3819
3820 /* Select the Trigger source */
3821 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3822 htim->Instance->SMCR |= TIM_TS_TI1FP1;
3823
3824 /* Select the Slave Mode */
3825 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3826 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3827 break;
3828 }
3829 case TIM_CHANNEL_2:
3830 {
3831 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3832
3833 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
3834 sConfig->ICSelection, sConfig->ICFilter);
3835
3836 /* Reset the IC2PSC Bits */
3837 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3838
3839 /* Select the Trigger source */
3840 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3841 htim->Instance->SMCR |= TIM_TS_TI2FP2;
3842
3843 /* Select the Slave Mode */
3844 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3845 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3846 break;
3847 }
3848
3849 default:
3850 break;
3851 }
3852
3853 htim->State = HAL_TIM_STATE_READY;
3854
3855 __HAL_UNLOCK(htim);
3856
3857 return HAL_OK;
3858 }
3859 else
3860 {
3861 return HAL_ERROR;
3862 }
3863 }
3864
3865 /**
3866 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
3867 * @param htim TIM handle
3868 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
3869 * This parameter can be one of the following values:
3870 * @arg TIM_DMABASE_CR1
3871 * @arg TIM_DMABASE_CR2
3872 * @arg TIM_DMABASE_SMCR
3873 * @arg TIM_DMABASE_DIER
3874 * @arg TIM_DMABASE_SR
3875 * @arg TIM_DMABASE_EGR
3876 * @arg TIM_DMABASE_CCMR1
3877 * @arg TIM_DMABASE_CCMR2
3878 * @arg TIM_DMABASE_CCER
3879 * @arg TIM_DMABASE_CNT
3880 * @arg TIM_DMABASE_PSC
3881 * @arg TIM_DMABASE_ARR
3882 * @arg TIM_DMABASE_RCR
3883 * @arg TIM_DMABASE_CCR1
3884 * @arg TIM_DMABASE_CCR2
3885 * @arg TIM_DMABASE_CCR3
3886 * @arg TIM_DMABASE_CCR4
3887 * @arg TIM_DMABASE_BDTR
3888 * @arg TIM_DMABASE_OR
3889 * @arg TIM_DMABASE_CCMR3
3890 * @arg TIM_DMABASE_CCR5
3891 * @arg TIM_DMABASE_CCR6
3892 * @arg TIM_DMABASE_AF1
3893 * @arg TIM_DMABASE_AF2
3894 * @param BurstRequestSrc TIM DMA Request sources
3895 * This parameter can be one of the following values:
3896 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3897 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3898 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3899 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3900 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3901 * @arg TIM_DMA_COM: TIM Commutation DMA source
3902 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3903 * @param BurstBuffer The Buffer address.
3904 * @param BurstLength DMA Burst length. This parameter can be one value
3905 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
3906 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
3907 * @retval HAL status
3908 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)3909 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3910 uint32_t *BurstBuffer, uint32_t BurstLength)
3911 {
3912 /* Check the parameters */
3913 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3914 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3915 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3916 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3917
3918 if (htim->State == HAL_TIM_STATE_BUSY)
3919 {
3920 return HAL_BUSY;
3921 }
3922 else if (htim->State == HAL_TIM_STATE_READY)
3923 {
3924 if ((BurstBuffer == NULL) && (BurstLength > 0U))
3925 {
3926 return HAL_ERROR;
3927 }
3928 else
3929 {
3930 htim->State = HAL_TIM_STATE_BUSY;
3931 }
3932 }
3933 else
3934 {
3935 /* nothing to do */
3936 }
3937 switch (BurstRequestSrc)
3938 {
3939 case TIM_DMA_UPDATE:
3940 {
3941 /* Set the DMA Period elapsed callbacks */
3942 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3943 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
3944
3945 /* Set the DMA error callback */
3946 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
3947
3948 /* Enable the DMA channel */
3949 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
3950 {
3951 return HAL_ERROR;
3952 }
3953 break;
3954 }
3955 case TIM_DMA_CC1:
3956 {
3957 /* Set the DMA compare callbacks */
3958 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
3959 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
3960
3961 /* Set the DMA error callback */
3962 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3963
3964 /* Enable the DMA channel */
3965 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
3966 (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
3967 {
3968 return HAL_ERROR;
3969 }
3970 break;
3971 }
3972 case TIM_DMA_CC2:
3973 {
3974 /* Set the DMA compare callbacks */
3975 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
3976 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
3977
3978 /* Set the DMA error callback */
3979 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3980
3981 /* Enable the DMA channel */
3982 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
3983 (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
3984 {
3985 return HAL_ERROR;
3986 }
3987 break;
3988 }
3989 case TIM_DMA_CC3:
3990 {
3991 /* Set the DMA compare callbacks */
3992 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
3993 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
3994
3995 /* Set the DMA error callback */
3996 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
3997
3998 /* Enable the DMA channel */
3999 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4000 (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4001 {
4002 return HAL_ERROR;
4003 }
4004 break;
4005 }
4006 case TIM_DMA_CC4:
4007 {
4008 /* Set the DMA compare callbacks */
4009 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4010 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4011
4012 /* Set the DMA error callback */
4013 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4014
4015 /* Enable the DMA channel */
4016 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4017 (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4018 {
4019 return HAL_ERROR;
4020 }
4021 break;
4022 }
4023 case TIM_DMA_COM:
4024 {
4025 /* Set the DMA commutation callbacks */
4026 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4027 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4028
4029 /* Set the DMA error callback */
4030 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4031
4032 /* Enable the DMA channel */
4033 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
4034 (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4035 {
4036 return HAL_ERROR;
4037 }
4038 break;
4039 }
4040 case TIM_DMA_TRIGGER:
4041 {
4042 /* Set the DMA trigger callbacks */
4043 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4044 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4045
4046 /* Set the DMA error callback */
4047 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4048
4049 /* Enable the DMA channel */
4050 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4051 (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4052 {
4053 return HAL_ERROR;
4054 }
4055 break;
4056 }
4057 default:
4058 break;
4059 }
4060 /* configure the DMA Burst Mode */
4061 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4062
4063 /* Enable the TIM DMA Request */
4064 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4065
4066 htim->State = HAL_TIM_STATE_READY;
4067
4068 /* Return function status */
4069 return HAL_OK;
4070 }
4071
4072 /**
4073 * @brief Stops the TIM DMA Burst mode
4074 * @param htim TIM handle
4075 * @param BurstRequestSrc TIM DMA Request sources to disable
4076 * @retval HAL status
4077 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4078 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4079 {
4080 HAL_StatusTypeDef status = HAL_OK;
4081 /* Check the parameters */
4082 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4083
4084 /* Abort the DMA transfer (at least disable the DMA channel) */
4085 switch (BurstRequestSrc)
4086 {
4087 case TIM_DMA_UPDATE:
4088 {
4089 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4090 break;
4091 }
4092 case TIM_DMA_CC1:
4093 {
4094 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4095 break;
4096 }
4097 case TIM_DMA_CC2:
4098 {
4099 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4100 break;
4101 }
4102 case TIM_DMA_CC3:
4103 {
4104 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4105 break;
4106 }
4107 case TIM_DMA_CC4:
4108 {
4109 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4110 break;
4111 }
4112 case TIM_DMA_COM:
4113 {
4114 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4115 break;
4116 }
4117 case TIM_DMA_TRIGGER:
4118 {
4119 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4120 break;
4121 }
4122 default:
4123 break;
4124 }
4125
4126 if (HAL_OK == status)
4127 {
4128 /* Disable the TIM Update DMA request */
4129 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4130 }
4131
4132 /* Return function status */
4133 return status;
4134 }
4135
4136 /**
4137 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4138 * @param htim TIM handle
4139 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4140 * This parameter can be one of the following values:
4141 * @arg TIM_DMABASE_CR1
4142 * @arg TIM_DMABASE_CR2
4143 * @arg TIM_DMABASE_SMCR
4144 * @arg TIM_DMABASE_DIER
4145 * @arg TIM_DMABASE_SR
4146 * @arg TIM_DMABASE_EGR
4147 * @arg TIM_DMABASE_CCMR1
4148 * @arg TIM_DMABASE_CCMR2
4149 * @arg TIM_DMABASE_CCER
4150 * @arg TIM_DMABASE_CNT
4151 * @arg TIM_DMABASE_PSC
4152 * @arg TIM_DMABASE_ARR
4153 * @arg TIM_DMABASE_RCR
4154 * @arg TIM_DMABASE_CCR1
4155 * @arg TIM_DMABASE_CCR2
4156 * @arg TIM_DMABASE_CCR3
4157 * @arg TIM_DMABASE_CCR4
4158 * @arg TIM_DMABASE_BDTR
4159 * @arg TIM_DMABASE_OR
4160 * @arg TIM_DMABASE_CCMR3
4161 * @arg TIM_DMABASE_CCR5
4162 * @arg TIM_DMABASE_CCR6
4163 * @arg TIM_DMABASE_AF1
4164 * @arg TIM_DMABASE_AF2
4165 * @param BurstRequestSrc TIM DMA Request sources
4166 * This parameter can be one of the following values:
4167 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4168 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4169 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4170 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4171 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4172 * @arg TIM_DMA_COM: TIM Commutation DMA source
4173 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4174 * @param BurstBuffer The Buffer address.
4175 * @param BurstLength DMA Burst length. This parameter can be one value
4176 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4177 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4178 * @retval HAL status
4179 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4180 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4181 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4182 {
4183 /* Check the parameters */
4184 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4185 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4186 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4187 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4188
4189 if (htim->State == HAL_TIM_STATE_BUSY)
4190 {
4191 return HAL_BUSY;
4192 }
4193 else if (htim->State == HAL_TIM_STATE_READY)
4194 {
4195 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4196 {
4197 return HAL_ERROR;
4198 }
4199 else
4200 {
4201 htim->State = HAL_TIM_STATE_BUSY;
4202 }
4203 }
4204 else
4205 {
4206 /* nothing to do */
4207 }
4208 switch (BurstRequestSrc)
4209 {
4210 case TIM_DMA_UPDATE:
4211 {
4212 /* Set the DMA Period elapsed callbacks */
4213 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4214 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4215
4216 /* Set the DMA error callback */
4217 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4218
4219 /* Enable the DMA channel */
4220 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4221 {
4222 return HAL_ERROR;
4223 }
4224 break;
4225 }
4226 case TIM_DMA_CC1:
4227 {
4228 /* Set the DMA capture callbacks */
4229 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
4230 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4231
4232 /* Set the DMA error callback */
4233 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4234
4235 /* Enable the DMA channel */
4236 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4237 {
4238 return HAL_ERROR;
4239 }
4240 break;
4241 }
4242 case TIM_DMA_CC2:
4243 {
4244 /* Set the DMA capture/compare callbacks */
4245 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
4246 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4247
4248 /* Set the DMA error callback */
4249 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4250
4251 /* Enable the DMA channel */
4252 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4253 {
4254 return HAL_ERROR;
4255 }
4256 break;
4257 }
4258 case TIM_DMA_CC3:
4259 {
4260 /* Set the DMA capture callbacks */
4261 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
4262 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4263
4264 /* Set the DMA error callback */
4265 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4266
4267 /* Enable the DMA channel */
4268 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4269 {
4270 return HAL_ERROR;
4271 }
4272 break;
4273 }
4274 case TIM_DMA_CC4:
4275 {
4276 /* Set the DMA capture callbacks */
4277 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
4278 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4279
4280 /* Set the DMA error callback */
4281 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4282
4283 /* Enable the DMA channel */
4284 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4285 {
4286 return HAL_ERROR;
4287 }
4288 break;
4289 }
4290 case TIM_DMA_COM:
4291 {
4292 /* Set the DMA commutation callbacks */
4293 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4294 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4295
4296 /* Set the DMA error callback */
4297 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4298
4299 /* Enable the DMA channel */
4300 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4301 {
4302 return HAL_ERROR;
4303 }
4304 break;
4305 }
4306 case TIM_DMA_TRIGGER:
4307 {
4308 /* Set the DMA trigger callbacks */
4309 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4310 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4311
4312 /* Set the DMA error callback */
4313 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4314
4315 /* Enable the DMA channel */
4316 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4317 {
4318 return HAL_ERROR;
4319 }
4320 break;
4321 }
4322 default:
4323 break;
4324 }
4325
4326 /* configure the DMA Burst Mode */
4327 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4328
4329 /* Enable the TIM DMA Request */
4330 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4331
4332 htim->State = HAL_TIM_STATE_READY;
4333
4334 /* Return function status */
4335 return HAL_OK;
4336 }
4337
4338 /**
4339 * @brief Stop the DMA burst reading
4340 * @param htim TIM handle
4341 * @param BurstRequestSrc TIM DMA Request sources to disable.
4342 * @retval HAL status
4343 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4344 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4345 {
4346 HAL_StatusTypeDef status = HAL_OK;
4347 /* Check the parameters */
4348 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4349
4350 /* Abort the DMA transfer (at least disable the DMA channel) */
4351 switch (BurstRequestSrc)
4352 {
4353 case TIM_DMA_UPDATE:
4354 {
4355 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4356 break;
4357 }
4358 case TIM_DMA_CC1:
4359 {
4360 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4361 break;
4362 }
4363 case TIM_DMA_CC2:
4364 {
4365 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4366 break;
4367 }
4368 case TIM_DMA_CC3:
4369 {
4370 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4371 break;
4372 }
4373 case TIM_DMA_CC4:
4374 {
4375 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4376 break;
4377 }
4378 case TIM_DMA_COM:
4379 {
4380 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4381 break;
4382 }
4383 case TIM_DMA_TRIGGER:
4384 {
4385 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4386 break;
4387 }
4388 default:
4389 break;
4390 }
4391
4392 if (HAL_OK == status)
4393 {
4394 /* Disable the TIM Update DMA request */
4395 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4396 }
4397
4398 /* Return function status */
4399 return status;
4400 }
4401
4402 /**
4403 * @brief Generate a software event
4404 * @param htim TIM handle
4405 * @param EventSource specifies the event source.
4406 * This parameter can be one of the following values:
4407 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
4408 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
4409 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
4410 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
4411 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
4412 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
4413 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
4414 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
4415 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
4416 * @note Basic timers can only generate an update event.
4417 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
4418 * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
4419 * only for timer instances supporting break input(s).
4420 * @retval HAL status
4421 */
4422
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)4423 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
4424 {
4425 /* Check the parameters */
4426 assert_param(IS_TIM_INSTANCE(htim->Instance));
4427 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
4428
4429 /* Process Locked */
4430 __HAL_LOCK(htim);
4431
4432 /* Change the TIM state */
4433 htim->State = HAL_TIM_STATE_BUSY;
4434
4435 /* Set the event sources */
4436 htim->Instance->EGR = EventSource;
4437
4438 /* Change the TIM state */
4439 htim->State = HAL_TIM_STATE_READY;
4440
4441 __HAL_UNLOCK(htim);
4442
4443 /* Return function status */
4444 return HAL_OK;
4445 }
4446
4447 /**
4448 * @brief Configures the OCRef clear feature
4449 * @param htim TIM handle
4450 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
4451 * contains the OCREF clear feature and parameters for the TIM peripheral.
4452 * @param Channel specifies the TIM Channel
4453 * This parameter can be one of the following values:
4454 * @arg TIM_CHANNEL_1: TIM Channel 1
4455 * @arg TIM_CHANNEL_2: TIM Channel 2
4456 * @arg TIM_CHANNEL_3: TIM Channel 3
4457 * @arg TIM_CHANNEL_4: TIM Channel 4
4458 * @arg TIM_CHANNEL_5: TIM Channel 5
4459 * @arg TIM_CHANNEL_6: TIM Channel 6
4460 * @retval HAL status
4461 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)4462 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
4463 TIM_ClearInputConfigTypeDef *sClearInputConfig,
4464 uint32_t Channel)
4465 {
4466 /* Check the parameters */
4467 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
4468 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
4469
4470 /* Process Locked */
4471 __HAL_LOCK(htim);
4472
4473 htim->State = HAL_TIM_STATE_BUSY;
4474
4475 switch (sClearInputConfig->ClearInputSource)
4476 {
4477 case TIM_CLEARINPUTSOURCE_NONE:
4478 {
4479 /* Clear the OCREF clear selection bit and the the ETR Bits */
4480 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
4481
4482 /* Clear TIMx_AF1_OCREF_CLR (reset value) */
4483 CLEAR_BIT(htim->Instance->AF1, TIM1_AF1_ETRSEL);
4484 break;
4485 }
4486 case TIM_CLEARINPUTSOURCE_COMP1:
4487 case TIM_CLEARINPUTSOURCE_COMP2:
4488 {
4489 /* Clear the OCREF clear selection bit */
4490 CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
4491
4492 /* OCREF_CLR_INT is connected to COMPx output */
4493 MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL, sClearInputConfig->ClearInputSource);
4494 break;
4495 }
4496
4497 case TIM_CLEARINPUTSOURCE_ETR:
4498 {
4499 /* Check the parameters */
4500 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
4501 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
4502 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
4503
4504 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
4505 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
4506 {
4507 htim->State = HAL_TIM_STATE_READY;
4508 __HAL_UNLOCK(htim);
4509 return HAL_ERROR;
4510 }
4511
4512 TIM_ETR_SetConfig(htim->Instance,
4513 sClearInputConfig->ClearInputPrescaler,
4514 sClearInputConfig->ClearInputPolarity,
4515 sClearInputConfig->ClearInputFilter);
4516
4517 /* Set the OCREF clear selection bit */
4518 SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
4519
4520 /* Clear TIMx_AF1_OCREF_CLR (reset value) */
4521 CLEAR_BIT(htim->Instance->AF1, TIM1_AF1_ETRSEL);
4522 break;
4523 }
4524
4525 default:
4526 break;
4527 }
4528
4529 switch (Channel)
4530 {
4531 case TIM_CHANNEL_1:
4532 {
4533 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4534 {
4535 /* Enable the OCREF clear feature for Channel 1 */
4536 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
4537 }
4538 else
4539 {
4540 /* Disable the OCREF clear feature for Channel 1 */
4541 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
4542 }
4543 break;
4544 }
4545 case TIM_CHANNEL_2:
4546 {
4547 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4548 {
4549 /* Enable the OCREF clear feature for Channel 2 */
4550 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
4551 }
4552 else
4553 {
4554 /* Disable the OCREF clear feature for Channel 2 */
4555 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
4556 }
4557 break;
4558 }
4559 case TIM_CHANNEL_3:
4560 {
4561 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4562 {
4563 /* Enable the OCREF clear feature for Channel 3 */
4564 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
4565 }
4566 else
4567 {
4568 /* Disable the OCREF clear feature for Channel 3 */
4569 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
4570 }
4571 break;
4572 }
4573 case TIM_CHANNEL_4:
4574 {
4575 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4576 {
4577 /* Enable the OCREF clear feature for Channel 4 */
4578 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
4579 }
4580 else
4581 {
4582 /* Disable the OCREF clear feature for Channel 4 */
4583 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
4584 }
4585 break;
4586 }
4587 case TIM_CHANNEL_5:
4588 {
4589 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4590 {
4591 /* Enable the OCREF clear feature for Channel 5 */
4592 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
4593 }
4594 else
4595 {
4596 /* Disable the OCREF clear feature for Channel 5 */
4597 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
4598 }
4599 break;
4600 }
4601 case TIM_CHANNEL_6:
4602 {
4603 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4604 {
4605 /* Enable the OCREF clear feature for Channel 6 */
4606 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
4607 }
4608 else
4609 {
4610 /* Disable the OCREF clear feature for Channel 6 */
4611 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
4612 }
4613 break;
4614 }
4615 default:
4616 break;
4617 }
4618
4619 htim->State = HAL_TIM_STATE_READY;
4620
4621 __HAL_UNLOCK(htim);
4622
4623 return HAL_OK;
4624 }
4625
4626 /**
4627 * @brief Configures the clock source to be used
4628 * @param htim TIM handle
4629 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
4630 * contains the clock source information for the TIM peripheral.
4631 * @retval HAL status
4632 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,TIM_ClockConfigTypeDef * sClockSourceConfig)4633 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
4634 {
4635 uint32_t tmpsmcr;
4636
4637 /* Process Locked */
4638 __HAL_LOCK(htim);
4639
4640 htim->State = HAL_TIM_STATE_BUSY;
4641
4642 /* Check the parameters */
4643 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
4644
4645 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
4646 tmpsmcr = htim->Instance->SMCR;
4647 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
4648 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
4649 htim->Instance->SMCR = tmpsmcr;
4650
4651 switch (sClockSourceConfig->ClockSource)
4652 {
4653 case TIM_CLOCKSOURCE_INTERNAL:
4654 {
4655 assert_param(IS_TIM_INSTANCE(htim->Instance));
4656 break;
4657 }
4658
4659 case TIM_CLOCKSOURCE_ETRMODE1:
4660 {
4661 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
4662 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
4663
4664 /* Check ETR input conditioning related parameters */
4665 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
4666 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4667 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4668
4669 /* Configure the ETR Clock source */
4670 TIM_ETR_SetConfig(htim->Instance,
4671 sClockSourceConfig->ClockPrescaler,
4672 sClockSourceConfig->ClockPolarity,
4673 sClockSourceConfig->ClockFilter);
4674
4675 /* Select the External clock mode1 and the ETRF trigger */
4676 tmpsmcr = htim->Instance->SMCR;
4677 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
4678 /* Write to TIMx SMCR */
4679 htim->Instance->SMCR = tmpsmcr;
4680 break;
4681 }
4682
4683 case TIM_CLOCKSOURCE_ETRMODE2:
4684 {
4685 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
4686 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
4687
4688 /* Check ETR input conditioning related parameters */
4689 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
4690 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4691 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4692
4693 /* Configure the ETR Clock source */
4694 TIM_ETR_SetConfig(htim->Instance,
4695 sClockSourceConfig->ClockPrescaler,
4696 sClockSourceConfig->ClockPolarity,
4697 sClockSourceConfig->ClockFilter);
4698 /* Enable the External clock mode2 */
4699 htim->Instance->SMCR |= TIM_SMCR_ECE;
4700 break;
4701 }
4702
4703 case TIM_CLOCKSOURCE_TI1:
4704 {
4705 /* Check whether or not the timer instance supports external clock mode 1 */
4706 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
4707
4708 /* Check TI1 input conditioning related parameters */
4709 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4710 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4711
4712 TIM_TI1_ConfigInputStage(htim->Instance,
4713 sClockSourceConfig->ClockPolarity,
4714 sClockSourceConfig->ClockFilter);
4715 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
4716 break;
4717 }
4718
4719 case TIM_CLOCKSOURCE_TI2:
4720 {
4721 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
4722 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
4723
4724 /* Check TI2 input conditioning related parameters */
4725 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4726 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4727
4728 TIM_TI2_ConfigInputStage(htim->Instance,
4729 sClockSourceConfig->ClockPolarity,
4730 sClockSourceConfig->ClockFilter);
4731 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
4732 break;
4733 }
4734
4735 case TIM_CLOCKSOURCE_TI1ED:
4736 {
4737 /* Check whether or not the timer instance supports external clock mode 1 */
4738 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
4739
4740 /* Check TI1 input conditioning related parameters */
4741 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4742 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4743
4744 TIM_TI1_ConfigInputStage(htim->Instance,
4745 sClockSourceConfig->ClockPolarity,
4746 sClockSourceConfig->ClockFilter);
4747 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
4748 break;
4749 }
4750
4751 case TIM_CLOCKSOURCE_ITR0:
4752 case TIM_CLOCKSOURCE_ITR1:
4753 case TIM_CLOCKSOURCE_ITR2:
4754 case TIM_CLOCKSOURCE_ITR3:
4755 {
4756 /* Check whether or not the timer instance supports internal trigger input */
4757 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
4758
4759 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
4760 break;
4761 }
4762
4763 default:
4764 break;
4765 }
4766 htim->State = HAL_TIM_STATE_READY;
4767
4768 __HAL_UNLOCK(htim);
4769
4770 return HAL_OK;
4771 }
4772
4773 /**
4774 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
4775 * or a XOR combination between CH1_input, CH2_input & CH3_input
4776 * @param htim TIM handle.
4777 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
4778 * output of a XOR gate.
4779 * This parameter can be one of the following values:
4780 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
4781 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
4782 * pins are connected to the TI1 input (XOR combination)
4783 * @retval HAL status
4784 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)4785 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
4786 {
4787 uint32_t tmpcr2;
4788
4789 /* Check the parameters */
4790 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
4791 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
4792
4793 /* Get the TIMx CR2 register value */
4794 tmpcr2 = htim->Instance->CR2;
4795
4796 /* Reset the TI1 selection */
4797 tmpcr2 &= ~TIM_CR2_TI1S;
4798
4799 /* Set the TI1 selection */
4800 tmpcr2 |= TI1_Selection;
4801
4802 /* Write to TIMxCR2 */
4803 htim->Instance->CR2 = tmpcr2;
4804
4805 return HAL_OK;
4806 }
4807
4808 /**
4809 * @brief Configures the TIM in Slave mode
4810 * @param htim TIM handle.
4811 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
4812 * contains the selected trigger (internal trigger input, filtered
4813 * timer input or external trigger input) and the Slave mode
4814 * (Disable, Reset, Gated, Trigger, External clock mode 1).
4815 * @retval HAL status
4816 */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)4817 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
4818 {
4819 /* Check the parameters */
4820 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
4821 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
4822 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4823
4824 __HAL_LOCK(htim);
4825
4826 htim->State = HAL_TIM_STATE_BUSY;
4827
4828 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
4829 {
4830 htim->State = HAL_TIM_STATE_READY;
4831 __HAL_UNLOCK(htim);
4832 return HAL_ERROR;
4833 }
4834
4835 /* Disable Trigger Interrupt */
4836 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
4837
4838 /* Disable Trigger DMA request */
4839 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
4840
4841 htim->State = HAL_TIM_STATE_READY;
4842
4843 __HAL_UNLOCK(htim);
4844
4845 return HAL_OK;
4846 }
4847
4848 /**
4849 * @brief Configures the TIM in Slave mode in interrupt mode
4850 * @param htim TIM handle.
4851 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
4852 * contains the selected trigger (internal trigger input, filtered
4853 * timer input or external trigger input) and the Slave mode
4854 * (Disable, Reset, Gated, Trigger, External clock mode 1).
4855 * @retval HAL status
4856 */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)4857 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
4858 TIM_SlaveConfigTypeDef *sSlaveConfig)
4859 {
4860 /* Check the parameters */
4861 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
4862 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
4863 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4864
4865 __HAL_LOCK(htim);
4866
4867 htim->State = HAL_TIM_STATE_BUSY;
4868
4869 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
4870 {
4871 htim->State = HAL_TIM_STATE_READY;
4872 __HAL_UNLOCK(htim);
4873 return HAL_ERROR;
4874 }
4875
4876 /* Enable Trigger Interrupt */
4877 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
4878
4879 /* Disable Trigger DMA request */
4880 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
4881
4882 htim->State = HAL_TIM_STATE_READY;
4883
4884 __HAL_UNLOCK(htim);
4885
4886 return HAL_OK;
4887 }
4888
4889 /**
4890 * @brief Read the captured value from Capture Compare unit
4891 * @param htim TIM handle.
4892 * @param Channel TIM Channels to be enabled
4893 * This parameter can be one of the following values:
4894 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4895 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4896 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4897 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4898 * @retval Captured value
4899 */
HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef * htim,uint32_t Channel)4900 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
4901 {
4902 uint32_t tmpreg = 0U;
4903
4904 switch (Channel)
4905 {
4906 case TIM_CHANNEL_1:
4907 {
4908 /* Check the parameters */
4909 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4910
4911 /* Return the capture 1 value */
4912 tmpreg = htim->Instance->CCR1;
4913
4914 break;
4915 }
4916 case TIM_CHANNEL_2:
4917 {
4918 /* Check the parameters */
4919 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4920
4921 /* Return the capture 2 value */
4922 tmpreg = htim->Instance->CCR2;
4923
4924 break;
4925 }
4926
4927 case TIM_CHANNEL_3:
4928 {
4929 /* Check the parameters */
4930 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4931
4932 /* Return the capture 3 value */
4933 tmpreg = htim->Instance->CCR3;
4934
4935 break;
4936 }
4937
4938 case TIM_CHANNEL_4:
4939 {
4940 /* Check the parameters */
4941 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4942
4943 /* Return the capture 4 value */
4944 tmpreg = htim->Instance->CCR4;
4945
4946 break;
4947 }
4948
4949 default:
4950 break;
4951 }
4952
4953 return tmpreg;
4954 }
4955
4956 /**
4957 * @}
4958 */
4959
4960 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
4961 * @brief TIM Callbacks functions
4962 *
4963 @verbatim
4964 ==============================================================================
4965 ##### TIM Callbacks functions #####
4966 ==============================================================================
4967 [..]
4968 This section provides TIM callback functions:
4969 (+) TIM Period elapsed callback
4970 (+) TIM Output Compare callback
4971 (+) TIM Input capture callback
4972 (+) TIM Trigger callback
4973 (+) TIM Error callback
4974
4975 @endverbatim
4976 * @{
4977 */
4978
4979 /**
4980 * @brief Period elapsed callback in non-blocking mode
4981 * @param htim TIM handle
4982 * @retval None
4983 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)4984 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
4985 {
4986 /* Prevent unused argument(s) compilation warning */
4987 UNUSED(htim);
4988
4989 /* NOTE : This function should not be modified, when the callback is needed,
4990 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
4991 */
4992 }
4993
4994 /**
4995 * @brief Period elapsed half complete callback in non-blocking mode
4996 * @param htim TIM handle
4997 * @retval None
4998 */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)4999 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
5000 {
5001 /* Prevent unused argument(s) compilation warning */
5002 UNUSED(htim);
5003
5004 /* NOTE : This function should not be modified, when the callback is needed,
5005 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
5006 */
5007 }
5008
5009 /**
5010 * @brief Output Compare callback in non-blocking mode
5011 * @param htim TIM OC handle
5012 * @retval None
5013 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)5014 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
5015 {
5016 /* Prevent unused argument(s) compilation warning */
5017 UNUSED(htim);
5018
5019 /* NOTE : This function should not be modified, when the callback is needed,
5020 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
5021 */
5022 }
5023
5024 /**
5025 * @brief Input Capture callback in non-blocking mode
5026 * @param htim TIM IC handle
5027 * @retval None
5028 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)5029 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
5030 {
5031 /* Prevent unused argument(s) compilation warning */
5032 UNUSED(htim);
5033
5034 /* NOTE : This function should not be modified, when the callback is needed,
5035 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
5036 */
5037 }
5038
5039 /**
5040 * @brief Input Capture half complete callback in non-blocking mode
5041 * @param htim TIM IC handle
5042 * @retval None
5043 */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)5044 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
5045 {
5046 /* Prevent unused argument(s) compilation warning */
5047 UNUSED(htim);
5048
5049 /* NOTE : This function should not be modified, when the callback is needed,
5050 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
5051 */
5052 }
5053
5054 /**
5055 * @brief PWM Pulse finished callback in non-blocking mode
5056 * @param htim TIM handle
5057 * @retval None
5058 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)5059 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
5060 {
5061 /* Prevent unused argument(s) compilation warning */
5062 UNUSED(htim);
5063
5064 /* NOTE : This function should not be modified, when the callback is needed,
5065 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
5066 */
5067 }
5068
5069 /**
5070 * @brief PWM Pulse finished half complete callback in non-blocking mode
5071 * @param htim TIM handle
5072 * @retval None
5073 */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)5074 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
5075 {
5076 /* Prevent unused argument(s) compilation warning */
5077 UNUSED(htim);
5078
5079 /* NOTE : This function should not be modified, when the callback is needed,
5080 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
5081 */
5082 }
5083
5084 /**
5085 * @brief Hall Trigger detection callback in non-blocking mode
5086 * @param htim TIM handle
5087 * @retval None
5088 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)5089 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
5090 {
5091 /* Prevent unused argument(s) compilation warning */
5092 UNUSED(htim);
5093
5094 /* NOTE : This function should not be modified, when the callback is needed,
5095 the HAL_TIM_TriggerCallback could be implemented in the user file
5096 */
5097 }
5098
5099 /**
5100 * @brief Hall Trigger detection half complete callback in non-blocking mode
5101 * @param htim TIM handle
5102 * @retval None
5103 */
HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef * htim)5104 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
5105 {
5106 /* Prevent unused argument(s) compilation warning */
5107 UNUSED(htim);
5108
5109 /* NOTE : This function should not be modified, when the callback is needed,
5110 the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
5111 */
5112 }
5113
5114 /**
5115 * @brief Timer error callback in non-blocking mode
5116 * @param htim TIM handle
5117 * @retval None
5118 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)5119 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
5120 {
5121 /* Prevent unused argument(s) compilation warning */
5122 UNUSED(htim);
5123
5124 /* NOTE : This function should not be modified, when the callback is needed,
5125 the HAL_TIM_ErrorCallback could be implemented in the user file
5126 */
5127 }
5128
5129 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5130 /**
5131 * @brief Register a User TIM callback to be used instead of the weak predefined callback
5132 * @param htim tim handle
5133 * @param CallbackID ID of the callback to be registered
5134 * This parameter can be one of the following values:
5135 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5136 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5137 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5138 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5139 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5140 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5141 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5142 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5143 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5144 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5145 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5146 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5147 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5148 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5149 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5150 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5151 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5152 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5153 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5154 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5155 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5156 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5157 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5158 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5159 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
5160 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
5161 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
5162 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
5163 * @param pCallback pointer to the callback function
5164 * @retval status
5165 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)5166 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
5167 pTIM_CallbackTypeDef pCallback)
5168 {
5169 HAL_StatusTypeDef status = HAL_OK;
5170
5171 if (pCallback == NULL)
5172 {
5173 return HAL_ERROR;
5174 }
5175 /* Process locked */
5176 __HAL_LOCK(htim);
5177
5178 if (htim->State == HAL_TIM_STATE_READY)
5179 {
5180 switch (CallbackID)
5181 {
5182 case HAL_TIM_BASE_MSPINIT_CB_ID :
5183 htim->Base_MspInitCallback = pCallback;
5184 break;
5185
5186 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5187 htim->Base_MspDeInitCallback = pCallback;
5188 break;
5189
5190 case HAL_TIM_IC_MSPINIT_CB_ID :
5191 htim->IC_MspInitCallback = pCallback;
5192 break;
5193
5194 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5195 htim->IC_MspDeInitCallback = pCallback;
5196 break;
5197
5198 case HAL_TIM_OC_MSPINIT_CB_ID :
5199 htim->OC_MspInitCallback = pCallback;
5200 break;
5201
5202 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5203 htim->OC_MspDeInitCallback = pCallback;
5204 break;
5205
5206 case HAL_TIM_PWM_MSPINIT_CB_ID :
5207 htim->PWM_MspInitCallback = pCallback;
5208 break;
5209
5210 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5211 htim->PWM_MspDeInitCallback = pCallback;
5212 break;
5213
5214 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5215 htim->OnePulse_MspInitCallback = pCallback;
5216 break;
5217
5218 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5219 htim->OnePulse_MspDeInitCallback = pCallback;
5220 break;
5221
5222 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5223 htim->Encoder_MspInitCallback = pCallback;
5224 break;
5225
5226 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5227 htim->Encoder_MspDeInitCallback = pCallback;
5228 break;
5229
5230 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5231 htim->HallSensor_MspInitCallback = pCallback;
5232 break;
5233
5234 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5235 htim->HallSensor_MspDeInitCallback = pCallback;
5236 break;
5237
5238 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5239 htim->PeriodElapsedCallback = pCallback;
5240 break;
5241
5242 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
5243 htim->PeriodElapsedHalfCpltCallback = pCallback;
5244 break;
5245
5246 case HAL_TIM_TRIGGER_CB_ID :
5247 htim->TriggerCallback = pCallback;
5248 break;
5249
5250 case HAL_TIM_TRIGGER_HALF_CB_ID :
5251 htim->TriggerHalfCpltCallback = pCallback;
5252 break;
5253
5254 case HAL_TIM_IC_CAPTURE_CB_ID :
5255 htim->IC_CaptureCallback = pCallback;
5256 break;
5257
5258 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
5259 htim->IC_CaptureHalfCpltCallback = pCallback;
5260 break;
5261
5262 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5263 htim->OC_DelayElapsedCallback = pCallback;
5264 break;
5265
5266 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5267 htim->PWM_PulseFinishedCallback = pCallback;
5268 break;
5269
5270 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
5271 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
5272 break;
5273
5274 case HAL_TIM_ERROR_CB_ID :
5275 htim->ErrorCallback = pCallback;
5276 break;
5277
5278 case HAL_TIM_COMMUTATION_CB_ID :
5279 htim->CommutationCallback = pCallback;
5280 break;
5281
5282 case HAL_TIM_COMMUTATION_HALF_CB_ID :
5283 htim->CommutationHalfCpltCallback = pCallback;
5284 break;
5285
5286 case HAL_TIM_BREAK_CB_ID :
5287 htim->BreakCallback = pCallback;
5288 break;
5289
5290 case HAL_TIM_BREAK2_CB_ID :
5291 htim->Break2Callback = pCallback;
5292 break;
5293
5294 default :
5295 /* Return error status */
5296 status = HAL_ERROR;
5297 break;
5298 }
5299 }
5300 else if (htim->State == HAL_TIM_STATE_RESET)
5301 {
5302 switch (CallbackID)
5303 {
5304 case HAL_TIM_BASE_MSPINIT_CB_ID :
5305 htim->Base_MspInitCallback = pCallback;
5306 break;
5307
5308 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5309 htim->Base_MspDeInitCallback = pCallback;
5310 break;
5311
5312 case HAL_TIM_IC_MSPINIT_CB_ID :
5313 htim->IC_MspInitCallback = pCallback;
5314 break;
5315
5316 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5317 htim->IC_MspDeInitCallback = pCallback;
5318 break;
5319
5320 case HAL_TIM_OC_MSPINIT_CB_ID :
5321 htim->OC_MspInitCallback = pCallback;
5322 break;
5323
5324 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5325 htim->OC_MspDeInitCallback = pCallback;
5326 break;
5327
5328 case HAL_TIM_PWM_MSPINIT_CB_ID :
5329 htim->PWM_MspInitCallback = pCallback;
5330 break;
5331
5332 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5333 htim->PWM_MspDeInitCallback = pCallback;
5334 break;
5335
5336 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5337 htim->OnePulse_MspInitCallback = pCallback;
5338 break;
5339
5340 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5341 htim->OnePulse_MspDeInitCallback = pCallback;
5342 break;
5343
5344 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5345 htim->Encoder_MspInitCallback = pCallback;
5346 break;
5347
5348 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5349 htim->Encoder_MspDeInitCallback = pCallback;
5350 break;
5351
5352 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5353 htim->HallSensor_MspInitCallback = pCallback;
5354 break;
5355
5356 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5357 htim->HallSensor_MspDeInitCallback = pCallback;
5358 break;
5359
5360 default :
5361 /* Return error status */
5362 status = HAL_ERROR;
5363 break;
5364 }
5365 }
5366 else
5367 {
5368 /* Return error status */
5369 status = HAL_ERROR;
5370 }
5371
5372 /* Release Lock */
5373 __HAL_UNLOCK(htim);
5374
5375 return status;
5376 }
5377
5378 /**
5379 * @brief Unregister a TIM callback
5380 * TIM callback is redirected to the weak predefined callback
5381 * @param htim tim handle
5382 * @param CallbackID ID of the callback to be unregistered
5383 * This parameter can be one of the following values:
5384 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5385 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5386 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5387 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5388 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5389 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5390 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5391 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5392 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5393 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5394 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5395 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5396 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5397 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5398 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5399 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5400 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5401 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5402 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5403 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5404 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5405 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5406 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5407 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5408 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
5409 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
5410 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
5411 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
5412 * @retval status
5413 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)5414 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
5415 {
5416 HAL_StatusTypeDef status = HAL_OK;
5417
5418 /* Process locked */
5419 __HAL_LOCK(htim);
5420
5421 if (htim->State == HAL_TIM_STATE_READY)
5422 {
5423 switch (CallbackID)
5424 {
5425 case HAL_TIM_BASE_MSPINIT_CB_ID :
5426 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
5427 break;
5428
5429 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5430 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
5431 break;
5432
5433 case HAL_TIM_IC_MSPINIT_CB_ID :
5434 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
5435 break;
5436
5437 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5438 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
5439 break;
5440
5441 case HAL_TIM_OC_MSPINIT_CB_ID :
5442 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
5443 break;
5444
5445 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5446 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
5447 break;
5448
5449 case HAL_TIM_PWM_MSPINIT_CB_ID :
5450 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
5451 break;
5452
5453 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5454 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
5455 break;
5456
5457 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5458 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
5459 break;
5460
5461 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5462 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
5463 break;
5464
5465 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5466 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
5467 break;
5468
5469 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5470 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
5471 break;
5472
5473 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5474 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
5475 break;
5476
5477 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5478 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
5479 break;
5480
5481 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5482 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
5483 break;
5484
5485 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
5486 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */
5487 break;
5488
5489 case HAL_TIM_TRIGGER_CB_ID :
5490 htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
5491 break;
5492
5493 case HAL_TIM_TRIGGER_HALF_CB_ID :
5494 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */
5495 break;
5496
5497 case HAL_TIM_IC_CAPTURE_CB_ID :
5498 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
5499 break;
5500
5501 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
5502 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */
5503 break;
5504
5505 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5506 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
5507 break;
5508
5509 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5510 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
5511 break;
5512
5513 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
5514 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
5515 break;
5516
5517 case HAL_TIM_ERROR_CB_ID :
5518 htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
5519 break;
5520
5521 case HAL_TIM_COMMUTATION_CB_ID :
5522 htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */
5523 break;
5524
5525 case HAL_TIM_COMMUTATION_HALF_CB_ID :
5526 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */
5527 break;
5528
5529 case HAL_TIM_BREAK_CB_ID :
5530 htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
5531 break;
5532
5533 case HAL_TIM_BREAK2_CB_ID :
5534 htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */
5535 break;
5536
5537 default :
5538 /* Return error status */
5539 status = HAL_ERROR;
5540 break;
5541 }
5542 }
5543 else if (htim->State == HAL_TIM_STATE_RESET)
5544 {
5545 switch (CallbackID)
5546 {
5547 case HAL_TIM_BASE_MSPINIT_CB_ID :
5548 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
5549 break;
5550
5551 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5552 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
5553 break;
5554
5555 case HAL_TIM_IC_MSPINIT_CB_ID :
5556 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
5557 break;
5558
5559 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5560 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
5561 break;
5562
5563 case HAL_TIM_OC_MSPINIT_CB_ID :
5564 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
5565 break;
5566
5567 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5568 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
5569 break;
5570
5571 case HAL_TIM_PWM_MSPINIT_CB_ID :
5572 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
5573 break;
5574
5575 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5576 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
5577 break;
5578
5579 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5580 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
5581 break;
5582
5583 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5584 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
5585 break;
5586
5587 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5588 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
5589 break;
5590
5591 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5592 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
5593 break;
5594
5595 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5596 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
5597 break;
5598
5599 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5600 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
5601 break;
5602
5603 default :
5604 /* Return error status */
5605 status = HAL_ERROR;
5606 break;
5607 }
5608 }
5609 else
5610 {
5611 /* Return error status */
5612 status = HAL_ERROR;
5613 }
5614
5615 /* Release Lock */
5616 __HAL_UNLOCK(htim);
5617
5618 return status;
5619 }
5620 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5621
5622 /**
5623 * @}
5624 */
5625
5626 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
5627 * @brief TIM Peripheral State functions
5628 *
5629 @verbatim
5630 ==============================================================================
5631 ##### Peripheral State functions #####
5632 ==============================================================================
5633 [..]
5634 This subsection permits to get in run-time the status of the peripheral
5635 and the data flow.
5636
5637 @endverbatim
5638 * @{
5639 */
5640
5641 /**
5642 * @brief Return the TIM Base handle state.
5643 * @param htim TIM Base handle
5644 * @retval HAL state
5645 */
HAL_TIM_Base_GetState(TIM_HandleTypeDef * htim)5646 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
5647 {
5648 return htim->State;
5649 }
5650
5651 /**
5652 * @brief Return the TIM OC handle state.
5653 * @param htim TIM Output Compare handle
5654 * @retval HAL state
5655 */
HAL_TIM_OC_GetState(TIM_HandleTypeDef * htim)5656 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
5657 {
5658 return htim->State;
5659 }
5660
5661 /**
5662 * @brief Return the TIM PWM handle state.
5663 * @param htim TIM handle
5664 * @retval HAL state
5665 */
HAL_TIM_PWM_GetState(TIM_HandleTypeDef * htim)5666 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
5667 {
5668 return htim->State;
5669 }
5670
5671 /**
5672 * @brief Return the TIM Input Capture handle state.
5673 * @param htim TIM IC handle
5674 * @retval HAL state
5675 */
HAL_TIM_IC_GetState(TIM_HandleTypeDef * htim)5676 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
5677 {
5678 return htim->State;
5679 }
5680
5681 /**
5682 * @brief Return the TIM One Pulse Mode handle state.
5683 * @param htim TIM OPM handle
5684 * @retval HAL state
5685 */
HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef * htim)5686 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
5687 {
5688 return htim->State;
5689 }
5690
5691 /**
5692 * @brief Return the TIM Encoder Mode handle state.
5693 * @param htim TIM Encoder Interface handle
5694 * @retval HAL state
5695 */
HAL_TIM_Encoder_GetState(TIM_HandleTypeDef * htim)5696 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
5697 {
5698 return htim->State;
5699 }
5700
5701 /**
5702 * @}
5703 */
5704
5705 /**
5706 * @}
5707 */
5708
5709 /** @defgroup TIM_Private_Functions TIM Private Functions
5710 * @{
5711 */
5712
5713 /**
5714 * @brief TIM DMA error callback
5715 * @param hdma pointer to DMA handle.
5716 * @retval None
5717 */
TIM_DMAError(DMA_HandleTypeDef * hdma)5718 void TIM_DMAError(DMA_HandleTypeDef *hdma)
5719 {
5720 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5721
5722 htim->State = HAL_TIM_STATE_READY;
5723
5724 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5725 htim->ErrorCallback(htim);
5726 #else
5727 HAL_TIM_ErrorCallback(htim);
5728 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5729 }
5730
5731 /**
5732 * @brief TIM DMA Delay Pulse complete callback.
5733 * @param hdma pointer to DMA handle.
5734 * @retval None
5735 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)5736 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
5737 {
5738 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5739
5740 htim->State = HAL_TIM_STATE_READY;
5741
5742 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
5743 {
5744 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
5745 }
5746 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
5747 {
5748 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
5749 }
5750 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
5751 {
5752 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
5753 }
5754 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
5755 {
5756 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
5757 }
5758 else
5759 {
5760 /* nothing to do */
5761 }
5762
5763 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5764 htim->PWM_PulseFinishedCallback(htim);
5765 #else
5766 HAL_TIM_PWM_PulseFinishedCallback(htim);
5767 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5768
5769 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
5770 }
5771
5772 /**
5773 * @brief TIM DMA Delay Pulse half complete callback.
5774 * @param hdma pointer to DMA handle.
5775 * @retval None
5776 */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)5777 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
5778 {
5779 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5780
5781 htim->State = HAL_TIM_STATE_READY;
5782
5783 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
5784 {
5785 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
5786 }
5787 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
5788 {
5789 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
5790 }
5791 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
5792 {
5793 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
5794 }
5795 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
5796 {
5797 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
5798 }
5799 else
5800 {
5801 /* nothing to do */
5802 }
5803
5804 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5805 htim->PWM_PulseFinishedHalfCpltCallback(htim);
5806 #else
5807 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
5808 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5809
5810 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
5811 }
5812
5813 /**
5814 * @brief TIM DMA Capture complete callback.
5815 * @param hdma pointer to DMA handle.
5816 * @retval None
5817 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)5818 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
5819 {
5820 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5821
5822 htim->State = HAL_TIM_STATE_READY;
5823
5824 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
5825 {
5826 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
5827 }
5828 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
5829 {
5830 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
5831 }
5832 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
5833 {
5834 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
5835 }
5836 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
5837 {
5838 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
5839 }
5840 else
5841 {
5842 /* nothing to do */
5843 }
5844
5845 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5846 htim->IC_CaptureCallback(htim);
5847 #else
5848 HAL_TIM_IC_CaptureCallback(htim);
5849 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5850
5851 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
5852 }
5853
5854 /**
5855 * @brief TIM DMA Capture half complete callback.
5856 * @param hdma pointer to DMA handle.
5857 * @retval None
5858 */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)5859 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
5860 {
5861 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5862
5863 htim->State = HAL_TIM_STATE_READY;
5864
5865 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
5866 {
5867 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
5868 }
5869 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
5870 {
5871 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
5872 }
5873 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
5874 {
5875 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
5876 }
5877 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
5878 {
5879 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
5880 }
5881 else
5882 {
5883 /* nothing to do */
5884 }
5885
5886 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5887 htim->IC_CaptureHalfCpltCallback(htim);
5888 #else
5889 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
5890 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5891
5892 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
5893 }
5894
5895 /**
5896 * @brief TIM DMA Period Elapse complete callback.
5897 * @param hdma pointer to DMA handle.
5898 * @retval None
5899 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)5900 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
5901 {
5902 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5903
5904 htim->State = HAL_TIM_STATE_READY;
5905
5906 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5907 htim->PeriodElapsedCallback(htim);
5908 #else
5909 HAL_TIM_PeriodElapsedCallback(htim);
5910 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5911 }
5912
5913 /**
5914 * @brief TIM DMA Period Elapse half complete callback.
5915 * @param hdma pointer to DMA handle.
5916 * @retval None
5917 */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)5918 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
5919 {
5920 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5921
5922 htim->State = HAL_TIM_STATE_READY;
5923
5924 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5925 htim->PeriodElapsedHalfCpltCallback(htim);
5926 #else
5927 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
5928 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5929 }
5930
5931 /**
5932 * @brief TIM DMA Trigger callback.
5933 * @param hdma pointer to DMA handle.
5934 * @retval None
5935 */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)5936 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
5937 {
5938 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5939
5940 htim->State = HAL_TIM_STATE_READY;
5941
5942 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5943 htim->TriggerCallback(htim);
5944 #else
5945 HAL_TIM_TriggerCallback(htim);
5946 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5947 }
5948
5949 /**
5950 * @brief TIM DMA Trigger half complete callback.
5951 * @param hdma pointer to DMA handle.
5952 * @retval None
5953 */
TIM_DMATriggerHalfCplt(DMA_HandleTypeDef * hdma)5954 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
5955 {
5956 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5957
5958 htim->State = HAL_TIM_STATE_READY;
5959
5960 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5961 htim->TriggerHalfCpltCallback(htim);
5962 #else
5963 HAL_TIM_TriggerHalfCpltCallback(htim);
5964 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5965 }
5966
5967 /**
5968 * @brief Time Base configuration
5969 * @param TIMx TIM peripheral
5970 * @param Structure TIM Base configuration structure
5971 * @retval None
5972 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,TIM_Base_InitTypeDef * Structure)5973 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
5974 {
5975 uint32_t tmpcr1;
5976 tmpcr1 = TIMx->CR1;
5977
5978 /* Set TIM Time Base Unit parameters ---------------------------------------*/
5979 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
5980 {
5981 /* Select the Counter Mode */
5982 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
5983 tmpcr1 |= Structure->CounterMode;
5984 }
5985
5986 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
5987 {
5988 /* Set the clock division */
5989 tmpcr1 &= ~TIM_CR1_CKD;
5990 tmpcr1 |= (uint32_t)Structure->ClockDivision;
5991 }
5992
5993 /* Set the auto-reload preload */
5994 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
5995
5996 TIMx->CR1 = tmpcr1;
5997
5998 /* Set the Autoreload value */
5999 TIMx->ARR = (uint32_t)Structure->Period ;
6000
6001 /* Set the Prescaler value */
6002 TIMx->PSC = Structure->Prescaler;
6003
6004 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
6005 {
6006 /* Set the Repetition Counter value */
6007 TIMx->RCR = Structure->RepetitionCounter;
6008 }
6009
6010 /* Generate an update event to reload the Prescaler
6011 and the repetition counter (only for advanced timer) value immediately */
6012 TIMx->EGR = TIM_EGR_UG;
6013 }
6014
6015 /**
6016 * @brief Timer Output Compare 1 configuration
6017 * @param TIMx to select the TIM peripheral
6018 * @param OC_Config The ouput configuration structure
6019 * @retval None
6020 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6021 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6022 {
6023 uint32_t tmpccmrx;
6024 uint32_t tmpccer;
6025 uint32_t tmpcr2;
6026
6027 /* Disable the Channel 1: Reset the CC1E Bit */
6028 TIMx->CCER &= ~TIM_CCER_CC1E;
6029
6030 /* Get the TIMx CCER register value */
6031 tmpccer = TIMx->CCER;
6032 /* Get the TIMx CR2 register value */
6033 tmpcr2 = TIMx->CR2;
6034
6035 /* Get the TIMx CCMR1 register value */
6036 tmpccmrx = TIMx->CCMR1;
6037
6038 /* Reset the Output Compare Mode Bits */
6039 tmpccmrx &= ~TIM_CCMR1_OC1M;
6040 tmpccmrx &= ~TIM_CCMR1_CC1S;
6041 /* Select the Output Compare Mode */
6042 tmpccmrx |= OC_Config->OCMode;
6043
6044 /* Reset the Output Polarity level */
6045 tmpccer &= ~TIM_CCER_CC1P;
6046 /* Set the Output Compare Polarity */
6047 tmpccer |= OC_Config->OCPolarity;
6048
6049 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
6050 {
6051 /* Check parameters */
6052 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6053
6054 /* Reset the Output N Polarity level */
6055 tmpccer &= ~TIM_CCER_CC1NP;
6056 /* Set the Output N Polarity */
6057 tmpccer |= OC_Config->OCNPolarity;
6058 /* Reset the Output N State */
6059 tmpccer &= ~TIM_CCER_CC1NE;
6060 }
6061
6062 if (IS_TIM_BREAK_INSTANCE(TIMx))
6063 {
6064 /* Check parameters */
6065 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6066 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6067
6068 /* Reset the Output Compare and Output Compare N IDLE State */
6069 tmpcr2 &= ~TIM_CR2_OIS1;
6070 tmpcr2 &= ~TIM_CR2_OIS1N;
6071 /* Set the Output Idle state */
6072 tmpcr2 |= OC_Config->OCIdleState;
6073 /* Set the Output N Idle state */
6074 tmpcr2 |= OC_Config->OCNIdleState;
6075 }
6076
6077 /* Write to TIMx CR2 */
6078 TIMx->CR2 = tmpcr2;
6079
6080 /* Write to TIMx CCMR1 */
6081 TIMx->CCMR1 = tmpccmrx;
6082
6083 /* Set the Capture Compare Register value */
6084 TIMx->CCR1 = OC_Config->Pulse;
6085
6086 /* Write to TIMx CCER */
6087 TIMx->CCER = tmpccer;
6088 }
6089
6090 /**
6091 * @brief Timer Output Compare 2 configuration
6092 * @param TIMx to select the TIM peripheral
6093 * @param OC_Config The ouput configuration structure
6094 * @retval None
6095 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6096 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6097 {
6098 uint32_t tmpccmrx;
6099 uint32_t tmpccer;
6100 uint32_t tmpcr2;
6101
6102 /* Disable the Channel 2: Reset the CC2E Bit */
6103 TIMx->CCER &= ~TIM_CCER_CC2E;
6104
6105 /* Get the TIMx CCER register value */
6106 tmpccer = TIMx->CCER;
6107 /* Get the TIMx CR2 register value */
6108 tmpcr2 = TIMx->CR2;
6109
6110 /* Get the TIMx CCMR1 register value */
6111 tmpccmrx = TIMx->CCMR1;
6112
6113 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6114 tmpccmrx &= ~TIM_CCMR1_OC2M;
6115 tmpccmrx &= ~TIM_CCMR1_CC2S;
6116
6117 /* Select the Output Compare Mode */
6118 tmpccmrx |= (OC_Config->OCMode << 8U);
6119
6120 /* Reset the Output Polarity level */
6121 tmpccer &= ~TIM_CCER_CC2P;
6122 /* Set the Output Compare Polarity */
6123 tmpccer |= (OC_Config->OCPolarity << 4U);
6124
6125 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
6126 {
6127 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6128
6129 /* Reset the Output N Polarity level */
6130 tmpccer &= ~TIM_CCER_CC2NP;
6131 /* Set the Output N Polarity */
6132 tmpccer |= (OC_Config->OCNPolarity << 4U);
6133 /* Reset the Output N State */
6134 tmpccer &= ~TIM_CCER_CC2NE;
6135
6136 }
6137
6138 if (IS_TIM_BREAK_INSTANCE(TIMx))
6139 {
6140 /* Check parameters */
6141 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6142 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6143
6144 /* Reset the Output Compare and Output Compare N IDLE State */
6145 tmpcr2 &= ~TIM_CR2_OIS2;
6146 tmpcr2 &= ~TIM_CR2_OIS2N;
6147 /* Set the Output Idle state */
6148 tmpcr2 |= (OC_Config->OCIdleState << 2U);
6149 /* Set the Output N Idle state */
6150 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
6151 }
6152
6153 /* Write to TIMx CR2 */
6154 TIMx->CR2 = tmpcr2;
6155
6156 /* Write to TIMx CCMR1 */
6157 TIMx->CCMR1 = tmpccmrx;
6158
6159 /* Set the Capture Compare Register value */
6160 TIMx->CCR2 = OC_Config->Pulse;
6161
6162 /* Write to TIMx CCER */
6163 TIMx->CCER = tmpccer;
6164 }
6165
6166 /**
6167 * @brief Timer Output Compare 3 configuration
6168 * @param TIMx to select the TIM peripheral
6169 * @param OC_Config The ouput configuration structure
6170 * @retval None
6171 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6172 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6173 {
6174 uint32_t tmpccmrx;
6175 uint32_t tmpccer;
6176 uint32_t tmpcr2;
6177
6178 /* Disable the Channel 3: Reset the CC2E Bit */
6179 TIMx->CCER &= ~TIM_CCER_CC3E;
6180
6181 /* Get the TIMx CCER register value */
6182 tmpccer = TIMx->CCER;
6183 /* Get the TIMx CR2 register value */
6184 tmpcr2 = TIMx->CR2;
6185
6186 /* Get the TIMx CCMR2 register value */
6187 tmpccmrx = TIMx->CCMR2;
6188
6189 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6190 tmpccmrx &= ~TIM_CCMR2_OC3M;
6191 tmpccmrx &= ~TIM_CCMR2_CC3S;
6192 /* Select the Output Compare Mode */
6193 tmpccmrx |= OC_Config->OCMode;
6194
6195 /* Reset the Output Polarity level */
6196 tmpccer &= ~TIM_CCER_CC3P;
6197 /* Set the Output Compare Polarity */
6198 tmpccer |= (OC_Config->OCPolarity << 8U);
6199
6200 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
6201 {
6202 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6203
6204 /* Reset the Output N Polarity level */
6205 tmpccer &= ~TIM_CCER_CC3NP;
6206 /* Set the Output N Polarity */
6207 tmpccer |= (OC_Config->OCNPolarity << 8U);
6208 /* Reset the Output N State */
6209 tmpccer &= ~TIM_CCER_CC3NE;
6210 }
6211
6212 if (IS_TIM_BREAK_INSTANCE(TIMx))
6213 {
6214 /* Check parameters */
6215 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6216 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6217
6218 /* Reset the Output Compare and Output Compare N IDLE State */
6219 tmpcr2 &= ~TIM_CR2_OIS3;
6220 tmpcr2 &= ~TIM_CR2_OIS3N;
6221 /* Set the Output Idle state */
6222 tmpcr2 |= (OC_Config->OCIdleState << 4U);
6223 /* Set the Output N Idle state */
6224 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
6225 }
6226
6227 /* Write to TIMx CR2 */
6228 TIMx->CR2 = tmpcr2;
6229
6230 /* Write to TIMx CCMR2 */
6231 TIMx->CCMR2 = tmpccmrx;
6232
6233 /* Set the Capture Compare Register value */
6234 TIMx->CCR3 = OC_Config->Pulse;
6235
6236 /* Write to TIMx CCER */
6237 TIMx->CCER = tmpccer;
6238 }
6239
6240 /**
6241 * @brief Timer Output Compare 4 configuration
6242 * @param TIMx to select the TIM peripheral
6243 * @param OC_Config The ouput configuration structure
6244 * @retval None
6245 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6246 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6247 {
6248 uint32_t tmpccmrx;
6249 uint32_t tmpccer;
6250 uint32_t tmpcr2;
6251
6252 /* Disable the Channel 4: Reset the CC4E Bit */
6253 TIMx->CCER &= ~TIM_CCER_CC4E;
6254
6255 /* Get the TIMx CCER register value */
6256 tmpccer = TIMx->CCER;
6257 /* Get the TIMx CR2 register value */
6258 tmpcr2 = TIMx->CR2;
6259
6260 /* Get the TIMx CCMR2 register value */
6261 tmpccmrx = TIMx->CCMR2;
6262
6263 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6264 tmpccmrx &= ~TIM_CCMR2_OC4M;
6265 tmpccmrx &= ~TIM_CCMR2_CC4S;
6266
6267 /* Select the Output Compare Mode */
6268 tmpccmrx |= (OC_Config->OCMode << 8U);
6269
6270 /* Reset the Output Polarity level */
6271 tmpccer &= ~TIM_CCER_CC4P;
6272 /* Set the Output Compare Polarity */
6273 tmpccer |= (OC_Config->OCPolarity << 12U);
6274
6275 if (IS_TIM_BREAK_INSTANCE(TIMx))
6276 {
6277 /* Check parameters */
6278 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6279
6280 /* Reset the Output Compare IDLE State */
6281 tmpcr2 &= ~TIM_CR2_OIS4;
6282
6283 /* Set the Output Idle state */
6284 tmpcr2 |= (OC_Config->OCIdleState << 6U);
6285 }
6286
6287 /* Write to TIMx CR2 */
6288 TIMx->CR2 = tmpcr2;
6289
6290 /* Write to TIMx CCMR2 */
6291 TIMx->CCMR2 = tmpccmrx;
6292
6293 /* Set the Capture Compare Register value */
6294 TIMx->CCR4 = OC_Config->Pulse;
6295
6296 /* Write to TIMx CCER */
6297 TIMx->CCER = tmpccer;
6298 }
6299
6300 /**
6301 * @brief Timer Output Compare 5 configuration
6302 * @param TIMx to select the TIM peripheral
6303 * @param OC_Config The ouput configuration structure
6304 * @retval None
6305 */
TIM_OC5_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6306 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
6307 TIM_OC_InitTypeDef *OC_Config)
6308 {
6309 uint32_t tmpccmrx;
6310 uint32_t tmpccer;
6311 uint32_t tmpcr2;
6312
6313 /* Disable the output: Reset the CCxE Bit */
6314 TIMx->CCER &= ~TIM_CCER_CC5E;
6315
6316 /* Get the TIMx CCER register value */
6317 tmpccer = TIMx->CCER;
6318 /* Get the TIMx CR2 register value */
6319 tmpcr2 = TIMx->CR2;
6320 /* Get the TIMx CCMR1 register value */
6321 tmpccmrx = TIMx->CCMR3;
6322
6323 /* Reset the Output Compare Mode Bits */
6324 tmpccmrx &= ~(TIM_CCMR3_OC5M);
6325 /* Select the Output Compare Mode */
6326 tmpccmrx |= OC_Config->OCMode;
6327
6328 /* Reset the Output Polarity level */
6329 tmpccer &= ~TIM_CCER_CC5P;
6330 /* Set the Output Compare Polarity */
6331 tmpccer |= (OC_Config->OCPolarity << 16U);
6332
6333 if (IS_TIM_BREAK_INSTANCE(TIMx))
6334 {
6335 /* Reset the Output Compare IDLE State */
6336 tmpcr2 &= ~TIM_CR2_OIS5;
6337 /* Set the Output Idle state */
6338 tmpcr2 |= (OC_Config->OCIdleState << 8U);
6339 }
6340 /* Write to TIMx CR2 */
6341 TIMx->CR2 = tmpcr2;
6342
6343 /* Write to TIMx CCMR3 */
6344 TIMx->CCMR3 = tmpccmrx;
6345
6346 /* Set the Capture Compare Register value */
6347 TIMx->CCR5 = OC_Config->Pulse;
6348
6349 /* Write to TIMx CCER */
6350 TIMx->CCER = tmpccer;
6351 }
6352
6353 /**
6354 * @brief Timer Output Compare 6 configuration
6355 * @param TIMx to select the TIM peripheral
6356 * @param OC_Config The ouput configuration structure
6357 * @retval None
6358 */
TIM_OC6_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6359 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
6360 TIM_OC_InitTypeDef *OC_Config)
6361 {
6362 uint32_t tmpccmrx;
6363 uint32_t tmpccer;
6364 uint32_t tmpcr2;
6365
6366 /* Disable the output: Reset the CCxE Bit */
6367 TIMx->CCER &= ~TIM_CCER_CC6E;
6368
6369 /* Get the TIMx CCER register value */
6370 tmpccer = TIMx->CCER;
6371 /* Get the TIMx CR2 register value */
6372 tmpcr2 = TIMx->CR2;
6373 /* Get the TIMx CCMR1 register value */
6374 tmpccmrx = TIMx->CCMR3;
6375
6376 /* Reset the Output Compare Mode Bits */
6377 tmpccmrx &= ~(TIM_CCMR3_OC6M);
6378 /* Select the Output Compare Mode */
6379 tmpccmrx |= (OC_Config->OCMode << 8U);
6380
6381 /* Reset the Output Polarity level */
6382 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
6383 /* Set the Output Compare Polarity */
6384 tmpccer |= (OC_Config->OCPolarity << 20U);
6385
6386 if (IS_TIM_BREAK_INSTANCE(TIMx))
6387 {
6388 /* Reset the Output Compare IDLE State */
6389 tmpcr2 &= ~TIM_CR2_OIS6;
6390 /* Set the Output Idle state */
6391 tmpcr2 |= (OC_Config->OCIdleState << 10U);
6392 }
6393
6394 /* Write to TIMx CR2 */
6395 TIMx->CR2 = tmpcr2;
6396
6397 /* Write to TIMx CCMR3 */
6398 TIMx->CCMR3 = tmpccmrx;
6399
6400 /* Set the Capture Compare Register value */
6401 TIMx->CCR6 = OC_Config->Pulse;
6402
6403 /* Write to TIMx CCER */
6404 TIMx->CCER = tmpccer;
6405 }
6406
6407 /**
6408 * @brief Slave Timer configuration function
6409 * @param htim TIM handle
6410 * @param sSlaveConfig Slave timer configuration
6411 * @retval None
6412 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)6413 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
6414 TIM_SlaveConfigTypeDef *sSlaveConfig)
6415 {
6416 uint32_t tmpsmcr;
6417 uint32_t tmpccmr1;
6418 uint32_t tmpccer;
6419
6420 /* Get the TIMx SMCR register value */
6421 tmpsmcr = htim->Instance->SMCR;
6422
6423 /* Reset the Trigger Selection Bits */
6424 tmpsmcr &= ~TIM_SMCR_TS;
6425 /* Set the Input Trigger source */
6426 tmpsmcr |= sSlaveConfig->InputTrigger;
6427
6428 /* Reset the slave mode Bits */
6429 tmpsmcr &= ~TIM_SMCR_SMS;
6430 /* Set the slave mode */
6431 tmpsmcr |= sSlaveConfig->SlaveMode;
6432
6433 /* Write to TIMx SMCR */
6434 htim->Instance->SMCR = tmpsmcr;
6435
6436 /* Configure the trigger prescaler, filter, and polarity */
6437 switch (sSlaveConfig->InputTrigger)
6438 {
6439 case TIM_TS_ETRF:
6440 {
6441 /* Check the parameters */
6442 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
6443 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
6444 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6445 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6446 /* Configure the ETR Trigger source */
6447 TIM_ETR_SetConfig(htim->Instance,
6448 sSlaveConfig->TriggerPrescaler,
6449 sSlaveConfig->TriggerPolarity,
6450 sSlaveConfig->TriggerFilter);
6451 break;
6452 }
6453
6454 case TIM_TS_TI1F_ED:
6455 {
6456 /* Check the parameters */
6457 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
6458 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6459
6460 if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
6461 {
6462 return HAL_ERROR;
6463 }
6464
6465 /* Disable the Channel 1: Reset the CC1E Bit */
6466 tmpccer = htim->Instance->CCER;
6467 htim->Instance->CCER &= ~TIM_CCER_CC1E;
6468 tmpccmr1 = htim->Instance->CCMR1;
6469
6470 /* Set the filter */
6471 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6472 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
6473
6474 /* Write to TIMx CCMR1 and CCER registers */
6475 htim->Instance->CCMR1 = tmpccmr1;
6476 htim->Instance->CCER = tmpccer;
6477 break;
6478 }
6479
6480 case TIM_TS_TI1FP1:
6481 {
6482 /* Check the parameters */
6483 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
6484 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6485 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6486
6487 /* Configure TI1 Filter and Polarity */
6488 TIM_TI1_ConfigInputStage(htim->Instance,
6489 sSlaveConfig->TriggerPolarity,
6490 sSlaveConfig->TriggerFilter);
6491 break;
6492 }
6493
6494 case TIM_TS_TI2FP2:
6495 {
6496 /* Check the parameters */
6497 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
6498 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6499 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6500
6501 /* Configure TI2 Filter and Polarity */
6502 TIM_TI2_ConfigInputStage(htim->Instance,
6503 sSlaveConfig->TriggerPolarity,
6504 sSlaveConfig->TriggerFilter);
6505 break;
6506 }
6507
6508 case TIM_TS_ITR0:
6509 case TIM_TS_ITR1:
6510 case TIM_TS_ITR2:
6511 case TIM_TS_ITR3:
6512 {
6513 /* Check the parameter */
6514 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
6515 break;
6516 }
6517
6518 default:
6519 break;
6520 }
6521 return HAL_OK;
6522 }
6523
6524 /**
6525 * @brief Configure the TI1 as Input.
6526 * @param TIMx to select the TIM peripheral.
6527 * @param TIM_ICPolarity The Input Polarity.
6528 * This parameter can be one of the following values:
6529 * @arg TIM_ICPOLARITY_RISING
6530 * @arg TIM_ICPOLARITY_FALLING
6531 * @arg TIM_ICPOLARITY_BOTHEDGE
6532 * @param TIM_ICSelection specifies the input to be used.
6533 * This parameter can be one of the following values:
6534 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
6535 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
6536 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
6537 * @param TIM_ICFilter Specifies the Input Capture Filter.
6538 * This parameter must be a value between 0x00 and 0x0F.
6539 * @retval None
6540 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
6541 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
6542 * protected against un-initialized filter and polarity values.
6543 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6544 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6545 uint32_t TIM_ICFilter)
6546 {
6547 uint32_t tmpccmr1;
6548 uint32_t tmpccer;
6549
6550 /* Disable the Channel 1: Reset the CC1E Bit */
6551 TIMx->CCER &= ~TIM_CCER_CC1E;
6552 tmpccmr1 = TIMx->CCMR1;
6553 tmpccer = TIMx->CCER;
6554
6555 /* Select the Input */
6556 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
6557 {
6558 tmpccmr1 &= ~TIM_CCMR1_CC1S;
6559 tmpccmr1 |= TIM_ICSelection;
6560 }
6561 else
6562 {
6563 tmpccmr1 |= TIM_CCMR1_CC1S_0;
6564 }
6565
6566 /* Set the filter */
6567 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6568 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
6569
6570 /* Select the Polarity and set the CC1E Bit */
6571 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
6572 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
6573
6574 /* Write to TIMx CCMR1 and CCER registers */
6575 TIMx->CCMR1 = tmpccmr1;
6576 TIMx->CCER = tmpccer;
6577 }
6578
6579 /**
6580 * @brief Configure the Polarity and Filter for TI1.
6581 * @param TIMx to select the TIM peripheral.
6582 * @param TIM_ICPolarity The Input Polarity.
6583 * This parameter can be one of the following values:
6584 * @arg TIM_ICPOLARITY_RISING
6585 * @arg TIM_ICPOLARITY_FALLING
6586 * @arg TIM_ICPOLARITY_BOTHEDGE
6587 * @param TIM_ICFilter Specifies the Input Capture Filter.
6588 * This parameter must be a value between 0x00 and 0x0F.
6589 * @retval None
6590 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)6591 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
6592 {
6593 uint32_t tmpccmr1;
6594 uint32_t tmpccer;
6595
6596 /* Disable the Channel 1: Reset the CC1E Bit */
6597 tmpccer = TIMx->CCER;
6598 TIMx->CCER &= ~TIM_CCER_CC1E;
6599 tmpccmr1 = TIMx->CCMR1;
6600
6601 /* Set the filter */
6602 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6603 tmpccmr1 |= (TIM_ICFilter << 4U);
6604
6605 /* Select the Polarity and set the CC1E Bit */
6606 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
6607 tmpccer |= TIM_ICPolarity;
6608
6609 /* Write to TIMx CCMR1 and CCER registers */
6610 TIMx->CCMR1 = tmpccmr1;
6611 TIMx->CCER = tmpccer;
6612 }
6613
6614 /**
6615 * @brief Configure the TI2 as Input.
6616 * @param TIMx to select the TIM peripheral
6617 * @param TIM_ICPolarity The Input Polarity.
6618 * This parameter can be one of the following values:
6619 * @arg TIM_ICPOLARITY_RISING
6620 * @arg TIM_ICPOLARITY_FALLING
6621 * @arg TIM_ICPOLARITY_BOTHEDGE
6622 * @param TIM_ICSelection specifies the input to be used.
6623 * This parameter can be one of the following values:
6624 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
6625 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
6626 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
6627 * @param TIM_ICFilter Specifies the Input Capture Filter.
6628 * This parameter must be a value between 0x00 and 0x0F.
6629 * @retval None
6630 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
6631 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
6632 * protected against un-initialized filter and polarity values.
6633 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6634 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6635 uint32_t TIM_ICFilter)
6636 {
6637 uint32_t tmpccmr1;
6638 uint32_t tmpccer;
6639
6640 /* Disable the Channel 2: Reset the CC2E Bit */
6641 TIMx->CCER &= ~TIM_CCER_CC2E;
6642 tmpccmr1 = TIMx->CCMR1;
6643 tmpccer = TIMx->CCER;
6644
6645 /* Select the Input */
6646 tmpccmr1 &= ~TIM_CCMR1_CC2S;
6647 tmpccmr1 |= (TIM_ICSelection << 8U);
6648
6649 /* Set the filter */
6650 tmpccmr1 &= ~TIM_CCMR1_IC2F;
6651 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
6652
6653 /* Select the Polarity and set the CC2E Bit */
6654 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
6655 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
6656
6657 /* Write to TIMx CCMR1 and CCER registers */
6658 TIMx->CCMR1 = tmpccmr1 ;
6659 TIMx->CCER = tmpccer;
6660 }
6661
6662 /**
6663 * @brief Configure the Polarity and Filter for TI2.
6664 * @param TIMx to select the TIM peripheral.
6665 * @param TIM_ICPolarity The Input Polarity.
6666 * This parameter can be one of the following values:
6667 * @arg TIM_ICPOLARITY_RISING
6668 * @arg TIM_ICPOLARITY_FALLING
6669 * @arg TIM_ICPOLARITY_BOTHEDGE
6670 * @param TIM_ICFilter Specifies the Input Capture Filter.
6671 * This parameter must be a value between 0x00 and 0x0F.
6672 * @retval None
6673 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)6674 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
6675 {
6676 uint32_t tmpccmr1;
6677 uint32_t tmpccer;
6678
6679 /* Disable the Channel 2: Reset the CC2E Bit */
6680 TIMx->CCER &= ~TIM_CCER_CC2E;
6681 tmpccmr1 = TIMx->CCMR1;
6682 tmpccer = TIMx->CCER;
6683
6684 /* Set the filter */
6685 tmpccmr1 &= ~TIM_CCMR1_IC2F;
6686 tmpccmr1 |= (TIM_ICFilter << 12U);
6687
6688 /* Select the Polarity and set the CC2E Bit */
6689 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
6690 tmpccer |= (TIM_ICPolarity << 4U);
6691
6692 /* Write to TIMx CCMR1 and CCER registers */
6693 TIMx->CCMR1 = tmpccmr1 ;
6694 TIMx->CCER = tmpccer;
6695 }
6696
6697 /**
6698 * @brief Configure the TI3 as Input.
6699 * @param TIMx to select the TIM peripheral
6700 * @param TIM_ICPolarity The Input Polarity.
6701 * This parameter can be one of the following values:
6702 * @arg TIM_ICPOLARITY_RISING
6703 * @arg TIM_ICPOLARITY_FALLING
6704 * @arg TIM_ICPOLARITY_BOTHEDGE
6705 * @param TIM_ICSelection specifies the input to be used.
6706 * This parameter can be one of the following values:
6707 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
6708 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
6709 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
6710 * @param TIM_ICFilter Specifies the Input Capture Filter.
6711 * This parameter must be a value between 0x00 and 0x0F.
6712 * @retval None
6713 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
6714 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
6715 * protected against un-initialized filter and polarity values.
6716 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6717 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6718 uint32_t TIM_ICFilter)
6719 {
6720 uint32_t tmpccmr2;
6721 uint32_t tmpccer;
6722
6723 /* Disable the Channel 3: Reset the CC3E Bit */
6724 TIMx->CCER &= ~TIM_CCER_CC3E;
6725 tmpccmr2 = TIMx->CCMR2;
6726 tmpccer = TIMx->CCER;
6727
6728 /* Select the Input */
6729 tmpccmr2 &= ~TIM_CCMR2_CC3S;
6730 tmpccmr2 |= TIM_ICSelection;
6731
6732 /* Set the filter */
6733 tmpccmr2 &= ~TIM_CCMR2_IC3F;
6734 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
6735
6736 /* Select the Polarity and set the CC3E Bit */
6737 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
6738 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
6739
6740 /* Write to TIMx CCMR2 and CCER registers */
6741 TIMx->CCMR2 = tmpccmr2;
6742 TIMx->CCER = tmpccer;
6743 }
6744
6745 /**
6746 * @brief Configure the TI4 as Input.
6747 * @param TIMx to select the TIM peripheral
6748 * @param TIM_ICPolarity The Input Polarity.
6749 * This parameter can be one of the following values:
6750 * @arg TIM_ICPOLARITY_RISING
6751 * @arg TIM_ICPOLARITY_FALLING
6752 * @arg TIM_ICPOLARITY_BOTHEDGE
6753 * @param TIM_ICSelection specifies the input to be used.
6754 * This parameter can be one of the following values:
6755 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
6756 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
6757 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
6758 * @param TIM_ICFilter Specifies the Input Capture Filter.
6759 * This parameter must be a value between 0x00 and 0x0F.
6760 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
6761 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
6762 * protected against un-initialized filter and polarity values.
6763 * @retval None
6764 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6765 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6766 uint32_t TIM_ICFilter)
6767 {
6768 uint32_t tmpccmr2;
6769 uint32_t tmpccer;
6770
6771 /* Disable the Channel 4: Reset the CC4E Bit */
6772 TIMx->CCER &= ~TIM_CCER_CC4E;
6773 tmpccmr2 = TIMx->CCMR2;
6774 tmpccer = TIMx->CCER;
6775
6776 /* Select the Input */
6777 tmpccmr2 &= ~TIM_CCMR2_CC4S;
6778 tmpccmr2 |= (TIM_ICSelection << 8U);
6779
6780 /* Set the filter */
6781 tmpccmr2 &= ~TIM_CCMR2_IC4F;
6782 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
6783
6784 /* Select the Polarity and set the CC4E Bit */
6785 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
6786 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
6787
6788 /* Write to TIMx CCMR2 and CCER registers */
6789 TIMx->CCMR2 = tmpccmr2;
6790 TIMx->CCER = tmpccer ;
6791 }
6792
6793 /**
6794 * @brief Selects the Input Trigger source
6795 * @param TIMx to select the TIM peripheral
6796 * @param InputTriggerSource The Input Trigger source.
6797 * This parameter can be one of the following values:
6798 * @arg TIM_TS_ITR0: Internal Trigger 0
6799 * @arg TIM_TS_ITR1: Internal Trigger 1
6800 * @arg TIM_TS_ITR2: Internal Trigger 2
6801 * @arg TIM_TS_ITR3: Internal Trigger 3
6802 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
6803 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
6804 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
6805 * @arg TIM_TS_ETRF: External Trigger input
6806 * @retval None
6807 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)6808 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
6809 {
6810 uint32_t tmpsmcr;
6811
6812 /* Get the TIMx SMCR register value */
6813 tmpsmcr = TIMx->SMCR;
6814 /* Reset the TS Bits */
6815 tmpsmcr &= ~TIM_SMCR_TS;
6816 /* Set the Input Trigger source and the slave mode*/
6817 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
6818 /* Write to TIMx SMCR */
6819 TIMx->SMCR = tmpsmcr;
6820 }
6821 /**
6822 * @brief Configures the TIMx External Trigger (ETR).
6823 * @param TIMx to select the TIM peripheral
6824 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
6825 * This parameter can be one of the following values:
6826 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
6827 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
6828 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
6829 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
6830 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
6831 * This parameter can be one of the following values:
6832 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
6833 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
6834 * @param ExtTRGFilter External Trigger Filter.
6835 * This parameter must be a value between 0x00 and 0x0F
6836 * @retval None
6837 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)6838 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
6839 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
6840 {
6841 uint32_t tmpsmcr;
6842
6843 tmpsmcr = TIMx->SMCR;
6844
6845 /* Reset the ETR Bits */
6846 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
6847
6848 /* Set the Prescaler, the Filter value and the Polarity */
6849 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
6850
6851 /* Write to TIMx SMCR */
6852 TIMx->SMCR = tmpsmcr;
6853 }
6854
6855 /**
6856 * @brief Enables or disables the TIM Capture Compare Channel x.
6857 * @param TIMx to select the TIM peripheral
6858 * @param Channel specifies the TIM Channel
6859 * This parameter can be one of the following values:
6860 * @arg TIM_CHANNEL_1: TIM Channel 1
6861 * @arg TIM_CHANNEL_2: TIM Channel 2
6862 * @arg TIM_CHANNEL_3: TIM Channel 3
6863 * @arg TIM_CHANNEL_4: TIM Channel 4
6864 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
6865 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
6866 * @param ChannelState specifies the TIM Channel CCxE bit new state.
6867 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
6868 * @retval None
6869 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)6870 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
6871 {
6872 uint32_t tmp;
6873
6874 /* Check the parameters */
6875 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
6876 assert_param(IS_TIM_CHANNELS(Channel));
6877
6878 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
6879
6880 /* Reset the CCxE Bit */
6881 TIMx->CCER &= ~tmp;
6882
6883 /* Set or reset the CCxE Bit */
6884 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
6885 }
6886
6887 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6888 /**
6889 * @brief Reset interrupt callbacks to the legacy weak callbacks.
6890 * @param htim pointer to a TIM_HandleTypeDef structure that contains
6891 * the configuration information for TIM module.
6892 * @retval None
6893 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)6894 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
6895 {
6896 /* Reset the TIM callback to the legacy weak callbacks */
6897 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */
6898 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */
6899 htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */
6900 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */
6901 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */
6902 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */
6903 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */
6904 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */
6905 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
6906 htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */
6907 htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */
6908 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */
6909 htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */
6910 htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */
6911 }
6912 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6913
6914 /**
6915 * @}
6916 */
6917
6918 #endif /* HAL_TIM_MODULE_ENABLED */
6919 /**
6920 * @}
6921 */
6922
6923 /**
6924 * @}
6925 */
6926 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
6927