1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_utils.h
4 * @author MCD Application Team
5 * @brief Header file of UTILS LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL UTILS driver contains a set of generic APIs that can be
12 used by user:
13 (+) Device electronic signature
14 (+) Timing functions
15 (+) PLL configuration functions
16
17 @endverbatim
18 ******************************************************************************
19 * @attention
20 *
21 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
22 * All rights reserved.</center></h2>
23 *
24 * This software component is licensed by ST under BSD 3-Clause license,
25 * the "License"; You may not use this file except in compliance with the
26 * License. You may obtain a copy of the License at:
27 * opensource.org/licenses/BSD-3-Clause
28 *
29 ******************************************************************************
30 */
31
32 /* Define to prevent recursive inclusion -------------------------------------*/
33 #ifndef STM32WBxx_LL_UTILS_H
34 #define STM32WBxx_LL_UTILS_H
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /* Includes ------------------------------------------------------------------*/
41 #include "stm32wbxx.h"
42
43 /** @addtogroup STM32WBxx_LL_Driver
44 * @{
45 */
46
47 /** @defgroup UTILS_LL UTILS
48 * @{
49 */
50
51 /* Private types -------------------------------------------------------------*/
52 /* Private variables ---------------------------------------------------------*/
53
54 /* Private constants ---------------------------------------------------------*/
55 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
56 * @{
57 */
58
59 /* Max delay can be used in LL_mDelay */
60 #define LL_MAX_DELAY 0xFFFFFFFFU
61
62 /**
63 * @brief Unique device ID register base address
64 */
65 #define UID_BASE_ADDRESS UID_BASE
66
67 /**
68 * @brief Flash size data register base address
69 */
70 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
71
72 /**
73 * @brief Package data register base address
74 */
75 #define PACKAGE_BASE_ADDRESS PACKAGE_BASE
76
77 /**
78 * @}
79 */
80
81 /* Private macros ------------------------------------------------------------*/
82 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
83 * @{
84 */
85 /**
86 * @}
87 */
88 /* Exported types ------------------------------------------------------------*/
89 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
90 * @{
91 */
92 /**
93 * @brief UTILS PLL structure definition
94 */
95 typedef struct
96 {
97 uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
98 This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
99
100 This feature can be modified afterwards using unitary function
101 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
102
103 uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
104 This parameter must be a number between Min_Data = 6 and Max_Data = 127
105
106 This feature can be modified afterwards using unitary function
107 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
108
109 uint32_t PLLR; /*!< Division for the main system clock.
110 This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV
111
112 This feature can be modified afterwards using unitary function
113 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
114 } LL_UTILS_PLLInitTypeDef;
115
116 /**
117 * @brief UTILS System, AHB and APB buses clock configuration structure definition
118 */
119 typedef struct
120 {
121 uint32_t CPU1CLKDivider; /*!< The CPU1 clock (HCLK1) divider. This clock is derived from the system clock (SYSCLK).
122 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
123
124 This feature can be modified afterwards using unitary function
125 @ref LL_RCC_SetAHBPrescaler(). */
126
127 uint32_t CPU2CLKDivider; /*!< The CPU2 clock (HCLK2) divider. This clock is derived from the system clock (SYSCLK).
128 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
129
130 This feature can be modified afterwards using unitary function
131 @ref LL_C2_RCC_SetAHBPrescaler(). */
132
133 uint32_t AHB4CLKDivider; /*!< The AHBS clock (HCLK4) divider. This clock is derived from the system clock (SYSCLK).
134 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
135
136 This feature can be modified afterwards using unitary function
137 @ref LL_RCC_SetAHB4Prescaler(). */
138
139 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK1).
140 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
141
142 This feature can be modified afterwards using unitary function
143 @ref LL_RCC_SetAPB1Prescaler(). */
144
145 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK1).
146 This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
147
148 This feature can be modified afterwards using unitary function
149 @ref LL_RCC_SetAPB2Prescaler(). */
150
151 } LL_UTILS_ClkInitTypeDef;
152
153 /**
154 * @}
155 */
156
157 /* Exported constants --------------------------------------------------------*/
158 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
159 * @{
160 */
161
162 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
163 * @{
164 */
165 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
166 #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
167 /**
168 * @}
169 */
170
171 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
172 * @{
173 */
174 #define LL_UTILS_PACKAGETYPE_CSP100 0x00000011U /*!< CSP100 package type */
175 #define LL_UTILS_PACKAGETYPE_CSP100_C 0x00000012U /*!< CSP100 package type w/ capfree LDO */
176 #define LL_UTILS_PACKAGETYPE_QFN68 0x00000013U /*!< QFN68 package type */
177 #define LL_UTILS_PACKAGETYPE_QFN68_C 0x00000014U /*!< QFN68 package type w/ capfree LDO */
178 #define LL_UTILS_PACKAGETYPE_QFN48 0x0000000AU /*!< QFN48 package type */
179 #define LL_UTILS_PACKAGETYPE_QFN48_C 0x00000015U /*!< QFN48 package type w/ capfree LDO */
180 /**
181 * @}
182 */
183
184 /**
185 * @}
186 */
187
188 /* Exported macro ------------------------------------------------------------*/
189
190 /* Exported functions --------------------------------------------------------*/
191 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
192 * @{
193 */
194
195 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
196 * @{
197 */
198 /**
199 * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
200 * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
201 */
LL_GetUID_Word0(void)202 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
203 {
204 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
205 }
206
207 /**
208 * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
209 * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
210 */
LL_GetUID_Word1(void)211 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
212 {
213 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
214 }
215
216 /**
217 * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
218 * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
219 */
LL_GetUID_Word2(void)220 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
221 {
222 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
223 }
224
225 /**
226 * @brief Get Flash memory size
227 * @note This bitfield indicates the size of the device Flash memory expressed in
228 * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
229 * @retval FLASH_SIZE[15:0]: Flash memory size
230 */
LL_GetFlashSize(void)231 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
232 {
233 return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0x0000FFFFUL);
234 }
235
236 /**
237 * @brief Get Package type
238 * @retval Returned value can be one of the following values:
239 * @arg @ref LL_UTILS_PACKAGETYPE_CSP100
240 * @arg @ref LL_UTILS_PACKAGETYPE_CSP100_C
241 * @arg @ref LL_UTILS_PACKAGETYPE_QFN68
242 * @arg @ref LL_UTILS_PACKAGETYPE_QFN68_C
243 * @arg @ref LL_UTILS_PACKAGETYPE_QFN48
244 * @arg @ref LL_UTILS_PACKAGETYPE_QFN48_C
245 *
246 */
LL_GetPackageType(void)247 __STATIC_INLINE uint32_t LL_GetPackageType(void)
248 {
249 return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
250 }
251
252 /**
253 * @}
254 */
255
256 /** @defgroup UTILS_LL_EF_DELAY DELAY
257 * @{
258 */
259 /**
260 * @brief This function configures the Cortex-M SysTick source of the time base.
261 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq (HCLK1_Frequency field))
262 * @note When a RTOS is used, it is recommended to avoid changing the SysTick
263 * configuration by calling this function, for a delay use rather osDelay RTOS service.
264 * @param Ticks Number of ticks
265 * @retval None
266 */
LL_InitTick(uint32_t HCLKFrequency,uint32_t Ticks)267 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
268 {
269 /* Configure the SysTick to have interrupt in 1ms time base */
270 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
271 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
272 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
273 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
274 }
275
276 void LL_Init1msTick(uint32_t HCLKFrequency);
277
278 void LL_mDelay(uint32_t Delay);
279
280 /**
281 * @}
282 */
283
284 /** @defgroup UTILS_EF_SYSTEM SYSTEM
285 * @{
286 */
287
288 void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
289 ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
290 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
291 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
292 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
293 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEBypass,
294 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
295
296 /**
297 * @}
298 */
299
300 /**
301 * @}
302 */
303
304 /**
305 * @}
306 */
307
308 /**
309 * @}
310 */
311
312 #ifdef __cplusplus
313 }
314 #endif
315
316 #endif /* STM32WBxx_LL_UTILS_H */
317
318 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
319