1 /**************************************************************************//**
2 * @file core_sc000.h
3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
4 * @version V5.0.5
5 * @date 28. May 2018
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef __CORE_SC000_H_GENERIC
32 #define __CORE_SC000_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58 /**
59 \ingroup SC000
60 @{
61 */
62
63 #include "cmsis_version.h"
64
65 /* CMSIS SC000 definitions */
66 #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67 #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
69 __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70
71 #define __CORTEX_SC (000U) /*!< Cortex secure core */
72
73 /** __FPU_USED indicates whether an FPU is used or not.
74 This core does not support an FPU at all
75 */
76 #define __FPU_USED 0U
77
78 #if defined ( __CC_ARM )
79 #if defined __TARGET_FPU_VFP
80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81 #endif
82
83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84 #if defined __ARM_PCS_VFP
85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86 #endif
87
88 #elif defined ( __GNUC__ )
89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91 #endif
92
93 #elif defined ( __ICCARM__ )
94 #if defined __ARMVFP__
95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96 #endif
97
98 #elif defined ( __TI_ARM__ )
99 #if defined __TI_VFP_SUPPORT__
100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101 #endif
102
103 #elif defined ( __TASKING__ )
104 #if defined __FPU_VFP__
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #endif
107
108 #elif defined ( __CSMC__ )
109 #if ( __CSMC__ & 0x400U)
110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111 #endif
112
113 #endif
114
115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
116
117
118 #ifdef __cplusplus
119 }
120 #endif
121
122 #endif /* __CORE_SC000_H_GENERIC */
123
124 #ifndef __CMSIS_GENERIC
125
126 #ifndef __CORE_SC000_H_DEPENDANT
127 #define __CORE_SC000_H_DEPENDANT
128
129 #ifdef __cplusplus
130 extern "C" {
131 #endif
132
133 /* check device defines and use defaults */
134 #if defined __CHECK_DEVICE_DEFINES
135 #ifndef __SC000_REV
136 #define __SC000_REV 0x0000U
137 #warning "__SC000_REV not defined in device header file; using default!"
138 #endif
139
140 #ifndef __MPU_PRESENT
141 #define __MPU_PRESENT 0U
142 #warning "__MPU_PRESENT not defined in device header file; using default!"
143 #endif
144
145 #ifndef __NVIC_PRIO_BITS
146 #define __NVIC_PRIO_BITS 2U
147 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
148 #endif
149
150 #ifndef __Vendor_SysTickConfig
151 #define __Vendor_SysTickConfig 0U
152 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
153 #endif
154 #endif
155
156 /* IO definitions (access restrictions to peripheral registers) */
157 /**
158 \defgroup CMSIS_glob_defs CMSIS Global Defines
159
160 <strong>IO Type Qualifiers</strong> are used
161 \li to specify the access to peripheral variables.
162 \li for automatic generation of peripheral register debug information.
163 */
164 #ifdef __cplusplus
165 #define __I volatile /*!< Defines 'read only' permissions */
166 #else
167 #define __I volatile const /*!< Defines 'read only' permissions */
168 #endif
169 #define __O volatile /*!< Defines 'write only' permissions */
170 #define __IO volatile /*!< Defines 'read / write' permissions */
171
172 /* following defines should be used for structure members */
173 #define __IM volatile const /*! Defines 'read only' structure member permissions */
174 #define __OM volatile /*! Defines 'write only' structure member permissions */
175 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
176
177 /*@} end of group SC000 */
178
179
180
181 /*******************************************************************************
182 * Register Abstraction
183 Core Register contain:
184 - Core Register
185 - Core NVIC Register
186 - Core SCB Register
187 - Core SysTick Register
188 - Core MPU Register
189 ******************************************************************************/
190 /**
191 \defgroup CMSIS_core_register Defines and Type Definitions
192 \brief Type definitions and defines for Cortex-M processor based devices.
193 */
194
195 /**
196 \ingroup CMSIS_core_register
197 \defgroup CMSIS_CORE Status and Control Registers
198 \brief Core Register type definitions.
199 @{
200 */
201
202 /**
203 \brief Union type to access the Application Program Status Register (APSR).
204 */
205 typedef union
206 {
207 struct
208 {
209 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
210 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
211 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
212 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
213 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
214 } b; /*!< Structure used for bit access */
215 uint32_t w; /*!< Type used for word access */
216 } APSR_Type;
217
218 /* APSR Register Definitions */
219 #define APSR_N_Pos 31U /*!< APSR: N Position */
220 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
221
222 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
223 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
224
225 #define APSR_C_Pos 29U /*!< APSR: C Position */
226 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
227
228 #define APSR_V_Pos 28U /*!< APSR: V Position */
229 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
230
231
232 /**
233 \brief Union type to access the Interrupt Program Status Register (IPSR).
234 */
235 typedef union
236 {
237 struct
238 {
239 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
240 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
241 } b; /*!< Structure used for bit access */
242 uint32_t w; /*!< Type used for word access */
243 } IPSR_Type;
244
245 /* IPSR Register Definitions */
246 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
247 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
248
249
250 /**
251 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
252 */
253 typedef union
254 {
255 struct
256 {
257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
258 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
259 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
260 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
261 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
262 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
263 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
264 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
265 } b; /*!< Structure used for bit access */
266 uint32_t w; /*!< Type used for word access */
267 } xPSR_Type;
268
269 /* xPSR Register Definitions */
270 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
271 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
272
273 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
274 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
275
276 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
277 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
278
279 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
280 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
281
282 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
283 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
284
285 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
286 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
287
288
289 /**
290 \brief Union type to access the Control Registers (CONTROL).
291 */
292 typedef union
293 {
294 struct
295 {
296 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
297 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
298 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
299 } b; /*!< Structure used for bit access */
300 uint32_t w; /*!< Type used for word access */
301 } CONTROL_Type;
302
303 /* CONTROL Register Definitions */
304 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
305 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
306
307 /*@} end of group CMSIS_CORE */
308
309
310 /**
311 \ingroup CMSIS_core_register
312 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
313 \brief Type definitions for the NVIC Registers
314 @{
315 */
316
317 /**
318 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
319 */
320 typedef struct
321 {
322 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
323 uint32_t RESERVED0[31U];
324 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
325 uint32_t RSERVED1[31U];
326 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
327 uint32_t RESERVED2[31U];
328 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
329 uint32_t RESERVED3[31U];
330 uint32_t RESERVED4[64U];
331 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
332 } NVIC_Type;
333
334 /*@} end of group CMSIS_NVIC */
335
336
337 /**
338 \ingroup CMSIS_core_register
339 \defgroup CMSIS_SCB System Control Block (SCB)
340 \brief Type definitions for the System Control Block Registers
341 @{
342 */
343
344 /**
345 \brief Structure type to access the System Control Block (SCB).
346 */
347 typedef struct
348 {
349 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
350 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
351 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
352 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
353 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
354 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
355 uint32_t RESERVED0[1U];
356 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
357 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
358 uint32_t RESERVED1[154U];
359 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
360 } SCB_Type;
361
362 /* SCB CPUID Register Definitions */
363 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
364 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
365
366 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
367 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
368
369 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
370 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
371
372 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
373 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
374
375 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
376 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
377
378 /* SCB Interrupt Control State Register Definitions */
379 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
380 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
381
382 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
383 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
384
385 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
386 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
387
388 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
389 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
390
391 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
392 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
393
394 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
395 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
396
397 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
398 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
399
400 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
401 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
402
403 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
404 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
405
406 /* SCB Interrupt Control State Register Definitions */
407 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
408 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
409
410 /* SCB Application Interrupt and Reset Control Register Definitions */
411 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
412 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
413
414 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
415 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
416
417 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
418 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
419
420 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
421 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
422
423 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
424 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
425
426 /* SCB System Control Register Definitions */
427 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
428 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
429
430 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
431 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
432
433 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
434 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
435
436 /* SCB Configuration Control Register Definitions */
437 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
438 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
439
440 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
441 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
442
443 /* SCB System Handler Control and State Register Definitions */
444 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
445 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
446
447 /*@} end of group CMSIS_SCB */
448
449
450 /**
451 \ingroup CMSIS_core_register
452 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
453 \brief Type definitions for the System Control and ID Register not in the SCB
454 @{
455 */
456
457 /**
458 \brief Structure type to access the System Control and ID Register not in the SCB.
459 */
460 typedef struct
461 {
462 uint32_t RESERVED0[2U];
463 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
464 } SCnSCB_Type;
465
466 /* Auxiliary Control Register Definitions */
467 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
468 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
469
470 /*@} end of group CMSIS_SCnotSCB */
471
472
473 /**
474 \ingroup CMSIS_core_register
475 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
476 \brief Type definitions for the System Timer Registers.
477 @{
478 */
479
480 /**
481 \brief Structure type to access the System Timer (SysTick).
482 */
483 typedef struct
484 {
485 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
486 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
487 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
488 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
489 } SysTick_Type;
490
491 /* SysTick Control / Status Register Definitions */
492 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
493 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
494
495 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
496 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
497
498 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
499 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
500
501 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
502 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
503
504 /* SysTick Reload Register Definitions */
505 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
506 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
507
508 /* SysTick Current Register Definitions */
509 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
510 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
511
512 /* SysTick Calibration Register Definitions */
513 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
514 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
515
516 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
517 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
518
519 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
520 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
521
522 /*@} end of group CMSIS_SysTick */
523
524 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
525 /**
526 \ingroup CMSIS_core_register
527 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
528 \brief Type definitions for the Memory Protection Unit (MPU)
529 @{
530 */
531
532 /**
533 \brief Structure type to access the Memory Protection Unit (MPU).
534 */
535 typedef struct
536 {
537 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
538 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
539 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
540 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
541 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
542 } MPU_Type;
543
544 /* MPU Type Register Definitions */
545 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
546 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
547
548 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
549 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
550
551 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
552 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
553
554 /* MPU Control Register Definitions */
555 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
556 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
557
558 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
559 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
560
561 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
562 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
563
564 /* MPU Region Number Register Definitions */
565 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
566 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
567
568 /* MPU Region Base Address Register Definitions */
569 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
570 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
571
572 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
573 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
574
575 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
576 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
577
578 /* MPU Region Attribute and Size Register Definitions */
579 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
580 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
581
582 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
583 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
584
585 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
586 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
587
588 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
589 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
590
591 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
592 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
593
594 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
595 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
596
597 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
598 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
599
600 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
601 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
602
603 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
604 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
605
606 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
607 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
608
609 /*@} end of group CMSIS_MPU */
610 #endif
611
612
613 /**
614 \ingroup CMSIS_core_register
615 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
616 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
617 Therefore they are not covered by the SC000 header file.
618 @{
619 */
620 /*@} end of group CMSIS_CoreDebug */
621
622
623 /**
624 \ingroup CMSIS_core_register
625 \defgroup CMSIS_core_bitfield Core register bit field macros
626 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
627 @{
628 */
629
630 /**
631 \brief Mask and shift a bit field value for use in a register bit range.
632 \param[in] field Name of the register bit field.
633 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
634 \return Masked and shifted value.
635 */
636 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
637
638 /**
639 \brief Mask and shift a register value to extract a bit filed value.
640 \param[in] field Name of the register bit field.
641 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
642 \return Masked and shifted bit field value.
643 */
644 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
645
646 /*@} end of group CMSIS_core_bitfield */
647
648
649 /**
650 \ingroup CMSIS_core_register
651 \defgroup CMSIS_core_base Core Definitions
652 \brief Definitions for base addresses, unions, and structures.
653 @{
654 */
655
656 /* Memory mapping of Core Hardware */
657 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
658 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
659 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
660 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
661
662 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
663 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
664 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
665 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
666
667 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
668 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
669 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
670 #endif
671
672 /*@} */
673
674
675
676 /*******************************************************************************
677 * Hardware Abstraction Layer
678 Core Function Interface contains:
679 - Core NVIC Functions
680 - Core SysTick Functions
681 - Core Register Access Functions
682 ******************************************************************************/
683 /**
684 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
685 */
686
687
688
689 /* ########################## NVIC functions #################################### */
690 /**
691 \ingroup CMSIS_Core_FunctionInterface
692 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
693 \brief Functions that manage interrupts and exceptions via the NVIC.
694 @{
695 */
696
697 #ifdef CMSIS_NVIC_VIRTUAL
698 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
699 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
700 #endif
701 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
702 #else
703 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
704 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
705 #define NVIC_EnableIRQ __NVIC_EnableIRQ
706 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
707 #define NVIC_DisableIRQ __NVIC_DisableIRQ
708 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
709 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
710 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
711 /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
712 #define NVIC_SetPriority __NVIC_SetPriority
713 #define NVIC_GetPriority __NVIC_GetPriority
714 #define NVIC_SystemReset __NVIC_SystemReset
715 #endif /* CMSIS_NVIC_VIRTUAL */
716
717 #ifdef CMSIS_VECTAB_VIRTUAL
718 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
719 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
720 #endif
721 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
722 #else
723 #define NVIC_SetVector __NVIC_SetVector
724 #define NVIC_GetVector __NVIC_GetVector
725 #endif /* (CMSIS_VECTAB_VIRTUAL) */
726
727 #define NVIC_USER_IRQ_OFFSET 16
728
729
730 /* The following EXC_RETURN values are saved the LR on exception entry */
731 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
732 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
733 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
734
735
736 /* Interrupt Priorities are WORD accessible only under Armv6-M */
737 /* The following MACROS handle generation of the register offset and byte masks */
738 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
739 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
740 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
741
742
743 /**
744 \brief Enable Interrupt
745 \details Enables a device specific interrupt in the NVIC interrupt controller.
746 \param [in] IRQn Device specific interrupt number.
747 \note IRQn must not be negative.
748 */
__NVIC_EnableIRQ(IRQn_Type IRQn)749 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
750 {
751 if ((int32_t)(IRQn) >= 0)
752 {
753 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
754 }
755 }
756
757
758 /**
759 \brief Get Interrupt Enable status
760 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
761 \param [in] IRQn Device specific interrupt number.
762 \return 0 Interrupt is not enabled.
763 \return 1 Interrupt is enabled.
764 \note IRQn must not be negative.
765 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)766 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
767 {
768 if ((int32_t)(IRQn) >= 0)
769 {
770 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
771 }
772 else
773 {
774 return(0U);
775 }
776 }
777
778
779 /**
780 \brief Disable Interrupt
781 \details Disables a device specific interrupt in the NVIC interrupt controller.
782 \param [in] IRQn Device specific interrupt number.
783 \note IRQn must not be negative.
784 */
__NVIC_DisableIRQ(IRQn_Type IRQn)785 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
786 {
787 if ((int32_t)(IRQn) >= 0)
788 {
789 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
790 __DSB();
791 __ISB();
792 }
793 }
794
795
796 /**
797 \brief Get Pending Interrupt
798 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
799 \param [in] IRQn Device specific interrupt number.
800 \return 0 Interrupt status is not pending.
801 \return 1 Interrupt status is pending.
802 \note IRQn must not be negative.
803 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)804 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
805 {
806 if ((int32_t)(IRQn) >= 0)
807 {
808 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
809 }
810 else
811 {
812 return(0U);
813 }
814 }
815
816
817 /**
818 \brief Set Pending Interrupt
819 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
820 \param [in] IRQn Device specific interrupt number.
821 \note IRQn must not be negative.
822 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)823 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
824 {
825 if ((int32_t)(IRQn) >= 0)
826 {
827 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
828 }
829 }
830
831
832 /**
833 \brief Clear Pending Interrupt
834 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
835 \param [in] IRQn Device specific interrupt number.
836 \note IRQn must not be negative.
837 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)838 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
839 {
840 if ((int32_t)(IRQn) >= 0)
841 {
842 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
843 }
844 }
845
846
847 /**
848 \brief Set Interrupt Priority
849 \details Sets the priority of a device specific interrupt or a processor exception.
850 The interrupt number can be positive to specify a device specific interrupt,
851 or negative to specify a processor exception.
852 \param [in] IRQn Interrupt number.
853 \param [in] priority Priority to set.
854 \note The priority cannot be set for every processor exception.
855 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)856 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
857 {
858 if ((int32_t)(IRQn) >= 0)
859 {
860 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
861 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
862 }
863 else
864 {
865 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
866 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
867 }
868 }
869
870
871 /**
872 \brief Get Interrupt Priority
873 \details Reads the priority of a device specific interrupt or a processor exception.
874 The interrupt number can be positive to specify a device specific interrupt,
875 or negative to specify a processor exception.
876 \param [in] IRQn Interrupt number.
877 \return Interrupt Priority.
878 Value is aligned automatically to the implemented priority bits of the microcontroller.
879 */
__NVIC_GetPriority(IRQn_Type IRQn)880 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
881 {
882
883 if ((int32_t)(IRQn) >= 0)
884 {
885 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
886 }
887 else
888 {
889 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
890 }
891 }
892
893
894 /**
895 \brief Set Interrupt Vector
896 \details Sets an interrupt vector in SRAM based interrupt vector table.
897 The interrupt number can be positive to specify a device specific interrupt,
898 or negative to specify a processor exception.
899 VTOR must been relocated to SRAM before.
900 \param [in] IRQn Interrupt number
901 \param [in] vector Address of interrupt handler function
902 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)903 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
904 {
905 uint32_t *vectors = (uint32_t *)SCB->VTOR;
906 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
907 }
908
909
910 /**
911 \brief Get Interrupt Vector
912 \details Reads an interrupt vector from interrupt vector table.
913 The interrupt number can be positive to specify a device specific interrupt,
914 or negative to specify a processor exception.
915 \param [in] IRQn Interrupt number.
916 \return Address of interrupt handler function
917 */
__NVIC_GetVector(IRQn_Type IRQn)918 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
919 {
920 uint32_t *vectors = (uint32_t *)SCB->VTOR;
921 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
922 }
923
924
925 /**
926 \brief System Reset
927 \details Initiates a system reset request to reset the MCU.
928 */
__NVIC_SystemReset(void)929 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
930 {
931 __DSB(); /* Ensure all outstanding memory accesses included
932 buffered write are completed before reset */
933 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
934 SCB_AIRCR_SYSRESETREQ_Msk);
935 __DSB(); /* Ensure completion of memory access */
936
937 for(;;) /* wait until reset */
938 {
939 __NOP();
940 }
941 }
942
943 /*@} end of CMSIS_Core_NVICFunctions */
944
945
946 /* ########################## FPU functions #################################### */
947 /**
948 \ingroup CMSIS_Core_FunctionInterface
949 \defgroup CMSIS_Core_FpuFunctions FPU Functions
950 \brief Function that provides FPU type.
951 @{
952 */
953
954 /**
955 \brief get FPU type
956 \details returns the FPU type
957 \returns
958 - \b 0: No FPU
959 - \b 1: Single precision FPU
960 - \b 2: Double + Single precision FPU
961 */
SCB_GetFPUType(void)962 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
963 {
964 return 0U; /* No FPU */
965 }
966
967
968 /*@} end of CMSIS_Core_FpuFunctions */
969
970
971
972 /* ################################## SysTick function ############################################ */
973 /**
974 \ingroup CMSIS_Core_FunctionInterface
975 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
976 \brief Functions that configure the System.
977 @{
978 */
979
980 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
981
982 /**
983 \brief System Tick Configuration
984 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
985 Counter is in free running mode to generate periodic interrupts.
986 \param [in] ticks Number of ticks between two interrupts.
987 \return 0 Function succeeded.
988 \return 1 Function failed.
989 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
990 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
991 must contain a vendor-specific implementation of this function.
992 */
SysTick_Config(uint32_t ticks)993 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
994 {
995 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
996 {
997 return (1UL); /* Reload value impossible */
998 }
999
1000 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1001 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1002 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1003 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1004 SysTick_CTRL_TICKINT_Msk |
1005 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1006 return (0UL); /* Function successful */
1007 }
1008
1009 #endif
1010
1011 /*@} end of CMSIS_Core_SysTickFunctions */
1012
1013
1014
1015
1016 #ifdef __cplusplus
1017 }
1018 #endif
1019
1020 #endif /* __CORE_SC000_H_DEPENDANT */
1021
1022 #endif /* __CMSIS_GENERIC */
1023