1 /** 2 ****************************************************************************** 3 * @file stm32wb50xx.h 4 * @author MCD Application Team 5 * @brief CMSIS Cortex Device Peripheral Access Layer Header File. 6 * This file contains all the peripheral register's definitions, bits 7 * definitions and memory mapping for stm32wb50xx devices. 8 * 9 * This file contains: 10 * - Data structures and the address mapping for all peripherals 11 * - Peripheral's registers declarations and bits definition 12 * - Macros to access peripheral's registers hardware 13 * 14 ****************************************************************************** 15 * @attention 16 * 17 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 18 * All rights reserved.</center></h2> 19 * 20 * This software component is licensed by ST under BSD 3-Clause license, 21 * the "License"; You may not use this file except in compliance with the 22 * License. You may obtain a copy of the License at: 23 * opensource.org/licenses/BSD-3-Clause 24 * 25 ****************************************************************************** 26 */ 27 28 /** @addtogroup CMSIS_Device 29 * @{ 30 */ 31 32 /** @addtogroup stm32wb50xx 33 * @{ 34 */ 35 36 #ifndef __STM32WB50xx_H 37 #define __STM32WB50xx_H 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** @addtogroup Configuration_section_for_CMSIS 44 * @{ 45 */ 46 /** 47 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 48 */ 49 #define __CM4_REV 1 /*!< Core Revision r0p1 */ 50 #define __MPU_PRESENT 1 /*!< M4 provides an MPU */ 51 #define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ 52 #define __NVIC_PRIO_BITS 4 /*!< STM32WBxx uses 4 Bits for the Priority Levels */ 53 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 54 #define __FPU_PRESENT 1 /*!< FPU present */ 55 /** 56 * @} 57 */ 58 59 /** @addtogroup Peripheral_interrupt_number_definition 60 * @{ 61 */ 62 63 /** 64 * @brief stm32wb50xx Interrupt Number Definition, according to the selected device 65 * in @ref Library_configuration_section 66 */ 67 /*!< Interrupt Number Definition for M4 */ 68 typedef enum 69 { 70 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ 71 NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt */ 72 HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt */ 73 MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt */ 74 BusFault_IRQn = -11, /*!< Cortex-M4 Bus Fault Interrupt */ 75 UsageFault_IRQn = -10, /*!< Cortex-M4 Usage Fault Interrupt */ 76 SVCall_IRQn = -5, /*!< Cortex-M4 SV Call Interrupt */ 77 DebugMonitor_IRQn = -4, /*!< Cortex-M4 Debug Monitor Interrupt */ 78 PendSV_IRQn = -2, /*!< Cortex-M4 Pend SV Interrupt */ 79 SysTick_IRQn = -1, /*!< Cortex-M4 System Tick Interrupt */ 80 81 /************* STM32WBxx specific Interrupt Numbers on M4 core ************************************************/ 82 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 83 PVD_PVM_IRQn = 1, /*!< PVD and PVM detector */ 84 TAMP_STAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts */ 85 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Interrupt */ 86 FLASH_IRQn = 4, /*!< FLASH (CFI) global Interrupt */ 87 RCC_IRQn = 5, /*!< RCC Interrupt */ 88 EXTI0_IRQn = 6, /*!< EXTI Line 0 Interrupt */ 89 EXTI1_IRQn = 7, /*!< EXTI Line 1 Interrupt */ 90 EXTI2_IRQn = 8, /*!< EXTI Line 2 Interrupt */ 91 EXTI3_IRQn = 9, /*!< EXTI Line 3 Interrupt */ 92 EXTI4_IRQn = 10, /*!< EXTI Line 4 Interrupt */ 93 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ 94 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ 95 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ 96 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ 97 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ 98 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ 99 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ 100 ADC1_IRQn = 18, /*!< ADC1 Interrupt */ 101 C2SEV_PWR_C2H_IRQn = 21, /*!< CPU2 SEV Interrupt */ 102 EXTI9_5_IRQn = 23, /*!< EXTI Lines [9:5] Interrupt */ 103 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ 104 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 global Interrupts */ 105 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Communication and TIM17 global Interrupts */ 106 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ 107 TIM2_IRQn = 28, /*!< TIM2 Global Interrupt */ 108 PKA_IRQn = 29, /*!< PKA Interrupt */ 109 I2C1_EV_IRQn = 30, /*!< I2C1 Event Interrupt */ 110 I2C1_ER_IRQn = 31, /*!< I2C1 Error Interrupt */ 111 SPI1_IRQn = 34, /*!< SPI1 Interrupt */ 112 USART1_IRQn = 36, /*!< USART1 Interrupt */ 113 TSC_IRQn = 39, /*!< TSC Interrupt */ 114 EXTI15_10_IRQn = 40, /*!< EXTI Lines1[15:10 ]Interrupts */ 115 RTC_Alarm_IRQn = 41, /*!< RTC Alarms (A and B) Interrupt */ 116 PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQn = 43, /*!< PWR switching on the fly interrupt 117 PWR end of BLE activity interrupt 118 PWR end of 802.15.4 (Zigbee) activity interrupt 119 PWR end of critical radio phase interrupt */ 120 IPCC_C1_RX_IRQn = 44, /*!< IPCC RX Occupied Interrupt */ 121 IPCC_C1_TX_IRQn = 45, /*!< IPCC TX Free Interrupt */ 122 HSEM_IRQn = 46, /*!< HSEM Interrupt */ 123 LPTIM1_IRQn = 47, /*!< LPTIM1 Interrupt */ 124 LPTIM2_IRQn = 48, /*!< LPTIM2 Interrupt */ 125 AES2_IRQn = 52, /*!< AES2 Interrupt */ 126 RNG_IRQn = 53, /*!< RNG Interrupt */ 127 FPU_IRQn = 54, /*!< FPU Interrupt */ 128 DMAMUX1_OVR_IRQn = 62 /*!< DMAMUX1 overrun Interrupt */ 129 } IRQn_Type; 130 /** 131 * @} 132 */ 133 134 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ 135 #include "system_stm32wbxx.h" 136 #include <stdint.h> 137 138 /** @addtogroup Peripheral_registers_structures 139 * @{ 140 */ 141 142 /** 143 * @brief Analog to Digital Converter 144 */ 145 typedef struct 146 { 147 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ 148 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ 149 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ 150 __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ 151 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ 152 __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ 153 __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ 154 uint32_t RESERVED1; /*!< Reserved, 0x1C */ 155 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ 156 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ 157 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ 158 uint32_t RESERVED2; /*!< Reserved, 0x2C */ 159 __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ 160 __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ 161 __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ 162 __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ 163 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ 164 uint32_t RESERVED3; /*!< Reserved, 0x44 */ 165 uint32_t RESERVED4; /*!< Reserved, 0x48 */ 166 __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ 167 uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ 168 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ 169 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ 170 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ 171 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ 172 uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ 173 __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ 174 __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ 175 __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ 176 __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ 177 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ 178 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */ 179 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ 180 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ 181 uint32_t RESERVED9; /*!< Reserved, 0x0AC */ 182 __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ 183 __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ 184 185 } ADC_TypeDef; 186 187 typedef struct 188 { 189 uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */ 190 uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */ 191 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ 192 uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */ 193 } ADC_Common_TypeDef; 194 195 /** 196 * @brief CRC calculation unit 197 */ 198 typedef struct 199 { 200 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 201 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 202 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 203 uint32_t RESERVED2; /*!< Reserved, 0x0C */ 204 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ 205 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ 206 } CRC_TypeDef; 207 208 /** 209 * @brief Debug MCU 210 */ 211 typedef struct 212 { 213 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 214 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 215 uint32_t RESERVED1[13]; /*!< Reserved, 0x08-0x38 */ 216 __IO uint32_t APB1FZR1; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x3C */ 217 __IO uint32_t C2APB1FZR1; /*!< Debug MCU CPU2 APB1 freeze register, Address offset: 0x40 */ 218 __IO uint32_t APB1FZR2; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x44 */ 219 __IO uint32_t C2APB1FZR2; /*!< Debug MCU CPU2 APB1 freeze register, Address offset: 0x48 */ 220 __IO uint32_t APB2FZR; /*!< Debug MCU CPU1 APB2 freeze register, Address offset: 0x4C */ 221 __IO uint32_t C2APB2FZR; /*!< Debug MCU CPU2 APB2 freeze register, Address offset: 0x50 */ 222 } DBGMCU_TypeDef; 223 224 /** 225 * @brief DMA Controller 226 */ 227 typedef struct 228 { 229 __IO uint32_t CCR; /*!< DMA channel x configuration register 0x00 */ 230 __IO uint32_t CNDTR; /*!< DMA channel x number of data register 0x04 */ 231 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register 0x08 */ 232 __IO uint32_t CMAR; /*!< DMA channel x memory address register 0x0C */ 233 uint32_t RESERVED; /*!< Reserved, 0x10 */ 234 } DMA_Channel_TypeDef; 235 236 typedef struct 237 { 238 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ 239 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ 240 } DMA_TypeDef; 241 242 /** 243 * @brief DMA Multiplexer 244 */ 245 typedef struct 246 { 247 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ 248 }DMAMUX_Channel_TypeDef; 249 250 typedef struct 251 { 252 __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ 253 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ 254 }DMAMUX_ChannelStatus_TypeDef; 255 256 typedef struct 257 { 258 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ 259 }DMAMUX_RequestGen_TypeDef; 260 261 typedef struct 262 { 263 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ 264 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ 265 }DMAMUX_RequestGenStatus_TypeDef; 266 267 /** 268 * @brief FLASH Registers 269 */ 270 typedef struct 271 { 272 __IO uint32_t ACR; /*!< FLASH Access control register, Address offset: 0x00 */ 273 __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x04 */ 274 __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ 275 __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ 276 __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ 277 __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ 278 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ 279 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ 280 __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ 281 __IO uint32_t PCROP1ASR; /*!< FLASH Bank 1 PCROP area A Start address register, Address offset: 0x24 */ 282 __IO uint32_t PCROP1AER; /*!< FLASH Bank 1 PCROP area A End address register, Address offset: 0x28 */ 283 __IO uint32_t WRP1AR; /*!< FLASH Bank 1 WRP area A address register, Address offset: 0x2C */ 284 __IO uint32_t WRP1BR; /*!< FLASH Bank 1 WRP area B address register, Address offset: 0x30 */ 285 __IO uint32_t PCROP1BSR; /*!< FLASH Bank 1 PCROP area B Start address register, Address offset: 0x34 */ 286 __IO uint32_t PCROP1BER; /*!< FLASH Bank 1 PCROP area B End address register, Address offset: 0x38 */ 287 __IO uint32_t IPCCBR; /*!< FLASH IPCC data buffer address, Address offset: 0x3C */ 288 uint32_t RESERVED2[7]; /*!< Reserved, Address offset: 0x40-0x58 */ 289 __IO uint32_t C2ACR; /*!< FLASH Core MO+ Access Control Register , Address offset: 0x5C */ 290 __IO uint32_t C2SR; /*!< FLASH Core MO+ Status Register, Address offset: 0x60 */ 291 __IO uint32_t C2CR; /*!< FLASH Core MO+ Control register, Address offset: 0x64 */ 292 uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x68-0x7C */ 293 __IO uint32_t SFR; /*!< FLASH secure start address, Address offset: 0x80 */ 294 __IO uint32_t SRRVR; /*!< FlASH secure SRAM2 start addr and CPU2 reset vector Address offset: 0x84 */ 295 } FLASH_TypeDef; 296 297 /** 298 * @brief General Purpose I/O 299 */ 300 typedef struct 301 { 302 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 303 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 304 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 305 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 306 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 307 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 308 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ 309 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 310 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ 311 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ 312 } GPIO_TypeDef; 313 314 /** 315 * @brief Inter-integrated Circuit Interface 316 */ 317 typedef struct 318 { 319 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 320 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 321 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ 322 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ 323 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ 324 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ 325 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ 326 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ 327 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ 328 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ 329 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ 330 } I2C_TypeDef; 331 332 /** 333 * @brief Independent WATCHDOG 334 */ 335 typedef struct 336 { 337 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ 338 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ 339 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ 340 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ 341 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ 342 } IWDG_TypeDef; 343 344 /** 345 * @brief LPTIMER 346 */ 347 typedef struct 348 { 349 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ 350 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ 351 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ 352 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ 353 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ 354 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ 355 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ 356 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ 357 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ 358 } LPTIM_TypeDef; 359 360 /** 361 * @brief Power Control 362 */ 363 typedef struct 364 { 365 __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ 366 __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */ 367 __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ 368 __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ 369 __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ 370 __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ 371 __IO uint32_t SCR; /*!< PWR Power Status Reset Register, Address offset: 0x18 */ 372 __IO uint32_t CR5; /*!< PWR Power Control Register 5, Address offset: 0x1C */ 373 __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ 374 __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ 375 __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ 376 __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ 377 __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ 378 __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ 379 uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x38-0x3C */ 380 __IO uint32_t PUCRE; /*!< PWR Pull-Up Control Register of port E, Address offset: 0x40 */ 381 __IO uint32_t PDCRE; /*!< PWR Pull-Down Control Register of port E, Address offset: 0x44 */ 382 uint32_t RESERVED0[4]; /*!< Reserved, Address offset: 0x48-0x54 */ 383 __IO uint32_t PUCRH; /*!< PWR Pull-Up Control Register of port H, Address offset: 0x58 */ 384 __IO uint32_t PDCRH; /*!< PWR Pull-Down Control Register of port H, Address offset: 0x5C */ 385 uint32_t RESERVED1[8]; /*!< Reserved, Address offset: 0x60-0x7C */ 386 __IO uint32_t C2CR1; /*!< PWR Power Control Register 1 for CPU2, Address offset: 0x80 */ 387 __IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset: 0x84 */ 388 __IO uint32_t EXTSCR; /*!< PWR Power Status Reset Register for CPU2, Address offset: 0x88 */ 389 } PWR_TypeDef; 390 391 /** 392 * @brief Reset and Clock Control 393 */ 394 typedef struct 395 { 396 __IO uint32_t CR; /*!< RCC clock Control Register, Address offset: 0x00 */ 397 __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ 398 __IO uint32_t CFGR; /*!< RCC Clocks Configuration Register, Address offset: 0x08 */ 399 __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ 400 uint32_t RESERVED11; /*!< Reserved, Address offset: 0x10 */ 401 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ 402 __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ 403 __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ 404 __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ 405 uint32_t RESERVED12; /*!< Reserved, Address offset: 0x24 */ 406 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ 407 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ 408 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 & AHB4 peripheral reset register, Address offset: 0x30 */ 409 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ 410 __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ 411 __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ 412 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ 413 __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x44 */ 414 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ 415 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ 416 __IO uint32_t AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable register, Address offset: 0x50 */ 417 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x54 */ 418 __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ 419 __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ 420 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ 421 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x64 */ 422 __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ 423 __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ 424 __IO uint32_t AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ 425 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x74 */ 426 __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ 427 __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ 428 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ 429 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x84 */ 430 __IO uint32_t CCIPR; /*!< RCC Peripherals Clock Configuration Independent Register, Address offset: 0x88 */ 431 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x8C */ 432 __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x90 */ 433 __IO uint32_t CSR; /*!< RCC Control and Status Register, Address offset: 0x94 */ 434 __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x98 */ 435 __IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */ 436 uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */ 437 __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */ 438 __IO uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */ 439 __IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */ 440 __IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */ 441 __IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */ 442 uint32_t RESERVED9; /*!< Reserved, Address offset: 0x154 */ 443 __IO uint32_t C2APB1ENR1; /*!< RCC APB1 peripheral CPU2 clocks enable register 1, Address offset: 0x158 */ 444 __IO uint32_t C2APB1ENR2; /*!< RCC APB1 peripheral CPU2 clocks enable register 2, Address offset: 0x15C */ 445 __IO uint32_t C2APB2ENR; /*!< RCC APB2 peripheral CPU2 clocks enable register 1, Address offset: 0x160 */ 446 __IO uint32_t C2APB3ENR; /*!< RCC APB3 peripheral CPU2 clocks enable register 1, Address offset: 0x164 */ 447 __IO uint32_t C2AHB1SMENR; /*!< RCC AHB1 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x168 */ 448 __IO uint32_t C2AHB2SMENR; /*!< RCC AHB2 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x16C */ 449 __IO uint32_t C2AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x170 */ 450 uint32_t RESERVED10; /*!< Reserved, */ 451 __IO uint32_t C2APB1SMENR1;/*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 1, Address offset: 0x178 */ 452 __IO uint32_t C2APB1SMENR2;/*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 2, Address offset: 0x17C */ 453 __IO uint32_t C2APB2SMENR; /*!< RCC APB2 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x180 */ 454 __IO uint32_t C2APB3SMENR; /*!< RCC APB3 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x184 */ 455 } RCC_TypeDef; 456 457 458 459 /** 460 * @brief Real-Time Clock 461 */ 462 typedef struct 463 { 464 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 465 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 466 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ 467 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ 468 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 469 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ 470 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ 471 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ 472 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ 473 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 474 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ 475 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ 476 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 477 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 478 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ 479 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ 480 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ 481 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ 482 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ 483 __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */ 484 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ 485 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ 486 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ 487 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ 488 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ 489 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ 490 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ 491 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ 492 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ 493 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ 494 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ 495 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ 496 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ 497 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ 498 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ 499 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ 500 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ 501 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ 502 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ 503 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ 504 } RTC_TypeDef; 505 506 507 508 509 /** 510 * @brief Serial Peripheral Interface 511 */ 512 typedef struct 513 { 514 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ 515 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ 516 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ 517 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ 518 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ 519 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ 520 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ 521 } SPI_TypeDef; 522 523 /** 524 * @brief System configuration controller 525 */ 526 typedef struct 527 { 528 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register Address offset: 0x00 */ 529 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ 530 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ 531 __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ 532 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ 533 __IO uint32_t SWPR1; /*!< SYSCFG SRAM2 write protection register part 1, Address offset: 0x20 */ 534 __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ 535 __IO uint32_t SWPR2; /*!< SYSCFG write protection register part 2, Address offset: 0x28 */ 536 uint32_t RESERVED1[53]; /*!< Reserved, Address offset: 0x2C-0xFC */ 537 __IO uint32_t IMR1; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 1, Address offset: 0x100 */ 538 __IO uint32_t IMR2; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 2, Address offset: 0x104 */ 539 __IO uint32_t C2IMR1; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 1, Address offset: 0x108 */ 540 __IO uint32_t C2IMR2; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 2, Address offset: 0x10C */ 541 __IO uint32_t SIPCR; /*!< SYSCFG secure IP control register, Address offset: 0x110 */ 542 543 } SYSCFG_TypeDef; 544 545 /** 546 * @brief VREFBUF 547 */ 548 typedef struct 549 { 550 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ 551 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ 552 } VREFBUF_TypeDef; 553 554 /** 555 * @brief TIM 556 */ 557 typedef struct 558 { 559 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 560 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 561 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ 562 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 563 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 564 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 565 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 566 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 567 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 568 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 569 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ 570 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 571 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 572 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 573 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 574 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 575 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 576 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ 577 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 578 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ 579 __IO uint32_t OR; /*!< TIM option register Address offset: 0x50 */ 580 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ 581 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ 582 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ 583 __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */ 584 __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */ 585 } TIM_TypeDef; 586 587 /** 588 * @brief Universal Synchronous Asynchronous Receiver Transmitter 589 */ 590 typedef struct 591 { 592 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ 593 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ 594 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ 595 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ 596 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ 597 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ 598 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ 599 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ 600 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ 601 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ 602 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ 603 __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ 604 } USART_TypeDef; 605 606 607 /** 608 * @brief Window WATCHDOG 609 */ 610 typedef struct 611 { 612 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 613 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 614 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 615 } WWDG_TypeDef; 616 617 618 /** 619 * @brief AES hardware accelerator 620 */ 621 typedef struct 622 { 623 __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ 624 __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ 625 __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ 626 __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ 627 __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ 628 __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ 629 __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ 630 __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ 631 __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ 632 __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ 633 __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ 634 __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ 635 __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ 636 __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ 637 __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ 638 __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ 639 __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ 640 __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ 641 __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ 642 __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ 643 __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ 644 __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ 645 __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ 646 __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */ 647 } AES_TypeDef; 648 649 /** 650 * @brief RNG 651 */ 652 typedef struct 653 { 654 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ 655 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ 656 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ 657 } RNG_TypeDef; 658 659 /** 660 * @brief Inter-Processor Communication 661 */ 662 typedef struct 663 { 664 __IO uint32_t C1CR; /*!< Inter-Processor Communication: C1 control register, Address offset: 0x000 */ 665 __IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, Address offset: 0x004 */ 666 __IO uint32_t C1SCR; /*!< Inter-Processor Communication: C1 status set clear register, Address offset: 0x008 */ 667 __IO uint32_t C1TOC2SR; /*!< Inter-Processor Communication: C1 to processor M4 status register, Address offset: 0x00C */ 668 __IO uint32_t C2CR; /*!< Inter-Processor Communication: C2 control register, Address offset: 0x010 */ 669 __IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, Address offset: 0x014 */ 670 __IO uint32_t C2SCR; /*!< Inter-Processor Communication: C2 status set clear register, Address offset: 0x018 */ 671 __IO uint32_t C2TOC1SR; /*!< Inter-Processor Communication: C2 to processor M4 status register, Address offset: 0x01C */ 672 } IPCC_TypeDef; 673 674 typedef struct 675 { 676 __IO uint32_t CR; /*!< Control register, Address offset: 0x000 */ 677 __IO uint32_t MR; /*!< Mask register, Address offset: 0x004 */ 678 __IO uint32_t SCR; /*!< Status set clear register, Address offset: 0x008 */ 679 __IO uint32_t SR; /*!< Status register, Address offset: 0x00C */ 680 } IPCC_CommonTypeDef; 681 682 /** 683 * @brief Async Interrupts and Events Controller 684 */ 685 typedef struct 686 { 687 __IO uint32_t RTSR1; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x00 */ 688 __IO uint32_t FTSR1; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x04 */ 689 __IO uint32_t SWIER1; /*!< EXTI software interrupt event register [31:0], Address offset: 0x08 */ 690 __IO uint32_t PR1; /*!< EXTI pending register [31:0], Address offset: 0x0C */ 691 __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x10 - 0x1C */ 692 __IO uint32_t RTSR2; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x20 */ 693 __IO uint32_t FTSR2; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x24 */ 694 __IO uint32_t SWIER2; /*!< EXTI software interrupt event register [31:0], Address offset: 0x28 */ 695 __IO uint32_t PR2; /*!< EXTI pending register [31:0], Address offset: 0x2C */ 696 __IO uint32_t RESERVED2[4]; /*!< Reserved, Address offset: 0x30 - 0x3C */ 697 __IO uint32_t RESERVED3[8]; /*!< Reserved, Address offset: 0x40 - 0x5C */ 698 __IO uint32_t RESERVED4[8]; /*!< Reserved, Address offset: 0x60 - 0x7C */ 699 __IO uint32_t IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ 700 __IO uint32_t EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ 701 __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ 702 __IO uint32_t IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ 703 __IO uint32_t EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ 704 __IO uint32_t RESERVED8[10]; /*!< Reserved, Address offset: 0x98 - 0xBC */ 705 __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ 706 __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ 707 __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ 708 __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */ 709 __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */ 710 }EXTI_TypeDef; 711 712 /** 713 * @brief Public Key Accelerator (PKA) 714 */ 715 typedef struct 716 { 717 __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ 718 __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ 719 __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ 720 uint32_t Reserved1[253]; /*!< Reserved Address offset: 0x000C-0x03FC*/ 721 __IO uint32_t RAM[894]; /*!< PKA RAM, Address offset: 0x0400-0x11F4 */ 722 } PKA_TypeDef; 723 724 /** 725 * @brief HW Semaphore HSEM 726 */ 727 typedef struct 728 { 729 __IO uint32_t R[32]; /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-7Ch */ 730 __IO uint32_t RLR[32]; /*!< HSEM 1-step read lock registers, Address offset: 80h-FCh */ 731 __IO uint32_t C1IER; /*!< HSEM CPU1 interrupt enable register , Address offset: 100h */ 732 __IO uint32_t C1ICR; /*!< HSEM CPU1 interrupt clear register , Address offset: 104h */ 733 __IO uint32_t C1ISR; /*!< HSEM CPU1 interrupt status register , Address offset: 108h */ 734 __IO uint32_t C1MISR; /*!< HSEM CPU1 masked interrupt status register , Address offset: 10Ch */ 735 __IO uint32_t C2IER; /*!< HSEM CPU2 interrupt enable register , Address offset: 110h */ 736 __IO uint32_t C2ICR; /*!< HSEM CPU2 interrupt clear register , Address offset: 114h */ 737 __IO uint32_t C2ISR; /*!< HSEM CPU2 interrupt status register , Address offset: 118h */ 738 __IO uint32_t C2MISR; /*!< HSEM CPU2 masked interrupt status register , Address offset: 11Ch */ 739 uint32_t Reserved[8]; /*!< Reserved Address offset: 120h-13Ch*/ 740 __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ 741 __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ 742 } HSEM_TypeDef; 743 744 typedef struct 745 { 746 __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ 747 __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ 748 __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ 749 __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ 750 } HSEM_Common_TypeDef; 751 752 /** 753 * @} 754 */ 755 756 /** @addtogroup Peripheral_memory_map 757 * @{ 758 */ 759 760 /*!< Boundary memory map */ 761 #define FLASH_BASE (0x08000000UL)/*!< FLASH(up to 1 MB) base address */ 762 #define SRAM_BASE (0x20000000UL)/*!< SRAM(up to 256 KB) base address */ 763 #define PERIPH_BASE (0x40000000UL)/*!< Peripheral base address */ 764 765 /*!< Memory, OTP and Option bytes */ 766 767 /* Base addresses */ 768 #define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 � 0x1FFF6FFF) */ 769 #define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 � 0x1FFF73FF) */ 770 #define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 � 0x1FFF8FFF) */ 771 #define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 � 0x1FFF7FFF) */ 772 773 #define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 64 KB) base address */ 774 #define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */ 775 #define SRAM2B_BASE (SRAM_BASE + 0x00038000UL)/*!< SRAM2B(32 KB) base address */ 776 777 /* Memory Size */ 778 #define FLASH_SIZE (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x07FFUL)) << 10U) 779 #define SRAM1_SIZE 0x00010000UL /*!< SRAM1 default size : 64 kB */ 780 #define SRAM2A_SIZE 0x00008000UL /*!< SRAM2a default size : 32 kB */ 781 #define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */ 782 783 /* End addresses */ 784 #define SRAM1_END_ADDR (0x2000FFFFUL) /*!< SRAM1 : 64KB (0x20000000 � 0x2000FFFF) */ 785 #define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 � 0x20037FFF) */ 786 #define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 � 0x2003FFFF) */ 787 788 #define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 � 0x1FFF6FFF) */ 789 #define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 � 0x1FFF73FF) */ 790 #define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 � 0x1FFF8FFF) */ 791 #define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 � 0x1FFF7FFF) */ 792 793 /*!< Peripheral memory map */ 794 #define APB1PERIPH_BASE PERIPH_BASE 795 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) 796 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) 797 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) 798 #define AHB4PERIPH_BASE (PERIPH_BASE + 0x18000000UL) 799 #define APB3PERIPH_BASE (PERIPH_BASE + 0x20000000UL) 800 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x50000000UL) 801 802 /*!< APB1 peripherals */ 803 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) 804 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) 805 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) 806 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) 807 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) 808 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x00007C00UL) 809 #define LPTIM2_BASE (APB1PERIPH_BASE + 0x00009400UL) 810 811 /*!< APB2 peripherals */ 812 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL) 813 #define VREFBUF_BASE (APB2PERIPH_BASE + 0x00000030UL) 814 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) 815 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) 816 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) 817 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL) 818 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL) 819 820 /*!< AHB1 peripherals */ 821 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL) 822 #define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x00000800UL) 823 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL) 824 825 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) 826 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) 827 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) 828 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) 829 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) 830 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) 831 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) 832 833 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) 834 #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) 835 #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) 836 #define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) 837 #define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) 838 #define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) 839 #define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) 840 841 #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) 842 #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) 843 #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) 844 #define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) 845 846 #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) 847 #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) 848 849 /*!< AHB2 peripherals */ 850 #define IOPORT_BASE (AHB2PERIPH_BASE + 0x00000000UL) 851 #define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) 852 #define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) 853 #define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) 854 #define GPIOE_BASE (IOPORT_BASE + 0x00001000UL) 855 #define GPIOH_BASE (IOPORT_BASE + 0x00001C00UL) 856 857 #define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) 858 #define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) 859 860 861 /*!< AHB Shared peripherals */ 862 #define RCC_BASE (AHB4PERIPH_BASE + 0x00000000UL) 863 #define PWR_BASE (AHB4PERIPH_BASE + 0x00000400UL) 864 #define EXTI_BASE (AHB4PERIPH_BASE + 0x00000800UL) 865 #define IPCC_BASE (AHB4PERIPH_BASE + 0x00000C00UL) 866 #define RNG_BASE (AHB4PERIPH_BASE + 0x00001000UL) 867 #define HSEM_BASE (AHB4PERIPH_BASE + 0x00001400UL) 868 #define AES2_BASE (AHB4PERIPH_BASE + 0x00001800UL) 869 #define PKA_BASE (AHB4PERIPH_BASE + 0x00002000UL) 870 #define FLASH_REG_BASE (AHB4PERIPH_BASE + 0x00004000UL) 871 872 /* Debug MCU registers base address */ 873 #define DBGMCU_BASE (0xE0042000UL) 874 875 876 /*!< AHB3 peripherals */ 877 878 /*!< Device Electronic Signature */ 879 #define PACKAGE_BASE ((uint32_t)0x1FFF7500UL) /*!< Package data register base address */ 880 #define UID64_BASE ((uint32_t)0x1FFF7580UL) /*!< 64-bit Unique device Identification */ 881 #define UID_BASE ((uint32_t)0x1FFF7590UL) /*!< Unique device ID register base address */ 882 #define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0UL) /*!< Flash size data register base address */ 883 884 /** 885 * @} 886 */ 887 888 /** @addtogroup Peripheral_declaration 889 * @{ 890 */ 891 892 /* Peripherals available on APB1 bus */ 893 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 894 #define RTC ((RTC_TypeDef *) RTC_BASE) 895 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 896 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 897 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 898 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) 899 #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) 900 901 /* Peripherals available on APB2 bus */ 902 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 903 #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) 904 #define TIM1 ((TIM_TypeDef *) TIM1_BASE) 905 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 906 #define USART1 ((USART_TypeDef *) USART1_BASE) 907 #define TIM16 ((TIM_TypeDef *) TIM16_BASE) 908 #define TIM17 ((TIM_TypeDef *) TIM17_BASE) 909 910 /* Peripherals available on AHB1 bus */ 911 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 912 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 913 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 914 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 915 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 916 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 917 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) 918 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) 919 920 #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) 921 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) 922 #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) 923 #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) 924 #define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) 925 #define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) 926 #define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) 927 #define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) 928 929 #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) 930 #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) 931 #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) 932 #define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) 933 934 #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) 935 #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) 936 937 #define CRC ((CRC_TypeDef *) CRC_BASE) 938 939 /* Peripherals available on AHB2 bus */ 940 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 941 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 942 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 943 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) 944 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) 945 946 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 947 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) 948 949 950 /* Peripherals available on AHB shared bus */ 951 #define RCC ((RCC_TypeDef *) RCC_BASE) 952 #define PWR ((PWR_TypeDef *) PWR_BASE) 953 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 954 #define IPCC ((IPCC_TypeDef *) IPCC_BASE) 955 #define IPCC_C1 ((IPCC_CommonTypeDef *) IPCC_BASE) 956 #define IPCC_C2 ((IPCC_CommonTypeDef *) (IPCC_BASE + 0x10U)) 957 #define RNG ((RNG_TypeDef *) RNG_BASE) 958 #define HSEM ((HSEM_TypeDef *) HSEM_BASE) 959 #define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100U)) 960 #define AES2 ((AES_TypeDef *) AES2_BASE) 961 #define PKA ((PKA_TypeDef *) PKA_BASE) 962 #define FLASH ((FLASH_TypeDef *) FLASH_REG_BASE) 963 964 /* Peripherals available on AHB3 bus */ 965 966 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 967 /** 968 * @} 969 */ 970 971 /** @addtogroup Exported_constants 972 * @{ 973 */ 974 975 /** @addtogroup Peripheral_Registers_Bits_Definition 976 * @{ 977 */ 978 979 /******************************************************************************/ 980 /* Peripheral Registers Bits Definition */ 981 /******************************************************************************/ 982 983 /******************************************************************************/ 984 /* */ 985 /* Analog to Digital Converter (ADC) */ 986 /* */ 987 /******************************************************************************/ 988 /******************** Bit definition for ADC_ISR register *******************/ 989 #define ADC_ISR_ADRDY_Pos (0U) 990 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ 991 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ 992 #define ADC_ISR_EOSMP_Pos (1U) 993 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ 994 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ 995 #define ADC_ISR_EOC_Pos (2U) 996 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ 997 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ 998 #define ADC_ISR_EOS_Pos (3U) 999 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ 1000 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ 1001 #define ADC_ISR_OVR_Pos (4U) 1002 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ 1003 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ 1004 #define ADC_ISR_JEOC_Pos (5U) 1005 #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ 1006 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ 1007 #define ADC_ISR_JEOS_Pos (6U) 1008 #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ 1009 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ 1010 #define ADC_ISR_AWD1_Pos (7U) 1011 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ 1012 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ 1013 #define ADC_ISR_AWD2_Pos (8U) 1014 #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ 1015 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ 1016 #define ADC_ISR_AWD3_Pos (9U) 1017 #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ 1018 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ 1019 #define ADC_ISR_JQOVF_Pos (10U) 1020 #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ 1021 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ 1022 1023 /******************** Bit definition for ADC_IER register *******************/ 1024 #define ADC_IER_ADRDYIE_Pos (0U) 1025 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ 1026 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ 1027 #define ADC_IER_EOSMPIE_Pos (1U) 1028 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ 1029 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ 1030 #define ADC_IER_EOCIE_Pos (2U) 1031 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ 1032 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ 1033 #define ADC_IER_EOSIE_Pos (3U) 1034 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ 1035 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ 1036 #define ADC_IER_OVRIE_Pos (4U) 1037 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ 1038 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ 1039 #define ADC_IER_JEOCIE_Pos (5U) 1040 #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ 1041 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ 1042 #define ADC_IER_JEOSIE_Pos (6U) 1043 #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ 1044 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ 1045 #define ADC_IER_AWD1IE_Pos (7U) 1046 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ 1047 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ 1048 #define ADC_IER_AWD2IE_Pos (8U) 1049 #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ 1050 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ 1051 #define ADC_IER_AWD3IE_Pos (9U) 1052 #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ 1053 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ 1054 #define ADC_IER_JQOVFIE_Pos (10U) 1055 #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ 1056 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ 1057 1058 /******************** Bit definition for ADC_CR register ********************/ 1059 #define ADC_CR_ADEN_Pos (0U) 1060 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ 1061 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ 1062 #define ADC_CR_ADDIS_Pos (1U) 1063 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ 1064 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ 1065 #define ADC_CR_ADSTART_Pos (2U) 1066 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ 1067 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ 1068 #define ADC_CR_JADSTART_Pos (3U) 1069 #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ 1070 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ 1071 #define ADC_CR_ADSTP_Pos (4U) 1072 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ 1073 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ 1074 #define ADC_CR_JADSTP_Pos (5U) 1075 #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ 1076 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ 1077 #define ADC_CR_ADVREGEN_Pos (28U) 1078 #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ 1079 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ 1080 #define ADC_CR_DEEPPWD_Pos (29U) 1081 #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ 1082 #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ 1083 #define ADC_CR_ADCALDIF_Pos (30U) 1084 #define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ 1085 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ 1086 #define ADC_CR_ADCAL_Pos (31U) 1087 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ 1088 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ 1089 1090 /******************** Bit definition for ADC_CFGR1 register *****************/ 1091 #define ADC_CFGR_DMAEN_Pos (0U) 1092 #define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ 1093 #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA enable */ 1094 #define ADC_CFGR_DMACFG_Pos (1U) 1095 #define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ 1096 #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA configuration */ 1097 1098 #define ADC_CFGR_RES_Pos (3U) 1099 #define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ 1100 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ 1101 #define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ 1102 #define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ 1103 1104 #define ADC_CFGR_ALIGN_Pos (5U) 1105 #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ 1106 #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ 1107 1108 #define ADC_CFGR_EXTSEL_Pos (6U) 1109 #define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ 1110 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ 1111 #define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ 1112 #define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ 1113 #define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ 1114 #define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ 1115 1116 #define ADC_CFGR_EXTEN_Pos (10U) 1117 #define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ 1118 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ 1119 #define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ 1120 #define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ 1121 1122 #define ADC_CFGR_OVRMOD_Pos (12U) 1123 #define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ 1124 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ 1125 #define ADC_CFGR_CONT_Pos (13U) 1126 #define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ 1127 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ 1128 #define ADC_CFGR_AUTDLY_Pos (14U) 1129 #define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ 1130 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ 1131 1132 #define ADC_CFGR_DISCEN_Pos (16U) 1133 #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ 1134 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ 1135 1136 #define ADC_CFGR_DISCNUM_Pos (17U) 1137 #define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ 1138 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ 1139 #define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ 1140 #define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ 1141 #define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ 1142 1143 #define ADC_CFGR_JDISCEN_Pos (20U) 1144 #define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ 1145 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ 1146 #define ADC_CFGR_JQM_Pos (21U) 1147 #define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ 1148 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ 1149 #define ADC_CFGR_AWD1SGL_Pos (22U) 1150 #define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ 1151 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ 1152 #define ADC_CFGR_AWD1EN_Pos (23U) 1153 #define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ 1154 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ 1155 #define ADC_CFGR_JAWD1EN_Pos (24U) 1156 #define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ 1157 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ 1158 #define ADC_CFGR_JAUTO_Pos (25U) 1159 #define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ 1160 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ 1161 1162 #define ADC_CFGR_AWD1CH_Pos (26U) 1163 #define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ 1164 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ 1165 #define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ 1166 #define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ 1167 #define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ 1168 #define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ 1169 #define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ 1170 1171 #define ADC_CFGR_JQDIS_Pos (31U) 1172 #define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x00800000 */ 1173 #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ 1174 1175 /******************** Bit definition for ADC_CFGR2 register *****************/ 1176 #define ADC_CFGR2_ROVSE_Pos (0U) 1177 #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ 1178 #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ 1179 1180 #define ADC_CFGR2_JOVSE_Pos (1U) 1181 #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ 1182 #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ 1183 1184 #define ADC_CFGR2_OVSR_Pos (2U) 1185 #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ 1186 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ 1187 #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ 1188 #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ 1189 #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ 1190 1191 #define ADC_CFGR2_OVSS_Pos (5U) 1192 #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ 1193 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ 1194 #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ 1195 #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ 1196 #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ 1197 #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ 1198 1199 #define ADC_CFGR2_TROVS_Pos (9U) 1200 #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ 1201 #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ 1202 1203 #define ADC_CFGR2_ROVSM_Pos (10U) 1204 #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ 1205 #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ 1206 1207 /******************** Bit definition for ADC_SMPR1 register *****************/ 1208 #define ADC_SMPR1_SMP0_Pos (0U) 1209 #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ 1210 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ 1211 #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ 1212 #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ 1213 #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ 1214 1215 #define ADC_SMPR1_SMP1_Pos (3U) 1216 #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ 1217 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ 1218 #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ 1219 #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ 1220 #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ 1221 1222 #define ADC_SMPR1_SMP2_Pos (6U) 1223 #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ 1224 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ 1225 #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ 1226 #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ 1227 #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ 1228 1229 #define ADC_SMPR1_SMP3_Pos (9U) 1230 #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ 1231 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ 1232 #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ 1233 #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ 1234 #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ 1235 1236 #define ADC_SMPR1_SMP4_Pos (12U) 1237 #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ 1238 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ 1239 #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ 1240 #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ 1241 #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ 1242 1243 #define ADC_SMPR1_SMP5_Pos (15U) 1244 #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ 1245 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ 1246 #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ 1247 #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ 1248 #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ 1249 1250 #define ADC_SMPR1_SMP6_Pos (18U) 1251 #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ 1252 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ 1253 #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ 1254 #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ 1255 #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ 1256 1257 #define ADC_SMPR1_SMP7_Pos (21U) 1258 #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ 1259 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ 1260 #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ 1261 #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ 1262 #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ 1263 1264 #define ADC_SMPR1_SMP8_Pos (24U) 1265 #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ 1266 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ 1267 #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ 1268 #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ 1269 #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ 1270 1271 #define ADC_SMPR1_SMP9_Pos (27U) 1272 #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ 1273 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ 1274 #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ 1275 #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ 1276 #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ 1277 1278 /******************** Bit definition for ADC_SMPR2 register *****************/ 1279 #define ADC_SMPR2_SMP10_Pos (0U) 1280 #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ 1281 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ 1282 #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ 1283 #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ 1284 #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ 1285 1286 #define ADC_SMPR2_SMP11_Pos (3U) 1287 #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ 1288 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ 1289 #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ 1290 #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ 1291 #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ 1292 1293 #define ADC_SMPR2_SMP12_Pos (6U) 1294 #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ 1295 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ 1296 #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ 1297 #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ 1298 #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ 1299 1300 #define ADC_SMPR2_SMP13_Pos (9U) 1301 #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ 1302 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ 1303 #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ 1304 #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ 1305 #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ 1306 1307 #define ADC_SMPR2_SMP14_Pos (12U) 1308 #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ 1309 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ 1310 #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ 1311 #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ 1312 #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ 1313 1314 #define ADC_SMPR2_SMP15_Pos (15U) 1315 #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ 1316 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ 1317 #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ 1318 #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ 1319 #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ 1320 1321 #define ADC_SMPR2_SMP16_Pos (18U) 1322 #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ 1323 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ 1324 #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ 1325 #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ 1326 #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ 1327 1328 #define ADC_SMPR2_SMP17_Pos (21U) 1329 #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ 1330 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ 1331 #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ 1332 #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ 1333 #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ 1334 1335 #define ADC_SMPR2_SMP18_Pos (24U) 1336 #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ 1337 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ 1338 #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ 1339 #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ 1340 #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ 1341 1342 /******************** Bit definition for ADC_TR1 register *******************/ 1343 #define ADC_TR1_LT1_Pos (0U) 1344 #define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ 1345 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ 1346 #define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ 1347 #define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ 1348 #define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ 1349 #define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ 1350 #define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ 1351 #define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ 1352 #define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ 1353 #define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ 1354 #define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ 1355 #define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ 1356 #define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ 1357 #define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ 1358 1359 #define ADC_TR1_HT1_Pos (16U) 1360 #define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ 1361 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ 1362 #define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ 1363 #define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ 1364 #define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ 1365 #define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ 1366 #define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ 1367 #define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ 1368 #define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ 1369 #define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ 1370 #define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ 1371 #define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ 1372 #define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ 1373 #define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ 1374 1375 /******************** Bit definition for ADC_TR2 register *******************/ 1376 #define ADC_TR2_LT2_Pos (0U) 1377 #define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ 1378 #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ 1379 #define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ 1380 #define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ 1381 #define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ 1382 #define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ 1383 #define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ 1384 #define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ 1385 #define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ 1386 #define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ 1387 1388 #define ADC_TR2_HT2_Pos (16U) 1389 #define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ 1390 #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ 1391 #define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ 1392 #define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ 1393 #define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ 1394 #define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ 1395 #define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ 1396 #define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ 1397 #define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ 1398 #define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ 1399 1400 /******************** Bit definition for ADC_TR3 register *******************/ 1401 #define ADC_TR3_LT3_Pos (0U) 1402 #define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ 1403 #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ 1404 #define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ 1405 #define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ 1406 #define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ 1407 #define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ 1408 #define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ 1409 #define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ 1410 #define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ 1411 #define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ 1412 1413 #define ADC_TR3_HT3_Pos (16U) 1414 #define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ 1415 #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ 1416 #define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ 1417 #define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ 1418 #define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ 1419 #define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ 1420 #define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ 1421 #define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ 1422 #define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ 1423 #define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ 1424 1425 /******************** Bit definition for ADC_SQR1 register ******************/ 1426 #define ADC_SQR1_L_Pos (0U) 1427 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ 1428 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ 1429 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ 1430 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ 1431 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ 1432 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ 1433 1434 #define ADC_SQR1_SQ1_Pos (6U) 1435 #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ 1436 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ 1437 #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ 1438 #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ 1439 #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ 1440 #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ 1441 #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ 1442 1443 #define ADC_SQR1_SQ2_Pos (12U) 1444 #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ 1445 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ 1446 #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ 1447 #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ 1448 #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ 1449 #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ 1450 #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ 1451 1452 #define ADC_SQR1_SQ3_Pos (18U) 1453 #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ 1454 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ 1455 #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ 1456 #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ 1457 #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ 1458 #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ 1459 #define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ 1460 1461 #define ADC_SQR1_SQ4_Pos (24U) 1462 #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ 1463 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ 1464 #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ 1465 #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ 1466 #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ 1467 #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ 1468 #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ 1469 1470 /******************** Bit definition for ADC_SQR2 register ******************/ 1471 #define ADC_SQR2_SQ5_Pos (0U) 1472 #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ 1473 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ 1474 #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ 1475 #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ 1476 #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ 1477 #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ 1478 #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ 1479 1480 #define ADC_SQR2_SQ6_Pos (6U) 1481 #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ 1482 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ 1483 #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ 1484 #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ 1485 #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ 1486 #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ 1487 #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ 1488 1489 #define ADC_SQR2_SQ7_Pos (12U) 1490 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ 1491 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ 1492 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ 1493 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ 1494 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ 1495 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ 1496 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ 1497 1498 #define ADC_SQR2_SQ8_Pos (18U) 1499 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ 1500 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ 1501 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ 1502 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ 1503 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ 1504 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ 1505 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ 1506 1507 #define ADC_SQR2_SQ9_Pos (24U) 1508 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ 1509 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ 1510 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ 1511 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ 1512 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ 1513 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ 1514 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ 1515 1516 /******************** Bit definition for ADC_SQR3 register ******************/ 1517 #define ADC_SQR3_SQ10_Pos (0U) 1518 #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ 1519 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ 1520 #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ 1521 #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ 1522 #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ 1523 #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ 1524 #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ 1525 1526 #define ADC_SQR3_SQ11_Pos (6U) 1527 #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ 1528 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ 1529 #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ 1530 #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ 1531 #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ 1532 #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ 1533 #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ 1534 1535 #define ADC_SQR3_SQ12_Pos (12U) 1536 #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ 1537 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ 1538 #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ 1539 #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ 1540 #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ 1541 #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ 1542 #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ 1543 1544 #define ADC_SQR3_SQ13_Pos (18U) 1545 #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ 1546 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ 1547 #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ 1548 #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ 1549 #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ 1550 #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ 1551 #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ 1552 1553 #define ADC_SQR3_SQ14_Pos (24U) 1554 #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ 1555 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ 1556 #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ 1557 #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ 1558 #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ 1559 #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ 1560 #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ 1561 1562 /******************** Bit definition for ADC_SQR4 register ******************/ 1563 #define ADC_SQR4_SQ15_Pos (0U) 1564 #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ 1565 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ 1566 #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ 1567 #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ 1568 #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ 1569 #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ 1570 #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ 1571 1572 #define ADC_SQR4_SQ16_Pos (6U) 1573 #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ 1574 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ 1575 #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ 1576 #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ 1577 #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ 1578 #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ 1579 #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ 1580 1581 /******************** Bit definition for ADC_DR register ********************/ 1582 #define ADC_DR_RDATA_Pos (0U) 1583 #define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ 1584 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ 1585 #define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ 1586 #define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ 1587 #define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ 1588 #define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ 1589 #define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ 1590 #define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ 1591 #define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ 1592 #define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ 1593 #define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ 1594 #define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ 1595 #define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ 1596 #define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ 1597 #define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ 1598 #define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ 1599 #define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ 1600 #define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ 1601 1602 /******************** Bit definition for ADC_JSQR register ******************/ 1603 #define ADC_JSQR_JL_Pos (0U) 1604 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ 1605 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ 1606 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ 1607 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ 1608 1609 #define ADC_JSQR_JEXTSEL_Pos (2U) 1610 #define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ 1611 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ 1612 #define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ 1613 #define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ 1614 #define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ 1615 #define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ 1616 1617 #define ADC_JSQR_JEXTEN_Pos (6U) 1618 #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ 1619 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ 1620 #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ 1621 #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ 1622 1623 #define ADC_JSQR_JSQ1_Pos (8U) 1624 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ 1625 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ 1626 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ 1627 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ 1628 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ 1629 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ 1630 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ 1631 1632 #define ADC_JSQR_JSQ2_Pos (14U) 1633 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ 1634 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ 1635 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ 1636 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ 1637 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ 1638 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ 1639 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ 1640 1641 #define ADC_JSQR_JSQ3_Pos (20U) 1642 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ 1643 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ 1644 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ 1645 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ 1646 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ 1647 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ 1648 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ 1649 1650 #define ADC_JSQR_JSQ4_Pos (26U) 1651 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ 1652 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ 1653 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ 1654 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ 1655 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ 1656 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ 1657 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ 1658 1659 /******************** Bit definition for ADC_OFR1 register ******************/ 1660 #define ADC_OFR1_OFFSET1_Pos (0U) 1661 #define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ 1662 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ 1663 #define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ 1664 #define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ 1665 #define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ 1666 #define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ 1667 #define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ 1668 #define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ 1669 #define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ 1670 #define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ 1671 #define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ 1672 #define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ 1673 #define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ 1674 #define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ 1675 1676 #define ADC_OFR1_OFFSET1_CH_Pos (26U) 1677 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ 1678 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ 1679 #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ 1680 #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ 1681 #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ 1682 #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ 1683 #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ 1684 1685 #define ADC_OFR1_OFFSET1_EN_Pos (31U) 1686 #define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ 1687 #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ 1688 1689 /******************** Bit definition for ADC_OFR2 register ******************/ 1690 #define ADC_OFR2_OFFSET2_Pos (0U) 1691 #define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ 1692 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ 1693 #define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ 1694 #define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ 1695 #define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ 1696 #define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ 1697 #define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ 1698 #define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ 1699 #define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ 1700 #define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ 1701 #define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ 1702 #define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ 1703 #define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ 1704 #define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ 1705 1706 #define ADC_OFR2_OFFSET2_CH_Pos (26U) 1707 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ 1708 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ 1709 #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ 1710 #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ 1711 #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ 1712 #define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ 1713 #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ 1714 1715 #define ADC_OFR2_OFFSET2_EN_Pos (31U) 1716 #define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ 1717 #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ 1718 1719 /******************** Bit definition for ADC_OFR3 register ******************/ 1720 #define ADC_OFR3_OFFSET3_Pos (0U) 1721 #define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ 1722 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ 1723 #define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ 1724 #define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ 1725 #define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ 1726 #define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ 1727 #define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ 1728 #define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ 1729 #define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ 1730 #define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ 1731 #define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ 1732 #define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ 1733 #define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ 1734 #define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ 1735 1736 #define ADC_OFR3_OFFSET3_CH_Pos (26U) 1737 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ 1738 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ 1739 #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ 1740 #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ 1741 #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ 1742 #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ 1743 #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ 1744 1745 #define ADC_OFR3_OFFSET3_EN_Pos (31U) 1746 #define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ 1747 #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ 1748 1749 /******************** Bit definition for ADC_OFR4 register ******************/ 1750 #define ADC_OFR4_OFFSET4_Pos (0U) 1751 #define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ 1752 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ 1753 #define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ 1754 #define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ 1755 #define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ 1756 #define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ 1757 #define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ 1758 #define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ 1759 #define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ 1760 #define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ 1761 #define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ 1762 #define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ 1763 #define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ 1764 #define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ 1765 1766 #define ADC_OFR4_OFFSET4_CH_Pos (26U) 1767 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ 1768 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ 1769 #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ 1770 #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ 1771 #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ 1772 #define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ 1773 #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ 1774 1775 #define ADC_OFR4_OFFSET4_EN_Pos (31U) 1776 #define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ 1777 #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ 1778 1779 /******************** Bit definition for ADC_JDR1 register ******************/ 1780 #define ADC_JDR1_JDATA_Pos (0U) 1781 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ 1782 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ 1783 #define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ 1784 #define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ 1785 #define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ 1786 #define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ 1787 #define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ 1788 #define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ 1789 #define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ 1790 #define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ 1791 #define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ 1792 #define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ 1793 #define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ 1794 #define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ 1795 #define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ 1796 #define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ 1797 #define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ 1798 #define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ 1799 1800 /******************** Bit definition for ADC_JDR2 register ******************/ 1801 #define ADC_JDR2_JDATA_Pos (0U) 1802 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ 1803 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ 1804 #define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ 1805 #define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ 1806 #define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ 1807 #define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ 1808 #define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ 1809 #define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ 1810 #define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ 1811 #define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ 1812 #define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ 1813 #define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ 1814 #define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ 1815 #define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ 1816 #define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ 1817 #define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ 1818 #define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ 1819 #define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ 1820 1821 /******************** Bit definition for ADC_JDR3 register ******************/ 1822 #define ADC_JDR3_JDATA_Pos (0U) 1823 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ 1824 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ 1825 #define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ 1826 #define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ 1827 #define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ 1828 #define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ 1829 #define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ 1830 #define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ 1831 #define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ 1832 #define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ 1833 #define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ 1834 #define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ 1835 #define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ 1836 #define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ 1837 #define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ 1838 #define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ 1839 #define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ 1840 #define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ 1841 1842 /******************** Bit definition for ADC_JDR4 register ******************/ 1843 #define ADC_JDR4_JDATA_Pos (0U) 1844 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ 1845 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ 1846 #define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ 1847 #define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ 1848 #define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ 1849 #define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ 1850 #define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ 1851 #define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ 1852 #define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ 1853 #define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ 1854 #define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ 1855 #define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ 1856 #define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ 1857 #define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ 1858 #define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ 1859 #define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ 1860 #define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ 1861 #define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ 1862 1863 /******************** Bit definition for ADC_AWD2CR register ****************/ 1864 #define ADC_AWD2CR_AWD2CH_Pos (0U) 1865 #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ 1866 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ 1867 #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ 1868 #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ 1869 #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ 1870 #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ 1871 #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ 1872 #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ 1873 #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ 1874 #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ 1875 #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ 1876 #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ 1877 #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ 1878 #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ 1879 #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ 1880 #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ 1881 #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ 1882 #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ 1883 #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ 1884 #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ 1885 #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ 1886 1887 /******************** Bit definition for ADC_AWD3CR register ****************/ 1888 #define ADC_AWD3CR_AWD3CH_Pos (0U) 1889 #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ 1890 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ 1891 #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ 1892 #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ 1893 #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ 1894 #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ 1895 #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ 1896 #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ 1897 #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ 1898 #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ 1899 #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ 1900 #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ 1901 #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ 1902 #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ 1903 #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ 1904 #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ 1905 #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ 1906 #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ 1907 #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ 1908 #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ 1909 #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ 1910 1911 /******************** Bit definition for ADC_DIFSEL register ****************/ 1912 #define ADC_DIFSEL_DIFSEL_Pos (0U) 1913 #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ 1914 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ 1915 #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ 1916 #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ 1917 #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ 1918 #define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ 1919 #define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ 1920 #define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ 1921 #define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ 1922 #define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ 1923 #define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ 1924 #define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ 1925 #define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ 1926 #define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ 1927 #define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ 1928 #define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ 1929 #define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ 1930 #define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ 1931 #define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ 1932 #define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ 1933 #define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ 1934 1935 /******************** Bit definition for ADC_CALFACT register ***************/ 1936 #define ADC_CALFACT_CALFACT_S_Pos (0U) 1937 #define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ 1938 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ 1939 #define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ 1940 #define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ 1941 #define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ 1942 #define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ 1943 #define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ 1944 #define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ 1945 #define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ 1946 1947 #define ADC_CALFACT_CALFACT_D_Pos (16U) 1948 #define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ 1949 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ 1950 #define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ 1951 #define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ 1952 #define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ 1953 #define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ 1954 #define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ 1955 #define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ 1956 #define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ 1957 1958 /************************* ADC Common registers *****************************/ 1959 /******************** Bit definition for ADC_CCR register *******************/ 1960 #define ADC_CCR_DUAL_Pos (0U) 1961 #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ 1962 #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ 1963 #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ 1964 #define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ 1965 #define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ 1966 #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ 1967 #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ 1968 1969 #define ADC_CCR_DELAY_Pos (8U) 1970 #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ 1971 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ 1972 #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ 1973 #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ 1974 #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ 1975 #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ 1976 1977 #define ADC_CCR_DMACFG_Pos (13U) 1978 #define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ 1979 #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ 1980 1981 #define ADC_CCR_MDMA_Pos (14U) 1982 #define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ 1983 #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ 1984 #define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ 1985 #define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ 1986 1987 #define ADC_CCR_CKMODE_Pos (16U) 1988 #define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ 1989 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ 1990 #define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ 1991 #define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ 1992 1993 #define ADC_CCR_PRESC_Pos (18U) 1994 #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003A0000 */ 1995 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ 1996 #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00000100 */ 1997 #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00000200 */ 1998 #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00000400 */ 1999 #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00000800 */ 2000 2001 #define ADC_CCR_VREFEN_Pos (22U) 2002 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ 2003 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ 2004 #define ADC_CCR_TSEN_Pos (23U) 2005 #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ 2006 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ 2007 #define ADC_CCR_VBATEN_Pos (24U) 2008 #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ 2009 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ 2010 2011 /* Legacy defines */ 2012 #define ADC_CCR_MULTI (ADC_CCR_DUAL) 2013 #define ADC_CCR_MULTI_0 (ADC_CCR_DUAL_0) 2014 #define ADC_CCR_MULTI_1 (ADC_CCR_DUAL_1) 2015 #define ADC_CCR_MULTI_2 (ADC_CCR_DUAL_2) 2016 #define ADC_CCR_MULTI_3 (ADC_CCR_DUAL_3) 2017 #define ADC_CCR_MULTI_4 (ADC_CCR_DUAL_4) 2018 2019 /******************************************************************************/ 2020 /* */ 2021 /* CRC calculation unit */ 2022 /* */ 2023 /******************************************************************************/ 2024 /******************* Bit definition for CRC_DR register *********************/ 2025 #define CRC_DR_DR_Pos (0U) 2026 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 2027 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 2028 2029 /******************* Bit definition for CRC_IDR register ********************/ 2030 #define CRC_IDR_IDR_Pos (0U) 2031 #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ 2032 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bits data register bits */ 2033 2034 /******************** Bit definition for CRC_CR register ********************/ 2035 #define CRC_CR_RESET_Pos (0U) 2036 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 2037 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ 2038 #define CRC_CR_POLYSIZE_Pos (3U) 2039 #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ 2040 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ 2041 #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ 2042 #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ 2043 #define CRC_CR_REV_IN_Pos (5U) 2044 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ 2045 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ 2046 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ 2047 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ 2048 #define CRC_CR_REV_OUT_Pos (7U) 2049 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ 2050 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ 2051 2052 /******************* Bit definition for CRC_INIT register *******************/ 2053 #define CRC_INIT_INIT_Pos (0U) 2054 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ 2055 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ 2056 2057 /******************* Bit definition for CRC_POL register ********************/ 2058 #define CRC_POL_POL_Pos (0U) 2059 #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ 2060 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ 2061 2062 /******************************************************************************/ 2063 /* */ 2064 /* Advanced Encryption Standard (AES) */ 2065 /* */ 2066 /******************************************************************************/ 2067 /******************* Bit definition for AES_CR register *********************/ 2068 #define AES_CR_EN_Pos (0U) 2069 #define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ 2070 #define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ 2071 #define AES_CR_DATATYPE_Pos (1U) 2072 #define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ 2073 #define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ 2074 #define AES_CR_DATATYPE_0 (0x1U << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ 2075 #define AES_CR_DATATYPE_1 (0x2U << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ 2076 2077 #define AES_CR_MODE_Pos (3U) 2078 #define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ 2079 #define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ 2080 #define AES_CR_MODE_0 (0x1U << AES_CR_MODE_Pos) /*!< 0x00000008 */ 2081 #define AES_CR_MODE_1 (0x2U << AES_CR_MODE_Pos) /*!< 0x00000010 */ 2082 2083 #define AES_CR_CHMOD_Pos (5U) 2084 #define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ 2085 #define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ 2086 #define AES_CR_CHMOD_0 (0x001U << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ 2087 #define AES_CR_CHMOD_1 (0x002U << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ 2088 #define AES_CR_CHMOD_2 (0x800U << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ 2089 2090 #define AES_CR_CCFC_Pos (7U) 2091 #define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */ 2092 #define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */ 2093 #define AES_CR_ERRC_Pos (8U) 2094 #define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */ 2095 #define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */ 2096 #define AES_CR_CCFIE_Pos (9U) 2097 #define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */ 2098 #define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */ 2099 #define AES_CR_ERRIE_Pos (10U) 2100 #define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */ 2101 #define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */ 2102 #define AES_CR_DMAINEN_Pos (11U) 2103 #define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ 2104 #define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ 2105 #define AES_CR_DMAOUTEN_Pos (12U) 2106 #define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ 2107 #define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ 2108 2109 #define AES_CR_GCMPH_Pos (13U) 2110 #define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ 2111 #define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ 2112 #define AES_CR_GCMPH_0 (0x1U << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ 2113 #define AES_CR_GCMPH_1 (0x2U << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ 2114 2115 #define AES_CR_KEYSIZE_Pos (18U) 2116 #define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ 2117 #define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ 2118 2119 #define AES_CR_NPBLB_Pos (20U) 2120 #define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ 2121 #define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in last payload block */ 2122 #define AES_CR_NPBLB_0 (0x1U << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ 2123 #define AES_CR_NPBLB_1 (0x2U << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ 2124 #define AES_CR_NPBLB_2 (0x4U << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ 2125 #define AES_CR_NPBLB_3 (0x8U << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ 2126 2127 /******************* Bit definition for AES_SR register *********************/ 2128 #define AES_SR_CCF_Pos (0U) 2129 #define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ 2130 #define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ 2131 #define AES_SR_RDERR_Pos (1U) 2132 #define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ 2133 #define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ 2134 #define AES_SR_WRERR_Pos (2U) 2135 #define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ 2136 #define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ 2137 #define AES_SR_BUSY_Pos (3U) 2138 #define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ 2139 #define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ 2140 2141 /******************* Bit definition for AES_DINR register *******************/ 2142 #define AES_DINR_Pos (0U) 2143 #define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ 2144 #define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ 2145 2146 /******************* Bit definition for AES_DOUTR register ******************/ 2147 #define AES_DOUTR_Pos (0U) 2148 #define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ 2149 #define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ 2150 2151 /******************* Bit definition for AES_KEYR0 register ******************/ 2152 #define AES_KEYR0_Pos (0U) 2153 #define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ 2154 #define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ 2155 2156 /******************* Bit definition for AES_KEYR1 register ******************/ 2157 #define AES_KEYR1_Pos (0U) 2158 #define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ 2159 #define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ 2160 2161 /******************* Bit definition for AES_KEYR2 register ******************/ 2162 #define AES_KEYR2_Pos (0U) 2163 #define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ 2164 #define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ 2165 2166 /******************* Bit definition for AES_KEYR3 register ******************/ 2167 #define AES_KEYR3_Pos (0U) 2168 #define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ 2169 #define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ 2170 2171 /******************* Bit definition for AES_KEYR4 register ******************/ 2172 #define AES_KEYR4_Pos (0U) 2173 #define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ 2174 #define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ 2175 2176 /******************* Bit definition for AES_KEYR5 register ******************/ 2177 #define AES_KEYR5_Pos (0U) 2178 #define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ 2179 #define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ 2180 2181 /******************* Bit definition for AES_KEYR6 register ******************/ 2182 #define AES_KEYR6_Pos (0U) 2183 #define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ 2184 #define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ 2185 2186 /******************* Bit definition for AES_KEYR7 register ******************/ 2187 #define AES_KEYR7_Pos (0U) 2188 #define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ 2189 #define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ 2190 2191 /******************* Bit definition for AES_IVR0 register ******************/ 2192 #define AES_IVR0_Pos (0U) 2193 #define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ 2194 #define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ 2195 2196 /******************* Bit definition for AES_IVR1 register ******************/ 2197 #define AES_IVR1_Pos (0U) 2198 #define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ 2199 #define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ 2200 2201 /******************* Bit definition for AES_IVR2 register ******************/ 2202 #define AES_IVR2_Pos (0U) 2203 #define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ 2204 #define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ 2205 2206 /******************* Bit definition for AES_IVR3 register ******************/ 2207 #define AES_IVR3_Pos (0U) 2208 #define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ 2209 #define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ 2210 2211 /******************* Bit definition for AES_SUSP0R register ******************/ 2212 #define AES_SUSP0R_Pos (0U) 2213 #define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ 2214 #define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ 2215 2216 /******************* Bit definition for AES_SUSP1R register ******************/ 2217 #define AES_SUSP1R_Pos (0U) 2218 #define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ 2219 #define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ 2220 2221 /******************* Bit definition for AES_SUSP2R register ******************/ 2222 #define AES_SUSP2R_Pos (0U) 2223 #define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ 2224 #define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ 2225 2226 /******************* Bit definition for AES_SUSP3R register ******************/ 2227 #define AES_SUSP3R_Pos (0U) 2228 #define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ 2229 #define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ 2230 2231 /******************* Bit definition for AES_SUSP4R register ******************/ 2232 #define AES_SUSP4R_Pos (0U) 2233 #define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ 2234 #define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ 2235 2236 /******************* Bit definition for AES_SUSP5R register ******************/ 2237 #define AES_SUSP5R_Pos (0U) 2238 #define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ 2239 #define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ 2240 2241 /******************* Bit definition for AES_SUSP6R register ******************/ 2242 #define AES_SUSP6R_Pos (0U) 2243 #define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ 2244 #define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ 2245 2246 /******************* Bit definition for AES_SUSP7R register ******************/ 2247 #define AES_SUSP7R_Pos (0U) 2248 #define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ 2249 #define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ 2250 2251 /******************************************************************************/ 2252 /* */ 2253 /* DMA Controller (DMA) */ 2254 /* */ 2255 /******************************************************************************/ 2256 2257 /******************* Bit definition for DMA_ISR register ********************/ 2258 #define DMA_ISR_GIF1_Pos (0U) 2259 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 2260 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 2261 #define DMA_ISR_TCIF1_Pos (1U) 2262 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 2263 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 2264 #define DMA_ISR_HTIF1_Pos (2U) 2265 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 2266 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 2267 #define DMA_ISR_TEIF1_Pos (3U) 2268 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 2269 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 2270 #define DMA_ISR_GIF2_Pos (4U) 2271 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 2272 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 2273 #define DMA_ISR_TCIF2_Pos (5U) 2274 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 2275 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 2276 #define DMA_ISR_HTIF2_Pos (6U) 2277 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 2278 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 2279 #define DMA_ISR_TEIF2_Pos (7U) 2280 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 2281 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 2282 #define DMA_ISR_GIF3_Pos (8U) 2283 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 2284 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 2285 #define DMA_ISR_TCIF3_Pos (9U) 2286 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 2287 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 2288 #define DMA_ISR_HTIF3_Pos (10U) 2289 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 2290 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 2291 #define DMA_ISR_TEIF3_Pos (11U) 2292 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 2293 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 2294 #define DMA_ISR_GIF4_Pos (12U) 2295 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 2296 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 2297 #define DMA_ISR_TCIF4_Pos (13U) 2298 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 2299 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 2300 #define DMA_ISR_HTIF4_Pos (14U) 2301 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 2302 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 2303 #define DMA_ISR_TEIF4_Pos (15U) 2304 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 2305 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 2306 #define DMA_ISR_GIF5_Pos (16U) 2307 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 2308 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 2309 #define DMA_ISR_TCIF5_Pos (17U) 2310 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 2311 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 2312 #define DMA_ISR_HTIF5_Pos (18U) 2313 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 2314 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 2315 #define DMA_ISR_TEIF5_Pos (19U) 2316 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 2317 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 2318 #define DMA_ISR_GIF6_Pos (20U) 2319 #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ 2320 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ 2321 #define DMA_ISR_TCIF6_Pos (21U) 2322 #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ 2323 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ 2324 #define DMA_ISR_HTIF6_Pos (22U) 2325 #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ 2326 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ 2327 #define DMA_ISR_TEIF6_Pos (23U) 2328 #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ 2329 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ 2330 #define DMA_ISR_GIF7_Pos (24U) 2331 #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ 2332 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ 2333 #define DMA_ISR_TCIF7_Pos (25U) 2334 #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ 2335 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ 2336 #define DMA_ISR_HTIF7_Pos (26U) 2337 #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ 2338 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ 2339 #define DMA_ISR_TEIF7_Pos (27U) 2340 #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ 2341 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ 2342 2343 /******************* Bit definition for DMA_IFCR register *******************/ 2344 #define DMA_IFCR_CGIF1_Pos (0U) 2345 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 2346 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ 2347 #define DMA_IFCR_CTCIF1_Pos (1U) 2348 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 2349 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 2350 #define DMA_IFCR_CHTIF1_Pos (2U) 2351 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 2352 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 2353 #define DMA_IFCR_CTEIF1_Pos (3U) 2354 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 2355 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 2356 #define DMA_IFCR_CGIF2_Pos (4U) 2357 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 2358 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 2359 #define DMA_IFCR_CTCIF2_Pos (5U) 2360 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 2361 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 2362 #define DMA_IFCR_CHTIF2_Pos (6U) 2363 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 2364 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 2365 #define DMA_IFCR_CTEIF2_Pos (7U) 2366 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 2367 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 2368 #define DMA_IFCR_CGIF3_Pos (8U) 2369 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 2370 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 2371 #define DMA_IFCR_CTCIF3_Pos (9U) 2372 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 2373 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 2374 #define DMA_IFCR_CHTIF3_Pos (10U) 2375 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 2376 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 2377 #define DMA_IFCR_CTEIF3_Pos (11U) 2378 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 2379 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 2380 #define DMA_IFCR_CGIF4_Pos (12U) 2381 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 2382 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 2383 #define DMA_IFCR_CTCIF4_Pos (13U) 2384 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 2385 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 2386 #define DMA_IFCR_CHTIF4_Pos (14U) 2387 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 2388 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 2389 #define DMA_IFCR_CTEIF4_Pos (15U) 2390 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 2391 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 2392 #define DMA_IFCR_CGIF5_Pos (16U) 2393 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 2394 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 2395 #define DMA_IFCR_CTCIF5_Pos (17U) 2396 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 2397 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 2398 #define DMA_IFCR_CHTIF5_Pos (18U) 2399 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 2400 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 2401 #define DMA_IFCR_CTEIF5_Pos (19U) 2402 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 2403 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 2404 #define DMA_IFCR_CGIF6_Pos (20U) 2405 #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ 2406 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ 2407 #define DMA_IFCR_CTCIF6_Pos (21U) 2408 #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ 2409 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ 2410 #define DMA_IFCR_CHTIF6_Pos (22U) 2411 #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ 2412 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ 2413 #define DMA_IFCR_CTEIF6_Pos (23U) 2414 #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ 2415 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ 2416 #define DMA_IFCR_CGIF7_Pos (24U) 2417 #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ 2418 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ 2419 #define DMA_IFCR_CTCIF7_Pos (25U) 2420 #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ 2421 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ 2422 #define DMA_IFCR_CHTIF7_Pos (26U) 2423 #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ 2424 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ 2425 #define DMA_IFCR_CTEIF7_Pos (27U) 2426 #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ 2427 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ 2428 2429 /******************* Bit definition for DMA_CCR register ********************/ 2430 #define DMA_CCR_EN_Pos (0U) 2431 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 2432 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ 2433 #define DMA_CCR_TCIE_Pos (1U) 2434 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 2435 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 2436 #define DMA_CCR_HTIE_Pos (2U) 2437 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 2438 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 2439 #define DMA_CCR_TEIE_Pos (3U) 2440 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 2441 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 2442 #define DMA_CCR_DIR_Pos (4U) 2443 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 2444 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 2445 #define DMA_CCR_CIRC_Pos (5U) 2446 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 2447 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 2448 #define DMA_CCR_PINC_Pos (6U) 2449 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 2450 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 2451 #define DMA_CCR_MINC_Pos (7U) 2452 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 2453 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 2454 2455 #define DMA_CCR_PSIZE_Pos (8U) 2456 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 2457 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 2458 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 2459 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 2460 2461 #define DMA_CCR_MSIZE_Pos (10U) 2462 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 2463 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 2464 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 2465 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 2466 2467 #define DMA_CCR_PL_Pos (12U) 2468 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 2469 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ 2470 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 2471 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 2472 2473 #define DMA_CCR_MEM2MEM_Pos (14U) 2474 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 2475 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 2476 2477 /****************** Bit definition for DMA_CNDTR register *******************/ 2478 #define DMA_CNDTR_NDT_Pos (0U) 2479 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 2480 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 2481 2482 /****************** Bit definition for DMA_CPAR register ********************/ 2483 #define DMA_CPAR_PA_Pos (0U) 2484 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 2485 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 2486 2487 /****************** Bit definition for DMA_CMAR register ********************/ 2488 #define DMA_CMAR_MA_Pos (0U) 2489 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 2490 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 2491 2492 /******************************************************************************/ 2493 /* */ 2494 /* DMAMUX Controller */ 2495 /* */ 2496 /******************************************************************************/ 2497 /******************** Bits definition for DMAMUX_CxCR register **************/ 2498 #define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) 2499 #define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */ 2500 #define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */ 2501 #define DMAMUX_CxCR_DMAREQ_ID_0 (0x01U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */ 2502 #define DMAMUX_CxCR_DMAREQ_ID_1 (0x02U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */ 2503 #define DMAMUX_CxCR_DMAREQ_ID_2 (0x04U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */ 2504 #define DMAMUX_CxCR_DMAREQ_ID_3 (0x08U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */ 2505 #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ 2506 #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ 2507 #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ 2508 #define DMAMUX_CxCR_DMAREQ_ID_7 (0x80U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ 2509 #define DMAMUX_CxCR_SOIE_Pos (8U) 2510 #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ 2511 #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ 2512 #define DMAMUX_CxCR_EGE_Pos (9U) 2513 #define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */ 2514 #define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */ 2515 #define DMAMUX_CxCR_SE_Pos (16U) 2516 #define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */ 2517 #define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */ 2518 #define DMAMUX_CxCR_SPOL_Pos (17U) 2519 #define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */ 2520 #define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */ 2521 #define DMAMUX_CxCR_SPOL_0 (0x1U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */ 2522 #define DMAMUX_CxCR_SPOL_1 (0x2U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */ 2523 #define DMAMUX_CxCR_NBREQ_Pos (19U) 2524 #define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */ 2525 #define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */ 2526 #define DMAMUX_CxCR_NBREQ_0 (0x01U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */ 2527 #define DMAMUX_CxCR_NBREQ_1 (0x02U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */ 2528 #define DMAMUX_CxCR_NBREQ_2 (0x04U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */ 2529 #define DMAMUX_CxCR_NBREQ_3 (0x08U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */ 2530 #define DMAMUX_CxCR_NBREQ_4 (0x10U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */ 2531 #define DMAMUX_CxCR_SYNC_ID_Pos (24U) 2532 #define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */ 2533 #define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */ 2534 #define DMAMUX_CxCR_SYNC_ID_0 (0x01U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */ 2535 #define DMAMUX_CxCR_SYNC_ID_1 (0x02U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */ 2536 #define DMAMUX_CxCR_SYNC_ID_2 (0x04U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */ 2537 #define DMAMUX_CxCR_SYNC_ID_3 (0x08U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */ 2538 #define DMAMUX_CxCR_SYNC_ID_4 (0x10U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */ 2539 2540 /******************* Bits definition for DMAMUX_CSR register **************/ 2541 #define DMAMUX_CSR_SOF0_Pos (0U) 2542 #define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */ 2543 #define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */ 2544 #define DMAMUX_CSR_SOF1_Pos (1U) 2545 #define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */ 2546 #define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */ 2547 #define DMAMUX_CSR_SOF2_Pos (2U) 2548 #define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */ 2549 #define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */ 2550 #define DMAMUX_CSR_SOF3_Pos (3U) 2551 #define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */ 2552 #define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */ 2553 #define DMAMUX_CSR_SOF4_Pos (4U) 2554 #define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */ 2555 #define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */ 2556 #define DMAMUX_CSR_SOF5_Pos (5U) 2557 #define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */ 2558 #define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Synchronization Overrun Flag 5 */ 2559 #define DMAMUX_CSR_SOF6_Pos (6U) 2560 #define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */ 2561 #define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */ 2562 #define DMAMUX_CSR_SOF7_Pos (7U) 2563 #define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */ 2564 #define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk /*!< Synchronization Overrun Flag 7 */ 2565 #define DMAMUX_CSR_SOF8_Pos (8U) 2566 #define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */ 2567 #define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk /*!< Synchronization Overrun Flag 8 */ 2568 #define DMAMUX_CSR_SOF9_Pos (9U) 2569 #define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */ 2570 #define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk /*!< Synchronization Overrun Flag 9 */ 2571 #define DMAMUX_CSR_SOF10_Pos (10U) 2572 #define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */ 2573 #define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk /*!< Synchronization Overrun Flag 10 */ 2574 #define DMAMUX_CSR_SOF11_Pos (11U) 2575 #define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */ 2576 #define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk /*!< Synchronization Overrun Flag 11 */ 2577 #define DMAMUX_CSR_SOF12_Pos (12U) 2578 #define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */ 2579 #define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk /*!< Synchronization Overrun Flag 12 */ 2580 #define DMAMUX_CSR_SOF13_Pos (13U) 2581 #define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */ 2582 #define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk /*!< Synchronization Overrun Flag 13 */ 2583 2584 /******************** Bits definition for DMAMUX_CFR register **************/ 2585 #define DMAMUX_CFR_CSOF0_Pos (0U) 2586 #define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */ 2587 #define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */ 2588 #define DMAMUX_CFR_CSOF1_Pos (1U) 2589 #define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */ 2590 #define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */ 2591 #define DMAMUX_CFR_CSOF2_Pos (2U) 2592 #define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */ 2593 #define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */ 2594 #define DMAMUX_CFR_CSOF3_Pos (3U) 2595 #define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */ 2596 #define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */ 2597 #define DMAMUX_CFR_CSOF4_Pos (4U) 2598 #define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */ 2599 #define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */ 2600 #define DMAMUX_CFR_CSOF5_Pos (5U) 2601 #define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */ 2602 #define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Clear Overrun Flag 5 */ 2603 #define DMAMUX_CFR_CSOF6_Pos (6U) 2604 #define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */ 2605 #define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */ 2606 #define DMAMUX_CFR_CSOF7_Pos (7U) 2607 #define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */ 2608 #define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk /*!< Clear Overrun Flag 7 */ 2609 #define DMAMUX_CFR_CSOF8_Pos (8U) 2610 #define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */ 2611 #define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk /*!< Clear Overrun Flag 8 */ 2612 #define DMAMUX_CFR_CSOF9_Pos (9U) 2613 #define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */ 2614 #define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk /*!< Clear Overrun Flag 9 */ 2615 #define DMAMUX_CFR_CSOF10_Pos (10U) 2616 #define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */ 2617 #define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk /*!< Clear Overrun Flag 10 */ 2618 #define DMAMUX_CFR_CSOF11_Pos (11U) 2619 #define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */ 2620 #define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk /*!< Clear Overrun Flag 11 */ 2621 #define DMAMUX_CFR_CSOF12_Pos (12U) 2622 #define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */ 2623 #define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk /*!< Clear Overrun Flag 12 */ 2624 #define DMAMUX_CFR_CSOF13_Pos (13U) 2625 #define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */ 2626 #define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk /*!< Clear Overrun Flag 13 */ 2627 2628 /******************** Bits definition for DMAMUX_RGxCR register ************/ 2629 #define DMAMUX_RGxCR_SIG_ID_Pos (0U) 2630 #define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */ 2631 #define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */ 2632 #define DMAMUX_RGxCR_SIG_ID_0 (0x01U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */ 2633 #define DMAMUX_RGxCR_SIG_ID_1 (0x02U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */ 2634 #define DMAMUX_RGxCR_SIG_ID_2 (0x04U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */ 2635 #define DMAMUX_RGxCR_SIG_ID_3 (0x08U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */ 2636 #define DMAMUX_RGxCR_SIG_ID_4 (0x10U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */ 2637 #define DMAMUX_RGxCR_OIE_Pos (8U) 2638 #define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */ 2639 #define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */ 2640 #define DMAMUX_RGxCR_GE_Pos (16U) 2641 #define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */ 2642 #define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */ 2643 #define DMAMUX_RGxCR_GPOL_Pos (17U) 2644 #define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */ 2645 #define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */ 2646 #define DMAMUX_RGxCR_GPOL_0 (0x1U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */ 2647 #define DMAMUX_RGxCR_GPOL_1 (0x2U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */ 2648 #define DMAMUX_RGxCR_GNBREQ_Pos (19U) 2649 #define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */ 2650 #define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */ 2651 #define DMAMUX_RGxCR_GNBREQ_0 (0x01U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */ 2652 #define DMAMUX_RGxCR_GNBREQ_1 (0x02U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */ 2653 #define DMAMUX_RGxCR_GNBREQ_2 (0x04U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */ 2654 #define DMAMUX_RGxCR_GNBREQ_3 (0x08U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */ 2655 #define DMAMUX_RGxCR_GNBREQ_4 (0x10U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */ 2656 2657 /******************** Bits definition for DMAMUX_RGSR register **************/ 2658 #define DMAMUX_RGSR_OF0_Pos (0U) 2659 #define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */ 2660 #define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */ 2661 #define DMAMUX_RGSR_OF1_Pos (1U) 2662 #define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */ 2663 #define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */ 2664 #define DMAMUX_RGSR_OF2_Pos (2U) 2665 #define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */ 2666 #define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */ 2667 #define DMAMUX_RGSR_OF3_Pos (3U) 2668 #define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */ 2669 #define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */ 2670 2671 /******************** Bits definition for DMAMUX_RGCFR register **************/ 2672 #define DMAMUX_RGCFR_COF0_Pos (0U) 2673 #define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */ 2674 #define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */ 2675 #define DMAMUX_RGCFR_COF1_Pos (1U) 2676 #define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */ 2677 #define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */ 2678 #define DMAMUX_RGCFR_COF2_Pos (2U) 2679 #define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */ 2680 #define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */ 2681 #define DMAMUX_RGCFR_COF3_Pos (3U) 2682 #define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ 2683 #define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ 2684 2685 /******************************************************************************/ 2686 /* */ 2687 /* External Interrupt/Event Controller */ 2688 /* */ 2689 /******************************************************************************/ 2690 2691 /****************** Bit definition for EXTI_RTSR1 register ******************/ 2692 #define EXTI_RTSR1_RT_Pos (0U) 2693 #define EXTI_RTSR1_RT_Msk (0x803FFFFFUL << EXTI_RTSR1_RT_Pos) /*!< 0x803FFFFF */ 2694 #define EXTI_RTSR1_RT EXTI_RTSR1_RT_Msk /*!< Rising trigger event configuration bit */ 2695 #define EXTI_RTSR1_RT0_Pos (0U) 2696 #define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ 2697 #define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */ 2698 #define EXTI_RTSR1_RT1_Pos (1U) 2699 #define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ 2700 #define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */ 2701 #define EXTI_RTSR1_RT2_Pos (2U) 2702 #define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ 2703 #define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */ 2704 #define EXTI_RTSR1_RT3_Pos (3U) 2705 #define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ 2706 #define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */ 2707 #define EXTI_RTSR1_RT4_Pos (4U) 2708 #define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ 2709 #define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */ 2710 #define EXTI_RTSR1_RT5_Pos (5U) 2711 #define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ 2712 #define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */ 2713 #define EXTI_RTSR1_RT6_Pos (6U) 2714 #define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ 2715 #define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */ 2716 #define EXTI_RTSR1_RT7_Pos (7U) 2717 #define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ 2718 #define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */ 2719 #define EXTI_RTSR1_RT8_Pos (8U) 2720 #define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ 2721 #define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */ 2722 #define EXTI_RTSR1_RT9_Pos (9U) 2723 #define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ 2724 #define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */ 2725 #define EXTI_RTSR1_RT10_Pos (10U) 2726 #define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ 2727 #define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */ 2728 #define EXTI_RTSR1_RT11_Pos (11U) 2729 #define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ 2730 #define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */ 2731 #define EXTI_RTSR1_RT12_Pos (12U) 2732 #define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ 2733 #define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */ 2734 #define EXTI_RTSR1_RT13_Pos (13U) 2735 #define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ 2736 #define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */ 2737 #define EXTI_RTSR1_RT14_Pos (14U) 2738 #define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ 2739 #define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */ 2740 #define EXTI_RTSR1_RT15_Pos (15U) 2741 #define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ 2742 #define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */ 2743 #define EXTI_RTSR1_RT16_Pos (16U) 2744 #define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ 2745 #define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ 2746 #define EXTI_RTSR1_RT17_Pos (17U) 2747 #define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */ 2748 #define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */ 2749 #define EXTI_RTSR1_RT18_Pos (18U) 2750 #define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */ 2751 #define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */ 2752 #define EXTI_RTSR1_RT19_Pos (19U) 2753 #define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */ 2754 #define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */ 2755 #define EXTI_RTSR1_RT20_Pos (20U) 2756 #define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */ 2757 #define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */ 2758 #define EXTI_RTSR1_RT21_Pos (21U) 2759 #define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */ 2760 #define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ 2761 #define EXTI_RTSR1_RT31_Pos (31U) 2762 #define EXTI_RTSR1_RT31_Msk (0x1UL << EXTI_RTSR1_RT31_Pos) /*!< 0x80000000 */ 2763 #define EXTI_RTSR1_RT31 EXTI_RTSR1_RT31_Msk /*!< Rising trigger event configuration bit of line 31 */ 2764 2765 /****************** Bit definition for EXTI_FTSR1 register ******************/ 2766 #define EXTI_FTSR1_FT_Pos (0U) 2767 #define EXTI_FTSR1_FT_Msk (0x803FFFFFUL << EXTI_FTSR1_FT_Pos) /*!< 0x803FFFFF */ 2768 #define EXTI_FTSR1_FT EXTI_FTSR1_FT_Msk /*!< Falling trigger event configuration bit */ 2769 #define EXTI_FTSR1_FT0_Pos (0U) 2770 #define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ 2771 #define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */ 2772 #define EXTI_FTSR1_FT1_Pos (1U) 2773 #define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ 2774 #define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */ 2775 #define EXTI_FTSR1_FT2_Pos (2U) 2776 #define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ 2777 #define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */ 2778 #define EXTI_FTSR1_FT3_Pos (3U) 2779 #define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ 2780 #define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */ 2781 #define EXTI_FTSR1_FT4_Pos (4U) 2782 #define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ 2783 #define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */ 2784 #define EXTI_FTSR1_FT5_Pos (5U) 2785 #define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ 2786 #define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */ 2787 #define EXTI_FTSR1_FT6_Pos (6U) 2788 #define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ 2789 #define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */ 2790 #define EXTI_FTSR1_FT7_Pos (7U) 2791 #define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ 2792 #define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */ 2793 #define EXTI_FTSR1_FT8_Pos (8U) 2794 #define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ 2795 #define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */ 2796 #define EXTI_FTSR1_FT9_Pos (9U) 2797 #define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ 2798 #define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */ 2799 #define EXTI_FTSR1_FT10_Pos (10U) 2800 #define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ 2801 #define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */ 2802 #define EXTI_FTSR1_FT11_Pos (11U) 2803 #define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ 2804 #define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */ 2805 #define EXTI_FTSR1_FT12_Pos (12U) 2806 #define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ 2807 #define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */ 2808 #define EXTI_FTSR1_FT13_Pos (13U) 2809 #define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ 2810 #define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */ 2811 #define EXTI_FTSR1_FT14_Pos (14U) 2812 #define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ 2813 #define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */ 2814 #define EXTI_FTSR1_FT15_Pos (15U) 2815 #define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ 2816 #define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */ 2817 #define EXTI_FTSR1_FT16_Pos (16U) 2818 #define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ 2819 #define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */ 2820 #define EXTI_FTSR1_FT17_Pos (17U) 2821 #define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */ 2822 #define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */ 2823 #define EXTI_FTSR1_FT18_Pos (18U) 2824 #define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */ 2825 #define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */ 2826 #define EXTI_FTSR1_FT19_Pos (19U) 2827 #define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */ 2828 #define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */ 2829 #define EXTI_FTSR1_FT20_Pos (20U) 2830 #define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */ 2831 #define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */ 2832 #define EXTI_FTSR1_FT21_Pos (21U) 2833 #define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */ 2834 #define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */ 2835 #define EXTI_FTSR1_FT31_Pos (31U) 2836 #define EXTI_FTSR1_FT31_Msk (0x1UL << EXTI_FTSR1_FT31_Pos) /*!< 0x80000000 */ 2837 #define EXTI_FTSR1_FT31 EXTI_FTSR1_FT31_Msk /*!< Falling trigger event configuration bit of line 31 */ 2838 2839 /****************** Bit definition for EXTI_SWIER1 register *****************/ 2840 #define EXTI_SWIER1_SWI_Pos (0U) 2841 #define EXTI_SWIER1_SWI_Msk (0x803FFFFFUL << EXTI_SWIER1_SWI_Pos) /*!< 0x803FFFFF */ 2842 #define EXTI_SWIER1_SWI EXTI_SWIER1_SWI_Msk /*!< Software interrupt */ 2843 #define EXTI_SWIER1_SWI0_Pos (0U) 2844 #define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ 2845 #define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ 2846 #define EXTI_SWIER1_SWI1_Pos (1U) 2847 #define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ 2848 #define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ 2849 #define EXTI_SWIER1_SWI2_Pos (2U) 2850 #define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ 2851 #define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ 2852 #define EXTI_SWIER1_SWI3_Pos (3U) 2853 #define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ 2854 #define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ 2855 #define EXTI_SWIER1_SWI4_Pos (4U) 2856 #define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ 2857 #define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ 2858 #define EXTI_SWIER1_SWI5_Pos (5U) 2859 #define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ 2860 #define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ 2861 #define EXTI_SWIER1_SWI6_Pos (6U) 2862 #define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ 2863 #define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ 2864 #define EXTI_SWIER1_SWI7_Pos (7U) 2865 #define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ 2866 #define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ 2867 #define EXTI_SWIER1_SWI8_Pos (8U) 2868 #define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ 2869 #define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ 2870 #define EXTI_SWIER1_SWI9_Pos (9U) 2871 #define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ 2872 #define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ 2873 #define EXTI_SWIER1_SWI10_Pos (10U) 2874 #define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ 2875 #define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ 2876 #define EXTI_SWIER1_SWI11_Pos (11U) 2877 #define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ 2878 #define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ 2879 #define EXTI_SWIER1_SWI12_Pos (12U) 2880 #define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ 2881 #define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ 2882 #define EXTI_SWIER1_SWI13_Pos (13U) 2883 #define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ 2884 #define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ 2885 #define EXTI_SWIER1_SWI14_Pos (14U) 2886 #define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ 2887 #define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ 2888 #define EXTI_SWIER1_SWI15_Pos (15U) 2889 #define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ 2890 #define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ 2891 #define EXTI_SWIER1_SWI16_Pos (16U) 2892 #define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ 2893 #define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */ 2894 #define EXTI_SWIER1_SWI17_Pos (17U) 2895 #define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */ 2896 #define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */ 2897 #define EXTI_SWIER1_SWI18_Pos (18U) 2898 #define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */ 2899 #define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */ 2900 #define EXTI_SWIER1_SWI19_Pos (19U) 2901 #define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */ 2902 #define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */ 2903 #define EXTI_SWIER1_SWI20_Pos (20U) 2904 #define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */ 2905 #define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */ 2906 #define EXTI_SWIER1_SWI21_Pos (21U) 2907 #define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */ 2908 #define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */ 2909 #define EXTI_SWIER1_SWI31_Pos (31U) 2910 #define EXTI_SWIER1_SWI31_Msk (0x1UL << EXTI_SWIER1_SWI31_Pos) /*!< 0x80000000 */ 2911 #define EXTI_SWIER1_SWI31 EXTI_SWIER1_SWI31_Msk /*!< Software Interrupt on line 31 */ 2912 2913 /******************* Bit definition for EXTI_PR1 register *******************/ 2914 #define EXTI_PR1_PIF_Pos (0U) 2915 #define EXTI_PR1_PIF_Msk (0x803FFFFFUL << EXTI_PR1_PIF_Pos) /*!< 0x803FFFFF */ 2916 #define EXTI_PR1_PIF EXTI_PR1_PIF_Msk /*!< Pending bit */ 2917 #define EXTI_PR1_PIF0_Pos (0U) 2918 #define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */ 2919 #define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */ 2920 #define EXTI_PR1_PIF1_Pos (1U) 2921 #define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */ 2922 #define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */ 2923 #define EXTI_PR1_PIF2_Pos (2U) 2924 #define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */ 2925 #define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */ 2926 #define EXTI_PR1_PIF3_Pos (3U) 2927 #define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */ 2928 #define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */ 2929 #define EXTI_PR1_PIF4_Pos (4U) 2930 #define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */ 2931 #define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */ 2932 #define EXTI_PR1_PIF5_Pos (5U) 2933 #define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */ 2934 #define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */ 2935 #define EXTI_PR1_PIF6_Pos (6U) 2936 #define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */ 2937 #define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */ 2938 #define EXTI_PR1_PIF7_Pos (7U) 2939 #define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */ 2940 #define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */ 2941 #define EXTI_PR1_PIF8_Pos (8U) 2942 #define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */ 2943 #define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */ 2944 #define EXTI_PR1_PIF9_Pos (9U) 2945 #define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */ 2946 #define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */ 2947 #define EXTI_PR1_PIF10_Pos (10U) 2948 #define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */ 2949 #define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */ 2950 #define EXTI_PR1_PIF11_Pos (11U) 2951 #define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */ 2952 #define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */ 2953 #define EXTI_PR1_PIF12_Pos (12U) 2954 #define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */ 2955 #define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */ 2956 #define EXTI_PR1_PIF13_Pos (13U) 2957 #define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */ 2958 #define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */ 2959 #define EXTI_PR1_PIF14_Pos (14U) 2960 #define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */ 2961 #define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */ 2962 #define EXTI_PR1_PIF15_Pos (15U) 2963 #define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */ 2964 #define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */ 2965 #define EXTI_PR1_PIF16_Pos (16U) 2966 #define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */ 2967 #define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */ 2968 #define EXTI_PR1_PIF17_Pos (17U) 2969 #define EXTI_PR1_PIF17_Msk (0x1UL << EXTI_PR1_PIF17_Pos) /*!< 0x00020000 */ 2970 #define EXTI_PR1_PIF17 EXTI_PR1_PIF17_Msk /*!< Pending bit for line 17 */ 2971 #define EXTI_PR1_PIF18_Pos (18U) 2972 #define EXTI_PR1_PIF18_Msk (0x1UL << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */ 2973 #define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */ 2974 #define EXTI_PR1_PIF19_Pos (19U) 2975 #define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */ 2976 #define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */ 2977 #define EXTI_PR1_PIF20_Pos (20U) 2978 #define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */ 2979 #define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */ 2980 #define EXTI_PR1_PIF21_Pos (21U) 2981 #define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */ 2982 #define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */ 2983 #define EXTI_PR1_PIF31_Pos (31U) 2984 #define EXTI_PR1_PIF31_Msk (0x1UL << EXTI_PR1_PIF31_Pos) /*!< 0x80000000 */ 2985 #define EXTI_PR1_PIF31 EXTI_PR1_PIF31_Msk /*!< Pending bit for line 31 */ 2986 2987 /****************** Bit definition for EXTI_RTSR2 register ******************/ 2988 #define EXTI_RTSR2_RT_Pos (0U) 2989 #define EXTI_RTSR2_RT_Msk (0x302UL << EXTI_RTSR2_RT_Pos) /*!< 0x00000302 */ 2990 #define EXTI_RTSR2_RT EXTI_RTSR2_RT_Msk /*!< Rising trigger event configuration bit */ 2991 #define EXTI_RTSR2_RT33_Pos (1U) 2992 #define EXTI_RTSR2_RT33_Msk (0x1UL << EXTI_RTSR2_RT33_Pos) /*!< 0x00000002 */ 2993 #define EXTI_RTSR2_RT33 EXTI_RTSR2_RT33_Msk /*!< Rising trigger event configuration bit of line 33 */ 2994 #define EXTI_RTSR2_RT40_Pos (8U) 2995 #define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos) /*!< 0x00000100 */ 2996 #define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk /*!< Rising trigger event configuration bit of line 40 */ 2997 #define EXTI_RTSR2_RT41_Pos (9U) 2998 #define EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos) /*!< 0x00000200 */ 2999 #define EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk /*!< Rising trigger event configuration bit of line 41 */ 3000 3001 /****************** Bit definition for EXTI_FTSR2 register ******************/ 3002 #define EXTI_FTSR2_FT_Pos (0U) 3003 #define EXTI_FTSR2_FT_Msk (0x302UL << EXTI_FTSR2_FT_Pos) /*!< 0x00000302 */ 3004 #define EXTI_FTSR2_FT EXTI_FTSR2_FT_Msk /*!< Falling trigger event configuration bit */ 3005 #define EXTI_FTSR2_FT33_Pos (1U) 3006 #define EXTI_FTSR2_FT33_Msk (0x1UL << EXTI_FTSR2_FT33_Pos) /*!< 0x00000002 */ 3007 #define EXTI_FTSR2_FT33 EXTI_FTSR2_FT33_Msk /*!< Falling trigger event configuration bit of line 33 */ 3008 #define EXTI_FTSR2_FT40_Pos (8U) 3009 #define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos) /*!< 0x00000100 */ 3010 #define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk /*!< Falling trigger event configuration bit of line 40 */ 3011 #define EXTI_FTSR2_FT41_Pos (9U) 3012 #define EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos) /*!< 0x00000200 */ 3013 #define EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk /*!< Falling trigger event configuration bit of line 41 */ 3014 3015 /****************** Bit definition for EXTI_SWIER2 register *****************/ 3016 #define EXTI_SWIER2_SWI_Pos (0U) 3017 #define EXTI_SWIER2_SWI_Msk (0x302UL << EXTI_SWIER2_SWI_Pos) /*!< 0x00000302 */ 3018 #define EXTI_SWIER2_SWI EXTI_SWIER2_SWI_Msk /*!< Falling trigger event configuration bit */ 3019 #define EXTI_SWIER2_SWI33_Pos (1U) 3020 #define EXTI_SWIER2_SWI33_Msk (0x1UL << EXTI_SWIER2_SWI33_Pos) /*!< 0x00000002 */ 3021 #define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWI33_Msk /*!< Software Interrupt on line 33 */ 3022 #define EXTI_SWIER2_SWI40_Pos (8U) 3023 #define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos) /*!< 0x00000100 */ 3024 #define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk /*!< Software Interrupt on line 40 */ 3025 #define EXTI_SWIER2_SWI41_Pos (9U) 3026 #define EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos) /*!< 0x00000200 */ 3027 #define EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk /*!< Software Interrupt on line 41 */ 3028 3029 /******************* Bit definition for EXTI_PR2 register *******************/ 3030 #define EXTI_PR2_PIF_Pos (0U) 3031 #define EXTI_PR2_PIF_Msk (0x302UL << EXTI_PR2_PIF_Pos) /*!< 0x00000302 */ 3032 #define EXTI_PR2_PIF EXTI_PR2_PIF_Msk /*!< Pending bit */ 3033 #define EXTI_PR2_PIF33_Pos (1U) 3034 #define EXTI_PR2_PIF33_Msk (0x1UL << EXTI_PR2_PIF33_Pos) /*!< 0x00000002 */ 3035 #define EXTI_PR2_PIF33 EXTI_PR2_PIF33_Msk /*!< Pending bit for line 33 */ 3036 #define EXTI_PR2_PIF40_Pos (8U) 3037 #define EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos) /*!< 0x00000100 */ 3038 #define EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk /*!< Pending bit for line 40 */ 3039 #define EXTI_PR2_PIF41_Pos (9U) 3040 #define EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos) /*!< 0x00000200 */ 3041 #define EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk /*!< Pending bit for line 41 */ 3042 3043 /******************** Bits definition for EXTI_IMR1 register ****************/ 3044 #define EXTI_IMR1_Pos (0U) 3045 #define EXTI_IMR1_Msk (0xFFFFFFFFUL << EXTI_IMR1_Pos) /*!< 0xFFFFFFFF */ 3046 #define EXTI_IMR1_IM EXTI_IMR1_Msk /*!< CPU1 wakeup with interrupt Mask on Event */ 3047 #define EXTI_IMR1_IM0_Pos (0U) 3048 #define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ 3049 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< CPU1 Interrupt Mask on line 0 */ 3050 #define EXTI_IMR1_IM1_Pos (1U) 3051 #define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ 3052 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< CPU1 Interrupt Mask on line 1 */ 3053 #define EXTI_IMR1_IM2_Pos (2U) 3054 #define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ 3055 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< CPU1 Interrupt Mask on line 2 */ 3056 #define EXTI_IMR1_IM3_Pos (3U) 3057 #define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ 3058 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< CPU1 Interrupt Mask on line 3 */ 3059 #define EXTI_IMR1_IM4_Pos (4U) 3060 #define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ 3061 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< CPU1 Interrupt Mask on line 4 */ 3062 #define EXTI_IMR1_IM5_Pos (5U) 3063 #define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ 3064 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< CPU1 Interrupt Mask on line 5 */ 3065 #define EXTI_IMR1_IM6_Pos (6U) 3066 #define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ 3067 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< CPU1 Interrupt Mask on line 6 */ 3068 #define EXTI_IMR1_IM7_Pos (7U) 3069 #define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ 3070 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< CPU1 Interrupt Mask on line 7 */ 3071 #define EXTI_IMR1_IM8_Pos (8U) 3072 #define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ 3073 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< CPU1 Interrupt Mask on line 8 */ 3074 #define EXTI_IMR1_IM9_Pos (9U) 3075 #define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ 3076 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< CPU1 Interrupt Mask on line 9 */ 3077 #define EXTI_IMR1_IM10_Pos (10U) 3078 #define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ 3079 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< CPU1 Interrupt Mask on line 10 */ 3080 #define EXTI_IMR1_IM11_Pos (11U) 3081 #define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ 3082 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< CPU1 Interrupt Mask on line 11 */ 3083 #define EXTI_IMR1_IM12_Pos (12U) 3084 #define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ 3085 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< CPU1 Interrupt Mask on line 12 */ 3086 #define EXTI_IMR1_IM13_Pos (13U) 3087 #define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ 3088 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< CPU1 Interrupt Mask on line 13 */ 3089 #define EXTI_IMR1_IM14_Pos (14U) 3090 #define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ 3091 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< CPU1 Interrupt Mask on line 14 */ 3092 #define EXTI_IMR1_IM15_Pos (15U) 3093 #define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ 3094 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< CPU1 Interrupt Mask on line 15 */ 3095 #define EXTI_IMR1_IM16_Pos (16U) 3096 #define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ 3097 #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< CPU1 Interrupt Mask on line 16 */ 3098 #define EXTI_IMR1_IM17_Pos (17U) 3099 #define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ 3100 #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< CPU1 Interrupt Mask on line 17 */ 3101 #define EXTI_IMR1_IM18_Pos (18U) 3102 #define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ 3103 #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< CPU1 Interrupt Mask on line 18 */ 3104 #define EXTI_IMR1_IM19_Pos (19U) 3105 #define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ 3106 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< CPU1 Interrupt Mask on line 19 */ 3107 #define EXTI_IMR1_IM20_Pos (20U) 3108 #define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ 3109 #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< CPU1 Interrupt Mask on line 20 */ 3110 #define EXTI_IMR1_IM21_Pos (21U) 3111 #define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ 3112 #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< CPU1 Interrupt Mask on line 21 */ 3113 #define EXTI_IMR1_IM22_Pos (22U) 3114 #define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ 3115 #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< CPU1 Interrupt Mask on line 22 */ 3116 #define EXTI_IMR1_IM23_Pos (23U) 3117 #define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ 3118 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< CPU1 Interrupt Mask on line 23 */ 3119 #define EXTI_IMR1_IM24_Pos (24U) 3120 #define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ 3121 #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< CPU1 Interrupt Mask on line 24 */ 3122 #define EXTI_IMR1_IM25_Pos (25U) 3123 #define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ 3124 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< CPU1 Interrupt Mask on line 25 */ 3125 #define EXTI_IMR1_IM28_Pos (28U) 3126 #define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ 3127 #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< CPU1 Interrupt Mask on line 28 */ 3128 #define EXTI_IMR1_IM29_Pos (29U) 3129 #define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ 3130 #define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< CPU1 Interrupt Mask on line 29 */ 3131 #define EXTI_IMR1_IM30_Pos (30U) 3132 #define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ 3133 #define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< CPU1 Interrupt Mask on line 30 */ 3134 #define EXTI_IMR1_IM31_Pos (31U) 3135 #define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ 3136 #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< CPU1 Interrupt Mask on line 31 */ 3137 3138 /******************** Bits definition for EXTI_EMR1 register ****************/ 3139 #define EXTI_EMR1_Pos (0U) 3140 #define EXTI_EMR1_Msk (0x003EFFFFUL << EXTI_EMR1_Pos) /*!< 0xFFFFFFFF */ 3141 #define EXTI_EMR1_EM EXTI_EMR1_Msk /*!< CPU1 Event Mask */ 3142 #define EXTI_EMR1_EM0_Pos (0U) 3143 #define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ 3144 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< CPU1 Event Mask on line 0 */ 3145 #define EXTI_EMR1_EM1_Pos (1U) 3146 #define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ 3147 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< CPU1 Event Mask on line 1 */ 3148 #define EXTI_EMR1_EM2_Pos (2U) 3149 #define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ 3150 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< CPU1 Event Mask on line 2 */ 3151 #define EXTI_EMR1_EM3_Pos (3U) 3152 #define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ 3153 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< CPU1 Event Mask on line 3 */ 3154 #define EXTI_EMR1_EM4_Pos (4U) 3155 #define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ 3156 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< CPU1 Event Mask on line 4 */ 3157 #define EXTI_EMR1_EM5_Pos (5U) 3158 #define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ 3159 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< CPU1 Event Mask on line 5 */ 3160 #define EXTI_EMR1_EM6_Pos (6U) 3161 #define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ 3162 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< CPU1 Event Mask on line 6 */ 3163 #define EXTI_EMR1_EM7_Pos (7U) 3164 #define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ 3165 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< CPU1 Event Mask on line 7 */ 3166 #define EXTI_EMR1_EM8_Pos (8U) 3167 #define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ 3168 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< CPU1 Event Mask on line 8 */ 3169 #define EXTI_EMR1_EM9_Pos (9U) 3170 #define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ 3171 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< CPU1 Event Mask on line 9 */ 3172 #define EXTI_EMR1_EM10_Pos (10U) 3173 #define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ 3174 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< CPU1 Event Mask on line 10 */ 3175 #define EXTI_EMR1_EM11_Pos (11U) 3176 #define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ 3177 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< CPU1 Event Mask on line 11 */ 3178 #define EXTI_EMR1_EM12_Pos (12U) 3179 #define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ 3180 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< CPU1 Event Mask on line 12 */ 3181 #define EXTI_EMR1_EM13_Pos (13U) 3182 #define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ 3183 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< CPU1 Event Mask on line 13 */ 3184 #define EXTI_EMR1_EM14_Pos (14U) 3185 #define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ 3186 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< CPU1 Event Mask on line 14 */ 3187 #define EXTI_EMR1_EM15_Pos (15U) 3188 #define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ 3189 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< CPU1 Event Mask on line 15 */ 3190 #define EXTI_EMR1_EM17_Pos (17U) 3191 #define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ 3192 #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< CPU1 Event Mask on line 17 */ 3193 #define EXTI_EMR1_EM18_Pos (18U) 3194 #define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ 3195 #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< CPU1 Event Mask on line 18 */ 3196 #define EXTI_EMR1_EM19_Pos (19U) 3197 #define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ 3198 #define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< CPU1 Event Mask on line 19 */ 3199 #define EXTI_EMR1_EM20_Pos (20U) 3200 #define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */ 3201 #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< CPU1 Event Mask on line 20 */ 3202 #define EXTI_EMR1_EM21_Pos (21U) 3203 #define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ 3204 #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< CPU1 Event Mask on line 21 */ 3205 3206 /******************** Bits definition for EXTI_IMR2 register ****************/ 3207 #define EXTI_IMR2_Pos (0U) 3208 #define EXTI_IMR2_Msk (0x0001FFFFUL << EXTI_IMR2_Pos) /*!< 0x0001FFFF */ 3209 #define EXTI_IMR2_IM EXTI_IMR2_Msk /*!< CPU1 Interrupt Mask */ 3210 #define EXTI_IMR2_IM33_Pos (1U) 3211 #define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ 3212 #define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< CPU1 Interrupt Mask on line 33 */ 3213 #define EXTI_IMR2_IM36_Pos (4U) 3214 #define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */ 3215 #define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< CPU1 Interrupt Mask on line 36 */ 3216 #define EXTI_IMR2_IM37_Pos (5U) 3217 #define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */ 3218 #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< CPU1 Interrupt Mask on line 37 */ 3219 #define EXTI_IMR2_IM38_Pos (6U) 3220 #define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */ 3221 #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< CPU1 Interrupt Mask on line 38 */ 3222 #define EXTI_IMR2_IM39_Pos (7U) 3223 #define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */ 3224 #define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< CPU1 Interrupt Mask on line 39 */ 3225 #define EXTI_IMR2_IM40_Pos (8U) 3226 #define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */ 3227 #define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< CPU1 Interrupt Mask on line 40 */ 3228 #define EXTI_IMR2_IM41_Pos (9U) 3229 #define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */ 3230 #define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< CPU1 Interrupt Mask on line 41 */ 3231 #define EXTI_IMR2_IM42_Pos (10U) 3232 #define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */ 3233 #define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< CPU1 Interrupt Mask on line 42 */ 3234 #define EXTI_IMR2_IM44_Pos (12U) 3235 #define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */ 3236 #define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< CPU1 Interrupt Mask on line 44 */ 3237 #define EXTI_IMR2_IM45_Pos (13U) 3238 #define EXTI_IMR2_IM45_Msk (0x1UL << EXTI_IMR2_IM45_Pos) /*!< 0x00002000 */ 3239 #define EXTI_IMR2_IM45 EXTI_IMR2_IM45_Msk /*!< CPU1 Interrupt Mask on line 45 */ 3240 #define EXTI_IMR2_IM46_Pos (14U) 3241 #define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */ 3242 #define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< CPU1 Interrupt Mask on line 46 */ 3243 #define EXTI_IMR2_IM48_Pos (16U) 3244 #define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */ 3245 #define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< CPU1 Interrupt Mask on line 48 */ 3246 3247 /******************** Bits definition for EXTI_EMR2 register ****************/ 3248 #define EXTI_EMR2_Pos (0U) 3249 #define EXTI_EMR2_Msk (0x00000300UL << EXTI_EMR2_Pos) /*!< 0x000003000 */ 3250 #define EXTI_EMR2_EM EXTI_EMR2_Msk /*!< CPU1 Interrupt Mask */ 3251 #define EXTI_EMR2_EM40_Pos (8U) 3252 #define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */ 3253 #define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< CPU1 Event Mask on line 40 */ 3254 #define EXTI_EMR2_EM41_Pos (9U) 3255 #define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */ 3256 #define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< CPU1 Event Mask on line 41 */ 3257 3258 /******************** Bits definition for EXTI_C2IMR1 register **************/ 3259 #define EXTI_C2IMR1_Pos (0U) 3260 #define EXTI_C2IMR1_Msk (0xFFFFFFFFUL << EXTI_C2IMR1_Pos) /*!< 0xFFFFFFFF */ 3261 #define EXTI_C2IMR1_IM EXTI_C2IMR1_Msk /*!< CPU2 wakeup with interrupt Mask on Event */ 3262 #define EXTI_C2IMR1_IM0_Pos (0U) 3263 #define EXTI_C2IMR1_IM0_Msk (0x1UL << EXTI_C2IMR1_IM0_Pos) /*!< 0x00000001 */ 3264 #define EXTI_C2IMR1_IM0 EXTI_C2IMR1_IM0_Msk /*!< CPU2 Interrupt Mask on line 0 */ 3265 #define EXTI_C2IMR1_IM1_Pos (1U) 3266 #define EXTI_C2IMR1_IM1_Msk (0x1UL << EXTI_C2IMR1_IM1_Pos) /*!< 0x00000002 */ 3267 #define EXTI_C2IMR1_IM1 EXTI_C2IMR1_IM1_Msk /*!< CPU2 Interrupt Mask on line 1 */ 3268 #define EXTI_C2IMR1_IM2_Pos (2U) 3269 #define EXTI_C2IMR1_IM2_Msk (0x1UL << EXTI_C2IMR1_IM2_Pos) /*!< 0x00000004 */ 3270 #define EXTI_C2IMR1_IM2 EXTI_C2IMR1_IM2_Msk /*!< CPU2 Interrupt Mask on line 2 */ 3271 #define EXTI_C2IMR1_IM3_Pos (3U) 3272 #define EXTI_C2IMR1_IM3_Msk (0x1UL << EXTI_C2IMR1_IM3_Pos) /*!< 0x00000008 */ 3273 #define EXTI_C2IMR1_IM3 EXTI_C2IMR1_IM3_Msk /*!< CPU2 Interrupt Mask on line 3 */ 3274 #define EXTI_C2IMR1_IM4_Pos (4U) 3275 #define EXTI_C2IMR1_IM4_Msk (0x1UL << EXTI_C2IMR1_IM4_Pos) /*!< 0x00000010 */ 3276 #define EXTI_C2IMR1_IM4 EXTI_C2IMR1_IM4_Msk /*!< CPU2 Interrupt Mask on line 4 */ 3277 #define EXTI_C2IMR1_IM5_Pos (5U) 3278 #define EXTI_C2IMR1_IM5_Msk (0x1UL << EXTI_C2IMR1_IM5_Pos) /*!< 0x00000020 */ 3279 #define EXTI_C2IMR1_IM5 EXTI_C2IMR1_IM5_Msk /*!< CPU2 Interrupt Mask on line 5 */ 3280 #define EXTI_C2IMR1_IM6_Pos (6U) 3281 #define EXTI_C2IMR1_IM6_Msk (0x1UL << EXTI_C2IMR1_IM6_Pos) /*!< 0x00000040 */ 3282 #define EXTI_C2IMR1_IM6 EXTI_C2IMR1_IM6_Msk /*!< CPU2 Interrupt Mask on line 6 */ 3283 #define EXTI_C2IMR1_IM7_Pos (7U) 3284 #define EXTI_C2IMR1_IM7_Msk (0x1UL << EXTI_C2IMR1_IM7_Pos) /*!< 0x00000080 */ 3285 #define EXTI_C2IMR1_IM7 EXTI_C2IMR1_IM7_Msk /*!< CPU2 Interrupt Mask on line 7 */ 3286 #define EXTI_C2IMR1_IM8_Pos (8U) 3287 #define EXTI_C2IMR1_IM8_Msk (0x1UL << EXTI_C2IMR1_IM8_Pos) /*!< 0x00000100 */ 3288 #define EXTI_C2IMR1_IM8 EXTI_C2IMR1_IM8_Msk /*!< CPU2 Interrupt Mask on line 8 */ 3289 #define EXTI_C2IMR1_IM9_Pos (9U) 3290 #define EXTI_C2IMR1_IM9_Msk (0x1UL << EXTI_C2IMR1_IM9_Pos) /*!< 0x00000200 */ 3291 #define EXTI_C2IMR1_IM9 EXTI_C2IMR1_IM9_Msk /*!< CPU2 Interrupt Mask on line 9 */ 3292 #define EXTI_C2IMR1_IM10_Pos (10U) 3293 #define EXTI_C2IMR1_IM10_Msk (0x1UL << EXTI_C2IMR1_IM10_Pos) /*!< 0x00000400 */ 3294 #define EXTI_C2IMR1_IM10 EXTI_C2IMR1_IM10_Msk /*!< CPU2 Interrupt Mask on line 10 */ 3295 #define EXTI_C2IMR1_IM11_Pos (11U) 3296 #define EXTI_C2IMR1_IM11_Msk (0x1UL << EXTI_C2IMR1_IM11_Pos) /*!< 0x00000800 */ 3297 #define EXTI_C2IMR1_IM11 EXTI_C2IMR1_IM11_Msk /*!< CPU2 Interrupt Mask on line 11 */ 3298 #define EXTI_C2IMR1_IM12_Pos (12U) 3299 #define EXTI_C2IMR1_IM12_Msk (0x1UL << EXTI_C2IMR1_IM12_Pos) /*!< 0x00001000 */ 3300 #define EXTI_C2IMR1_IM12 EXTI_C2IMR1_IM12_Msk /*!< CPU2 Interrupt Mask on line 12 */ 3301 #define EXTI_C2IMR1_IM13_Pos (13U) 3302 #define EXTI_C2IMR1_IM13_Msk (0x1UL << EXTI_C2IMR1_IM13_Pos) /*!< 0x00002000 */ 3303 #define EXTI_C2IMR1_IM13 EXTI_C2IMR1_IM13_Msk /*!< CPU2 Interrupt Mask on line 13 */ 3304 #define EXTI_C2IMR1_IM14_Pos (14U) 3305 #define EXTI_C2IMR1_IM14_Msk (0x1UL << EXTI_C2IMR1_IM14_Pos) /*!< 0x00004000 */ 3306 #define EXTI_C2IMR1_IM14 EXTI_C2IMR1_IM14_Msk /*!< CPU2 Interrupt Mask on line 14 */ 3307 #define EXTI_C2IMR1_IM15_Pos (15U) 3308 #define EXTI_C2IMR1_IM15_Msk (0x1UL << EXTI_C2IMR1_IM15_Pos) /*!< 0x00008000 */ 3309 #define EXTI_C2IMR1_IM15 EXTI_C2IMR1_IM15_Msk /*!< CPU2 Interrupt Mask on line 15 */ 3310 #define EXTI_C2IMR1_IM16_Pos (16U) 3311 #define EXTI_C2IMR1_IM16_Msk (0x1UL << EXTI_C2IMR1_IM16_Pos) /*!< 0x00010000 */ 3312 #define EXTI_C2IMR1_IM16 EXTI_C2IMR1_IM16_Msk /*!< CPU2 Interrupt Mask on line 16 */ 3313 #define EXTI_C2IMR1_IM17_Pos (17U) 3314 #define EXTI_C2IMR1_IM17_Msk (0x1UL << EXTI_C2IMR1_IM17_Pos) /*!< 0x00020000 */ 3315 #define EXTI_C2IMR1_IM17 EXTI_C2IMR1_IM17_Msk /*!< CPU2 Interrupt Mask on line 17 */ 3316 #define EXTI_C2IMR1_IM18_Pos (18U) 3317 #define EXTI_C2IMR1_IM18_Msk (0x1UL << EXTI_C2IMR1_IM18_Pos) /*!< 0x00040000 */ 3318 #define EXTI_C2IMR1_IM18 EXTI_C2IMR1_IM18_Msk /*!< CPU2 Interrupt Mask on line 18 */ 3319 #define EXTI_C2IMR1_IM19_Pos (19U) 3320 #define EXTI_C2IMR1_IM19_Msk (0x1UL << EXTI_C2IMR1_IM19_Pos) /*!< 0x00080000 */ 3321 #define EXTI_C2IMR1_IM19 EXTI_C2IMR1_IM19_Msk /*!< CPU2 Interrupt Mask on line 19 */ 3322 #define EXTI_C2IMR1_IM20_Pos (20U) 3323 #define EXTI_C2IMR1_IM20_Msk (0x1UL << EXTI_C2IMR1_IM20_Pos) /*!< 0x00100000 */ 3324 #define EXTI_C2IMR1_IM20 EXTI_C2IMR1_IM20_Msk /*!< CPU2 Interrupt Mask on line 20 */ 3325 #define EXTI_C2IMR1_IM21_Pos (21U) 3326 #define EXTI_C2IMR1_IM21_Msk (0x1UL << EXTI_C2IMR1_IM21_Pos) /*!< 0x00200000 */ 3327 #define EXTI_C2IMR1_IM21 EXTI_C2IMR1_IM21_Msk /*!< CPU2 Interrupt Mask on line 21 */ 3328 #define EXTI_C2IMR1_IM22_Pos (22U) 3329 #define EXTI_C2IMR1_IM22_Msk (0x1UL << EXTI_C2IMR1_IM22_Pos) /*!< 0x00400000 */ 3330 #define EXTI_C2IMR1_IM22 EXTI_C2IMR1_IM22_Msk /*!< CPU2 Interrupt Mask on line 22 */ 3331 #define EXTI_C2IMR1_IM23_Pos (23U) 3332 #define EXTI_C2IMR1_IM23_Msk (0x1UL << EXTI_C2IMR1_IM23_Pos) /*!< 0x00800000 */ 3333 #define EXTI_C2IMR1_IM23 EXTI_C2IMR1_IM23_Msk /*!< CPU2 Interrupt Mask on line 23 */ 3334 #define EXTI_C2IMR1_IM24_Pos (24U) 3335 #define EXTI_C2IMR1_IM24_Msk (0x1UL << EXTI_C2IMR1_IM24_Pos) /*!< 0x01000000 */ 3336 #define EXTI_C2IMR1_IM24 EXTI_C2IMR1_IM24_Msk /*!< CPU2 Interrupt Mask on line 24 */ 3337 #define EXTI_C2IMR1_IM25_Pos (25U) 3338 #define EXTI_C2IMR1_IM25_Msk (0x1UL << EXTI_C2IMR1_IM25_Pos) /*!< 0x02000000 */ 3339 #define EXTI_C2IMR1_IM25 EXTI_C2IMR1_IM25_Msk /*!< CPU2 Interrupt Mask on line 25 */ 3340 #define EXTI_C2IMR1_IM28_Pos (28U) 3341 #define EXTI_C2IMR1_IM28_Msk (0x1UL << EXTI_C2IMR1_IM28_Pos) /*!< 0x10000000 */ 3342 #define EXTI_C2IMR1_IM28 EXTI_C2IMR1_IM28_Msk /*!< CPU2 Interrupt Mask on line 28 */ 3343 #define EXTI_C2IMR1_IM29_Pos (29U) 3344 #define EXTI_C2IMR1_IM29_Msk (0x1UL << EXTI_C2IMR1_IM29_Pos) /*!< 0x20000000 */ 3345 #define EXTI_C2IMR1_IM29 EXTI_C2IMR1_IM29_Msk /*!< CPU2 Interrupt Mask on line 29 */ 3346 #define EXTI_C2IMR1_IM30_Pos (30U) 3347 #define EXTI_C2IMR1_IM30_Msk (0x1UL << EXTI_C2IMR1_IM30_Pos) /*!< 0x40000000 */ 3348 #define EXTI_C2IMR1_IM30 EXTI_C2IMR1_IM30_Msk /*!< CPU2 Interrupt Mask on line 30 */ 3349 #define EXTI_C2IMR1_IM31_Pos (31U) 3350 #define EXTI_C2IMR1_IM31_Msk (0x1UL << EXTI_C2IMR1_IM31_Pos) /*!< 0x80000000 */ 3351 #define EXTI_C2IMR1_IM31 EXTI_C2IMR1_IM31_Msk /*!< CPU2 Interrupt Mask on line 31 */ 3352 3353 /******************** Bits definition for EXTI_C2EMR1 register **************/ 3354 #define EXTI_C2EMR1_Pos (0U) 3355 #define EXTI_C2EMR1_Msk (0x003EFFFFUL << EXTI_C2EMR1_Pos) /*!< 0xFFFFFFFF */ 3356 #define EXTI_C2EMR1_EM EXTI_C2EMR1_Msk /*!< CPU2 Event Mask */ 3357 #define EXTI_C2EMR1_EM0_Pos (0U) 3358 #define EXTI_C2EMR1_EM0_Msk (0x1UL << EXTI_C2EMR1_EM0_Pos) /*!< 0x00000001 */ 3359 #define EXTI_C2EMR1_EM0 EXTI_C2EMR1_EM0_Msk /*!< CPU2 Event Mask on line 0 */ 3360 #define EXTI_C2EMR1_EM1_Pos (1U) 3361 #define EXTI_C2EMR1_EM1_Msk (0x1UL << EXTI_C2EMR1_EM1_Pos) /*!< 0x00000002 */ 3362 #define EXTI_C2EMR1_EM1 EXTI_C2EMR1_EM1_Msk /*!< CPU2 Event Mask on line 1 */ 3363 #define EXTI_C2EMR1_EM2_Pos (2U) 3364 #define EXTI_C2EMR1_EM2_Msk (0x1UL << EXTI_C2EMR1_EM2_Pos) /*!< 0x00000004 */ 3365 #define EXTI_C2EMR1_EM2 EXTI_C2EMR1_EM2_Msk /*!< CPU2 Event Mask on line 2 */ 3366 #define EXTI_C2EMR1_EM3_Pos (3U) 3367 #define EXTI_C2EMR1_EM3_Msk (0x1UL << EXTI_C2EMR1_EM3_Pos) /*!< 0x00000008 */ 3368 #define EXTI_C2EMR1_EM3 EXTI_C2EMR1_EM3_Msk /*!< CPU2 Event Mask on line 3 */ 3369 #define EXTI_C2EMR1_EM4_Pos (4U) 3370 #define EXTI_C2EMR1_EM4_Msk (0x1UL << EXTI_C2EMR1_EM4_Pos) /*!< 0x00000010 */ 3371 #define EXTI_C2EMR1_EM4 EXTI_C2EMR1_EM4_Msk /*!< CPU2 Event Mask on line 4 */ 3372 #define EXTI_C2EMR1_EM5_Pos (5U) 3373 #define EXTI_C2EMR1_EM5_Msk (0x1UL << EXTI_C2EMR1_EM5_Pos) /*!< 0x00000020 */ 3374 #define EXTI_C2EMR1_EM5 EXTI_C2EMR1_EM5_Msk /*!< CPU2 Event Mask on line 5 */ 3375 #define EXTI_C2EMR1_EM6_Pos (6U) 3376 #define EXTI_C2EMR1_EM6_Msk (0x1UL << EXTI_C2EMR1_EM6_Pos) /*!< 0x00000040 */ 3377 #define EXTI_C2EMR1_EM6 EXTI_C2EMR1_EM6_Msk /*!< CPU2 Event Mask on line 6 */ 3378 #define EXTI_C2EMR1_EM7_Pos (7U) 3379 #define EXTI_C2EMR1_EM7_Msk (0x1UL << EXTI_C2EMR1_EM7_Pos) /*!< 0x00000080 */ 3380 #define EXTI_C2EMR1_EM7 EXTI_C2EMR1_EM7_Msk /*!< CPU2 Event Mask on line 7 */ 3381 #define EXTI_C2EMR1_EM8_Pos (8U) 3382 #define EXTI_C2EMR1_EM8_Msk (0x1UL << EXTI_C2EMR1_EM8_Pos) /*!< 0x00000100 */ 3383 #define EXTI_C2EMR1_EM8 EXTI_C2EMR1_EM8_Msk /*!< CPU2 Event Mask on line 8 */ 3384 #define EXTI_C2EMR1_EM9_Pos (9U) 3385 #define EXTI_C2EMR1_EM9_Msk (0x1UL << EXTI_C2EMR1_EM9_Pos) /*!< 0x00000200 */ 3386 #define EXTI_C2EMR1_EM9 EXTI_C2EMR1_EM9_Msk /*!< CPU2 Event Mask on line 9 */ 3387 #define EXTI_C2EMR1_EM10_Pos (10U) 3388 #define EXTI_C2EMR1_EM10_Msk (0x1UL << EXTI_C2EMR1_EM10_Pos) /*!< 0x00000400 */ 3389 #define EXTI_C2EMR1_EM10 EXTI_C2EMR1_EM10_Msk /*!< CPU2 Event Mask on line 10 */ 3390 #define EXTI_C2EMR1_EM11_Pos (11U) 3391 #define EXTI_C2EMR1_EM11_Msk (0x1UL << EXTI_C2EMR1_EM11_Pos) /*!< 0x00000800 */ 3392 #define EXTI_C2EMR1_EM11 EXTI_C2EMR1_EM11_Msk /*!< CPU2 Event Mask on line 11 */ 3393 #define EXTI_C2EMR1_EM12_Pos (12U) 3394 #define EXTI_C2EMR1_EM12_Msk (0x1UL << EXTI_C2EMR1_EM12_Pos) /*!< 0x00001000 */ 3395 #define EXTI_C2EMR1_EM12 EXTI_C2EMR1_EM12_Msk /*!< CPU2 Event Mask on line 12 */ 3396 #define EXTI_C2EMR1_EM13_Pos (13U) 3397 #define EXTI_C2EMR1_EM13_Msk (0x1UL << EXTI_C2EMR1_EM13_Pos) /*!< 0x00002000 */ 3398 #define EXTI_C2EMR1_EM13 EXTI_C2EMR1_EM13_Msk /*!< CPU2 Event Mask on line 13 */ 3399 #define EXTI_C2EMR1_EM14_Pos (14U) 3400 #define EXTI_C2EMR1_EM14_Msk (0x1UL << EXTI_C2EMR1_EM14_Pos) /*!< 0x00004000 */ 3401 #define EXTI_C2EMR1_EM14 EXTI_C2EMR1_EM14_Msk /*!< CPU2 Event Mask on line 14 */ 3402 #define EXTI_C2EMR1_EM15_Pos (15U) 3403 #define EXTI_C2EMR1_EM15_Msk (0x1UL << EXTI_C2EMR1_EM15_Pos) /*!< 0x00008000 */ 3404 #define EXTI_C2EMR1_EM15 EXTI_C2EMR1_EM15_Msk /*!< CPU2 Event Mask on line 15 */ 3405 #define EXTI_C2EMR1_EM17_Pos (17U) 3406 #define EXTI_C2EMR1_EM17_Msk (0x1UL << EXTI_C2EMR1_EM17_Pos) /*!< 0x00020000 */ 3407 #define EXTI_C2EMR1_EM17 EXTI_C2EMR1_EM17_Msk /*!< CPU2 Event Mask on line 17 */ 3408 #define EXTI_C2EMR1_EM18_Pos (18U) 3409 #define EXTI_C2EMR1_EM18_Msk (0x1UL << EXTI_C2EMR1_EM18_Pos) /*!< 0x00040000 */ 3410 #define EXTI_C2EMR1_EM18 EXTI_C2EMR1_EM18_Msk /*!< CPU2 Event Mask on line 18 */ 3411 #define EXTI_C2EMR1_EM19_Pos (19U) 3412 #define EXTI_C2EMR1_EM19_Msk (0x1UL << EXTI_C2EMR1_EM19_Pos) /*!< 0x00080000 */ 3413 #define EXTI_C2EMR1_EM19 EXTI_C2EMR1_EM19_Msk /*!< CPU2 Event Mask on line 19 */ 3414 #define EXTI_C2EMR1_EM20_Pos (20U) 3415 #define EXTI_C2EMR1_EM20_Msk (0x1UL << EXTI_C2EMR1_EM20_Pos) /*!< 0x00100000 */ 3416 #define EXTI_C2EMR1_EM20 EXTI_C2EMR1_EM20_Msk /*!< CPU2 Event Mask on line 20 */ 3417 #define EXTI_C2EMR1_EM21_Pos (21U) 3418 #define EXTI_C2EMR1_EM21_Msk (0x1UL << EXTI_C2EMR1_EM21_Pos) /*!< 0x00200000 */ 3419 #define EXTI_C2EMR1_EM21 EXTI_C2EMR1_EM21_Msk /*!< CPU2 Event Mask on line 21 */ 3420 3421 /******************** Bits definition for EXTI_C2IMR2 register **************/ 3422 #define EXTI_C2IMR2_Pos (0U) 3423 #define EXTI_C2IMR2_Msk (0x0001FFFFUL << EXTI_C2IMR2_Pos) /*!< 0x0001FFFF */ 3424 #define EXTI_C2IMR2_IM EXTI_C2IMR2_Msk /*!< CPU2 Interrupt Mask */ 3425 #define EXTI_C2IMR2_IM33_Pos (1U) 3426 #define EXTI_C2IMR2_IM33_Msk (0x1UL << EXTI_C2IMR2_IM33_Pos) /*!< 0x00000002 */ 3427 #define EXTI_C2IMR2_IM33 EXTI_C2IMR2_IM33_Msk /*!< CPU2 Interrupt Mask on line 33 */ 3428 #define EXTI_C2IMR2_IM36_Pos (4U) 3429 #define EXTI_C2IMR2_IM36_Msk (0x1UL << EXTI_C2IMR2_IM36_Pos) /*!< 0x00000010 */ 3430 #define EXTI_C2IMR2_IM36 EXTI_C2IMR2_IM36_Msk /*!< CPU2 Interrupt Mask on line 36 */ 3431 #define EXTI_C2IMR2_IM37_Pos (5U) 3432 #define EXTI_C2IMR2_IM37_Msk (0x1UL << EXTI_C2IMR2_IM37_Pos) /*!< 0x00000020 */ 3433 #define EXTI_C2IMR2_IM37 EXTI_C2IMR2_IM37_Msk /*!< CPU2 Interrupt Mask on line 37 */ 3434 #define EXTI_C2IMR2_IM38_Pos (6U) 3435 #define EXTI_C2IMR2_IM38_Msk (0x1UL << EXTI_C2IMR2_IM38_Pos) /*!< 0x00000040 */ 3436 #define EXTI_C2IMR2_IM38 EXTI_C2IMR2_IM38_Msk /*!< CPU2 Interrupt Mask on line 38 */ 3437 #define EXTI_C2IMR2_IM39_Pos (7U) 3438 #define EXTI_C2IMR2_IM39_Msk (0x1UL << EXTI_C2IMR2_IM39_Pos) /*!< 0x00000080 */ 3439 #define EXTI_C2IMR2_IM39 EXTI_C2IMR2_IM39_Msk /*!< CPU2 Interrupt Mask on line 39 */ 3440 #define EXTI_C2IMR2_IM40_Pos (8U) 3441 #define EXTI_C2IMR2_IM40_Msk (0x1UL << EXTI_C2IMR2_IM40_Pos) /*!< 0x00000100 */ 3442 #define EXTI_C2IMR2_IM40 EXTI_C2IMR2_IM40_Msk /*!< CPU2 Interrupt Mask on line 40 */ 3443 #define EXTI_C2IMR2_IM41_Pos (9U) 3444 #define EXTI_C2IMR2_IM41_Msk (0x1UL << EXTI_C2IMR2_IM41_Pos) /*!< 0x00000200 */ 3445 #define EXTI_C2IMR2_IM41 EXTI_C2IMR2_IM41_Msk /*!< CPU2 Interrupt Mask on line 41 */ 3446 #define EXTI_C2IMR2_IM42_Pos (10U) 3447 #define EXTI_C2IMR2_IM42_Msk (0x1UL << EXTI_C2IMR2_IM42_Pos) /*!< 0x00000400 */ 3448 #define EXTI_C2IMR2_IM42 EXTI_C2IMR2_IM42_Msk /*!< CPU2 Interrupt Mask on line 42 */ 3449 #define EXTI_C2IMR2_IM44_Pos (12U) 3450 #define EXTI_C2IMR2_IM44_Msk (0x1UL << EXTI_C2IMR2_IM44_Pos) /*!< 0x00001000 */ 3451 #define EXTI_C2IMR2_IM44 EXTI_C2IMR2_IM44_Msk /*!< CPU2 Interrupt Mask on line 44 */ 3452 #define EXTI_C2IMR2_IM45_Pos (13U) 3453 #define EXTI_C2IMR2_IM45_Msk (0x1UL << EXTI_C2IMR2_IM45_Pos) /*!< 0x00002000 */ 3454 #define EXTI_C2IMR2_IM45 EXTI_C2IMR2_IM45_Msk /*!< CPU2 Interrupt Mask on line 45 */ 3455 #define EXTI_C2IMR2_IM46_Pos (14U) 3456 #define EXTI_C2IMR2_IM46_Msk (0x1UL << EXTI_C2IMR2_IM46_Pos) /*!< 0x00004000 */ 3457 #define EXTI_C2IMR2_IM46 EXTI_C2IMR2_IM46_Msk /*!< CPU2 Interrupt Mask on line 46 */ 3458 #define EXTI_C2IMR2_IM48_Pos (16U) 3459 #define EXTI_C2IMR2_IM48_Msk (0x1UL << EXTI_C2IMR2_IM48_Pos) /*!< 0x00010000 */ 3460 #define EXTI_C2IMR2_IM48 EXTI_C2IMR2_IM48_Msk /*!< CPU2 Interrupt Mask on line 48 */ 3461 3462 /******************** Bits definition for EXTI_C2EMR2 register **************/ 3463 #define EXTI_C2EMR2_Pos (8U) 3464 #define EXTI_C2EMR2_Msk (0x00000300UL << EXTI_C2EMR2_Pos) /*!< 0x000003000 */ 3465 #define EXTI_C2EMR2_EM EXTI_C2EMR2_Msk /*!< CPU2 Interrupt Mask */ 3466 #define EXTI_C2EMR2_EM40_Pos (8U) 3467 #define EXTI_C2EMR2_EM40_Msk (0x1UL << EXTI_C2EMR2_EM40_Pos) /*!< 0x00000100 */ 3468 #define EXTI_C2EMR2_EM40 EXTI_C2EMR2_EM40_Msk /*!< CPU2 Event Mask on line 40 */ 3469 #define EXTI_C2EMR2_EM41_Pos (9U) 3470 #define EXTI_C2EMR2_EM41_Msk (0x1UL << EXTI_C2EMR2_EM41_Pos) /*!< 0x00000200 */ 3471 #define EXTI_C2EMR2_EM41 EXTI_C2EMR2_EM41_Msk /*!< CPU2 Event Mask on line 41 */ 3472 3473 /******************************************************************************/ 3474 /* */ 3475 /* Public Key Accelerator (PKA) */ 3476 /* */ 3477 /******************************************************************************/ 3478 3479 /******************* Bits definition for PKA_CR register **************/ 3480 #define PKA_CR_EN_Pos (0U) 3481 #define PKA_CR_EN_Msk (0x1UL << PKA_CR_EN_Pos) /*!< 0x00000001 */ 3482 #define PKA_CR_EN PKA_CR_EN_Msk /*!< PKA enable */ 3483 #define PKA_CR_START_Pos (1U) 3484 #define PKA_CR_START_Msk (0x1UL << PKA_CR_START_Pos) /*!< 0x00000002 */ 3485 #define PKA_CR_START PKA_CR_START_Msk /*!< Start operation */ 3486 #define PKA_CR_MODE_Pos (8U) 3487 #define PKA_CR_MODE_Msk (0x3FUL << PKA_CR_MODE_Pos) /*!< 0x00003F00 */ 3488 #define PKA_CR_MODE PKA_CR_MODE_Msk /*!< MODE[5:0] PKA operation code */ 3489 #define PKA_CR_MODE_0 (0x01U << PKA_CR_MODE_Pos) /*!< 0x00000100 */ 3490 #define PKA_CR_MODE_1 (0x02U << PKA_CR_MODE_Pos) /*!< 0x00000200 */ 3491 #define PKA_CR_MODE_2 (0x04U << PKA_CR_MODE_Pos) /*!< 0x00000400 */ 3492 #define PKA_CR_MODE_3 (0x08U << PKA_CR_MODE_Pos) /*!< 0x00000800 */ 3493 #define PKA_CR_MODE_4 (0x10U << PKA_CR_MODE_Pos) /*!< 0x00001000 */ 3494 #define PKA_CR_MODE_5 (0x20U << PKA_CR_MODE_Pos) /*!< 0x00002000 */ 3495 #define PKA_CR_PROCENDIE_Pos (17U) 3496 #define PKA_CR_PROCENDIE_Msk (0x1UL << PKA_CR_PROCENDIE_Pos) /*!< 0x00020000 */ 3497 #define PKA_CR_PROCENDIE PKA_CR_PROCENDIE_Msk /*!< End of operation interrupt enable */ 3498 #define PKA_CR_RAMERRIE_Pos (19U) 3499 #define PKA_CR_RAMERRIE_Msk (0x1UL << PKA_CR_RAMERRIE_Pos) /*!< 0x00080000 */ 3500 #define PKA_CR_RAMERRIE PKA_CR_RAMERRIE_Msk /*!< RAM error interrupt enable */ 3501 #define PKA_CR_ADDRERRIE_Pos (20U) 3502 #define PKA_CR_ADDRERRIE_Msk (0x1UL << PKA_CR_ADDRERRIE_Pos) /*!< 0x00100000 */ 3503 #define PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE_Msk /*!< RAM error interrupt enable */ 3504 3505 /******************* Bits definition for PKA_SR register **************/ 3506 #define PKA_SR_BUSY_Pos (16U) 3507 #define PKA_SR_BUSY_Msk (0x1UL << PKA_SR_BUSY_Pos) /*!< 0x00010000 */ 3508 #define PKA_SR_BUSY PKA_SR_BUSY_Msk /*!< PKA operation is in progress */ 3509 #define PKA_SR_PROCENDF_Pos (17U) 3510 #define PKA_SR_PROCENDF_Msk (0x1UL << PKA_SR_PROCENDF_Pos) /*!< 0x00020000 */ 3511 #define PKA_SR_PROCENDF PKA_SR_PROCENDF_Msk /*!< PKA end of operation flag */ 3512 #define PKA_SR_RAMERRF_Pos (19U) 3513 #define PKA_SR_RAMERRF_Msk (0x1UL << PKA_SR_RAMERRF_Pos) /*!< 0x00080000 */ 3514 #define PKA_SR_RAMERRF PKA_SR_RAMERRF_Msk /*!< PKA RAM error flag */ 3515 #define PKA_SR_ADDRERRF_Pos (20U) 3516 #define PKA_SR_ADDRERRF_Msk (0x1UL << PKA_SR_ADDRERRF_Pos) /*!< 0x00100000 */ 3517 #define PKA_SR_ADDRERRF PKA_SR_ADDRERRF_Msk /*!< Address error flag */ 3518 3519 /******************* Bits definition for PKA_CLRFR register **************/ 3520 #define PKA_CLRFR_PROCENDFC_Pos (17U) 3521 #define PKA_CLRFR_PROCENDFC_Msk (0x1UL << PKA_CLRFR_PROCENDFC_Pos) /*!< 0x00020000 */ 3522 #define PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC_Msk /*!< Clear PKA end of operation flag */ 3523 #define PKA_CLRFR_RAMERRFC_Pos (19U) 3524 #define PKA_CLRFR_RAMERRFC_Msk (0x1UL << PKA_CLRFR_RAMERRFC_Pos) /*!< 0x00080000 */ 3525 #define PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC_Msk /*!< Clear PKA RAM error flag */ 3526 #define PKA_CLRFR_ADDRERRFC_Pos (20U) 3527 #define PKA_CLRFR_ADDRERRFC_Msk (0x1UL << PKA_CLRFR_ADDRERRFC_Pos) /*!< 0x00100000 */ 3528 #define PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC_Msk /*!< Clear address error flag */ 3529 3530 /******************* Bits definition for PKA RAM *************************/ 3531 #define PKA_RAM_OFFSET 0x400U /*!< PKA RAM address offset */ 3532 3533 /* Compute Montgomery parameter input data */ 3534 #define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ 3535 #define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ 3536 3537 /* Compute Montgomery parameter output data */ 3538 #define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ 3539 3540 /* Compute modular exponentiation input data */ 3541 #define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ 3542 #define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 3543 #define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ 3544 #define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ 3545 #define PKA_MODULAR_EXP_IN_EXPONENT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ 3546 #define PKA_MODULAR_EXP_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ 3547 3548 /* Compute modular exponentiation output data */ 3549 #define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ 3550 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1 ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 1 */ 3551 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 2 */ 3552 #define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ 3553 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 3 */ 3554 3555 /* Compute ECC scalar multiplication input data */ 3556 #define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ 3557 #define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 3558 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ 3559 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ 3560 #define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ 3561 #define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ 3562 #define PKA_ECC_SCALAR_MUL_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ 3563 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ 3564 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ 3565 3566 /* Compute ECC scalar multiplication output data */ 3567 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ 3568 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ 3569 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1 ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Output last double X1 coordinate */ 3570 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output last double Y1 coordinate */ 3571 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1 ((0xE90U - PKA_RAM_OFFSET)>>2) /*!< Output last double Z1 coordinate */ 3572 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2 ((0xEE4U - PKA_RAM_OFFSET)>>2) /*!< Output check point X2 coordinate */ 3573 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2 ((0xF38U - PKA_RAM_OFFSET)>>2) /*!< Output check point Y2 coordinate */ 3574 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2 ((0xF8CU - PKA_RAM_OFFSET)>>2) /*!< Output check point Z2 coordinate */ 3575 3576 /* Point check input data */ 3577 #define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ 3578 #define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ 3579 #define PKA_POINT_CHECK_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ 3580 #define PKA_POINT_CHECK_IN_B_COEFF ((0x7FCU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ 3581 #define PKA_POINT_CHECK_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ 3582 #define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ 3583 #define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ 3584 3585 /* Point check output data */ 3586 #define PKA_POINT_CHECK_OUT_ERROR ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Output error */ 3587 3588 /* ECDSA signature input data */ 3589 #define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ 3590 #define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ 3591 #define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ 3592 #define PKA_ECDSA_SIGN_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ 3593 #define PKA_ECDSA_SIGN_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ 3594 #define PKA_ECDSA_SIGN_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ 3595 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ 3596 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ 3597 #define PKA_ECDSA_SIGN_IN_HASH_E ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ 3598 #define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ 3599 #define PKA_ECDSA_SIGN_IN_ORDER_N ((0xE94U - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ 3600 3601 /* ECDSA signature output data */ 3602 #define PKA_ECDSA_SIGN_OUT_ERROR ((0xEE8U - PKA_RAM_OFFSET)>>2) /*!< Output error */ 3603 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x700U - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ 3604 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x754U - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ 3605 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x103CU - PKA_RAM_OFFSET)>>2) /*!< Output final point kP X coordinate */ 3606 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1090U - PKA_RAM_OFFSET)>>2) /*!< Output final point kP Y coordinate */ 3607 3608 /* ECDSA verification input data */ 3609 #define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ 3610 #define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ 3611 #define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x45CU - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ 3612 #define PKA_ECDSA_VERIF_IN_A_COEFF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ 3613 #define PKA_ECDSA_VERIF_IN_MOD_GF ((0x4B8U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ 3614 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x5E8U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ 3615 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x63CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ 3616 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0xF40U - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ 3617 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0xF94U - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ 3618 #define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x1098U - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ 3619 #define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ 3620 #define PKA_ECDSA_VERIF_IN_HASH_E ((0xFE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ 3621 #define PKA_ECDSA_VERIF_IN_ORDER_N ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ 3622 3623 /* ECDSA verification output data */ 3624 #define PKA_ECDSA_VERIF_OUT_RESULT ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 3625 3626 /* RSA CRT exponentiation input data */ 3627 #define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ 3628 #define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x65CU - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ 3629 #define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ 3630 #define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x7ECU - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ 3631 #define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x97CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ 3632 #define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ 3633 #define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0xEECU - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ 3634 3635 /* RSA CRT exponentiation output data */ 3636 #define PKA_RSA_CRT_EXP_OUT_RESULT ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 3637 3638 /* Modular reduction input data */ 3639 #define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ 3640 #define PKA_MODULAR_REDUC_IN_OPERAND ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand */ 3641 #define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ 3642 #define PKA_MODULAR_REDUC_IN_MODULUS ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ 3643 3644 /* Modular reduction output data */ 3645 #define PKA_MODULAR_REDUC_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 3646 3647 /* Arithmetic addition input data */ 3648 #define PKA_ARITHMETIC_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 3649 #define PKA_ARITHMETIC_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ 3650 #define PKA_ARITHMETIC_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ 3651 3652 /* Arithmetic addition output data */ 3653 #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 3654 3655 /* Arithmetic substraction input data */ 3656 #define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 3657 #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ 3658 #define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ 3659 3660 /* Arithmetic substraction output data */ 3661 #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 3662 3663 /* Arithmetic multiplication input data */ 3664 #define PKA_ARITHMETIC_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 3665 #define PKA_ARITHMETIC_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ 3666 #define PKA_ARITHMETIC_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ 3667 3668 /* Arithmetic multiplication output data */ 3669 #define PKA_ARITHMETIC_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 3670 3671 /* Comparison input data */ 3672 #define PKA_COMPARISON_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 3673 #define PKA_COMPARISON_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ 3674 #define PKA_COMPARISON_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ 3675 3676 /* Comparison output data */ 3677 #define PKA_COMPARISON_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 3678 3679 /* Modular addition input data */ 3680 #define PKA_MODULAR_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 3681 #define PKA_MODULAR_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ 3682 #define PKA_MODULAR_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ 3683 #define PKA_MODULAR_ADD_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ 3684 3685 /* Modular addition output data */ 3686 #define PKA_MODULAR_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 3687 3688 /* Modular inversion input data */ 3689 #define PKA_MODULAR_INV_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 3690 #define PKA_MODULAR_INV_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ 3691 #define PKA_MODULAR_INV_IN_OP2_MOD ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ 3692 3693 /* Modular inversion output data */ 3694 #define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 3695 3696 /* Modular substraction input data */ 3697 #define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 3698 #define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ 3699 #define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ 3700 #define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ 3701 3702 /* Modular substraction output data */ 3703 #define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 3704 3705 /* Montgomery multiplication input data */ 3706 #define PKA_MONTGOMERY_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 3707 #define PKA_MONTGOMERY_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ 3708 #define PKA_MONTGOMERY_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ 3709 #define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ 3710 3711 /* Montgomery multiplication output data */ 3712 #define PKA_MONTGOMERY_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 3713 3714 /* Generic Arithmetic input data */ 3715 #define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ 3716 #define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ 3717 #define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ 3718 #define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ 3719 3720 /* Generic Arithmetic output data */ 3721 #define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */ 3722 3723 /******************************************************************************/ 3724 /* */ 3725 /* FLASH */ 3726 /* */ 3727 /******************************************************************************/ 3728 /******************* Bits definition for FLASH_ACR register *****************/ 3729 #define FLASH_ACR_LATENCY_Pos (0U) 3730 #define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ 3731 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ 3732 #define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ 3733 #define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ 3734 #define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ 3735 #define FLASH_ACR_PRFTEN_Pos (8U) 3736 #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ 3737 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ 3738 #define FLASH_ACR_ICEN_Pos (9U) 3739 #define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ 3740 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk /*!< Instruction cache enable */ 3741 #define FLASH_ACR_DCEN_Pos (10U) 3742 #define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */ 3743 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk /*!< Data cache enable */ 3744 #define FLASH_ACR_ICRST_Pos (11U) 3745 #define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ 3746 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk /*!< Instruction cache reset */ 3747 #define FLASH_ACR_DCRST_Pos (12U) 3748 #define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */ 3749 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk /*!< Data cache reset */ 3750 #define FLASH_ACR_PES_Pos (15U) 3751 #define FLASH_ACR_PES_Msk (0x1UL << FLASH_ACR_PES_Pos) /*!< 0x00008000 */ 3752 #define FLASH_ACR_PES FLASH_ACR_PES_Msk /*!< Program/erase suspend request */ 3753 #define FLASH_ACR_EMPTY_Pos (16U) 3754 #define FLASH_ACR_EMPTY_Msk (0x1UL << FLASH_ACR_EMPTY_Pos) /*!< 0x00010000 */ 3755 #define FLASH_ACR_EMPTY FLASH_ACR_EMPTY_Msk /*!< Flash use area empty */ 3756 3757 #define FLASH_ACR_LATENCY_0WS (0x0UL << FLASH_ACR_LATENCY_Pos) /*!< FLASH Zero wait state */ 3758 #define FLASH_ACR_LATENCY_1WS (FLASH_ACR_LATENCY_0 << FLASH_ACR_LATENCY_Pos) /*!< FLASH One wait state */ 3759 #define FLASH_ACR_LATENCY_2WS (FLASH_ACR_LATENCY_1 << FLASH_ACR_LATENCY_Pos) /*!< FLASH Two wait states */ 3760 #define FLASH_ACR_LATENCY_3WS ((FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) << FLASH_ACR_LATENCY_Pos) /*!< FLASH Three wait states */ 3761 3762 /******************* Bits definition for FLASH_SR register ******************/ 3763 #define FLASH_SR_EOP_Pos (0U) 3764 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ 3765 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of Operation */ 3766 #define FLASH_SR_OPERR_Pos (1U) 3767 #define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ 3768 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk /*!< Operation error */ 3769 #define FLASH_SR_PROGERR_Pos (3U) 3770 #define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ 3771 #define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk /*!< Programming error */ 3772 #define FLASH_SR_WRPERR_Pos (4U) 3773 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ 3774 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */ 3775 #define FLASH_SR_PGAERR_Pos (5U) 3776 #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ 3777 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming alignment error */ 3778 #define FLASH_SR_SIZERR_Pos (6U) 3779 #define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ 3780 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */ 3781 #define FLASH_SR_PGSERR_Pos (7U) 3782 #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ 3783 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error */ 3784 #define FLASH_SR_MISERR_Pos (8U) 3785 #define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ 3786 #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk /*!< Fast programming data miss error */ 3787 #define FLASH_SR_FASTERR_Pos (9U) 3788 #define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ 3789 #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk /*!< Fast programming error */ 3790 #define FLASH_SR_OPTNV_Pos (13U) 3791 #define FLASH_SR_OPTNV_Msk (0x1UL << FLASH_SR_OPTNV_Pos) /*!< 0x00002000 */ 3792 #define FLASH_SR_OPTNV FLASH_SR_OPTNV_Msk /*!< User option OPTVAL indication */ 3793 #define FLASH_SR_RDERR_Pos (14U) 3794 #define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */ 3795 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< PCROP read error */ 3796 #define FLASH_SR_OPTVERR_Pos (15U) 3797 #define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ 3798 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option validity error */ 3799 #define FLASH_SR_BSY_Pos (16U) 3800 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */ 3801 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Flash Busy */ 3802 #define FLASH_SR_CFGBSY_Pos (18U) 3803 #define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */ 3804 #define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk /*!< Programming or erase configuration busy */ 3805 #define FLASH_SR_PESD_Pos (19U) 3806 #define FLASH_SR_PESD_Msk (0x1UL << FLASH_SR_PESD_Pos) /*!< 0x00080000 */ 3807 #define FLASH_SR_PESD FLASH_SR_PESD_Msk /*!< Programming/erase operation suspended */ 3808 3809 /******************* Bits definition for FLASH_CR register ******************/ 3810 #define FLASH_CR_PG_Pos (0U) 3811 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ 3812 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Flash programming */ 3813 #define FLASH_CR_PER_Pos (1U) 3814 #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ 3815 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page erase */ 3816 #define FLASH_CR_MER_Pos (2U) 3817 #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ 3818 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase */ 3819 #define FLASH_CR_PNB_Pos (3U) 3820 #define FLASH_CR_PNB_Msk (0xFFUL << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */ 3821 #define FLASH_CR_PNB FLASH_CR_PNB_Msk /*!< Page number selection mask */ 3822 #define FLASH_CR_STRT_Pos (16U) 3823 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ 3824 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start an erase operation */ 3825 #define FLASH_CR_OPTSTRT_Pos (17U) 3826 #define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ 3827 #define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk /*!< Options modification start */ 3828 #define FLASH_CR_FSTPG_Pos (18U) 3829 #define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ 3830 #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk /*!< Fast programming */ 3831 #define FLASH_CR_EOPIE_Pos (24U) 3832 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ 3833 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ 3834 #define FLASH_CR_ERRIE_Pos (25U) 3835 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ 3836 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error interrupt enable */ 3837 #define FLASH_CR_RDERRIE_Pos (26U) 3838 #define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */ 3839 #define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk /*!< PCROP read error interrupt enable */ 3840 #define FLASH_CR_OBL_LAUNCH_Pos (27U) 3841 #define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ 3842 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ 3843 #define FLASH_CR_OPTLOCK_Pos (30U) 3844 #define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ 3845 #define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk /*!< Options lock */ 3846 #define FLASH_CR_LOCK_Pos (31U) 3847 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ 3848 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Flash control register lock */ 3849 3850 /******************* Bits definition for FLASH_ECCR register ****************/ 3851 #define FLASH_ECCR_ADDR_ECC_Pos (0U) 3852 #define FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0001FFFF */ 3853 #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< double-word address ECC fail */ 3854 #define FLASH_ECCR_SYSF_ECC_Pos (20U) 3855 #define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ 3856 #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System flash ECC fail */ 3857 #define FLASH_ECCR_ECCCIE_Pos (24U) 3858 #define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */ 3859 #define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk /*!< ECC correction interrupt enable */ 3860 #define FLASH_ECCR_CPUID_Pos (26U) 3861 #define FLASH_ECCR_CPUID_Msk (0x7UL << FLASH_ECCR_CPUID_Pos) /*!< 0x1C000000 */ 3862 #define FLASH_ECCR_CPUID FLASH_ECCR_CPUID_Msk /*!< CPU identification */ 3863 #define FLASH_ECCR_ECCC_Pos (30U) 3864 #define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ 3865 #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ 3866 #define FLASH_ECCR_ECCD_Pos (31U) 3867 #define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ 3868 #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ 3869 3870 /******************* Bits definition for FLASH_OPTR register ****************/ 3871 #define FLASH_OPTR_RDP_Pos (0U) 3872 #define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ 3873 #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Read protection level */ 3874 #define FLASH_OPTR_ESE_Pos (8U) 3875 #define FLASH_OPTR_ESE_Msk (0x1UL << FLASH_OPTR_ESE_Pos) /*!< 0x00000100 */ 3876 #define FLASH_OPTR_ESE FLASH_OPTR_ESE_Msk /*!< Security enable */ 3877 #define FLASH_OPTR_BOR_LEV_Pos (9U) 3878 #define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000E00 */ 3879 #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset level mask */ 3880 #define FLASH_OPTR_BOR_LEV_0 (0x1U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ 3881 #define FLASH_OPTR_BOR_LEV_1 (0x2U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ 3882 #define FLASH_OPTR_BOR_LEV_2 (0x4U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000800 */ 3883 #define FLASH_OPTR_nRST_STOP_Pos (12U) 3884 #define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ 3885 #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< Reset option in Stop mode */ 3886 #define FLASH_OPTR_nRST_STDBY_Pos (13U) 3887 #define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ 3888 #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< Reset option in Standby mode */ 3889 #define FLASH_OPTR_nRST_SHDW_Pos (14U) 3890 #define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ 3891 #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< Reset option in Shutdown mode */ 3892 #define FLASH_OPTR_IWDG_SW_Pos (16U) 3893 #define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ 3894 #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ 3895 #define FLASH_OPTR_IWDG_STOP_Pos (17U) 3896 #define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ 3897 #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter option in Stop mode */ 3898 #define FLASH_OPTR_IWDG_STDBY_Pos (18U) 3899 #define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ 3900 #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter option in Standby mode */ 3901 #define FLASH_OPTR_WWDG_SW_Pos (19U) 3902 #define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ 3903 #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ 3904 #define FLASH_OPTR_nBOOT1_Pos (23U) 3905 #define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */ 3906 #define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk /*!< Boot Configuration */ 3907 #define FLASH_OPTR_SRAM2PE_Pos (24U) 3908 #define FLASH_OPTR_SRAM2PE_Msk (0x1UL << FLASH_OPTR_SRAM2PE_Pos) /*!< 0x01000000 */ 3909 #define FLASH_OPTR_SRAM2PE FLASH_OPTR_SRAM2PE_Msk /*!< SRAM2 parity check enable */ 3910 #define FLASH_OPTR_SRAM2RST_Pos (25U) 3911 #define FLASH_OPTR_SRAM2RST_Msk (0x1UL << FLASH_OPTR_SRAM2RST_Pos) /*!< 0x02000000 */ 3912 #define FLASH_OPTR_SRAM2RST FLASH_OPTR_SRAM2RST_Msk /*!< SRAM2 erase option when system reset */ 3913 #define FLASH_OPTR_nSWBOOT0_Pos (26U) 3914 #define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ 3915 #define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ 3916 #define FLASH_OPTR_nBOOT0_Pos (27U) 3917 #define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ 3918 #define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< BOOT0 option bit */ 3919 #define FLASH_OPTR_AGC_TRIM_Pos (29U) 3920 #define FLASH_OPTR_AGC_TRIM_Msk (0x7UL << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0xE0000000 */ 3921 #define FLASH_OPTR_AGC_TRIM FLASH_OPTR_AGC_TRIM_Msk /*!< Automatic Gain Control trimming mask */ 3922 #define FLASH_OPTR_AGC_TRIM_0 (0x1U << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0x20000000 */ 3923 #define FLASH_OPTR_AGC_TRIM_1 (0x2U << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0x40000000 */ 3924 #define FLASH_OPTR_AGC_TRIM_2 (0x4U << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0x80000000 */ 3925 3926 /****************** Bits definition for FLASH_PCROP1ASR register ************/ 3927 #define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U) 3928 #define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0x1FFUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x000001FF */ 3929 #define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk /*!< PCROP area A start offset */ 3930 3931 /****************** Bits definition for FLASH_PCROP1AER register ************/ 3932 #define FLASH_PCROP1AER_PCROP1A_END_Pos (0U) 3933 #define FLASH_PCROP1AER_PCROP1A_END_Msk (0x1FFUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x000001FF */ 3934 #define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk /*!< PCROP area A end offset */ 3935 #define FLASH_PCROP1AER_PCROP_RDP_Pos (31U) 3936 #define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */ 3937 #define FLASH_PCROP1AER_PCROP_RDP FLASH_PCROP1AER_PCROP_RDP_Msk /*!< PCROP area preserved when RDP level decreased */ 3938 3939 /****************** Bits definition for FLASH_WRP1AR register ***************/ 3940 #define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) 3941 #define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */ 3942 #define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk /*!< WRP area A start offset */ 3943 #define FLASH_WRP1AR_WRP1A_END_Pos (16U) 3944 #define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */ 3945 #define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk /*!< WRP area A end offset */ 3946 3947 /****************** Bits definition for FLASH_WRP1BR register ***************/ 3948 #define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) 3949 #define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */ 3950 #define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk /*!< WRP area B start offset */ 3951 #define FLASH_WRP1BR_WRP1B_END_Pos (16U) 3952 #define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */ 3953 #define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk /*!< WRP area B end offset */ 3954 3955 /****************** Bits definition for FLASH_PCROP1BSR register ************/ 3956 #define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U) 3957 #define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0x1FFUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x000001FF */ 3958 #define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk /*!< PCROP area B start offset */ 3959 3960 /****************** Bits definition for FLASH_PCROP1BER register ************/ 3961 #define FLASH_PCROP1BER_PCROP1B_END_Pos (0U) 3962 #define FLASH_PCROP1BER_PCROP1B_END_Msk (0x1FFUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x000001FF */ 3963 #define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk /*!< PCROP area B end offset */ 3964 3965 /****************** Bits definition for FLASH_IPCCBR register ************/ 3966 #define FLASH_IPCCBR_IPCCDBA_Pos (0U) 3967 #define FLASH_IPCCBR_IPCCDBA_Msk (0x3FFFUL << FLASH_IPCCBR_IPCCDBA_Pos) /*!< 0x00003FFF */ 3968 #define FLASH_IPCCBR_IPCCDBA FLASH_IPCCBR_IPCCDBA_Msk /*!< IPCC data buffer base address */ 3969 3970 /****************** Bits definition for FLASH_SFR register ************/ 3971 #define FLASH_SFR_SFSA_Pos (0U) 3972 #define FLASH_SFR_SFSA_Msk (0xFFUL << FLASH_SFR_SFSA_Pos) /*!< 0x000000FF */ 3973 #define FLASH_SFR_SFSA FLASH_SFR_SFSA_Msk /* Secure flash start address */ 3974 #define FLASH_SFR_FSD_Pos (8U) 3975 #define FLASH_SFR_FSD_Msk (0x1UL << FLASH_SFR_FSD_Pos) /*!< 0x00000100 */ 3976 #define FLASH_SFR_FSD FLASH_SFR_FSD_Msk /* Flash mode secure */ 3977 #define FLASH_SFR_DDS_Pos (12U) 3978 #define FLASH_SFR_DDS_Msk (0x1UL << FLASH_SFR_DDS_Pos) /*!< 0x00001000 */ 3979 #define FLASH_SFR_DDS FLASH_SFR_DDS_Msk /* Enabling and disabling CPU2 Debug access */ 3980 3981 /****************** Bits definition for FLASH_SRRVR register ************/ 3982 #define FLASH_SRRVR_SBRV_Pos (0U) 3983 #define FLASH_SRRVR_SBRV_Msk (0x3FFFFUL << FLASH_SRRVR_SBRV_Pos) /*!< 0x0003FFFF */ 3984 #define FLASH_SRRVR_SBRV FLASH_SRRVR_SBRV_Msk /* SCPU2 boot reset vector memory offset */ 3985 3986 #define FLASH_SRRVR_SBRSA_Pos (18U) 3987 #define FLASH_SRRVR_SBRSA_Msk (0x1FUL << FLASH_SRRVR_SBRSA_Pos) /*!< 0x007C0000 */ 3988 #define FLASH_SRRVR_SBRSA FLASH_SRRVR_SBRSA_Msk /* Secure backup SRAM2a start address */ 3989 #define FLASH_SRRVR_BRSD_Pos (23U) 3990 #define FLASH_SRRVR_BRSD_Msk (0x1UL << FLASH_SRRVR_BRSD_Pos) /*!< 0x00800000 */ 3991 #define FLASH_SRRVR_BRSD FLASH_SRRVR_BRSD_Msk /* Backup SRAM2A secure mode */ 3992 3993 #define FLASH_SRRVR_SNBRSA_Pos (25U) 3994 #define FLASH_SRRVR_SNBRSA_Msk (0x1FUL << FLASH_SRRVR_SNBRSA_Pos) /*!< 0x3E000000 */ 3995 #define FLASH_SRRVR_SNBRSA FLASH_SRRVR_SNBRSA_Msk /* Secure non-backup SRAM2b start address */ 3996 #define FLASH_SRRVR_NBRSD_Pos (30U) 3997 #define FLASH_SRRVR_NBRSD_Msk (0x1UL << FLASH_SRRVR_NBRSD_Pos) /*!< 0x40000000 */ 3998 #define FLASH_SRRVR_NBRSD FLASH_SRRVR_NBRSD_Msk /* Non-backup SRAM2B secure mode */ 3999 #define FLASH_SRRVR_C2OPT_Pos (31U) 4000 #define FLASH_SRRVR_C2OPT_Msk (0x1UL << FLASH_SRRVR_C2OPT_Pos) /*!< 0x80000000 */ 4001 #define FLASH_SRRVR_C2OPT FLASH_SRRVR_C2OPT_Msk /* SCPU2 boot reset vector memory selection */ 4002 4003 /****************** Bits definition for FLASH_C2ACR register ************/ 4004 #define FLASH_C2ACR_PRFTEN_Pos (8U) 4005 #define FLASH_C2ACR_PRFTEN_Msk (0x1UL << FLASH_C2ACR_PRFTEN_Pos) /*!< 0x00000100 */ 4006 #define FLASH_C2ACR_PRFTEN FLASH_C2ACR_PRFTEN_Msk /*!< CPU2 Prefetch enable */ 4007 #define FLASH_C2ACR_ICEN_Pos (9U) 4008 #define FLASH_C2ACR_ICEN_Msk (0x1UL << FLASH_C2ACR_ICEN_Pos) /*!< 0x00000200 */ 4009 #define FLASH_C2ACR_ICEN FLASH_C2ACR_ICEN_Msk /*!< CPU2 Instruction cache enable */ 4010 #define FLASH_C2ACR_ICRST_Pos (11U) 4011 #define FLASH_C2ACR_ICRST_Msk (0x1UL << FLASH_C2ACR_ICRST_Pos) /*!< 0x00000800 */ 4012 #define FLASH_C2ACR_ICRST FLASH_C2ACR_ICRST_Msk /*!< CPU2 Instruction cache reset */ 4013 #define FLASH_C2ACR_PES_Pos (15U) 4014 #define FLASH_C2ACR_PES_Msk (0x1UL << FLASH_C2ACR_PES_Pos) /*!< 0x00008000 */ 4015 #define FLASH_C2ACR_PES FLASH_C2ACR_PES_Msk /*!< CPU2 Program/erase suspend request */ 4016 4017 /****************** Bits definition for FLASH_C2SR register ************/ 4018 #define FLASH_C2SR_EOP_Pos (0U) 4019 #define FLASH_C2SR_EOP_Msk (0x1UL << FLASH_C2SR_EOP_Pos) /*!< 0x00000001 */ 4020 #define FLASH_C2SR_EOP FLASH_C2SR_EOP_Msk /*!< CPU2 End of operation */ 4021 #define FLASH_C2SR_OPERR_Pos (1U) 4022 #define FLASH_C2SR_OPERR_Msk (0x1UL << FLASH_C2SR_OPERR_Pos) /*!< 0x00000002 */ 4023 #define FLASH_C2SR_OPERR FLASH_C2SR_OPERR_Msk /*!< CPU2 Operation error */ 4024 #define FLASH_C2SR_PROGERR_Pos (3U) 4025 #define FLASH_C2SR_PROGERR_Msk (0x1UL << FLASH_C2SR_PROGERR_Pos) /*!< 0x00000008 */ 4026 #define FLASH_C2SR_PROGERR FLASH_C2SR_PROGERR_Msk /*!< CPU2 Programming error */ 4027 #define FLASH_C2SR_WRPERR_Pos (4U) 4028 #define FLASH_C2SR_WRPERR_Msk (0x1UL << FLASH_C2SR_WRPERR_Pos) /*!< 0x00000010 */ 4029 #define FLASH_C2SR_WRPERR FLASH_C2SR_WRPERR_Msk /*!< CPU2 Write protection error */ 4030 #define FLASH_C2SR_PGAERR_Pos (5U) 4031 #define FLASH_C2SR_PGAERR_Msk (0x1UL << FLASH_C2SR_PGAERR_Pos) /*!< 0x00000020 */ 4032 #define FLASH_C2SR_PGAERR FLASH_C2SR_PGAERR_Msk /*!< CPU2 Programming alignment error */ 4033 #define FLASH_C2SR_SIZERR_Pos (6U) 4034 #define FLASH_C2SR_SIZERR_Msk (0x1UL << FLASH_C2SR_SIZERR_Pos) /*!< 0x00000040 */ 4035 #define FLASH_C2SR_SIZERR FLASH_C2SR_SIZERR_Msk /*!< CPU2 Size error */ 4036 #define FLASH_C2SR_PGSERR_Pos (7U) 4037 #define FLASH_C2SR_PGSERR_Msk (0x1UL << FLASH_C2SR_PGSERR_Pos) /*!< 0x00000080 */ 4038 #define FLASH_C2SR_PGSERR FLASH_C2SR_PGSERR_Msk /*!< CPU2 Programming sequence error */ 4039 #define FLASH_C2SR_MISERR_Pos (8U) 4040 #define FLASH_C2SR_MISERR_Msk (0x1UL << FLASH_C2SR_MISERR_Pos) /*!< 0x00000100 */ 4041 #define FLASH_C2SR_MISERR FLASH_C2SR_MISERR_Msk /*!< CPU2 Fast programming data miss error */ 4042 #define FLASH_C2SR_FASTERR_Pos (9U) 4043 #define FLASH_C2SR_FASTERR_Msk (0x1UL << FLASH_C2SR_FASTERR_Pos) /*!< 0x00000200 */ 4044 #define FLASH_C2SR_FASTERR FLASH_C2SR_FASTERR_Msk /*!< CPU2 Fast programming error */ 4045 #define FLASH_C2SR_RDERR_Pos (14U) 4046 #define FLASH_C2SR_RDERR_Msk (0x1UL << FLASH_C2SR_RDERR_Pos) /*!< 0x00004000 */ 4047 #define FLASH_C2SR_RDERR FLASH_C2SR_RDERR_Msk /*!< CPU2 PCROP read error */ 4048 #define FLASH_C2SR_BSY_Pos (16U) 4049 #define FLASH_C2SR_BSY_Msk (0x1UL << FLASH_C2SR_BSY_Pos) /*!< 0x00010000 */ 4050 #define FLASH_C2SR_BSY FLASH_C2SR_BSY_Msk /*!< CPU2 Flash busy */ 4051 #define FLASH_C2SR_CFGBSY_Pos (18U) 4052 #define FLASH_C2SR_CFGBSY_Msk (0x1UL << FLASH_C2SR_CFGBSY_Pos) /*!< 0x00040000 */ 4053 #define FLASH_C2SR_CFGBSY FLASH_C2SR_CFGBSY_Msk /*!< CPU2 Programming or erase configuration busy */ 4054 #define FLASH_C2SR_PESD_Pos (19U) 4055 #define FLASH_C2SR_PESD_Msk (0x1UL << FLASH_C2SR_PESD_Pos) /*!< 0x00080000 */ 4056 #define FLASH_C2SR_PESD FLASH_C2SR_PESD_Msk /*!< CPU2 Programming/erase operation suspended */ 4057 4058 /****************** Bits definition for FLASH_C2CR register ************/ 4059 #define FLASH_C2CR_PG_Pos (0U) 4060 #define FLASH_C2CR_PG_Msk (0x1UL << FLASH_C2CR_PG_Pos) /*!< 0x00000001 */ 4061 #define FLASH_C2CR_PG FLASH_C2CR_PG_Msk /*!< CPU2 Flash programming */ 4062 #define FLASH_C2CR_PER_Pos (1U) 4063 #define FLASH_C2CR_PER_Msk (0x1UL << FLASH_C2CR_PER_Pos) /*!< 0x00000002 */ 4064 #define FLASH_C2CR_PER FLASH_C2CR_PER_Msk /*!< CPU2 Page erase */ 4065 #define FLASH_C2CR_MER_Pos (2U) 4066 #define FLASH_C2CR_MER_Msk (0x1UL << FLASH_C2CR_MER_Pos) /*!< 0x00000004 */ 4067 #define FLASH_C2CR_MER FLASH_C2CR_MER_Msk /*!< CPU2 Mass erase */ 4068 #define FLASH_C2CR_PNB_Pos (3U) 4069 #define FLASH_C2CR_PNB_Msk (0xFFUL << FLASH_C2CR_PNB_Pos) /*!< 0x000007F8 */ 4070 #define FLASH_C2CR_PNB FLASH_C2CR_PNB_Msk /*!< CPU2 Page number selection mask */ 4071 #define FLASH_C2CR_STRT_Pos (16U) 4072 #define FLASH_C2CR_STRT_Msk (0x1UL << FLASH_C2CR_STRT_Pos) /*!< 0x00010000 */ 4073 #define FLASH_C2CR_STRT FLASH_C2CR_STRT_Msk /*!< CPU2 Start an erase operation */ 4074 #define FLASH_C2CR_FSTPG_Pos (18U) 4075 #define FLASH_C2CR_FSTPG_Msk (0x1UL << FLASH_C2CR_FSTPG_Pos) /*!< 0x00040000 */ 4076 #define FLASH_C2CR_FSTPG FLASH_C2CR_FSTPG_Msk /*!< CPU2 Fast programming */ 4077 #define FLASH_C2CR_EOPIE_Pos (24U) 4078 #define FLASH_C2CR_EOPIE_Msk (0x1UL << FLASH_C2CR_EOPIE_Pos) /*!< 0x01000000 */ 4079 #define FLASH_C2CR_EOPIE FLASH_C2CR_EOPIE_Msk /*!< CPU2 End of operation interrupt enable */ 4080 #define FLASH_C2CR_ERRIE_Pos (25U) 4081 #define FLASH_C2CR_ERRIE_Msk (0x1UL << FLASH_C2CR_ERRIE_Pos) /*!< 0x02000000 */ 4082 #define FLASH_C2CR_ERRIE FLASH_C2CR_ERRIE_Msk /*!< CPU2 Error interrupt enable */ 4083 #define FLASH_C2CR_RDERRIE_Pos (26U) 4084 #define FLASH_C2CR_RDERRIE_Msk (0x1UL << FLASH_C2CR_RDERRIE_Pos) /*!< 0x04000000 */ 4085 #define FLASH_C2CR_RDERRIE FLASH_C2CR_RDERRIE_Msk /*!< CPU2 PCROP read error interrupt enable */ 4086 4087 /******************************************************************************/ 4088 /* */ 4089 /* General Purpose I/O */ 4090 /* */ 4091 /******************************************************************************/ 4092 /****************** Bits definition for GPIO_MODER register *****************/ 4093 #define GPIO_MODER_MODE0_Pos (0U) 4094 #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ 4095 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk 4096 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ 4097 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ 4098 #define GPIO_MODER_MODE1_Pos (2U) 4099 #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ 4100 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk 4101 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ 4102 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ 4103 #define GPIO_MODER_MODE2_Pos (4U) 4104 #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ 4105 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk 4106 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ 4107 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ 4108 #define GPIO_MODER_MODE3_Pos (6U) 4109 #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ 4110 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk 4111 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ 4112 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ 4113 #define GPIO_MODER_MODE4_Pos (8U) 4114 #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ 4115 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk 4116 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ 4117 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ 4118 #define GPIO_MODER_MODE5_Pos (10U) 4119 #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ 4120 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk 4121 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ 4122 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ 4123 #define GPIO_MODER_MODE6_Pos (12U) 4124 #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ 4125 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk 4126 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ 4127 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ 4128 #define GPIO_MODER_MODE7_Pos (14U) 4129 #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ 4130 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk 4131 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ 4132 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ 4133 #define GPIO_MODER_MODE8_Pos (16U) 4134 #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ 4135 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk 4136 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ 4137 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ 4138 #define GPIO_MODER_MODE9_Pos (18U) 4139 #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ 4140 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk 4141 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ 4142 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ 4143 #define GPIO_MODER_MODE10_Pos (20U) 4144 #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ 4145 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk 4146 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ 4147 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ 4148 #define GPIO_MODER_MODE11_Pos (22U) 4149 #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ 4150 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk 4151 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ 4152 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ 4153 #define GPIO_MODER_MODE12_Pos (24U) 4154 #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ 4155 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk 4156 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ 4157 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ 4158 #define GPIO_MODER_MODE13_Pos (26U) 4159 #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ 4160 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk 4161 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ 4162 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ 4163 #define GPIO_MODER_MODE14_Pos (28U) 4164 #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ 4165 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk 4166 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ 4167 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ 4168 #define GPIO_MODER_MODE15_Pos (30U) 4169 #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ 4170 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk 4171 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ 4172 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ 4173 4174 /****************** Bits definition for GPIO_OTYPER register ****************/ 4175 #define GPIO_OTYPER_OT0_Pos (0U) 4176 #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ 4177 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk 4178 #define GPIO_OTYPER_OT1_Pos (1U) 4179 #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ 4180 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk 4181 #define GPIO_OTYPER_OT2_Pos (2U) 4182 #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ 4183 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk 4184 #define GPIO_OTYPER_OT3_Pos (3U) 4185 #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ 4186 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk 4187 #define GPIO_OTYPER_OT4_Pos (4U) 4188 #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ 4189 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk 4190 #define GPIO_OTYPER_OT5_Pos (5U) 4191 #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ 4192 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk 4193 #define GPIO_OTYPER_OT6_Pos (6U) 4194 #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ 4195 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk 4196 #define GPIO_OTYPER_OT7_Pos (7U) 4197 #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ 4198 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk 4199 #define GPIO_OTYPER_OT8_Pos (8U) 4200 #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ 4201 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk 4202 #define GPIO_OTYPER_OT9_Pos (9U) 4203 #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ 4204 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk 4205 #define GPIO_OTYPER_OT10_Pos (10U) 4206 #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ 4207 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk 4208 #define GPIO_OTYPER_OT11_Pos (11U) 4209 #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ 4210 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk 4211 #define GPIO_OTYPER_OT12_Pos (12U) 4212 #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ 4213 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk 4214 #define GPIO_OTYPER_OT13_Pos (13U) 4215 #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ 4216 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk 4217 #define GPIO_OTYPER_OT14_Pos (14U) 4218 #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ 4219 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk 4220 #define GPIO_OTYPER_OT15_Pos (15U) 4221 #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ 4222 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk 4223 4224 /****************** Bits definition for GPIO_OSPEEDR register ***************/ 4225 #define GPIO_OSPEEDR_OSPEED0_Pos (0U) 4226 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ 4227 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk 4228 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ 4229 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ 4230 #define GPIO_OSPEEDR_OSPEED1_Pos (2U) 4231 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ 4232 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk 4233 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ 4234 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ 4235 #define GPIO_OSPEEDR_OSPEED2_Pos (4U) 4236 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ 4237 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk 4238 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ 4239 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ 4240 #define GPIO_OSPEEDR_OSPEED3_Pos (6U) 4241 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ 4242 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk 4243 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ 4244 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ 4245 #define GPIO_OSPEEDR_OSPEED4_Pos (8U) 4246 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ 4247 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk 4248 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ 4249 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ 4250 #define GPIO_OSPEEDR_OSPEED5_Pos (10U) 4251 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ 4252 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk 4253 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ 4254 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ 4255 #define GPIO_OSPEEDR_OSPEED6_Pos (12U) 4256 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ 4257 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk 4258 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ 4259 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ 4260 #define GPIO_OSPEEDR_OSPEED7_Pos (14U) 4261 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ 4262 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk 4263 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ 4264 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ 4265 #define GPIO_OSPEEDR_OSPEED8_Pos (16U) 4266 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ 4267 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk 4268 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ 4269 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ 4270 #define GPIO_OSPEEDR_OSPEED9_Pos (18U) 4271 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ 4272 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk 4273 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ 4274 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ 4275 #define GPIO_OSPEEDR_OSPEED10_Pos (20U) 4276 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ 4277 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk 4278 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ 4279 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ 4280 #define GPIO_OSPEEDR_OSPEED11_Pos (22U) 4281 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ 4282 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk 4283 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ 4284 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ 4285 #define GPIO_OSPEEDR_OSPEED12_Pos (24U) 4286 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ 4287 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk 4288 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ 4289 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ 4290 #define GPIO_OSPEEDR_OSPEED13_Pos (26U) 4291 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ 4292 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk 4293 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ 4294 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ 4295 #define GPIO_OSPEEDR_OSPEED14_Pos (28U) 4296 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ 4297 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk 4298 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ 4299 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ 4300 #define GPIO_OSPEEDR_OSPEED15_Pos (30U) 4301 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ 4302 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk 4303 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ 4304 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ 4305 4306 /****************** Bits definition for GPIO_PUPDR register *****************/ 4307 #define GPIO_PUPDR_PUPD0_Pos (0U) 4308 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ 4309 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk 4310 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ 4311 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ 4312 #define GPIO_PUPDR_PUPD1_Pos (2U) 4313 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ 4314 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk 4315 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ 4316 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ 4317 #define GPIO_PUPDR_PUPD2_Pos (4U) 4318 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ 4319 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk 4320 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ 4321 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ 4322 #define GPIO_PUPDR_PUPD3_Pos (6U) 4323 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ 4324 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk 4325 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ 4326 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ 4327 #define GPIO_PUPDR_PUPD4_Pos (8U) 4328 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ 4329 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk 4330 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ 4331 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ 4332 #define GPIO_PUPDR_PUPD5_Pos (10U) 4333 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ 4334 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk 4335 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ 4336 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ 4337 #define GPIO_PUPDR_PUPD6_Pos (12U) 4338 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ 4339 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk 4340 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ 4341 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ 4342 #define GPIO_PUPDR_PUPD7_Pos (14U) 4343 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ 4344 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk 4345 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ 4346 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ 4347 #define GPIO_PUPDR_PUPD8_Pos (16U) 4348 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ 4349 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk 4350 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ 4351 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ 4352 #define GPIO_PUPDR_PUPD9_Pos (18U) 4353 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ 4354 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk 4355 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ 4356 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ 4357 #define GPIO_PUPDR_PUPD10_Pos (20U) 4358 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ 4359 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk 4360 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ 4361 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ 4362 #define GPIO_PUPDR_PUPD11_Pos (22U) 4363 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ 4364 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk 4365 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ 4366 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ 4367 #define GPIO_PUPDR_PUPD12_Pos (24U) 4368 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ 4369 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk 4370 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ 4371 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ 4372 #define GPIO_PUPDR_PUPD13_Pos (26U) 4373 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ 4374 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk 4375 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ 4376 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ 4377 #define GPIO_PUPDR_PUPD14_Pos (28U) 4378 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ 4379 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk 4380 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ 4381 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ 4382 #define GPIO_PUPDR_PUPD15_Pos (30U) 4383 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ 4384 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk 4385 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ 4386 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ 4387 4388 /****************** Bits definition for GPIO_IDR register *******************/ 4389 #define GPIO_IDR_ID0_Pos (0U) 4390 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ 4391 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk 4392 #define GPIO_IDR_ID1_Pos (1U) 4393 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ 4394 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk 4395 #define GPIO_IDR_ID2_Pos (2U) 4396 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ 4397 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk 4398 #define GPIO_IDR_ID3_Pos (3U) 4399 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ 4400 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk 4401 #define GPIO_IDR_ID4_Pos (4U) 4402 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ 4403 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk 4404 #define GPIO_IDR_ID5_Pos (5U) 4405 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ 4406 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk 4407 #define GPIO_IDR_ID6_Pos (6U) 4408 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ 4409 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk 4410 #define GPIO_IDR_ID7_Pos (7U) 4411 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ 4412 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk 4413 #define GPIO_IDR_ID8_Pos (8U) 4414 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ 4415 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk 4416 #define GPIO_IDR_ID9_Pos (9U) 4417 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ 4418 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk 4419 #define GPIO_IDR_ID10_Pos (10U) 4420 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ 4421 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk 4422 #define GPIO_IDR_ID11_Pos (11U) 4423 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ 4424 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk 4425 #define GPIO_IDR_ID12_Pos (12U) 4426 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ 4427 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk 4428 #define GPIO_IDR_ID13_Pos (13U) 4429 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ 4430 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk 4431 #define GPIO_IDR_ID14_Pos (14U) 4432 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ 4433 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk 4434 #define GPIO_IDR_ID15_Pos (15U) 4435 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ 4436 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk 4437 4438 /****************** Bits definition for GPIO_ODR register *******************/ 4439 #define GPIO_ODR_OD0_Pos (0U) 4440 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ 4441 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk 4442 #define GPIO_ODR_OD1_Pos (1U) 4443 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ 4444 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk 4445 #define GPIO_ODR_OD2_Pos (2U) 4446 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ 4447 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk 4448 #define GPIO_ODR_OD3_Pos (3U) 4449 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ 4450 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk 4451 #define GPIO_ODR_OD4_Pos (4U) 4452 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ 4453 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk 4454 #define GPIO_ODR_OD5_Pos (5U) 4455 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ 4456 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk 4457 #define GPIO_ODR_OD6_Pos (6U) 4458 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ 4459 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk 4460 #define GPIO_ODR_OD7_Pos (7U) 4461 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ 4462 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk 4463 #define GPIO_ODR_OD8_Pos (8U) 4464 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ 4465 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk 4466 #define GPIO_ODR_OD9_Pos (9U) 4467 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ 4468 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk 4469 #define GPIO_ODR_OD10_Pos (10U) 4470 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ 4471 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk 4472 #define GPIO_ODR_OD11_Pos (11U) 4473 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ 4474 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk 4475 #define GPIO_ODR_OD12_Pos (12U) 4476 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ 4477 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk 4478 #define GPIO_ODR_OD13_Pos (13U) 4479 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ 4480 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk 4481 #define GPIO_ODR_OD14_Pos (14U) 4482 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ 4483 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk 4484 #define GPIO_ODR_OD15_Pos (15U) 4485 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ 4486 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk 4487 4488 /****************** Bits definition for GPIO_BSRR register ******************/ 4489 #define GPIO_BSRR_BS0_Pos (0U) 4490 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ 4491 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk 4492 #define GPIO_BSRR_BS1_Pos (1U) 4493 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ 4494 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk 4495 #define GPIO_BSRR_BS2_Pos (2U) 4496 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ 4497 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk 4498 #define GPIO_BSRR_BS3_Pos (3U) 4499 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ 4500 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk 4501 #define GPIO_BSRR_BS4_Pos (4U) 4502 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ 4503 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk 4504 #define GPIO_BSRR_BS5_Pos (5U) 4505 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ 4506 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk 4507 #define GPIO_BSRR_BS6_Pos (6U) 4508 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ 4509 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk 4510 #define GPIO_BSRR_BS7_Pos (7U) 4511 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ 4512 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk 4513 #define GPIO_BSRR_BS8_Pos (8U) 4514 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ 4515 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk 4516 #define GPIO_BSRR_BS9_Pos (9U) 4517 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ 4518 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk 4519 #define GPIO_BSRR_BS10_Pos (10U) 4520 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ 4521 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk 4522 #define GPIO_BSRR_BS11_Pos (11U) 4523 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ 4524 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk 4525 #define GPIO_BSRR_BS12_Pos (12U) 4526 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ 4527 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk 4528 #define GPIO_BSRR_BS13_Pos (13U) 4529 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ 4530 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk 4531 #define GPIO_BSRR_BS14_Pos (14U) 4532 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ 4533 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk 4534 #define GPIO_BSRR_BS15_Pos (15U) 4535 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ 4536 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk 4537 #define GPIO_BSRR_BR0_Pos (16U) 4538 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ 4539 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk 4540 #define GPIO_BSRR_BR1_Pos (17U) 4541 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ 4542 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk 4543 #define GPIO_BSRR_BR2_Pos (18U) 4544 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ 4545 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk 4546 #define GPIO_BSRR_BR3_Pos (19U) 4547 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ 4548 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk 4549 #define GPIO_BSRR_BR4_Pos (20U) 4550 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ 4551 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk 4552 #define GPIO_BSRR_BR5_Pos (21U) 4553 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ 4554 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk 4555 #define GPIO_BSRR_BR6_Pos (22U) 4556 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ 4557 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk 4558 #define GPIO_BSRR_BR7_Pos (23U) 4559 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ 4560 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk 4561 #define GPIO_BSRR_BR8_Pos (24U) 4562 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ 4563 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk 4564 #define GPIO_BSRR_BR9_Pos (25U) 4565 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ 4566 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk 4567 #define GPIO_BSRR_BR10_Pos (26U) 4568 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ 4569 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk 4570 #define GPIO_BSRR_BR11_Pos (27U) 4571 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ 4572 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk 4573 #define GPIO_BSRR_BR12_Pos (28U) 4574 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ 4575 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk 4576 #define GPIO_BSRR_BR13_Pos (29U) 4577 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ 4578 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk 4579 #define GPIO_BSRR_BR14_Pos (30U) 4580 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ 4581 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk 4582 #define GPIO_BSRR_BR15_Pos (31U) 4583 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ 4584 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk 4585 4586 /****************** Bit definition for GPIO_LCKR register *********************/ 4587 #define GPIO_LCKR_LCK0_Pos (0U) 4588 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 4589 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk 4590 #define GPIO_LCKR_LCK1_Pos (1U) 4591 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 4592 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk 4593 #define GPIO_LCKR_LCK2_Pos (2U) 4594 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 4595 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk 4596 #define GPIO_LCKR_LCK3_Pos (3U) 4597 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 4598 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk 4599 #define GPIO_LCKR_LCK4_Pos (4U) 4600 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 4601 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk 4602 #define GPIO_LCKR_LCK5_Pos (5U) 4603 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 4604 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk 4605 #define GPIO_LCKR_LCK6_Pos (6U) 4606 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 4607 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk 4608 #define GPIO_LCKR_LCK7_Pos (7U) 4609 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 4610 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk 4611 #define GPIO_LCKR_LCK8_Pos (8U) 4612 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 4613 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk 4614 #define GPIO_LCKR_LCK9_Pos (9U) 4615 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 4616 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk 4617 #define GPIO_LCKR_LCK10_Pos (10U) 4618 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 4619 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk 4620 #define GPIO_LCKR_LCK11_Pos (11U) 4621 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 4622 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk 4623 #define GPIO_LCKR_LCK12_Pos (12U) 4624 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 4625 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk 4626 #define GPIO_LCKR_LCK13_Pos (13U) 4627 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 4628 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk 4629 #define GPIO_LCKR_LCK14_Pos (14U) 4630 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 4631 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk 4632 #define GPIO_LCKR_LCK15_Pos (15U) 4633 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 4634 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk 4635 #define GPIO_LCKR_LCKK_Pos (16U) 4636 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 4637 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk 4638 4639 /****************** Bit definition for GPIO_AFRL register *********************/ 4640 #define GPIO_AFRL_AFSEL0_Pos (0U) 4641 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ 4642 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk 4643 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ 4644 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ 4645 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ 4646 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ 4647 #define GPIO_AFRL_AFSEL1_Pos (4U) 4648 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ 4649 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk 4650 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ 4651 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ 4652 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ 4653 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ 4654 #define GPIO_AFRL_AFSEL2_Pos (8U) 4655 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ 4656 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk 4657 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ 4658 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ 4659 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ 4660 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ 4661 #define GPIO_AFRL_AFSEL3_Pos (12U) 4662 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ 4663 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk 4664 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ 4665 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ 4666 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ 4667 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ 4668 #define GPIO_AFRL_AFSEL4_Pos (16U) 4669 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ 4670 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk 4671 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ 4672 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ 4673 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ 4674 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ 4675 #define GPIO_AFRL_AFSEL5_Pos (20U) 4676 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ 4677 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk 4678 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ 4679 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ 4680 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ 4681 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ 4682 #define GPIO_AFRL_AFSEL6_Pos (24U) 4683 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ 4684 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk 4685 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ 4686 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ 4687 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ 4688 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ 4689 #define GPIO_AFRL_AFSEL7_Pos (28U) 4690 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ 4691 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk 4692 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ 4693 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ 4694 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ 4695 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ 4696 4697 /****************** Bit definition for GPIO_AFRH register *********************/ 4698 #define GPIO_AFRH_AFSEL8_Pos (0U) 4699 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ 4700 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk 4701 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ 4702 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ 4703 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ 4704 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ 4705 #define GPIO_AFRH_AFSEL9_Pos (4U) 4706 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ 4707 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk 4708 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ 4709 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ 4710 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ 4711 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ 4712 #define GPIO_AFRH_AFSEL10_Pos (8U) 4713 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ 4714 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk 4715 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ 4716 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ 4717 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ 4718 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ 4719 #define GPIO_AFRH_AFSEL11_Pos (12U) 4720 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ 4721 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk 4722 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ 4723 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ 4724 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ 4725 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ 4726 #define GPIO_AFRH_AFSEL12_Pos (16U) 4727 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ 4728 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk 4729 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ 4730 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ 4731 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ 4732 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ 4733 #define GPIO_AFRH_AFSEL13_Pos (20U) 4734 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ 4735 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk 4736 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ 4737 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ 4738 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ 4739 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ 4740 #define GPIO_AFRH_AFSEL14_Pos (24U) 4741 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ 4742 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk 4743 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ 4744 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ 4745 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ 4746 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ 4747 #define GPIO_AFRH_AFSEL15_Pos (28U) 4748 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ 4749 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk 4750 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ 4751 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ 4752 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ 4753 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ 4754 4755 /****************** Bits definition for GPIO_BRR register ******************/ 4756 #define GPIO_BRR_BR0_Pos (0U) 4757 #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ 4758 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk 4759 #define GPIO_BRR_BR1_Pos (1U) 4760 #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ 4761 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk 4762 #define GPIO_BRR_BR2_Pos (2U) 4763 #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ 4764 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk 4765 #define GPIO_BRR_BR3_Pos (3U) 4766 #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ 4767 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk 4768 #define GPIO_BRR_BR4_Pos (4U) 4769 #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ 4770 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk 4771 #define GPIO_BRR_BR5_Pos (5U) 4772 #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ 4773 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk 4774 #define GPIO_BRR_BR6_Pos (6U) 4775 #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ 4776 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk 4777 #define GPIO_BRR_BR7_Pos (7U) 4778 #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ 4779 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk 4780 #define GPIO_BRR_BR8_Pos (8U) 4781 #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ 4782 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk 4783 #define GPIO_BRR_BR9_Pos (9U) 4784 #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ 4785 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk 4786 #define GPIO_BRR_BR10_Pos (10U) 4787 #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ 4788 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk 4789 #define GPIO_BRR_BR11_Pos (11U) 4790 #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ 4791 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk 4792 #define GPIO_BRR_BR12_Pos (12U) 4793 #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ 4794 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk 4795 #define GPIO_BRR_BR13_Pos (13U) 4796 #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ 4797 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk 4798 #define GPIO_BRR_BR14_Pos (14U) 4799 #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ 4800 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk 4801 #define GPIO_BRR_BR15_Pos (15U) 4802 #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ 4803 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk 4804 4805 /******************************************************************************/ 4806 /* */ 4807 /* HSEM HW Semaphore */ 4808 /* */ 4809 /******************************************************************************/ 4810 /******************** Bit definition for HSEM_R register ********************/ 4811 #define HSEM_R_PROCID_Pos (0U) 4812 #define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */ 4813 #define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!<Semaphore ProcessID */ 4814 #define HSEM_R_COREID_Pos (8U) 4815 #define HSEM_R_COREID_Msk (0xFUL << HSEM_R_COREID_Pos) /*!< 0x00000F00 */ 4816 #define HSEM_R_COREID HSEM_R_COREID_Msk /*!<Semaphore CoreID. */ 4817 #define HSEM_R_LOCK_Pos (31U) 4818 #define HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos) /*!< 0x80000000 */ 4819 #define HSEM_R_LOCK HSEM_R_LOCK_Msk /*!<Lock indication. */ 4820 4821 /******************** Bit definition for HSEM_RLR register ******************/ 4822 #define HSEM_RLR_PROCID_Pos (0U) 4823 #define HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos) /*!< 0x000000FF */ 4824 #define HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk /*!<Semaphore ProcessID */ 4825 #define HSEM_RLR_COREID_Pos (8U) 4826 #define HSEM_RLR_COREID_Msk (0xFUL << HSEM_RLR_COREID_Pos) /*!< 0x00000F00 */ 4827 #define HSEM_RLR_COREID HSEM_RLR_COREID_Msk /*!<Semaphore CoreID. */ 4828 #define HSEM_RLR_LOCK_Pos (31U) 4829 #define HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos) /*!< 0x80000000 */ 4830 #define HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk /*!<Lock indication. */ 4831 4832 /******************** Bit definition for HSEM_C1IER register ****************/ 4833 #define HSEM_C1IER_ISE0_Pos (0U) 4834 #define HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos) /*!< 0x00000001 */ 4835 #define HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk /*!<semaphore 0 CPU1 interrupt enable bit. */ 4836 #define HSEM_C1IER_ISE1_Pos (1U) 4837 #define HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos) /*!< 0x00000002 */ 4838 #define HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk /*!<semaphore 1 CPU1 interrupt enable bit. */ 4839 #define HSEM_C1IER_ISE2_Pos (2U) 4840 #define HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos) /*!< 0x00000004 */ 4841 #define HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk /*!<semaphore 2 CPU1 interrupt enable bit. */ 4842 #define HSEM_C1IER_ISE3_Pos (3U) 4843 #define HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos) /*!< 0x00000008 */ 4844 #define HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk /*!<semaphore 3 CPU1 interrupt enable bit. */ 4845 #define HSEM_C1IER_ISE4_Pos (4U) 4846 #define HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos) /*!< 0x00000010 */ 4847 #define HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk /*!<semaphore 4 CPU1 interrupt enable bit. */ 4848 #define HSEM_C1IER_ISE5_Pos (5U) 4849 #define HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos) /*!< 0x00000020 */ 4850 #define HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk /*!<semaphore 5 CPU1 interrupt enable bit. */ 4851 #define HSEM_C1IER_ISE6_Pos (6U) 4852 #define HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos) /*!< 0x00000040 */ 4853 #define HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk /*!<semaphore 6 CPU1 interrupt enable bit. */ 4854 #define HSEM_C1IER_ISE7_Pos (7U) 4855 #define HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos) /*!< 0x00000080 */ 4856 #define HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk /*!<semaphore 7 CPU1 interrupt enable bit. */ 4857 #define HSEM_C1IER_ISE8_Pos (8U) 4858 #define HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos) /*!< 0x00000100 */ 4859 #define HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk /*!<semaphore 8 CPU1 interrupt enable bit. */ 4860 #define HSEM_C1IER_ISE9_Pos (9U) 4861 #define HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos) /*!< 0x00000200 */ 4862 #define HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk /*!<semaphore 9 CPU1 interrupt enable bit. */ 4863 #define HSEM_C1IER_ISE10_Pos (10U) 4864 #define HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos) /*!< 0x00000400 */ 4865 #define HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk /*!<semaphore 10 CPU1 interrupt enable bit. */ 4866 #define HSEM_C1IER_ISE11_Pos (11U) 4867 #define HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos) /*!< 0x00000800 */ 4868 #define HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk /*!<semaphore 11 CPU1 interrupt enable bit. */ 4869 #define HSEM_C1IER_ISE12_Pos (12U) 4870 #define HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos) /*!< 0x00001000 */ 4871 #define HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk /*!<semaphore 12 CPU1 interrupt enable bit. */ 4872 #define HSEM_C1IER_ISE13_Pos (13U) 4873 #define HSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos) /*!< 0x00002000 */ 4874 #define HSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk /*!<semaphore 13 CPU1 interrupt enable bit. */ 4875 #define HSEM_C1IER_ISE14_Pos (14U) 4876 #define HSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos) /*!< 0x00004000 */ 4877 #define HSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk /*!<semaphore 14 CPU1 interrupt enable bit. */ 4878 #define HSEM_C1IER_ISE15_Pos (15U) 4879 #define HSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos) /*!< 0x00008000 */ 4880 #define HSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk /*!<semaphore 15 CPU1 interrupt enable bit. */ 4881 #define HSEM_C1IER_ISE16_Pos (16U) 4882 #define HSEM_C1IER_ISE16_Msk (0x1UL << HSEM_C1IER_ISE16_Pos) /*!< 0x00010000 */ 4883 #define HSEM_C1IER_ISE16 HSEM_C1IER_ISE16_Msk /*!<semaphore 16 CPU1 interrupt enable bit. */ 4884 #define HSEM_C1IER_ISE17_Pos (17U) 4885 #define HSEM_C1IER_ISE17_Msk (0x1UL << HSEM_C1IER_ISE17_Pos) /*!< 0x00020000 */ 4886 #define HSEM_C1IER_ISE17 HSEM_C1IER_ISE17_Msk /*!<semaphore 17 CPU1 interrupt enable bit. */ 4887 #define HSEM_C1IER_ISE18_Pos (18U) 4888 #define HSEM_C1IER_ISE18_Msk (0x1UL << HSEM_C1IER_ISE18_Pos) /*!< 0x00040000 */ 4889 #define HSEM_C1IER_ISE18 HSEM_C1IER_ISE18_Msk /*!<semaphore 18 CPU1 interrupt enable bit. */ 4890 #define HSEM_C1IER_ISE19_Pos (19U) 4891 #define HSEM_C1IER_ISE19_Msk (0x1UL << HSEM_C1IER_ISE19_Pos) /*!< 0x00080000 */ 4892 #define HSEM_C1IER_ISE19 HSEM_C1IER_ISE19_Msk /*!<semaphore 19 CPU1 interrupt enable bit. */ 4893 #define HSEM_C1IER_ISE20_Pos (20U) 4894 #define HSEM_C1IER_ISE20_Msk (0x1UL << HSEM_C1IER_ISE20_Pos) /*!< 0x00100000 */ 4895 #define HSEM_C1IER_ISE20 HSEM_C1IER_ISE20_Msk /*!<semaphore 20 CPU1 interrupt enable bit. */ 4896 #define HSEM_C1IER_ISE21_Pos (21U) 4897 #define HSEM_C1IER_ISE21_Msk (0x1UL << HSEM_C1IER_ISE21_Pos) /*!< 0x00200000 */ 4898 #define HSEM_C1IER_ISE21 HSEM_C1IER_ISE21_Msk /*!<semaphore 21 CPU1 interrupt enable bit. */ 4899 #define HSEM_C1IER_ISE22_Pos (22U) 4900 #define HSEM_C1IER_ISE22_Msk (0x1UL << HSEM_C1IER_ISE22_Pos) /*!< 0x00400000 */ 4901 #define HSEM_C1IER_ISE22 HSEM_C1IER_ISE22_Msk /*!<semaphore 22 CPU1 interrupt enable bit. */ 4902 #define HSEM_C1IER_ISE23_Pos (23U) 4903 #define HSEM_C1IER_ISE23_Msk (0x1UL << HSEM_C1IER_ISE23_Pos) /*!< 0x00800000 */ 4904 #define HSEM_C1IER_ISE23 HSEM_C1IER_ISE23_Msk /*!<semaphore 23 CPU1 interrupt enable bit. */ 4905 #define HSEM_C1IER_ISE24_Pos (24U) 4906 #define HSEM_C1IER_ISE24_Msk (0x1UL << HSEM_C1IER_ISE24_Pos) /*!< 0x01000000 */ 4907 #define HSEM_C1IER_ISE24 HSEM_C1IER_ISE24_Msk /*!<semaphore 24 CPU1 interrupt enable bit. */ 4908 #define HSEM_C1IER_ISE25_Pos (25U) 4909 #define HSEM_C1IER_ISE25_Msk (0x1UL << HSEM_C1IER_ISE25_Pos) /*!< 0x02000000 */ 4910 #define HSEM_C1IER_ISE25 HSEM_C1IER_ISE25_Msk /*!<semaphore 25 CPU1 interrupt enable bit. */ 4911 #define HSEM_C1IER_ISE26_Pos (26U) 4912 #define HSEM_C1IER_ISE26_Msk (0x1UL << HSEM_C1IER_ISE26_Pos) /*!< 0x04000000 */ 4913 #define HSEM_C1IER_ISE26 HSEM_C1IER_ISE26_Msk /*!<semaphore 26 CPU1 interrupt enable bit. */ 4914 #define HSEM_C1IER_ISE27_Pos (27U) 4915 #define HSEM_C1IER_ISE27_Msk (0x1UL << HSEM_C1IER_ISE27_Pos) /*!< 0x08000000 */ 4916 #define HSEM_C1IER_ISE27 HSEM_C1IER_ISE27_Msk /*!<semaphore 27 CPU1 interrupt enable bit. */ 4917 #define HSEM_C1IER_ISE28_Pos (28U) 4918 #define HSEM_C1IER_ISE28_Msk (0x1UL << HSEM_C1IER_ISE28_Pos) /*!< 0x10000000 */ 4919 #define HSEM_C1IER_ISE28 HSEM_C1IER_ISE28_Msk /*!<semaphore 28 CPU1 interrupt enable bit. */ 4920 #define HSEM_C1IER_ISE29_Pos (29U) 4921 #define HSEM_C1IER_ISE29_Msk (0x1UL << HSEM_C1IER_ISE29_Pos) /*!< 0x20000000 */ 4922 #define HSEM_C1IER_ISE29 HSEM_C1IER_ISE29_Msk /*!<semaphore 29 CPU1 interrupt enable bit. */ 4923 #define HSEM_C1IER_ISE30_Pos (30U) 4924 #define HSEM_C1IER_ISE30_Msk (0x1UL << HSEM_C1IER_ISE30_Pos) /*!< 0x40000000 */ 4925 #define HSEM_C1IER_ISE30 HSEM_C1IER_ISE30_Msk /*!<semaphore 30 CPU1 interrupt enable bit. */ 4926 #define HSEM_C1IER_ISE31_Pos (31U) 4927 #define HSEM_C1IER_ISE31_Msk (0x1UL << HSEM_C1IER_ISE31_Pos) /*!< 0x80000000 */ 4928 #define HSEM_C1IER_ISE31 HSEM_C1IER_ISE31_Msk /*!<semaphore 31 CPU1 interrupt enable bit. */ 4929 4930 /******************** Bit definition for HSEM_C1ICR register *****************/ 4931 #define HSEM_C1ICR_ISC0_Pos (0U) 4932 #define HSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos) /*!< 0x00000001 */ 4933 #define HSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk /*!<semaphore 0 CPU1 interrupt clear bit. */ 4934 #define HSEM_C1ICR_ISC1_Pos (1U) 4935 #define HSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos) /*!< 0x00000002 */ 4936 #define HSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk /*!<semaphore 1 CPU1 interrupt clear bit. */ 4937 #define HSEM_C1ICR_ISC2_Pos (2U) 4938 #define HSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos) /*!< 0x00000004 */ 4939 #define HSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk /*!<semaphore 2 CPU1 interrupt clear bit. */ 4940 #define HSEM_C1ICR_ISC3_Pos (3U) 4941 #define HSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos) /*!< 0x00000008 */ 4942 #define HSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk /*!<semaphore 3 CPU1 interrupt clear bit. */ 4943 #define HSEM_C1ICR_ISC4_Pos (4U) 4944 #define HSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos) /*!< 0x00000010 */ 4945 #define HSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk /*!<semaphore 4 CPU1 interrupt clear bit. */ 4946 #define HSEM_C1ICR_ISC5_Pos (5U) 4947 #define HSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos) /*!< 0x00000020 */ 4948 #define HSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk /*!<semaphore 5 CPU1 interrupt clear bit. */ 4949 #define HSEM_C1ICR_ISC6_Pos (6U) 4950 #define HSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos) /*!< 0x00000040 */ 4951 #define HSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk /*!<semaphore 6 CPU1 interrupt clear bit. */ 4952 #define HSEM_C1ICR_ISC7_Pos (7U) 4953 #define HSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos) /*!< 0x00000080 */ 4954 #define HSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk /*!<semaphore 7 CPU1 interrupt clear bit. */ 4955 #define HSEM_C1ICR_ISC8_Pos (8U) 4956 #define HSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos) /*!< 0x00000100 */ 4957 #define HSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk /*!<semaphore 8 CPU1 interrupt clear bit. */ 4958 #define HSEM_C1ICR_ISC9_Pos (9U) 4959 #define HSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos) /*!< 0x00000200 */ 4960 #define HSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk /*!<semaphore 9 CPU1 interrupt clear bit. */ 4961 #define HSEM_C1ICR_ISC10_Pos (10U) 4962 #define HSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos) /*!< 0x00000400 */ 4963 #define HSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk /*!<semaphore 10 CPU1 interrupt clear bit. */ 4964 #define HSEM_C1ICR_ISC11_Pos (11U) 4965 #define HSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos) /*!< 0x00000800 */ 4966 #define HSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk /*!<semaphore 11 CPU1 interrupt clear bit. */ 4967 #define HSEM_C1ICR_ISC12_Pos (12U) 4968 #define HSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos) /*!< 0x00001000 */ 4969 #define HSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk /*!<semaphore 12 CPU1 interrupt clear bit. */ 4970 #define HSEM_C1ICR_ISC13_Pos (13U) 4971 #define HSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos) /*!< 0x00002000 */ 4972 #define HSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk /*!<semaphore 13 CPU1 interrupt clear bit. */ 4973 #define HSEM_C1ICR_ISC14_Pos (14U) 4974 #define HSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos) /*!< 0x00004000 */ 4975 #define HSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk /*!<semaphore 14 CPU1 interrupt clear bit. */ 4976 #define HSEM_C1ICR_ISC15_Pos (15U) 4977 #define HSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos) /*!< 0x00008000 */ 4978 #define HSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk /*!<semaphore 15 CPU1 interrupt clear bit. */ 4979 #define HSEM_C1ICR_ISC16_Pos (16U) 4980 #define HSEM_C1ICR_ISC16_Msk (0x1UL << HSEM_C1ICR_ISC16_Pos) /*!< 0x00010000 */ 4981 #define HSEM_C1ICR_ISC16 HSEM_C1ICR_ISC16_Msk /*!<semaphore 16 CPU1 interrupt clear bit. */ 4982 #define HSEM_C1ICR_ISC17_Pos (17U) 4983 #define HSEM_C1ICR_ISC17_Msk (0x1UL << HSEM_C1ICR_ISC17_Pos) /*!< 0x00020000 */ 4984 #define HSEM_C1ICR_ISC17 HSEM_C1ICR_ISC17_Msk /*!<semaphore 17 CPU1 interrupt clear bit. */ 4985 #define HSEM_C1ICR_ISC18_Pos (18U) 4986 #define HSEM_C1ICR_ISC18_Msk (0x1UL << HSEM_C1ICR_ISC18_Pos) /*!< 0x00040000 */ 4987 #define HSEM_C1ICR_ISC18 HSEM_C1ICR_ISC18_Msk /*!<semaphore 18 CPU1 interrupt clear bit. */ 4988 #define HSEM_C1ICR_ISC19_Pos (19U) 4989 #define HSEM_C1ICR_ISC19_Msk (0x1UL << HSEM_C1ICR_ISC19_Pos) /*!< 0x00080000 */ 4990 #define HSEM_C1ICR_ISC19 HSEM_C1ICR_ISC19_Msk /*!<semaphore 19 CPU1 interrupt clear bit. */ 4991 #define HSEM_C1ICR_ISC20_Pos (20U) 4992 #define HSEM_C1ICR_ISC20_Msk (0x1UL << HSEM_C1ICR_ISC20_Pos) /*!< 0x00100000 */ 4993 #define HSEM_C1ICR_ISC20 HSEM_C1ICR_ISC20_Msk /*!<semaphore 20 CPU1 interrupt clear bit. */ 4994 #define HSEM_C1ICR_ISC21_Pos (21U) 4995 #define HSEM_C1ICR_ISC21_Msk (0x1UL << HSEM_C1ICR_ISC21_Pos) /*!< 0x00200000 */ 4996 #define HSEM_C1ICR_ISC21 HSEM_C1ICR_ISC21_Msk /*!<semaphore 21 CPU1 interrupt clear bit. */ 4997 #define HSEM_C1ICR_ISC22_Pos (22U) 4998 #define HSEM_C1ICR_ISC22_Msk (0x1UL << HSEM_C1ICR_ISC22_Pos) /*!< 0x00400000 */ 4999 #define HSEM_C1ICR_ISC22 HSEM_C1ICR_ISC22_Msk /*!<semaphore 22 CPU1 interrupt clear bit. */ 5000 #define HSEM_C1ICR_ISC23_Pos (23U) 5001 #define HSEM_C1ICR_ISC23_Msk (0x1UL << HSEM_C1ICR_ISC23_Pos) /*!< 0x00800000 */ 5002 #define HSEM_C1ICR_ISC23 HSEM_C1ICR_ISC23_Msk /*!<semaphore 23 CPU1 interrupt clear bit. */ 5003 #define HSEM_C1ICR_ISC24_Pos (24U) 5004 #define HSEM_C1ICR_ISC24_Msk (0x1UL << HSEM_C1ICR_ISC24_Pos) /*!< 0x01000000 */ 5005 #define HSEM_C1ICR_ISC24 HSEM_C1ICR_ISC24_Msk /*!<semaphore 24 CPU1 interrupt clear bit. */ 5006 #define HSEM_C1ICR_ISC25_Pos (25U) 5007 #define HSEM_C1ICR_ISC25_Msk (0x1UL << HSEM_C1ICR_ISC25_Pos) /*!< 0x02000000 */ 5008 #define HSEM_C1ICR_ISC25 HSEM_C1ICR_ISC25_Msk /*!<semaphore 25 CPU1 interrupt clear bit. */ 5009 #define HSEM_C1ICR_ISC26_Pos (26U) 5010 #define HSEM_C1ICR_ISC26_Msk (0x1UL << HSEM_C1ICR_ISC26_Pos) /*!< 0x04000000 */ 5011 #define HSEM_C1ICR_ISC26 HSEM_C1ICR_ISC26_Msk /*!<semaphore 26 CPU1 interrupt clear bit. */ 5012 #define HSEM_C1ICR_ISC27_Pos (27U) 5013 #define HSEM_C1ICR_ISC27_Msk (0x1UL << HSEM_C1ICR_ISC27_Pos) /*!< 0x08000000 */ 5014 #define HSEM_C1ICR_ISC27 HSEM_C1ICR_ISC27_Msk /*!<semaphore 27 CPU1 interrupt clear bit. */ 5015 #define HSEM_C1ICR_ISC28_Pos (28U) 5016 #define HSEM_C1ICR_ISC28_Msk (0x1UL << HSEM_C1ICR_ISC28_Pos) /*!< 0x10000000 */ 5017 #define HSEM_C1ICR_ISC28 HSEM_C1ICR_ISC28_Msk /*!<semaphore 28 CPU1 interrupt clear bit. */ 5018 #define HSEM_C1ICR_ISC29_Pos (29U) 5019 #define HSEM_C1ICR_ISC29_Msk (0x1UL << HSEM_C1ICR_ISC29_Pos) /*!< 0x20000000 */ 5020 #define HSEM_C1ICR_ISC29 HSEM_C1ICR_ISC29_Msk /*!<semaphore 29 CPU1 interrupt clear bit. */ 5021 #define HSEM_C1ICR_ISC30_Pos (30U) 5022 #define HSEM_C1ICR_ISC30_Msk (0x1UL << HSEM_C1ICR_ISC30_Pos) /*!< 0x40000000 */ 5023 #define HSEM_C1ICR_ISC30 HSEM_C1ICR_ISC30_Msk /*!<semaphore 30 CPU1 interrupt clear bit. */ 5024 #define HSEM_C1ICR_ISC31_Pos (31U) 5025 #define HSEM_C1ICR_ISC31_Msk (0x1UL << HSEM_C1ICR_ISC31_Pos) /*!< 0x80000000 */ 5026 #define HSEM_C1ICR_ISC31 HSEM_C1ICR_ISC31_Msk /*!<semaphore 31 CPU1 interrupt clear bit. */ 5027 5028 /******************** Bit definition for HSEM_C1ISR register *****************/ 5029 #define HSEM_C1ISR_ISF0_Pos (0U) 5030 #define HSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos) /*!< 0x00000001 */ 5031 #define HSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk /*!<semaphore 0 CPU1 interrupt status bit. */ 5032 #define HSEM_C1ISR_ISF1_Pos (1U) 5033 #define HSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos) /*!< 0x00000002 */ 5034 #define HSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk /*!<semaphore 1 CPU1 interrupt status bit. */ 5035 #define HSEM_C1ISR_ISF2_Pos (2U) 5036 #define HSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos) /*!< 0x00000004 */ 5037 #define HSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk /*!<semaphore 2 CPU1 interrupt status bit. */ 5038 #define HSEM_C1ISR_ISF3_Pos (3U) 5039 #define HSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos) /*!< 0x00000008 */ 5040 #define HSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk /*!<semaphore 3 CPU1 interrupt status bit. */ 5041 #define HSEM_C1ISR_ISF4_Pos (4U) 5042 #define HSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos) /*!< 0x00000010 */ 5043 #define HSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk /*!<semaphore 4 CPU1 interrupt status bit. */ 5044 #define HSEM_C1ISR_ISF5_Pos (5U) 5045 #define HSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos) /*!< 0x00000020 */ 5046 #define HSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk /*!<semaphore 5 CPU1 interrupt status bit. */ 5047 #define HSEM_C1ISR_ISF6_Pos (6U) 5048 #define HSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos) /*!< 0x00000040 */ 5049 #define HSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk /*!<semaphore 6 CPU1 interrupt status bit. */ 5050 #define HSEM_C1ISR_ISF7_Pos (7U) 5051 #define HSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos) /*!< 0x00000080 */ 5052 #define HSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk /*!<semaphore 7 CPU1 interrupt status bit. */ 5053 #define HSEM_C1ISR_ISF8_Pos (8U) 5054 #define HSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos) /*!< 0x00000100 */ 5055 #define HSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk /*!<semaphore 8 CPU1 interrupt status bit. */ 5056 #define HSEM_C1ISR_ISF9_Pos (9U) 5057 #define HSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos) /*!< 0x00000200 */ 5058 #define HSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk /*!<semaphore 9 CPU1 interrupt status bit. */ 5059 #define HSEM_C1ISR_ISF10_Pos (10U) 5060 #define HSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos) /*!< 0x00000400 */ 5061 #define HSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk /*!<semaphore 10 CPU1 interrupt status bit. */ 5062 #define HSEM_C1ISR_ISF11_Pos (11U) 5063 #define HSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos) /*!< 0x00000800 */ 5064 #define HSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk /*!<semaphore 11 CPU1 interrupt status bit. */ 5065 #define HSEM_C1ISR_ISF12_Pos (12U) 5066 #define HSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos) /*!< 0x00001000 */ 5067 #define HSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk /*!<semaphore 12 CPU1 interrupt status bit. */ 5068 #define HSEM_C1ISR_ISF13_Pos (13U) 5069 #define HSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos) /*!< 0x00002000 */ 5070 #define HSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk /*!<semaphore 13 CPU1 interrupt status bit. */ 5071 #define HSEM_C1ISR_ISF14_Pos (14U) 5072 #define HSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos) /*!< 0x00004000 */ 5073 #define HSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk /*!<semaphore 14 CPU1 interrupt status bit. */ 5074 #define HSEM_C1ISR_ISF15_Pos (15U) 5075 #define HSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos) /*!< 0x00008000 */ 5076 #define HSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk /*!<semaphore 15 CPU1 interrupt status bit. */ 5077 #define HSEM_C1ISR_ISF16_Pos (16U) 5078 #define HSEM_C1ISR_ISF16_Msk (0x1UL << HSEM_C1ISR_ISF16_Pos) /*!< 0x00010000 */ 5079 #define HSEM_C1ISR_ISF16 HSEM_C1ISR_ISF16_Msk /*!<semaphore 16 CPU1 interrupt status bit. */ 5080 #define HSEM_C1ISR_ISF17_Pos (17U) 5081 #define HSEM_C1ISR_ISF17_Msk (0x1UL << HSEM_C1ISR_ISF17_Pos) /*!< 0x00020000 */ 5082 #define HSEM_C1ISR_ISF17 HSEM_C1ISR_ISF17_Msk /*!<semaphore 17 CPU1 interrupt status bit. */ 5083 #define HSEM_C1ISR_ISF18_Pos (18U) 5084 #define HSEM_C1ISR_ISF18_Msk (0x1UL << HSEM_C1ISR_ISF18_Pos) /*!< 0x00040000 */ 5085 #define HSEM_C1ISR_ISF18 HSEM_C1ISR_ISF18_Msk /*!<semaphore 18 CPU1 interrupt status bit. */ 5086 #define HSEM_C1ISR_ISF19_Pos (19U) 5087 #define HSEM_C1ISR_ISF19_Msk (0x1UL << HSEM_C1ISR_ISF19_Pos) /*!< 0x00080000 */ 5088 #define HSEM_C1ISR_ISF19 HSEM_C1ISR_ISF19_Msk /*!<semaphore 19 CPU1 interrupt status bit. */ 5089 #define HSEM_C1ISR_ISF20_Pos (20U) 5090 #define HSEM_C1ISR_ISF20_Msk (0x1UL << HSEM_C1ISR_ISF20_Pos) /*!< 0x00100000 */ 5091 #define HSEM_C1ISR_ISF20 HSEM_C1ISR_ISF20_Msk /*!<semaphore 20 CPU1 interrupt status bit. */ 5092 #define HSEM_C1ISR_ISF21_Pos (21U) 5093 #define HSEM_C1ISR_ISF21_Msk (0x1UL << HSEM_C1ISR_ISF21_Pos) /*!< 0x00200000 */ 5094 #define HSEM_C1ISR_ISF21 HSEM_C1ISR_ISF21_Msk /*!<semaphore 21 CPU1 interrupt status bit. */ 5095 #define HSEM_C1ISR_ISF22_Pos (22U) 5096 #define HSEM_C1ISR_ISF22_Msk (0x1UL << HSEM_C1ISR_ISF22_Pos) /*!< 0x00400000 */ 5097 #define HSEM_C1ISR_ISF22 HSEM_C1ISR_ISF22_Msk /*!<semaphore 22 CPU1 interrupt status bit. */ 5098 #define HSEM_C1ISR_ISF23_Pos (23U) 5099 #define HSEM_C1ISR_ISF23_Msk (0x1UL << HSEM_C1ISR_ISF23_Pos) /*!< 0x00800000 */ 5100 #define HSEM_C1ISR_ISF23 HSEM_C1ISR_ISF23_Msk /*!<semaphore 23 CPU1 interrupt status bit. */ 5101 #define HSEM_C1ISR_ISF24_Pos (24U) 5102 #define HSEM_C1ISR_ISF24_Msk (0x1UL << HSEM_C1ISR_ISF24_Pos) /*!< 0x01000000 */ 5103 #define HSEM_C1ISR_ISF24 HSEM_C1ISR_ISF24_Msk /*!<semaphore 24 CPU1 interrupt status bit. */ 5104 #define HSEM_C1ISR_ISF25_Pos (25U) 5105 #define HSEM_C1ISR_ISF25_Msk (0x1UL << HSEM_C1ISR_ISF25_Pos) /*!< 0x02000000 */ 5106 #define HSEM_C1ISR_ISF25 HSEM_C1ISR_ISF25_Msk /*!<semaphore 25 CPU1 interrupt status bit. */ 5107 #define HSEM_C1ISR_ISF26_Pos (26U) 5108 #define HSEM_C1ISR_ISF26_Msk (0x1UL << HSEM_C1ISR_ISF26_Pos) /*!< 0x04000000 */ 5109 #define HSEM_C1ISR_ISF26 HSEM_C1ISR_ISF26_Msk /*!<semaphore 26 CPU1 interrupt status bit. */ 5110 #define HSEM_C1ISR_ISF27_Pos (27U) 5111 #define HSEM_C1ISR_ISF27_Msk (0x1UL << HSEM_C1ISR_ISF27_Pos) /*!< 0x08000000 */ 5112 #define HSEM_C1ISR_ISF27 HSEM_C1ISR_ISF27_Msk /*!<semaphore 27 CPU1 interrupt status bit. */ 5113 #define HSEM_C1ISR_ISF28_Pos (28U) 5114 #define HSEM_C1ISR_ISF28_Msk (0x1UL << HSEM_C1ISR_ISF28_Pos) /*!< 0x10000000 */ 5115 #define HSEM_C1ISR_ISF28 HSEM_C1ISR_ISF28_Msk /*!<semaphore 28 CPU1 interrupt status bit. */ 5116 #define HSEM_C1ISR_ISF29_Pos (29U) 5117 #define HSEM_C1ISR_ISF29_Msk (0x1UL << HSEM_C1ISR_ISF29_Pos) /*!< 0x20000000 */ 5118 #define HSEM_C1ISR_ISF29 HSEM_C1ISR_ISF29_Msk /*!<semaphore 29 CPU1 interrupt status bit. */ 5119 #define HSEM_C1ISR_ISF30_Pos (30U) 5120 #define HSEM_C1ISR_ISF30_Msk (0x1UL << HSEM_C1ISR_ISF30_Pos) /*!< 0x40000000 */ 5121 #define HSEM_C1ISR_ISF30 HSEM_C1ISR_ISF30_Msk /*!<semaphore 30 CPU1 interrupt status bit. */ 5122 #define HSEM_C1ISR_ISF31_Pos (31U) 5123 #define HSEM_C1ISR_ISF31_Msk (0x1UL << HSEM_C1ISR_ISF31_Pos) /*!< 0x80000000 */ 5124 #define HSEM_C1ISR_ISF31 HSEM_C1ISR_ISF31_Msk /*!<semaphore 31 CPU1 interrupt status bit. */ 5125 5126 /******************** Bit definition for HSEM_C1MISR register *****************/ 5127 #define HSEM_C1MISR_MISF0_Pos (0U) 5128 #define HSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos) /*!< 0x00000001 */ 5129 #define HSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk /*!<semaphore 0 CPU1 interrupt masked status bit. */ 5130 #define HSEM_C1MISR_MISF1_Pos (1U) 5131 #define HSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos) /*!< 0x00000002 */ 5132 #define HSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk /*!<semaphore 1 CPU1 interrupt masked status bit. */ 5133 #define HSEM_C1MISR_MISF2_Pos (2U) 5134 #define HSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos) /*!< 0x00000004 */ 5135 #define HSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk /*!<semaphore 2 CPU1 interrupt masked status bit. */ 5136 #define HSEM_C1MISR_MISF3_Pos (3U) 5137 #define HSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos) /*!< 0x00000008 */ 5138 #define HSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk /*!<semaphore 3 CPU1 interrupt masked status bit. */ 5139 #define HSEM_C1MISR_MISF4_Pos (4U) 5140 #define HSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos) /*!< 0x00000010 */ 5141 #define HSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk /*!<semaphore 4 CPU1 interrupt masked status bit. */ 5142 #define HSEM_C1MISR_MISF5_Pos (5U) 5143 #define HSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos) /*!< 0x00000020 */ 5144 #define HSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk /*!<semaphore 5 CPU1 interrupt masked status bit. */ 5145 #define HSEM_C1MISR_MISF6_Pos (6U) 5146 #define HSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos) /*!< 0x00000040 */ 5147 #define HSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk /*!<semaphore 6 CPU1 interrupt masked status bit. */ 5148 #define HSEM_C1MISR_MISF7_Pos (7U) 5149 #define HSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos) /*!< 0x00000080 */ 5150 #define HSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk /*!<semaphore 7 CPU1 interrupt masked status bit. */ 5151 #define HSEM_C1MISR_MISF8_Pos (8U) 5152 #define HSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos) /*!< 0x00000100 */ 5153 #define HSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk /*!<semaphore 8 CPU1 interrupt masked status bit. */ 5154 #define HSEM_C1MISR_MISF9_Pos (9U) 5155 #define HSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos) /*!< 0x00000200 */ 5156 #define HSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk /*!<semaphore 9 CPU1 interrupt masked status bit. */ 5157 #define HSEM_C1MISR_MISF10_Pos (10U) 5158 #define HSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos) /*!< 0x00000400 */ 5159 #define HSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk /*!<semaphore 10 CPU1 interrupt masked status bit. */ 5160 #define HSEM_C1MISR_MISF11_Pos (11U) 5161 #define HSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos) /*!< 0x00000800 */ 5162 #define HSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk /*!<semaphore 11 CPU1 interrupt masked status bit. */ 5163 #define HSEM_C1MISR_MISF12_Pos (12U) 5164 #define HSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos) /*!< 0x00001000 */ 5165 #define HSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk /*!<semaphore 12 CPU1 interrupt masked status bit. */ 5166 #define HSEM_C1MISR_MISF13_Pos (13U) 5167 #define HSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos) /*!< 0x00002000 */ 5168 #define HSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk /*!<semaphore 13 CPU1 interrupt masked status bit. */ 5169 #define HSEM_C1MISR_MISF14_Pos (14U) 5170 #define HSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos) /*!< 0x00004000 */ 5171 #define HSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk /*!<semaphore 14 CPU1 interrupt masked status bit. */ 5172 #define HSEM_C1MISR_MISF15_Pos (15U) 5173 #define HSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos) /*!< 0x00008000 */ 5174 #define HSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk /*!<semaphore 15 CPU1 interrupt masked status bit. */ 5175 #define HSEM_C1MISR_MISF16_Pos (16U) 5176 #define HSEM_C1MISR_MISF16_Msk (0x1UL << HSEM_C1MISR_MISF16_Pos) /*!< 0x00010000 */ 5177 #define HSEM_C1MISR_MISF16 HSEM_C1MISR_MISF16_Msk /*!<semaphore 16 CPU1 interrupt masked status bit. */ 5178 #define HSEM_C1MISR_MISF17_Pos (17U) 5179 #define HSEM_C1MISR_MISF17_Msk (0x1UL << HSEM_C1MISR_MISF17_Pos) /*!< 0x00020000 */ 5180 #define HSEM_C1MISR_MISF17 HSEM_C1MISR_MISF17_Msk /*!<semaphore 17 CPU1 interrupt masked status bit. */ 5181 #define HSEM_C1MISR_MISF18_Pos (18U) 5182 #define HSEM_C1MISR_MISF18_Msk (0x1UL << HSEM_C1MISR_MISF18_Pos) /*!< 0x00040000 */ 5183 #define HSEM_C1MISR_MISF18 HSEM_C1MISR_MISF18_Msk /*!<semaphore 18 CPU1 interrupt masked status bit. */ 5184 #define HSEM_C1MISR_MISF19_Pos (19U) 5185 #define HSEM_C1MISR_MISF19_Msk (0x1UL << HSEM_C1MISR_MISF19_Pos) /*!< 0x00080000 */ 5186 #define HSEM_C1MISR_MISF19 HSEM_C1MISR_MISF19_Msk /*!<semaphore 19 CPU1 interrupt masked status bit. */ 5187 #define HSEM_C1MISR_MISF20_Pos (20U) 5188 #define HSEM_C1MISR_MISF20_Msk (0x1UL << HSEM_C1MISR_MISF20_Pos) /*!< 0x00100000 */ 5189 #define HSEM_C1MISR_MISF20 HSEM_C1MISR_MISF20_Msk /*!<semaphore 20 CPU1 interrupt masked status bit. */ 5190 #define HSEM_C1MISR_MISF21_Pos (21U) 5191 #define HSEM_C1MISR_MISF21_Msk (0x1UL << HSEM_C1MISR_MISF21_Pos) /*!< 0x00200000 */ 5192 #define HSEM_C1MISR_MISF21 HSEM_C1MISR_MISF21_Msk /*!<semaphore 21 CPU1 interrupt masked status bit. */ 5193 #define HSEM_C1MISR_MISF22_Pos (22U) 5194 #define HSEM_C1MISR_MISF22_Msk (0x1UL << HSEM_C1MISR_MISF22_Pos) /*!< 0x00400000 */ 5195 #define HSEM_C1MISR_MISF22 HSEM_C1MISR_MISF22_Msk /*!<semaphore 22 CPU1 interrupt masked status bit. */ 5196 #define HSEM_C1MISR_MISF23_Pos (23U) 5197 #define HSEM_C1MISR_MISF23_Msk (0x1UL << HSEM_C1MISR_MISF23_Pos) /*!< 0x00800000 */ 5198 #define HSEM_C1MISR_MISF23 HSEM_C1MISR_MISF23_Msk /*!<semaphore 23 CPU1 interrupt masked status bit. */ 5199 #define HSEM_C1MISR_MISF24_Pos (24U) 5200 #define HSEM_C1MISR_MISF24_Msk (0x1UL << HSEM_C1MISR_MISF24_Pos) /*!< 0x01000000 */ 5201 #define HSEM_C1MISR_MISF24 HSEM_C1MISR_MISF24_Msk /*!<semaphore 24 CPU1 interrupt masked status bit. */ 5202 #define HSEM_C1MISR_MISF25_Pos (25U) 5203 #define HSEM_C1MISR_MISF25_Msk (0x1UL << HSEM_C1MISR_MISF25_Pos) /*!< 0x02000000 */ 5204 #define HSEM_C1MISR_MISF25 HSEM_C1MISR_MISF25_Msk /*!<semaphore 25 CPU1 interrupt masked status bit. */ 5205 #define HSEM_C1MISR_MISF26_Pos (26U) 5206 #define HSEM_C1MISR_MISF26_Msk (0x1UL << HSEM_C1MISR_MISF26_Pos) /*!< 0x04000000 */ 5207 #define HSEM_C1MISR_MISF26 HSEM_C1MISR_MISF26_Msk /*!<semaphore 26 CPU1 interrupt masked status bit. */ 5208 #define HSEM_C1MISR_MISF27_Pos (27U) 5209 #define HSEM_C1MISR_MISF27_Msk (0x1UL << HSEM_C1MISR_MISF27_Pos) /*!< 0x08000000 */ 5210 #define HSEM_C1MISR_MISF27 HSEM_C1MISR_MISF27_Msk /*!<semaphore 27 CPU1 interrupt masked status bit. */ 5211 #define HSEM_C1MISR_MISF28_Pos (28U) 5212 #define HSEM_C1MISR_MISF28_Msk (0x1UL << HSEM_C1MISR_MISF28_Pos) /*!< 0x10000000 */ 5213 #define HSEM_C1MISR_MISF28 HSEM_C1MISR_MISF28_Msk /*!<semaphore 28 CPU1 interrupt masked status bit. */ 5214 #define HSEM_C1MISR_MISF29_Pos (29U) 5215 #define HSEM_C1MISR_MISF29_Msk (0x1UL << HSEM_C1MISR_MISF29_Pos) /*!< 0x20000000 */ 5216 #define HSEM_C1MISR_MISF29 HSEM_C1MISR_MISF29_Msk /*!<semaphore 29 CPU1 interrupt masked status bit. */ 5217 #define HSEM_C1MISR_MISF30_Pos (30U) 5218 #define HSEM_C1MISR_MISF30_Msk (0x1UL << HSEM_C1MISR_MISF30_Pos) /*!< 0x40000000 */ 5219 #define HSEM_C1MISR_MISF30 HSEM_C1MISR_MISF30_Msk /*!<semaphore 30 CPU1 interrupt masked status bit. */ 5220 #define HSEM_C1MISR_MISF31_Pos (31U) 5221 #define HSEM_C1MISR_MISF31_Msk (0x1UL << HSEM_C1MISR_MISF31_Pos) /*!< 0x80000000 */ 5222 #define HSEM_C1MISR_MISF31 HSEM_C1MISR_MISF31_Msk /*!<semaphore 31 CPU1 interrupt masked status bit. */ 5223 5224 /******************** Bit definition for HSEM_C2IER register *****************/ 5225 #define HSEM_C2IER_ISE0_Pos (0U) 5226 #define HSEM_C2IER_ISE0_Msk (0x1UL << HSEM_C2IER_ISE0_Pos) /*!< 0x00000001 */ 5227 #define HSEM_C2IER_ISE0 HSEM_C2IER_ISE0_Msk /*!<semaphore 0 CPU2 interrupt enable bit. */ 5228 #define HSEM_C2IER_ISE1_Pos (1U) 5229 #define HSEM_C2IER_ISE1_Msk (0x1UL << HSEM_C2IER_ISE1_Pos) /*!< 0x00000002 */ 5230 #define HSEM_C2IER_ISE1 HSEM_C2IER_ISE1_Msk /*!<semaphore 1 CPU2 interrupt enable bit. */ 5231 #define HSEM_C2IER_ISE2_Pos (2U) 5232 #define HSEM_C2IER_ISE2_Msk (0x1UL << HSEM_C2IER_ISE2_Pos) /*!< 0x00000004 */ 5233 #define HSEM_C2IER_ISE2 HSEM_C2IER_ISE2_Msk /*!<semaphore 2 CPU2 interrupt enable bit. */ 5234 #define HSEM_C2IER_ISE3_Pos (3U) 5235 #define HSEM_C2IER_ISE3_Msk (0x1UL << HSEM_C2IER_ISE3_Pos) /*!< 0x00000008 */ 5236 #define HSEM_C2IER_ISE3 HSEM_C2IER_ISE3_Msk /*!<semaphore 3 CPU2 interrupt enable bit. */ 5237 #define HSEM_C2IER_ISE4_Pos (4U) 5238 #define HSEM_C2IER_ISE4_Msk (0x1UL << HSEM_C2IER_ISE4_Pos) /*!< 0x00000010 */ 5239 #define HSEM_C2IER_ISE4 HSEM_C2IER_ISE4_Msk /*!<semaphore 4 CPU2 interrupt enable bit. */ 5240 #define HSEM_C2IER_ISE5_Pos (5U) 5241 #define HSEM_C2IER_ISE5_Msk (0x1UL << HSEM_C2IER_ISE5_Pos) /*!< 0x00000020 */ 5242 #define HSEM_C2IER_ISE5 HSEM_C2IER_ISE5_Msk /*!<semaphore 5 CPU2 interrupt enable bit. */ 5243 #define HSEM_C2IER_ISE6_Pos (6U) 5244 #define HSEM_C2IER_ISE6_Msk (0x1UL << HSEM_C2IER_ISE6_Pos) /*!< 0x00000040 */ 5245 #define HSEM_C2IER_ISE6 HSEM_C2IER_ISE6_Msk /*!<semaphore 6 CPU2 interrupt enable bit. */ 5246 #define HSEM_C2IER_ISE7_Pos (7U) 5247 #define HSEM_C2IER_ISE7_Msk (0x1UL << HSEM_C2IER_ISE7_Pos) /*!< 0x00000080 */ 5248 #define HSEM_C2IER_ISE7 HSEM_C2IER_ISE7_Msk /*!<semaphore 7 CPU2 interrupt enable bit. */ 5249 #define HSEM_C2IER_ISE8_Pos (8U) 5250 #define HSEM_C2IER_ISE8_Msk (0x1UL << HSEM_C2IER_ISE8_Pos) /*!< 0x00000100 */ 5251 #define HSEM_C2IER_ISE8 HSEM_C2IER_ISE8_Msk /*!<semaphore 8 CPU2 interrupt enable bit. */ 5252 #define HSEM_C2IER_ISE9_Pos (9U) 5253 #define HSEM_C2IER_ISE9_Msk (0x1UL << HSEM_C2IER_ISE9_Pos) /*!< 0x00000200 */ 5254 #define HSEM_C2IER_ISE9 HSEM_C2IER_ISE9_Msk /*!<semaphore 9 CPU2 interrupt enable bit. */ 5255 #define HSEM_C2IER_ISE10_Pos (10U) 5256 #define HSEM_C2IER_ISE10_Msk (0x1UL << HSEM_C2IER_ISE10_Pos) /*!< 0x00000400 */ 5257 #define HSEM_C2IER_ISE10 HSEM_C2IER_ISE10_Msk /*!<semaphore 10 CPU2 interrupt enable bit. */ 5258 #define HSEM_C2IER_ISE11_Pos (11U) 5259 #define HSEM_C2IER_ISE11_Msk (0x1UL << HSEM_C2IER_ISE11_Pos) /*!< 0x00000800 */ 5260 #define HSEM_C2IER_ISE11 HSEM_C2IER_ISE11_Msk /*!<semaphore 11 CPU2 interrupt enable bit. */ 5261 #define HSEM_C2IER_ISE12_Pos (12U) 5262 #define HSEM_C2IER_ISE12_Msk (0x1UL << HSEM_C2IER_ISE12_Pos) /*!< 0x00001000 */ 5263 #define HSEM_C2IER_ISE12 HSEM_C2IER_ISE12_Msk /*!<semaphore 12 CPU2 interrupt enable bit. */ 5264 #define HSEM_C2IER_ISE13_Pos (13U) 5265 #define HSEM_C2IER_ISE13_Msk (0x1UL << HSEM_C2IER_ISE13_Pos) /*!< 0x00002000 */ 5266 #define HSEM_C2IER_ISE13 HSEM_C2IER_ISE13_Msk /*!<semaphore 13 CPU2 interrupt enable bit. */ 5267 #define HSEM_C2IER_ISE14_Pos (14U) 5268 #define HSEM_C2IER_ISE14_Msk (0x1UL << HSEM_C2IER_ISE14_Pos) /*!< 0x00004000 */ 5269 #define HSEM_C2IER_ISE14 HSEM_C2IER_ISE14_Msk /*!<semaphore 14 CPU2 interrupt enable bit. */ 5270 #define HSEM_C2IER_ISE15_Pos (15U) 5271 #define HSEM_C2IER_ISE15_Msk (0x1UL << HSEM_C2IER_ISE15_Pos) /*!< 0x00008000 */ 5272 #define HSEM_C2IER_ISE15 HSEM_C2IER_ISE15_Msk /*!<semaphore 15 CPU2 interrupt enable bit. */ 5273 #define HSEM_C2IER_ISE16_Pos (16U) 5274 #define HSEM_C2IER_ISE16_Msk (0x1UL << HSEM_C2IER_ISE16_Pos) /*!< 0x00010000 */ 5275 #define HSEM_C2IER_ISE16 HSEM_C2IER_ISE16_Msk /*!<semaphore 16 CPU2 interrupt enable bit. */ 5276 #define HSEM_C2IER_ISE17_Pos (17U) 5277 #define HSEM_C2IER_ISE17_Msk (0x1UL << HSEM_C2IER_ISE17_Pos) /*!< 0x00020000 */ 5278 #define HSEM_C2IER_ISE17 HSEM_C2IER_ISE17_Msk /*!<semaphore 17 CPU2 interrupt enable bit. */ 5279 #define HSEM_C2IER_ISE18_Pos (18U) 5280 #define HSEM_C2IER_ISE18_Msk (0x1UL << HSEM_C2IER_ISE18_Pos) /*!< 0x00040000 */ 5281 #define HSEM_C2IER_ISE18 HSEM_C2IER_ISE18_Msk /*!<semaphore 18 CPU2 interrupt enable bit. */ 5282 #define HSEM_C2IER_ISE19_Pos (19U) 5283 #define HSEM_C2IER_ISE19_Msk (0x1UL << HSEM_C2IER_ISE19_Pos) /*!< 0x00080000 */ 5284 #define HSEM_C2IER_ISE19 HSEM_C2IER_ISE19_Msk /*!<semaphore 19 CPU2 interrupt enable bit. */ 5285 #define HSEM_C2IER_ISE20_Pos (20U) 5286 #define HSEM_C2IER_ISE20_Msk (0x1UL << HSEM_C2IER_ISE20_Pos) /*!< 0x00100000 */ 5287 #define HSEM_C2IER_ISE20 HSEM_C2IER_ISE20_Msk /*!<semaphore 20 CPU2 interrupt enable bit. */ 5288 #define HSEM_C2IER_ISE21_Pos (21U) 5289 #define HSEM_C2IER_ISE21_Msk (0x1UL << HSEM_C2IER_ISE21_Pos) /*!< 0x00200000 */ 5290 #define HSEM_C2IER_ISE21 HSEM_C2IER_ISE21_Msk /*!<semaphore 21 CPU2 interrupt enable bit. */ 5291 #define HSEM_C2IER_ISE22_Pos (22U) 5292 #define HSEM_C2IER_ISE22_Msk (0x1UL << HSEM_C2IER_ISE22_Pos) /*!< 0x00400000 */ 5293 #define HSEM_C2IER_ISE22 HSEM_C2IER_ISE22_Msk /*!<semaphore 22 CPU2 interrupt enable bit. */ 5294 #define HSEM_C2IER_ISE23_Pos (23U) 5295 #define HSEM_C2IER_ISE23_Msk (0x1UL << HSEM_C2IER_ISE23_Pos) /*!< 0x00800000 */ 5296 #define HSEM_C2IER_ISE23 HSEM_C2IER_ISE23_Msk /*!<semaphore 23 CPU2 interrupt enable bit. */ 5297 #define HSEM_C2IER_ISE24_Pos (24U) 5298 #define HSEM_C2IER_ISE24_Msk (0x1UL << HSEM_C2IER_ISE24_Pos) /*!< 0x01000000 */ 5299 #define HSEM_C2IER_ISE24 HSEM_C2IER_ISE24_Msk /*!<semaphore 24 CPU2 interrupt enable bit. */ 5300 #define HSEM_C2IER_ISE25_Pos (25U) 5301 #define HSEM_C2IER_ISE25_Msk (0x1UL << HSEM_C2IER_ISE25_Pos) /*!< 0x02000000 */ 5302 #define HSEM_C2IER_ISE25 HSEM_C2IER_ISE25_Msk /*!<semaphore 25 CPU2 interrupt enable bit. */ 5303 #define HSEM_C2IER_ISE26_Pos (26U) 5304 #define HSEM_C2IER_ISE26_Msk (0x1UL << HSEM_C2IER_ISE26_Pos) /*!< 0x04000000 */ 5305 #define HSEM_C2IER_ISE26 HSEM_C2IER_ISE26_Msk /*!<semaphore 26 CPU2 interrupt enable bit. */ 5306 #define HSEM_C2IER_ISE27_Pos (27U) 5307 #define HSEM_C2IER_ISE27_Msk (0x1UL << HSEM_C2IER_ISE27_Pos) /*!< 0x08000000 */ 5308 #define HSEM_C2IER_ISE27 HSEM_C2IER_ISE27_Msk /*!<semaphore 27 CPU2 interrupt enable bit. */ 5309 #define HSEM_C2IER_ISE28_Pos (28U) 5310 #define HSEM_C2IER_ISE28_Msk (0x1UL << HSEM_C2IER_ISE28_Pos) /*!< 0x10000000 */ 5311 #define HSEM_C2IER_ISE28 HSEM_C2IER_ISE28_Msk /*!<semaphore 28 CPU2 interrupt enable bit. */ 5312 #define HSEM_C2IER_ISE29_Pos (29U) 5313 #define HSEM_C2IER_ISE29_Msk (0x1UL << HSEM_C2IER_ISE29_Pos) /*!< 0x20000000 */ 5314 #define HSEM_C2IER_ISE29 HSEM_C2IER_ISE29_Msk /*!<semaphore 29 CPU2 interrupt enable bit. */ 5315 #define HSEM_C2IER_ISE30_Pos (30U) 5316 #define HSEM_C2IER_ISE30_Msk (0x1UL << HSEM_C2IER_ISE30_Pos) /*!< 0x40000000 */ 5317 #define HSEM_C2IER_ISE30 HSEM_C2IER_ISE30_Msk /*!<semaphore 30 CPU2 interrupt enable bit. */ 5318 #define HSEM_C2IER_ISE31_Pos (31U) 5319 #define HSEM_C2IER_ISE31_Msk (0x1UL << HSEM_C2IER_ISE31_Pos) /*!< 0x80000000 */ 5320 #define HSEM_C2IER_ISE31 HSEM_C2IER_ISE31_Msk /*!<semaphore 31 CPU2 interrupt enable bit. */ 5321 5322 /******************** Bit definition for HSEM_C2ICR register *****************/ 5323 #define HSEM_C2ICR_ISC0_Pos (0U) 5324 #define HSEM_C2ICR_ISC0_Msk (0x1UL << HSEM_C2ICR_ISC0_Pos) /*!< 0x00000001 */ 5325 #define HSEM_C2ICR_ISC0 HSEM_C2ICR_ISC0_Msk /*!<semaphore 0 CPU2 interrupt clear bit. */ 5326 #define HSEM_C2ICR_ISC1_Pos (1U) 5327 #define HSEM_C2ICR_ISC1_Msk (0x1UL << HSEM_C2ICR_ISC1_Pos) /*!< 0x00000002 */ 5328 #define HSEM_C2ICR_ISC1 HSEM_C2ICR_ISC1_Msk /*!<semaphore 1 CPU2 interrupt clear bit. */ 5329 #define HSEM_C2ICR_ISC2_Pos (2U) 5330 #define HSEM_C2ICR_ISC2_Msk (0x1UL << HSEM_C2ICR_ISC2_Pos) /*!< 0x00000004 */ 5331 #define HSEM_C2ICR_ISC2 HSEM_C2ICR_ISC2_Msk /*!<semaphore 2 CPU2 interrupt clear bit. */ 5332 #define HSEM_C2ICR_ISC3_Pos (3U) 5333 #define HSEM_C2ICR_ISC3_Msk (0x1UL << HSEM_C2ICR_ISC3_Pos) /*!< 0x00000008 */ 5334 #define HSEM_C2ICR_ISC3 HSEM_C2ICR_ISC3_Msk /*!<semaphore 3 CPU2 interrupt clear bit. */ 5335 #define HSEM_C2ICR_ISC4_Pos (4U) 5336 #define HSEM_C2ICR_ISC4_Msk (0x1UL << HSEM_C2ICR_ISC4_Pos) /*!< 0x00000010 */ 5337 #define HSEM_C2ICR_ISC4 HSEM_C2ICR_ISC4_Msk /*!<semaphore 4 CPU2 interrupt clear bit. */ 5338 #define HSEM_C2ICR_ISC5_Pos (5U) 5339 #define HSEM_C2ICR_ISC5_Msk (0x1UL << HSEM_C2ICR_ISC5_Pos) /*!< 0x00000020 */ 5340 #define HSEM_C2ICR_ISC5 HSEM_C2ICR_ISC5_Msk /*!<semaphore 5 CPU2 interrupt clear bit. */ 5341 #define HSEM_C2ICR_ISC6_Pos (6U) 5342 #define HSEM_C2ICR_ISC6_Msk (0x1UL << HSEM_C2ICR_ISC6_Pos) /*!< 0x00000040 */ 5343 #define HSEM_C2ICR_ISC6 HSEM_C2ICR_ISC6_Msk /*!<semaphore 6 CPU2 interrupt clear bit. */ 5344 #define HSEM_C2ICR_ISC7_Pos (7U) 5345 #define HSEM_C2ICR_ISC7_Msk (0x1UL << HSEM_C2ICR_ISC7_Pos) /*!< 0x00000080 */ 5346 #define HSEM_C2ICR_ISC7 HSEM_C2ICR_ISC7_Msk /*!<semaphore 7 CPU2 interrupt clear bit. */ 5347 #define HSEM_C2ICR_ISC8_Pos (8U) 5348 #define HSEM_C2ICR_ISC8_Msk (0x1UL << HSEM_C2ICR_ISC8_Pos) /*!< 0x00000100 */ 5349 #define HSEM_C2ICR_ISC8 HSEM_C2ICR_ISC8_Msk /*!<semaphore 8 CPU2 interrupt clear bit. */ 5350 #define HSEM_C2ICR_ISC9_Pos (9U) 5351 #define HSEM_C2ICR_ISC9_Msk (0x1UL << HSEM_C2ICR_ISC9_Pos) /*!< 0x00000200 */ 5352 #define HSEM_C2ICR_ISC9 HSEM_C2ICR_ISC9_Msk /*!<semaphore 9 CPU2 interrupt clear bit. */ 5353 #define HSEM_C2ICR_ISC10_Pos (10U) 5354 #define HSEM_C2ICR_ISC10_Msk (0x1UL << HSEM_C2ICR_ISC10_Pos) /*!< 0x00000400 */ 5355 #define HSEM_C2ICR_ISC10 HSEM_C2ICR_ISC10_Msk /*!<semaphore 10 CPU2 interrupt clear bit. */ 5356 #define HSEM_C2ICR_ISC11_Pos (11U) 5357 #define HSEM_C2ICR_ISC11_Msk (0x1UL << HSEM_C2ICR_ISC11_Pos) /*!< 0x00000800 */ 5358 #define HSEM_C2ICR_ISC11 HSEM_C2ICR_ISC11_Msk /*!<semaphore 11 CPU2 interrupt clear bit. */ 5359 #define HSEM_C2ICR_ISC12_Pos (12U) 5360 #define HSEM_C2ICR_ISC12_Msk (0x1UL << HSEM_C2ICR_ISC12_Pos) /*!< 0x00001000 */ 5361 #define HSEM_C2ICR_ISC12 HSEM_C2ICR_ISC12_Msk /*!<semaphore 12 CPU2 interrupt clear bit. */ 5362 #define HSEM_C2ICR_ISC13_Pos (13U) 5363 #define HSEM_C2ICR_ISC13_Msk (0x1UL << HSEM_C2ICR_ISC13_Pos) /*!< 0x00002000 */ 5364 #define HSEM_C2ICR_ISC13 HSEM_C2ICR_ISC13_Msk /*!<semaphore 13 CPU2 interrupt clear bit. */ 5365 #define HSEM_C2ICR_ISC14_Pos (14U) 5366 #define HSEM_C2ICR_ISC14_Msk (0x1UL << HSEM_C2ICR_ISC14_Pos) /*!< 0x00004000 */ 5367 #define HSEM_C2ICR_ISC14 HSEM_C2ICR_ISC14_Msk /*!<semaphore 14 CPU2 interrupt clear bit. */ 5368 #define HSEM_C2ICR_ISC15_Pos (15U) 5369 #define HSEM_C2ICR_ISC15_Msk (0x1UL << HSEM_C2ICR_ISC15_Pos) /*!< 0x00008000 */ 5370 #define HSEM_C2ICR_ISC15 HSEM_C2ICR_ISC15_Msk /*!<semaphore 15 CPU2 interrupt clear bit. */ 5371 #define HSEM_C2ICR_ISC16_Pos (16U) 5372 #define HSEM_C2ICR_ISC16_Msk (0x1UL << HSEM_C2ICR_ISC16_Pos) /*!< 0x00010000 */ 5373 #define HSEM_C2ICR_ISC16 HSEM_C2ICR_ISC16_Msk /*!<semaphore 16 CPU2 interrupt clear bit. */ 5374 #define HSEM_C2ICR_ISC17_Pos (17U) 5375 #define HSEM_C2ICR_ISC17_Msk (0x1UL << HSEM_C2ICR_ISC17_Pos) /*!< 0x00020000 */ 5376 #define HSEM_C2ICR_ISC17 HSEM_C2ICR_ISC17_Msk /*!<semaphore 17 CPU2 interrupt clear bit. */ 5377 #define HSEM_C2ICR_ISC18_Pos (18U) 5378 #define HSEM_C2ICR_ISC18_Msk (0x1UL << HSEM_C2ICR_ISC18_Pos) /*!< 0x00040000 */ 5379 #define HSEM_C2ICR_ISC18 HSEM_C2ICR_ISC18_Msk /*!<semaphore 18 CPU2 interrupt clear bit. */ 5380 #define HSEM_C2ICR_ISC19_Pos (19U) 5381 #define HSEM_C2ICR_ISC19_Msk (0x1UL << HSEM_C2ICR_ISC19_Pos) /*!< 0x00080000 */ 5382 #define HSEM_C2ICR_ISC19 HSEM_C2ICR_ISC19_Msk /*!<semaphore 19 CPU2 interrupt clear bit. */ 5383 #define HSEM_C2ICR_ISC20_Pos (20U) 5384 #define HSEM_C2ICR_ISC20_Msk (0x1UL << HSEM_C2ICR_ISC20_Pos) /*!< 0x00100000 */ 5385 #define HSEM_C2ICR_ISC20 HSEM_C2ICR_ISC20_Msk /*!<semaphore 20 CPU2 interrupt clear bit. */ 5386 #define HSEM_C2ICR_ISC21_Pos (21U) 5387 #define HSEM_C2ICR_ISC21_Msk (0x1UL << HSEM_C2ICR_ISC21_Pos) /*!< 0x00200000 */ 5388 #define HSEM_C2ICR_ISC21 HSEM_C2ICR_ISC21_Msk /*!<semaphore 21 CPU2 interrupt clear bit. */ 5389 #define HSEM_C2ICR_ISC22_Pos (22U) 5390 #define HSEM_C2ICR_ISC22_Msk (0x1UL << HSEM_C2ICR_ISC22_Pos) /*!< 0x00400000 */ 5391 #define HSEM_C2ICR_ISC22 HSEM_C2ICR_ISC22_Msk /*!<semaphore 22 CPU2 interrupt clear bit. */ 5392 #define HSEM_C2ICR_ISC23_Pos (23U) 5393 #define HSEM_C2ICR_ISC23_Msk (0x1UL << HSEM_C2ICR_ISC23_Pos) /*!< 0x00800000 */ 5394 #define HSEM_C2ICR_ISC23 HSEM_C2ICR_ISC23_Msk /*!<semaphore 23 CPU2 interrupt clear bit. */ 5395 #define HSEM_C2ICR_ISC24_Pos (24U) 5396 #define HSEM_C2ICR_ISC24_Msk (0x1UL << HSEM_C2ICR_ISC24_Pos) /*!< 0x01000000 */ 5397 #define HSEM_C2ICR_ISC24 HSEM_C2ICR_ISC24_Msk /*!<semaphore 24 CPU2 interrupt clear bit. */ 5398 #define HSEM_C2ICR_ISC25_Pos (25U) 5399 #define HSEM_C2ICR_ISC25_Msk (0x1UL << HSEM_C2ICR_ISC25_Pos) /*!< 0x02000000 */ 5400 #define HSEM_C2ICR_ISC25 HSEM_C2ICR_ISC25_Msk /*!<semaphore 25 CPU2 interrupt clear bit. */ 5401 #define HSEM_C2ICR_ISC26_Pos (26U) 5402 #define HSEM_C2ICR_ISC26_Msk (0x1UL << HSEM_C2ICR_ISC26_Pos) /*!< 0x04000000 */ 5403 #define HSEM_C2ICR_ISC26 HSEM_C2ICR_ISC26_Msk /*!<semaphore 26 CPU2 interrupt clear bit. */ 5404 #define HSEM_C2ICR_ISC27_Pos (27U) 5405 #define HSEM_C2ICR_ISC27_Msk (0x1UL << HSEM_C2ICR_ISC27_Pos) /*!< 0x08000000 */ 5406 #define HSEM_C2ICR_ISC27 HSEM_C2ICR_ISC27_Msk /*!<semaphore 27 CPU2 interrupt clear bit. */ 5407 #define HSEM_C2ICR_ISC28_Pos (28U) 5408 #define HSEM_C2ICR_ISC28_Msk (0x1UL << HSEM_C2ICR_ISC28_Pos) /*!< 0x10000000 */ 5409 #define HSEM_C2ICR_ISC28 HSEM_C2ICR_ISC28_Msk /*!<semaphore 28 CPU2 interrupt clear bit. */ 5410 #define HSEM_C2ICR_ISC29_Pos (29U) 5411 #define HSEM_C2ICR_ISC29_Msk (0x1UL << HSEM_C2ICR_ISC29_Pos) /*!< 0x20000000 */ 5412 #define HSEM_C2ICR_ISC29 HSEM_C2ICR_ISC29_Msk /*!<semaphore 29 CPU2 interrupt clear bit. */ 5413 #define HSEM_C2ICR_ISC30_Pos (30U) 5414 #define HSEM_C2ICR_ISC30_Msk (0x1UL << HSEM_C2ICR_ISC30_Pos) /*!< 0x40000000 */ 5415 #define HSEM_C2ICR_ISC30 HSEM_C2ICR_ISC30_Msk /*!<semaphore 30 CPU2 interrupt clear bit. */ 5416 #define HSEM_C2ICR_ISC31_Pos (31U) 5417 #define HSEM_C2ICR_ISC31_Msk (0x1UL << HSEM_C2ICR_ISC31_Pos) /*!< 0x80000000 */ 5418 #define HSEM_C2ICR_ISC31 HSEM_C2ICR_ISC31_Msk /*!<semaphore 31 CPU2 interrupt clear bit. */ 5419 5420 /******************** Bit definition for HSEM_C2ISR register *****************/ 5421 #define HSEM_C2ISR_ISF0_Pos (0U) 5422 #define HSEM_C2ISR_ISF0_Msk (0x1UL << HSEM_C2ISR_ISF0_Pos) /*!< 0x00000001 */ 5423 #define HSEM_C2ISR_ISF0 HSEM_C2ISR_ISF0_Msk /*!<semaphore 0 CPU2 interrupt status bit. */ 5424 #define HSEM_C2ISR_ISF1_Pos (1U) 5425 #define HSEM_C2ISR_ISF1_Msk (0x1UL << HSEM_C2ISR_ISF1_Pos) /*!< 0x00000002 */ 5426 #define HSEM_C2ISR_ISF1 HSEM_C2ISR_ISF1_Msk /*!<semaphore 1 CPU2 interrupt status bit. */ 5427 #define HSEM_C2ISR_ISF2_Pos (2U) 5428 #define HSEM_C2ISR_ISF2_Msk (0x1UL << HSEM_C2ISR_ISF2_Pos) /*!< 0x00000004 */ 5429 #define HSEM_C2ISR_ISF2 HSEM_C2ISR_ISF2_Msk /*!<semaphore 2 CPU2 interrupt status bit. */ 5430 #define HSEM_C2ISR_ISF3_Pos (3U) 5431 #define HSEM_C2ISR_ISF3_Msk (0x1UL << HSEM_C2ISR_ISF3_Pos) /*!< 0x00000008 */ 5432 #define HSEM_C2ISR_ISF3 HSEM_C2ISR_ISF3_Msk /*!<semaphore 3 CPU2 interrupt status bit. */ 5433 #define HSEM_C2ISR_ISF4_Pos (4U) 5434 #define HSEM_C2ISR_ISF4_Msk (0x1UL << HSEM_C2ISR_ISF4_Pos) /*!< 0x00000010 */ 5435 #define HSEM_C2ISR_ISF4 HSEM_C2ISR_ISF4_Msk /*!<semaphore 4 CPU2 interrupt status bit. */ 5436 #define HSEM_C2ISR_ISF5_Pos (5U) 5437 #define HSEM_C2ISR_ISF5_Msk (0x1UL << HSEM_C2ISR_ISF5_Pos) /*!< 0x00000020 */ 5438 #define HSEM_C2ISR_ISF5 HSEM_C2ISR_ISF5_Msk /*!<semaphore 5 CPU2 interrupt status bit. */ 5439 #define HSEM_C2ISR_ISF6_Pos (6U) 5440 #define HSEM_C2ISR_ISF6_Msk (0x1UL << HSEM_C2ISR_ISF6_Pos) /*!< 0x00000040 */ 5441 #define HSEM_C2ISR_ISF6 HSEM_C2ISR_ISF6_Msk /*!<semaphore 6 CPU2 interrupt status bit. */ 5442 #define HSEM_C2ISR_ISF7_Pos (7U) 5443 #define HSEM_C2ISR_ISF7_Msk (0x1UL << HSEM_C2ISR_ISF7_Pos) /*!< 0x00000080 */ 5444 #define HSEM_C2ISR_ISF7 HSEM_C2ISR_ISF7_Msk /*!<semaphore 7 CPU2 interrupt status bit. */ 5445 #define HSEM_C2ISR_ISF8_Pos (8U) 5446 #define HSEM_C2ISR_ISF8_Msk (0x1UL << HSEM_C2ISR_ISF8_Pos) /*!< 0x00000100 */ 5447 #define HSEM_C2ISR_ISF8 HSEM_C2ISR_ISF8_Msk /*!<semaphore 8 CPU2 interrupt status bit. */ 5448 #define HSEM_C2ISR_ISF9_Pos (9U) 5449 #define HSEM_C2ISR_ISF9_Msk (0x1UL << HSEM_C2ISR_ISF9_Pos) /*!< 0x00000200 */ 5450 #define HSEM_C2ISR_ISF9 HSEM_C2ISR_ISF9_Msk /*!<semaphore 9 CPU2 interrupt status bit. */ 5451 #define HSEM_C2ISR_ISF10_Pos (10U) 5452 #define HSEM_C2ISR_ISF10_Msk (0x1UL << HSEM_C2ISR_ISF10_Pos) /*!< 0x00000400 */ 5453 #define HSEM_C2ISR_ISF10 HSEM_C2ISR_ISF10_Msk /*!<semaphore 10 CPU2 interrupt status bit. */ 5454 #define HSEM_C2ISR_ISF11_Pos (11U) 5455 #define HSEM_C2ISR_ISF11_Msk (0x1UL << HSEM_C2ISR_ISF11_Pos) /*!< 0x00000800 */ 5456 #define HSEM_C2ISR_ISF11 HSEM_C2ISR_ISF11_Msk /*!<semaphore 11 CPU2 interrupt status bit. */ 5457 #define HSEM_C2ISR_ISF12_Pos (12U) 5458 #define HSEM_C2ISR_ISF12_Msk (0x1UL << HSEM_C2ISR_ISF12_Pos) /*!< 0x00001000 */ 5459 #define HSEM_C2ISR_ISF12 HSEM_C2ISR_ISF12_Msk /*!<semaphore 12 CPU2 interrupt status bit. */ 5460 #define HSEM_C2ISR_ISF13_Pos (13U) 5461 #define HSEM_C2ISR_ISF13_Msk (0x1UL << HSEM_C2ISR_ISF13_Pos) /*!< 0x00002000 */ 5462 #define HSEM_C2ISR_ISF13 HSEM_C2ISR_ISF13_Msk /*!<semaphore 13 CPU2 interrupt status bit. */ 5463 #define HSEM_C2ISR_ISF14_Pos (14U) 5464 #define HSEM_C2ISR_ISF14_Msk (0x1UL << HSEM_C2ISR_ISF14_Pos) /*!< 0x00004000 */ 5465 #define HSEM_C2ISR_ISF14 HSEM_C2ISR_ISF14_Msk /*!<semaphore 14 CPU2 interrupt status bit. */ 5466 #define HSEM_C2ISR_ISF15_Pos (15U) 5467 #define HSEM_C2ISR_ISF15_Msk (0x1UL << HSEM_C2ISR_ISF15_Pos) /*!< 0x00008000 */ 5468 #define HSEM_C2ISR_ISF15 HSEM_C2ISR_ISF15_Msk /*!<semaphore 15 CPU2 interrupt status bit. */ 5469 #define HSEM_C2ISR_ISF16_Pos (16U) 5470 #define HSEM_C2ISR_ISF16_Msk (0x1UL << HSEM_C2ISR_ISF16_Pos) /*!< 0x00010000 */ 5471 #define HSEM_C2ISR_ISF16 HSEM_C2ISR_ISF16_Msk /*!<semaphore 16 CPU2 interrupt status bit. */ 5472 #define HSEM_C2ISR_ISF17_Pos (17U) 5473 #define HSEM_C2ISR_ISF17_Msk (0x1UL << HSEM_C2ISR_ISF17_Pos) /*!< 0x00020000 */ 5474 #define HSEM_C2ISR_ISF17 HSEM_C2ISR_ISF17_Msk /*!<semaphore 17 CPU2 interrupt status bit. */ 5475 #define HSEM_C2ISR_ISF18_Pos (18U) 5476 #define HSEM_C2ISR_ISF18_Msk (0x1UL << HSEM_C2ISR_ISF18_Pos) /*!< 0x00040000 */ 5477 #define HSEM_C2ISR_ISF18 HSEM_C2ISR_ISF18_Msk /*!<semaphore 18 CPU2 interrupt status bit. */ 5478 #define HSEM_C2ISR_ISF19_Pos (19U) 5479 #define HSEM_C2ISR_ISF19_Msk (0x1UL << HSEM_C2ISR_ISF19_Pos) /*!< 0x00080000 */ 5480 #define HSEM_C2ISR_ISF19 HSEM_C2ISR_ISF19_Msk /*!<semaphore 19 CPU2 interrupt status bit. */ 5481 #define HSEM_C2ISR_ISF20_Pos (20U) 5482 #define HSEM_C2ISR_ISF20_Msk (0x1UL << HSEM_C2ISR_ISF20_Pos) /*!< 0x00100000 */ 5483 #define HSEM_C2ISR_ISF20 HSEM_C2ISR_ISF20_Msk /*!<semaphore 20 CPU2 interrupt status bit. */ 5484 #define HSEM_C2ISR_ISF21_Pos (21U) 5485 #define HSEM_C2ISR_ISF21_Msk (0x1UL << HSEM_C2ISR_ISF21_Pos) /*!< 0x00200000 */ 5486 #define HSEM_C2ISR_ISF21 HSEM_C2ISR_ISF21_Msk /*!<semaphore 21 CPU2 interrupt status bit. */ 5487 #define HSEM_C2ISR_ISF22_Pos (22U) 5488 #define HSEM_C2ISR_ISF22_Msk (0x1UL << HSEM_C2ISR_ISF22_Pos) /*!< 0x00400000 */ 5489 #define HSEM_C2ISR_ISF22 HSEM_C2ISR_ISF22_Msk /*!<semaphore 22 CPU2 interrupt status bit. */ 5490 #define HSEM_C2ISR_ISF23_Pos (23U) 5491 #define HSEM_C2ISR_ISF23_Msk (0x1UL << HSEM_C2ISR_ISF23_Pos) /*!< 0x00800000 */ 5492 #define HSEM_C2ISR_ISF23 HSEM_C2ISR_ISF23_Msk /*!<semaphore 23 CPU2 interrupt status bit. */ 5493 #define HSEM_C2ISR_ISF24_Pos (24U) 5494 #define HSEM_C2ISR_ISF24_Msk (0x1UL << HSEM_C2ISR_ISF24_Pos) /*!< 0x01000000 */ 5495 #define HSEM_C2ISR_ISF24 HSEM_C2ISR_ISF24_Msk /*!<semaphore 24 CPU2 interrupt status bit. */ 5496 #define HSEM_C2ISR_ISF25_Pos (25U) 5497 #define HSEM_C2ISR_ISF25_Msk (0x1UL << HSEM_C2ISR_ISF25_Pos) /*!< 0x02000000 */ 5498 #define HSEM_C2ISR_ISF25 HSEM_C2ISR_ISF25_Msk /*!<semaphore 25 CPU2 interrupt status bit. */ 5499 #define HSEM_C2ISR_ISF26_Pos (26U) 5500 #define HSEM_C2ISR_ISF26_Msk (0x1UL << HSEM_C2ISR_ISF26_Pos) /*!< 0x04000000 */ 5501 #define HSEM_C2ISR_ISF26 HSEM_C2ISR_ISF26_Msk /*!<semaphore 26 CPU2 interrupt status bit. */ 5502 #define HSEM_C2ISR_ISF27_Pos (27U) 5503 #define HSEM_C2ISR_ISF27_Msk (0x1UL << HSEM_C2ISR_ISF27_Pos) /*!< 0x08000000 */ 5504 #define HSEM_C2ISR_ISF27 HSEM_C2ISR_ISF27_Msk /*!<semaphore 27 CPU2 interrupt status bit. */ 5505 #define HSEM_C2ISR_ISF28_Pos (28U) 5506 #define HSEM_C2ISR_ISF28_Msk (0x1UL << HSEM_C2ISR_ISF28_Pos) /*!< 0x10000000 */ 5507 #define HSEM_C2ISR_ISF28 HSEM_C2ISR_ISF28_Msk /*!<semaphore 28 CPU2 interrupt status bit. */ 5508 #define HSEM_C2ISR_ISF29_Pos (29U) 5509 #define HSEM_C2ISR_ISF29_Msk (0x1UL << HSEM_C2ISR_ISF29_Pos) /*!< 0x20000000 */ 5510 #define HSEM_C2ISR_ISF29 HSEM_C2ISR_ISF29_Msk /*!<semaphore 29 CPU2 interrupt status bit. */ 5511 #define HSEM_C2ISR_ISF30_Pos (30U) 5512 #define HSEM_C2ISR_ISF30_Msk (0x1UL << HSEM_C2ISR_ISF30_Pos) /*!< 0x40000000 */ 5513 #define HSEM_C2ISR_ISF30 HSEM_C2ISR_ISF30_Msk /*!<semaphore 30 CPU2 interrupt status bit. */ 5514 #define HSEM_C2ISR_ISF31_Pos (31U) 5515 #define HSEM_C2ISR_ISF31_Msk (0x1UL << HSEM_C2ISR_ISF31_Pos) /*!< 0x80000000 */ 5516 #define HSEM_C2ISR_ISF31 HSEM_C2ISR_ISF31_Msk /*!<semaphore 31 CPU2 interrupt status bit. */ 5517 5518 /******************** Bit definition for HSEM_C2MISR register *****************/ 5519 #define HSEM_C2MISR_MISF0_Pos (0U) 5520 #define HSEM_C2MISR_MISF0_Msk (0x1UL << HSEM_C2MISR_MISF0_Pos) /*!< 0x00000001 */ 5521 #define HSEM_C2MISR_MISF0 HSEM_C2MISR_MISF0_Msk /*!<semaphore 0 CPU2 interrupt masked status bit. */ 5522 #define HSEM_C2MISR_MISF1_Pos (1U) 5523 #define HSEM_C2MISR_MISF1_Msk (0x1UL << HSEM_C2MISR_MISF1_Pos) /*!< 0x00000002 */ 5524 #define HSEM_C2MISR_MISF1 HSEM_C2MISR_MISF1_Msk /*!<semaphore 1 CPU2 interrupt masked status bit. */ 5525 #define HSEM_C2MISR_MISF2_Pos (2U) 5526 #define HSEM_C2MISR_MISF2_Msk (0x1UL << HSEM_C2MISR_MISF2_Pos) /*!< 0x00000004 */ 5527 #define HSEM_C2MISR_MISF2 HSEM_C2MISR_MISF2_Msk /*!<semaphore 2 CPU2 interrupt masked status bit. */ 5528 #define HSEM_C2MISR_MISF3_Pos (3U) 5529 #define HSEM_C2MISR_MISF3_Msk (0x1UL << HSEM_C2MISR_MISF3_Pos) /*!< 0x00000008 */ 5530 #define HSEM_C2MISR_MISF3 HSEM_C2MISR_MISF3_Msk /*!<semaphore 3 CPU2 interrupt masked status bit. */ 5531 #define HSEM_C2MISR_MISF4_Pos (4U) 5532 #define HSEM_C2MISR_MISF4_Msk (0x1UL << HSEM_C2MISR_MISF4_Pos) /*!< 0x00000010 */ 5533 #define HSEM_C2MISR_MISF4 HSEM_C2MISR_MISF4_Msk /*!<semaphore 4 CPU2 interrupt masked status bit. */ 5534 #define HSEM_C2MISR_MISF5_Pos (5U) 5535 #define HSEM_C2MISR_MISF5_Msk (0x1UL << HSEM_C2MISR_MISF5_Pos) /*!< 0x00000020 */ 5536 #define HSEM_C2MISR_MISF5 HSEM_C2MISR_MISF5_Msk /*!<semaphore 5 CPU2 interrupt masked status bit. */ 5537 #define HSEM_C2MISR_MISF6_Pos (6U) 5538 #define HSEM_C2MISR_MISF6_Msk (0x1UL << HSEM_C2MISR_MISF6_Pos) /*!< 0x00000040 */ 5539 #define HSEM_C2MISR_MISF6 HSEM_C2MISR_MISF6_Msk /*!<semaphore 6 CPU2 interrupt masked status bit. */ 5540 #define HSEM_C2MISR_MISF7_Pos (7U) 5541 #define HSEM_C2MISR_MISF7_Msk (0x1UL << HSEM_C2MISR_MISF7_Pos) /*!< 0x00000080 */ 5542 #define HSEM_C2MISR_MISF7 HSEM_C2MISR_MISF7_Msk /*!<semaphore 7 CPU2 interrupt masked status bit. */ 5543 #define HSEM_C2MISR_MISF8_Pos (8U) 5544 #define HSEM_C2MISR_MISF8_Msk (0x1UL << HSEM_C2MISR_MISF8_Pos) /*!< 0x00000100 */ 5545 #define HSEM_C2MISR_MISF8 HSEM_C2MISR_MISF8_Msk /*!<semaphore 8 CPU2 interrupt masked status bit. */ 5546 #define HSEM_C2MISR_MISF9_Pos (9U) 5547 #define HSEM_C2MISR_MISF9_Msk (0x1UL << HSEM_C2MISR_MISF9_Pos) /*!< 0x00000200 */ 5548 #define HSEM_C2MISR_MISF9 HSEM_C2MISR_MISF9_Msk /*!<semaphore 9 CPU2 interrupt masked status bit. */ 5549 #define HSEM_C2MISR_MISF10_Pos (10U) 5550 #define HSEM_C2MISR_MISF10_Msk (0x1UL << HSEM_C2MISR_MISF10_Pos) /*!< 0x00000400 */ 5551 #define HSEM_C2MISR_MISF10 HSEM_C2MISR_MISF10_Msk /*!<semaphore 10 CPU2 interrupt masked status bit. */ 5552 #define HSEM_C2MISR_MISF11_Pos (11U) 5553 #define HSEM_C2MISR_MISF11_Msk (0x1UL << HSEM_C2MISR_MISF11_Pos) /*!< 0x00000800 */ 5554 #define HSEM_C2MISR_MISF11 HSEM_C2MISR_MISF11_Msk /*!<semaphore 11 CPU2 interrupt masked status bit. */ 5555 #define HSEM_C2MISR_MISF12_Pos (12U) 5556 #define HSEM_C2MISR_MISF12_Msk (0x1UL << HSEM_C2MISR_MISF12_Pos) /*!< 0x00001000 */ 5557 #define HSEM_C2MISR_MISF12 HSEM_C2MISR_MISF12_Msk /*!<semaphore 12 CPU2 interrupt masked status bit. */ 5558 #define HSEM_C2MISR_MISF13_Pos (13U) 5559 #define HSEM_C2MISR_MISF13_Msk (0x1UL << HSEM_C2MISR_MISF13_Pos) /*!< 0x00002000 */ 5560 #define HSEM_C2MISR_MISF13 HSEM_C2MISR_MISF13_Msk /*!<semaphore 13 CPU2 interrupt masked status bit. */ 5561 #define HSEM_C2MISR_MISF14_Pos (14U) 5562 #define HSEM_C2MISR_MISF14_Msk (0x1UL << HSEM_C2MISR_MISF14_Pos) /*!< 0x00004000 */ 5563 #define HSEM_C2MISR_MISF14 HSEM_C2MISR_MISF14_Msk /*!<semaphore 14 CPU2 interrupt masked status bit. */ 5564 #define HSEM_C2MISR_MISF15_Pos (15U) 5565 #define HSEM_C2MISR_MISF15_Msk (0x1UL << HSEM_C2MISR_MISF15_Pos) /*!< 0x00008000 */ 5566 #define HSEM_C2MISR_MISF15 HSEM_C2MISR_MISF15_Msk /*!<semaphore 15 CPU2 interrupt masked status bit. */ 5567 #define HSEM_C2MISR_MISF16_Pos (16U) 5568 #define HSEM_C2MISR_MISF16_Msk (0x1UL << HSEM_C2MISR_MISF16_Pos) /*!< 0x00010000 */ 5569 #define HSEM_C2MISR_MISF16 HSEM_C2MISR_MISF16_Msk /*!<semaphore 16 CPU2 interrupt masked status bit. */ 5570 #define HSEM_C2MISR_MISF17_Pos (17U) 5571 #define HSEM_C2MISR_MISF17_Msk (0x1UL << HSEM_C2MISR_MISF17_Pos) /*!< 0x00020000 */ 5572 #define HSEM_C2MISR_MISF17 HSEM_C2MISR_MISF17_Msk /*!<semaphore 17 CPU2 interrupt masked status bit. */ 5573 #define HSEM_C2MISR_MISF18_Pos (18U) 5574 #define HSEM_C2MISR_MISF18_Msk (0x1UL << HSEM_C2MISR_MISF18_Pos) /*!< 0x00040000 */ 5575 #define HSEM_C2MISR_MISF18 HSEM_C2MISR_MISF18_Msk /*!<semaphore 18 CPU2 interrupt masked status bit. */ 5576 #define HSEM_C2MISR_MISF19_Pos (19U) 5577 #define HSEM_C2MISR_MISF19_Msk (0x1UL << HSEM_C2MISR_MISF19_Pos) /*!< 0x00080000 */ 5578 #define HSEM_C2MISR_MISF19 HSEM_C2MISR_MISF19_Msk /*!<semaphore 19 CPU2 interrupt masked status bit. */ 5579 #define HSEM_C2MISR_MISF20_Pos (20U) 5580 #define HSEM_C2MISR_MISF20_Msk (0x1UL << HSEM_C2MISR_MISF20_Pos) /*!< 0x00100000 */ 5581 #define HSEM_C2MISR_MISF20 HSEM_C2MISR_MISF20_Msk /*!<semaphore 20 CPU2 interrupt masked status bit. */ 5582 #define HSEM_C2MISR_MISF21_Pos (21U) 5583 #define HSEM_C2MISR_MISF21_Msk (0x1UL << HSEM_C2MISR_MISF21_Pos) /*!< 0x00200000 */ 5584 #define HSEM_C2MISR_MISF21 HSEM_C2MISR_MISF21_Msk /*!<semaphore 21 CPU2 interrupt masked status bit. */ 5585 #define HSEM_C2MISR_MISF22_Pos (22U) 5586 #define HSEM_C2MISR_MISF22_Msk (0x1UL << HSEM_C2MISR_MISF22_Pos) /*!< 0x00400000 */ 5587 #define HSEM_C2MISR_MISF22 HSEM_C2MISR_MISF22_Msk /*!<semaphore 22 CPU2 interrupt masked status bit. */ 5588 #define HSEM_C2MISR_MISF23_Pos (23U) 5589 #define HSEM_C2MISR_MISF23_Msk (0x1UL << HSEM_C2MISR_MISF23_Pos) /*!< 0x00800000 */ 5590 #define HSEM_C2MISR_MISF23 HSEM_C2MISR_MISF23_Msk /*!<semaphore 23 CPU2 interrupt masked status bit. */ 5591 #define HSEM_C2MISR_MISF24_Pos (24U) 5592 #define HSEM_C2MISR_MISF24_Msk (0x1UL << HSEM_C2MISR_MISF24_Pos) /*!< 0x01000000 */ 5593 #define HSEM_C2MISR_MISF24 HSEM_C2MISR_MISF24_Msk /*!<semaphore 24 CPU2 interrupt masked status bit. */ 5594 #define HSEM_C2MISR_MISF25_Pos (25U) 5595 #define HSEM_C2MISR_MISF25_Msk (0x1UL << HSEM_C2MISR_MISF25_Pos) /*!< 0x02000000 */ 5596 #define HSEM_C2MISR_MISF25 HSEM_C2MISR_MISF25_Msk /*!<semaphore 25 CPU2 interrupt masked status bit. */ 5597 #define HSEM_C2MISR_MISF26_Pos (26U) 5598 #define HSEM_C2MISR_MISF26_Msk (0x1UL << HSEM_C2MISR_MISF26_Pos) /*!< 0x04000000 */ 5599 #define HSEM_C2MISR_MISF26 HSEM_C2MISR_MISF26_Msk /*!<semaphore 26 CPU2 interrupt masked status bit. */ 5600 #define HSEM_C2MISR_MISF27_Pos (27U) 5601 #define HSEM_C2MISR_MISF27_Msk (0x1UL << HSEM_C2MISR_MISF27_Pos) /*!< 0x08000000 */ 5602 #define HSEM_C2MISR_MISF27 HSEM_C2MISR_MISF27_Msk /*!<semaphore 27 CPU2 interrupt masked status bit. */ 5603 #define HSEM_C2MISR_MISF28_Pos (28U) 5604 #define HSEM_C2MISR_MISF28_Msk (0x1UL << HSEM_C2MISR_MISF28_Pos) /*!< 0x10000000 */ 5605 #define HSEM_C2MISR_MISF28 HSEM_C2MISR_MISF28_Msk /*!<semaphore 28 CPU2 interrupt masked status bit. */ 5606 #define HSEM_C2MISR_MISF29_Pos (29U) 5607 #define HSEM_C2MISR_MISF29_Msk (0x1UL << HSEM_C2MISR_MISF29_Pos) /*!< 0x20000000 */ 5608 #define HSEM_C2MISR_MISF29 HSEM_C2MISR_MISF29_Msk /*!<semaphore 29 CPU2 interrupt masked status bit. */ 5609 #define HSEM_C2MISR_MISF30_Pos (30U) 5610 #define HSEM_C2MISR_MISF30_Msk (0x1UL << HSEM_C2MISR_MISF30_Pos) /*!< 0x40000000 */ 5611 #define HSEM_C2MISR_MISF30 HSEM_C2MISR_MISF30_Msk /*!<semaphore 30 CPU2 interrupt masked status bit. */ 5612 #define HSEM_C2MISR_MISF31_Pos (31U) 5613 #define HSEM_C2MISR_MISF31_Msk (0x1UL << HSEM_C2MISR_MISF31_Pos) /*!< 0x80000000 */ 5614 #define HSEM_C2MISR_MISF31 HSEM_C2MISR_MISF31_Msk /*!<semaphore 31 CPU2 interrupt masked status bit. */ 5615 5616 /******************** Bit definition for HSEM_CR register *****************/ 5617 #define HSEM_CR_COREID_Pos (8U) 5618 #define HSEM_CR_COREID_Msk (0xFUL << HSEM_CR_COREID_Pos) /*!< 0x00000F00 */ 5619 #define HSEM_CR_COREID HSEM_CR_COREID_Msk /*!<CoreID of semaphores to be cleared. */ 5620 #define HSEM_CR_COREID_CPU1 (0x4U << HSEM_CR_COREID_Pos) 5621 #define HSEM_CR_COREID_CPU2 (0x8U << HSEM_CR_COREID_Pos) 5622 #define HSEM_CR_COREID_CURRENT HSEM_CR_COREID_CPU1 5623 #define HSEM_CR_KEY_Pos (16U) 5624 #define HSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos) /*!< 0xFFFF0000 */ 5625 #define HSEM_CR_KEY HSEM_CR_KEY_Msk /*!<semaphores clear key. */ 5626 5627 /******************** Bit definition for HSEM_KEYR register *****************/ 5628 #define HSEM_KEYR_KEY_Pos (16U) 5629 #define HSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos) /*!< 0xFFFF0000 */ 5630 #define HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk /*!<semaphores clear key. */ 5631 5632 /******************************************************************************/ 5633 /* */ 5634 /* Inter-integrated Circuit Interface (I2C) */ 5635 /* */ 5636 /******************************************************************************/ 5637 /******************* Bit definition for I2C_CR1 register *******************/ 5638 #define I2C_CR1_PE_Pos (0U) 5639 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 5640 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ 5641 #define I2C_CR1_TXIE_Pos (1U) 5642 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ 5643 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ 5644 #define I2C_CR1_RXIE_Pos (2U) 5645 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ 5646 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ 5647 #define I2C_CR1_ADDRIE_Pos (3U) 5648 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ 5649 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ 5650 #define I2C_CR1_NACKIE_Pos (4U) 5651 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ 5652 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ 5653 #define I2C_CR1_STOPIE_Pos (5U) 5654 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ 5655 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ 5656 #define I2C_CR1_TCIE_Pos (6U) 5657 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ 5658 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ 5659 #define I2C_CR1_ERRIE_Pos (7U) 5660 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ 5661 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ 5662 #define I2C_CR1_DNF_Pos (8U) 5663 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ 5664 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ 5665 #define I2C_CR1_ANFOFF_Pos (12U) 5666 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ 5667 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ 5668 #define I2C_CR1_SWRST_Pos (13U) 5669 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ 5670 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ 5671 #define I2C_CR1_TXDMAEN_Pos (14U) 5672 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ 5673 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ 5674 #define I2C_CR1_RXDMAEN_Pos (15U) 5675 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ 5676 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ 5677 #define I2C_CR1_SBC_Pos (16U) 5678 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ 5679 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ 5680 #define I2C_CR1_NOSTRETCH_Pos (17U) 5681 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ 5682 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ 5683 #define I2C_CR1_WUPEN_Pos (18U) 5684 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ 5685 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ 5686 #define I2C_CR1_GCEN_Pos (19U) 5687 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ 5688 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ 5689 #define I2C_CR1_SMBHEN_Pos (20U) 5690 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ 5691 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ 5692 #define I2C_CR1_SMBDEN_Pos (21U) 5693 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ 5694 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ 5695 #define I2C_CR1_ALERTEN_Pos (22U) 5696 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ 5697 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ 5698 #define I2C_CR1_PECEN_Pos (23U) 5699 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ 5700 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ 5701 5702 /****************** Bit definition for I2C_CR2 register ********************/ 5703 #define I2C_CR2_SADD_Pos (0U) 5704 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ 5705 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ 5706 #define I2C_CR2_RD_WRN_Pos (10U) 5707 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ 5708 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ 5709 #define I2C_CR2_ADD10_Pos (11U) 5710 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ 5711 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ 5712 #define I2C_CR2_HEAD10R_Pos (12U) 5713 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ 5714 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ 5715 #define I2C_CR2_START_Pos (13U) 5716 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ 5717 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ 5718 #define I2C_CR2_STOP_Pos (14U) 5719 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ 5720 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ 5721 #define I2C_CR2_NACK_Pos (15U) 5722 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ 5723 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ 5724 #define I2C_CR2_NBYTES_Pos (16U) 5725 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ 5726 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ 5727 #define I2C_CR2_RELOAD_Pos (24U) 5728 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ 5729 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ 5730 #define I2C_CR2_AUTOEND_Pos (25U) 5731 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ 5732 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ 5733 #define I2C_CR2_PECBYTE_Pos (26U) 5734 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ 5735 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ 5736 5737 /******************* Bit definition for I2C_OAR1 register ******************/ 5738 #define I2C_OAR1_OA1_Pos (0U) 5739 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ 5740 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ 5741 #define I2C_OAR1_OA1MODE_Pos (10U) 5742 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ 5743 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ 5744 #define I2C_OAR1_OA1EN_Pos (15U) 5745 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ 5746 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ 5747 5748 /******************* Bit definition for I2C_OAR2 register ******************/ 5749 #define I2C_OAR2_OA2_Pos (1U) 5750 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ 5751 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ 5752 #define I2C_OAR2_OA2MSK_Pos (8U) 5753 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ 5754 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ 5755 #define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ 5756 #define I2C_OAR2_OA2MASK01_Pos (8U) 5757 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ 5758 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ 5759 #define I2C_OAR2_OA2MASK02_Pos (9U) 5760 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ 5761 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ 5762 #define I2C_OAR2_OA2MASK03_Pos (8U) 5763 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ 5764 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ 5765 #define I2C_OAR2_OA2MASK04_Pos (10U) 5766 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ 5767 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ 5768 #define I2C_OAR2_OA2MASK05_Pos (8U) 5769 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ 5770 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ 5771 #define I2C_OAR2_OA2MASK06_Pos (9U) 5772 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ 5773 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ 5774 #define I2C_OAR2_OA2MASK07_Pos (8U) 5775 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ 5776 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ 5777 #define I2C_OAR2_OA2EN_Pos (15U) 5778 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ 5779 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ 5780 5781 /******************* Bit definition for I2C_TIMINGR register *******************/ 5782 #define I2C_TIMINGR_SCLL_Pos (0U) 5783 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ 5784 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ 5785 #define I2C_TIMINGR_SCLH_Pos (8U) 5786 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ 5787 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ 5788 #define I2C_TIMINGR_SDADEL_Pos (16U) 5789 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ 5790 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ 5791 #define I2C_TIMINGR_SCLDEL_Pos (20U) 5792 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ 5793 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ 5794 #define I2C_TIMINGR_PRESC_Pos (28U) 5795 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ 5796 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ 5797 5798 /******************* Bit definition for I2C_TIMEOUTR register *******************/ 5799 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) 5800 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ 5801 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ 5802 #define I2C_TIMEOUTR_TIDLE_Pos (12U) 5803 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ 5804 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ 5805 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) 5806 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ 5807 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ 5808 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) 5809 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ 5810 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ 5811 #define I2C_TIMEOUTR_TEXTEN_Pos (31U) 5812 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ 5813 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ 5814 5815 /****************** Bit definition for I2C_ISR register *********************/ 5816 #define I2C_ISR_TXE_Pos (0U) 5817 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ 5818 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ 5819 #define I2C_ISR_TXIS_Pos (1U) 5820 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ 5821 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ 5822 #define I2C_ISR_RXNE_Pos (2U) 5823 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ 5824 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ 5825 #define I2C_ISR_ADDR_Pos (3U) 5826 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ 5827 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ 5828 #define I2C_ISR_NACKF_Pos (4U) 5829 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ 5830 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ 5831 #define I2C_ISR_STOPF_Pos (5U) 5832 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ 5833 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ 5834 #define I2C_ISR_TC_Pos (6U) 5835 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ 5836 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ 5837 #define I2C_ISR_TCR_Pos (7U) 5838 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ 5839 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ 5840 #define I2C_ISR_BERR_Pos (8U) 5841 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ 5842 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ 5843 #define I2C_ISR_ARLO_Pos (9U) 5844 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ 5845 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ 5846 #define I2C_ISR_OVR_Pos (10U) 5847 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ 5848 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ 5849 #define I2C_ISR_PECERR_Pos (11U) 5850 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ 5851 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ 5852 #define I2C_ISR_TIMEOUT_Pos (12U) 5853 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ 5854 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ 5855 #define I2C_ISR_ALERT_Pos (13U) 5856 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ 5857 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ 5858 #define I2C_ISR_BUSY_Pos (15U) 5859 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ 5860 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ 5861 #define I2C_ISR_DIR_Pos (16U) 5862 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ 5863 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ 5864 #define I2C_ISR_ADDCODE_Pos (17U) 5865 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ 5866 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ 5867 5868 /****************** Bit definition for I2C_ICR register *********************/ 5869 #define I2C_ICR_ADDRCF_Pos (3U) 5870 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ 5871 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ 5872 #define I2C_ICR_NACKCF_Pos (4U) 5873 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ 5874 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ 5875 #define I2C_ICR_STOPCF_Pos (5U) 5876 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ 5877 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ 5878 #define I2C_ICR_BERRCF_Pos (8U) 5879 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ 5880 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ 5881 #define I2C_ICR_ARLOCF_Pos (9U) 5882 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ 5883 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ 5884 #define I2C_ICR_OVRCF_Pos (10U) 5885 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ 5886 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ 5887 #define I2C_ICR_PECCF_Pos (11U) 5888 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ 5889 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ 5890 #define I2C_ICR_TIMOUTCF_Pos (12U) 5891 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ 5892 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ 5893 #define I2C_ICR_ALERTCF_Pos (13U) 5894 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ 5895 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ 5896 5897 /****************** Bit definition for I2C_PECR register *********************/ 5898 #define I2C_PECR_PEC_Pos (0U) 5899 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ 5900 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ 5901 5902 /****************** Bit definition for I2C_RXDR register *********************/ 5903 #define I2C_RXDR_RXDATA_Pos (0U) 5904 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ 5905 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ 5906 5907 /****************** Bit definition for I2C_TXDR register *********************/ 5908 #define I2C_TXDR_TXDATA_Pos (0U) 5909 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ 5910 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ 5911 5912 /******************************************************************************/ 5913 /* */ 5914 /* Independent WATCHDOG (IWDG) */ 5915 /* */ 5916 /******************************************************************************/ 5917 /******************* Bit definition for IWDG_KR register ********************/ 5918 #define IWDG_KR_KEY_Pos (0U) 5919 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 5920 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */ 5921 5922 /******************* Bit definition for IWDG_PR register ********************/ 5923 #define IWDG_PR_PR_Pos (0U) 5924 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 5925 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */ 5926 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */ 5927 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */ 5928 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */ 5929 5930 /******************* Bit definition for IWDG_RLR register *******************/ 5931 #define IWDG_RLR_RL_Pos (0U) 5932 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 5933 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */ 5934 5935 /******************* Bit definition for IWDG_SR register ********************/ 5936 #define IWDG_SR_PVU_Pos (0U) 5937 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 5938 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 5939 #define IWDG_SR_RVU_Pos (1U) 5940 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 5941 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 5942 #define IWDG_SR_WVU_Pos (2U) 5943 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ 5944 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ 5945 5946 /******************* Bit definition for IWDG_KR register ********************/ 5947 #define IWDG_WINR_WIN_Pos (0U) 5948 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ 5949 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ 5950 5951 /******************************************************************************/ 5952 /* */ 5953 /* Power Control */ 5954 /* */ 5955 /******************************************************************************/ 5956 5957 /******************** Bit definition for PWR_CR1 register ********************/ 5958 #define PWR_CR1_LPMS_Pos (0U) 5959 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */ 5960 #define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low Power Mode Selection for CPU1 */ 5961 #define PWR_CR1_LPMS_0 (0x1U << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */ 5962 #define PWR_CR1_LPMS_1 (0x2U << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */ 5963 #define PWR_CR1_LPMS_2 (0x4U << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */ 5964 5965 #define PWR_CR1_FPDR_Pos (4U) 5966 #define PWR_CR1_FPDR_Msk (0x1UL << PWR_CR1_FPDR_Pos) /*!< 0x00000010 */ 5967 #define PWR_CR1_FPDR PWR_CR1_FPDR_Msk /*!< Flash power down mode during LPrun for CPU1 */ 5968 5969 #define PWR_CR1_FPDS_Pos (5U) 5970 #define PWR_CR1_FPDS_Msk (0x1UL << PWR_CR1_FPDS_Pos) /*!< 0x00000020 */ 5971 #define PWR_CR1_FPDS PWR_CR1_FPDS_Msk /*!< Flash power down mode during LPsleep for CPU1 */ 5972 5973 #define PWR_CR1_DBP_Pos (8U) 5974 #define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */ 5975 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Backup Domain write protection */ 5976 5977 #define PWR_CR1_LPR_Pos (14U) 5978 #define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */ 5979 #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator Low-Power Run mode */ 5980 5981 /******************** Bit definition for PWR_CR2 register ********************/ 5982 #define PWR_CR2_PVDE_Pos (0U) 5983 #define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */ 5984 #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power voltage detector enable */ 5985 5986 #define PWR_CR2_PLS_Pos (1U) 5987 #define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos) /*!< 0x0000000E */ 5988 #define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< Power voltage detector level selection */ 5989 #define PWR_CR2_PLS_0 (0x1U << PWR_CR2_PLS_Pos) /*!< 0x00000002 */ 5990 #define PWR_CR2_PLS_1 (0x2U << PWR_CR2_PLS_Pos) /*!< 0x00000004 */ 5991 #define PWR_CR2_PLS_2 (0x4U << PWR_CR2_PLS_Pos) /*!< 0x00000008 */ 5992 5993 #define PWR_CR2_PVME_Pos (4U) 5994 #define PWR_CR2_PVME_Msk (0x4UL << PWR_CR2_PVME_Pos) /*!< 0x00000040 */ 5995 #define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< Peripherical Voltage Monitor Enable for all power domains */ 5996 #define PWR_CR2_PVME3_Pos (6U) 5997 #define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */ 5998 #define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< Peripherical Voltage Monitor Vdda Enable */ 5999 6000 /******************** Bit definition for PWR_CR3 register ********************/ 6001 #define PWR_CR3_EWUP_Pos (0U) 6002 #define PWR_CR3_EWUP_Msk (0x09UL << PWR_CR3_EWUP_Pos) /*!< 0x00000009 */ 6003 #define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable all external Wake-Up lines */ 6004 #define PWR_CR3_EWUP1_Pos (0U) 6005 #define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */ 6006 #define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable external WKUP Pin 1 [line 0] */ 6007 #define PWR_CR3_EWUP4_Pos (3U) 6008 #define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */ 6009 #define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable external WKUP Pin 4 [line 3] */ 6010 6011 #define PWR_CR3_RRS_Pos (9U) 6012 #define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos) /*!< 0x00000200 */ 6013 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 retention in STANDBY mode */ 6014 6015 #define PWR_CR3_APC_Pos (10U) 6016 #define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */ 6017 #define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration for CPU1 */ 6018 6019 #define PWR_CR3_ECRPE_Pos (11U) 6020 #define PWR_CR3_ECRPE_Msk (0x1UL << PWR_CR3_ECRPE_Pos) /*!< 0x00000800 */ 6021 #define PWR_CR3_ECRPE PWR_CR3_ECRPE_Msk /*!< Critical radio phase end of activity interrupt for CPU1 */ 6022 #define PWR_CR3_EBLEA_Pos (12U) 6023 #define PWR_CR3_EBLEA_Msk (0x1UL << PWR_CR3_EBLEA_Pos) /*!< 0x00010000 */ 6024 #define PWR_CR3_EBLEA PWR_CR3_EBLEA_Msk /*!< BLE end of activity interrupt for CPU1 */ 6025 #define PWR_CR3_E802A_Pos (13U) 6026 #define PWR_CR3_E802A_Msk (0x1UL << PWR_CR3_E802A_Pos) /*!< 0x00020000 */ 6027 #define PWR_CR3_E802A PWR_CR3_E802A_Msk /*!< 802.15.4 end of activity interrupt for CPU1 */ 6028 #define PWR_CR3_EC2H_Pos (14U) 6029 #define PWR_CR3_EC2H_Msk (0x1UL << PWR_CR3_EC2H_Pos) /*!< 0x00040000 */ 6030 #define PWR_CR3_EC2H PWR_CR3_EC2H_Msk /*!< CPU2 Hold interrupt for CPU1 */ 6031 6032 #define PWR_CR3_EIWUL_Pos (15U) 6033 #define PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos) /*!< 0x00080000 */ 6034 #define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Internal Wake-Up line interrupt for CPU1 */ 6035 6036 /******************** Bit definition for PWR_CR4 register ********************/ 6037 #define PWR_CR4_WP_Pos (0U) 6038 #define PWR_CR4_WP_Msk (0x09UL << PWR_CR4_WP_Pos) /*!< 0x00000009 */ 6039 #define PWR_CR4_WP PWR_CR4_WP_Msk /*!< Wake-Up polarity for all pins */ 6040 #define PWR_CR4_WP1_Pos (0U) 6041 #define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */ 6042 #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 [line 0] polarity */ 6043 #define PWR_CR4_WP4_Pos (3U) 6044 #define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos) /*!< 0x00000008 */ 6045 #define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 [line 3] polarity */ 6046 6047 #define PWR_CR4_VBE_Pos (8U) 6048 #define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */ 6049 #define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT battery charging enable */ 6050 #define PWR_CR4_VBRS_Pos (9U) 6051 #define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */ 6052 #define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT battery charging resistor selection */ 6053 6054 #define PWR_CR4_C2BOOT_Pos (15U) 6055 #define PWR_CR4_C2BOOT_Msk (0x1UL << PWR_CR4_C2BOOT_Pos) /*!< 0x00008000 */ 6056 #define PWR_CR4_C2BOOT PWR_CR4_C2BOOT_Msk /*!< Boot CPU2 after reset or wakeup from Stop or Standby modes */ 6057 6058 /******************** Bit definition for PWR_SR1 register ********************/ 6059 #define PWR_SR1_WUF_Pos (0U) 6060 #define PWR_SR1_WUF_Msk (0x09UL << PWR_SR1_WUF_Pos) /*!< 0x00000009 */ 6061 #define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wakeup Flags of all pins */ 6062 #define PWR_SR1_WUF1_Pos (0U) 6063 #define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */ 6064 #define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wakeup Pin 1 [Flag 0] */ 6065 #define PWR_SR1_WUF4_Pos (3U) 6066 #define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */ 6067 #define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wakeup Pin 4 [Flag 3] */ 6068 6069 #define PWR_SR1_BORHF_Pos (8U) 6070 #define PWR_SR1_BORHF_Msk (0x1UL << PWR_SR1_BORHF_Pos) /*!< 0x00000100 */ 6071 #define PWR_SR1_BORHF PWR_SR1_BORHF_Msk /*!< BORH interrupt flag */ 6072 6073 #define PWR_SR1_BLEWUF_Pos (9U) 6074 #define PWR_SR1_BLEWUF_Msk (0x1UL << PWR_SR1_BLEWUF_Pos) /*!< 0x00000200 */ 6075 #define PWR_SR1_BLEWUF PWR_SR1_BLEWUF_Msk /*!< BLE wakeup interrupt flag */ 6076 #define PWR_SR1_802WUF_Pos (10U) 6077 #define PWR_SR1_802WUF_Msk (0x1UL << PWR_SR1_802WUF_Pos) /*!< 0x00000400 */ 6078 #define PWR_SR1_802WUF PWR_SR1_802WUF_Msk /*!< 802.15.4 wakeup interrupt flag */ 6079 6080 #define PWR_SR1_CRPEF_Pos (11U) 6081 #define PWR_SR1_CRPEF_Msk (0x1UL << PWR_SR1_CRPEF_Pos) /*!< 0x00000800 */ 6082 #define PWR_SR1_CRPEF PWR_SR1_CRPEF_Msk /*!< Critical radio phase end of activity interrupt flag */ 6083 #define PWR_SR1_BLEAF_Pos (12U) 6084 #define PWR_SR1_BLEAF_Msk (0x1UL << PWR_SR1_BLEAF_Pos) /*!< 0x00001000 */ 6085 #define PWR_SR1_BLEAF PWR_SR1_BLEAF_Msk /*!< BLE end of activity interrupt flag */ 6086 #define PWR_SR1_802AF_Pos (13U) 6087 #define PWR_SR1_802AF_Msk (0x1UL << PWR_SR1_802AF_Pos) /*!< 0x00002000 */ 6088 #define PWR_SR1_802AF PWR_SR1_802AF_Msk /*!< 802.15.4 end of activity interrupt flag */ 6089 6090 #define PWR_SR1_C2HF_Pos (14U) 6091 #define PWR_SR1_C2HF_Msk (0x1UL << PWR_SR1_C2HF_Pos) /*!< 0x00004000 */ 6092 #define PWR_SR1_C2HF PWR_SR1_C2HF_Msk /*!< CPU2 Hold interrupt flag */ 6093 6094 #define PWR_SR1_WUFI_Pos (15U) 6095 #define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */ 6096 #define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Internal wakeup interrupt flag */ 6097 6098 /******************** Bit definition for PWR_SR2 register ********************/ 6099 #define PWR_SR2_REGLPS_Pos (8U) 6100 #define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */ 6101 #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power regulator started */ 6102 #define PWR_SR2_REGLPF_Pos (9U) 6103 #define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */ 6104 #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power regulator flag */ 6105 6106 #define PWR_SR2_PVDO_Pos (11U) 6107 #define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */ 6108 #define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power voltage detector output */ 6109 6110 #define PWR_SR2_PVMO_Pos (12U) 6111 #define PWR_SR2_PVMO_Msk (0x4UL << PWR_SR2_PVMO_Pos) /*!< 0x00004000 */ 6112 #define PWR_SR2_PVMO PWR_SR2_PVMO_Msk /*!< Peripheral voltage monitor output for all power domains */ 6113 #define PWR_SR2_PVMO3_Pos (14U) 6114 #define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */ 6115 #define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral voltage monitor output 3: VDDA vs. 1.62V */ 6116 6117 /******************** Bit definition for PWR_SCR register ********************/ 6118 #define PWR_SCR_CWUF_Pos (0U) 6119 #define PWR_SCR_CWUF_Msk (0x09UL << PWR_SCR_CWUF_Pos) /*!< 0x00000009 */ 6120 #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags for all pins */ 6121 #define PWR_SCR_CWUF1_Pos (0U) 6122 #define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */ 6123 #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Pin 1 [Flag 0] */ 6124 #define PWR_SCR_CWUF4_Pos (3U) 6125 #define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */ 6126 #define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Pin 4 [Flag 3] */ 6127 6128 #define PWR_SCR_CBORHF_Pos (8U) 6129 #define PWR_SCR_CBORHF_Msk (0x1UL << PWR_SCR_CBORHF_Pos) /*!< 0x00000100 */ 6130 #define PWR_SCR_CBORHF PWR_SCR_CBORHF_Msk /*!< Clear BORH interrupt flag */ 6131 6132 #define PWR_SCR_CBLEWUF_Pos (9U) 6133 #define PWR_SCR_CBLEWUF_Msk (0x1UL << PWR_SCR_CBLEWUF_Pos) /*!< 0x00000200 */ 6134 #define PWR_SCR_CBLEWUF PWR_SCR_CBLEWUF_Msk /*!< Clear BLE wakeup interrupt flag */ 6135 #define PWR_SCR_C802WUF_Pos (10U) 6136 #define PWR_SCR_C802WUF_Msk (0x1UL << PWR_SCR_C802WUF_Pos) /*!< 0x00000400 */ 6137 #define PWR_SCR_C802WUF PWR_SCR_C802WUF_Msk /*!< Clear 802.15.4 wakeup interrupt flag */ 6138 6139 #define PWR_SCR_CCRPEF_Pos (11U) 6140 #define PWR_SCR_CCRPEF_Msk (0x1UL << PWR_SCR_CCRPEF_Pos) /*!< 0x00000800 */ 6141 #define PWR_SCR_CCRPEF PWR_SCR_CCRPEF_Msk /*!< Clear Critical radio phase end of activity interrupt flag */ 6142 #define PWR_SCR_CBLEAF_Pos (12U) 6143 #define PWR_SCR_CBLEAF_Msk (0x1UL << PWR_SCR_CBLEAF_Pos) /*!< 0x00001000 */ 6144 #define PWR_SCR_CBLEAF PWR_SCR_CBLEAF_Msk /*!< Clear BLE end of activity interrupt flag */ 6145 #define PWR_SCR_C802AF_Pos (13U) 6146 #define PWR_SCR_C802AF_Msk (0x1UL << PWR_SCR_C802AF_Pos) /*!< 0x00002000 */ 6147 #define PWR_SCR_C802AF PWR_SCR_C802AF_Msk /*!< Clear 802.15.4 end of activity interrupt flag */ 6148 6149 #define PWR_SCR_CC2HF_Pos (14U) 6150 #define PWR_SCR_CC2HF_Msk (0x1UL << PWR_SCR_CC2HF_Pos) /*!< 0x00004000 */ 6151 #define PWR_SCR_CC2HF PWR_SCR_CC2HF_Msk /*!< Clear CPU2 Hold interrupt flag */ 6152 6153 /******************** Bit definition for PWR_PUCRA register *****************/ 6154 #define PWR_PUCRA_PA0_Pos (0U) 6155 #define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */ 6156 #define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Pin PA0 Pull-Up set */ 6157 #define PWR_PUCRA_PA1_Pos (1U) 6158 #define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */ 6159 #define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Pin PA1 Pull-Up set */ 6160 #define PWR_PUCRA_PA2_Pos (2U) 6161 #define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */ 6162 #define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Pin PA2 Pull-Up set */ 6163 #define PWR_PUCRA_PA3_Pos (3U) 6164 #define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */ 6165 #define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Pin PA3 Pull-Up set */ 6166 #define PWR_PUCRA_PA4_Pos (4U) 6167 #define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */ 6168 #define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Pin PA4 Pull-Up set */ 6169 #define PWR_PUCRA_PA5_Pos (5U) 6170 #define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */ 6171 #define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Pin PA5 Pull-Up set */ 6172 #define PWR_PUCRA_PA6_Pos (6U) 6173 #define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */ 6174 #define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Pin PA6 Pull-Up set */ 6175 #define PWR_PUCRA_PA7_Pos (7U) 6176 #define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */ 6177 #define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Pin PA7 Pull-Up set */ 6178 #define PWR_PUCRA_PA8_Pos (8U) 6179 #define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */ 6180 #define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Pin PA8 Pull-Up set */ 6181 #define PWR_PUCRA_PA9_Pos (9U) 6182 #define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */ 6183 #define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Pin PA9 Pull-Up set */ 6184 #define PWR_PUCRA_PA10_Pos (10U) 6185 #define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */ 6186 #define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Pin PA10 Pull-Up set */ 6187 #define PWR_PUCRA_PA11_Pos (11U) 6188 #define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */ 6189 #define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Pin PA11 Pull-Up set */ 6190 #define PWR_PUCRA_PA12_Pos (12U) 6191 #define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */ 6192 #define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Pin PA12 Pull-Up set */ 6193 #define PWR_PUCRA_PA13_Pos (13U) 6194 #define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */ 6195 #define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Pin PA13 Pull-Up set */ 6196 #define PWR_PUCRA_PA15_Pos (15U) 6197 #define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */ 6198 #define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Pin PA15 Pull-Up set */ 6199 6200 /******************** Bit definition for PWR_PDCRA register *****************/ 6201 #define PWR_PDCRA_PA0_Pos (0U) 6202 #define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */ 6203 #define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Pin PA0 Pull-Down set */ 6204 #define PWR_PDCRA_PA1_Pos (1U) 6205 #define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */ 6206 #define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Pin PA1 Pull-Down set */ 6207 #define PWR_PDCRA_PA2_Pos (2U) 6208 #define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */ 6209 #define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Pin PA2 Pull-Down set */ 6210 #define PWR_PDCRA_PA3_Pos (3U) 6211 #define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */ 6212 #define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Pin PA3 Pull-Down set */ 6213 #define PWR_PDCRA_PA4_Pos (4U) 6214 #define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */ 6215 #define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Pin PA4 Pull-Down set */ 6216 #define PWR_PDCRA_PA5_Pos (5U) 6217 #define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */ 6218 #define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Pin PA5 Pull-Down set */ 6219 #define PWR_PDCRA_PA6_Pos (6U) 6220 #define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */ 6221 #define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Pin PA6 Pull-Down set */ 6222 #define PWR_PDCRA_PA7_Pos (7U) 6223 #define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */ 6224 #define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Pin PA7 Pull-Down set */ 6225 #define PWR_PDCRA_PA8_Pos (8U) 6226 #define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */ 6227 #define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Pin PA8 Pull-Down set */ 6228 #define PWR_PDCRA_PA9_Pos (9U) 6229 #define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */ 6230 #define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Pin PA9 Pull-Down set */ 6231 #define PWR_PDCRA_PA10_Pos (10U) 6232 #define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */ 6233 #define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Pin PA10 Pull-Down set */ 6234 #define PWR_PDCRA_PA11_Pos (11U) 6235 #define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */ 6236 #define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Pin PA11 Pull-Down set */ 6237 #define PWR_PDCRA_PA12_Pos (12U) 6238 #define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */ 6239 #define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Pin PA12 Pull-Down set */ 6240 #define PWR_PDCRA_PA14_Pos (14U) 6241 #define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */ 6242 #define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Pin PA14 Pull-Down set */ 6243 6244 /******************** Bit definition for PWR_PUCRB register *****************/ 6245 #define PWR_PUCRB_PB0_Pos (0U) 6246 #define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */ 6247 #define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Pin PB0 Pull-Up set */ 6248 #define PWR_PUCRB_PB1_Pos (1U) 6249 #define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */ 6250 #define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Pin PB1 Pull-Up set */ 6251 #define PWR_PUCRB_PB2_Pos (2U) 6252 #define PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */ 6253 #define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Pin PB2 Pull-Up set */ 6254 #define PWR_PUCRB_PB3_Pos (3U) 6255 #define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */ 6256 #define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Pin PB3 Pull-Up set */ 6257 #define PWR_PUCRB_PB4_Pos (4U) 6258 #define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */ 6259 #define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Pin PB4 Pull-Up set */ 6260 #define PWR_PUCRB_PB5_Pos (5U) 6261 #define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */ 6262 #define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Pin PB5 Pull-Up set */ 6263 #define PWR_PUCRB_PB6_Pos (6U) 6264 #define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */ 6265 #define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Pin PB6 Pull-Up set */ 6266 #define PWR_PUCRB_PB7_Pos (7U) 6267 #define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */ 6268 #define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Pin PB7 Pull-Up set */ 6269 #define PWR_PUCRB_PB8_Pos (8U) 6270 #define PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */ 6271 #define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Pin PB8 Pull-Up set */ 6272 #define PWR_PUCRB_PB9_Pos (9U) 6273 #define PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */ 6274 #define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Pin PB9 Pull-Up set */ 6275 6276 /******************** Bit definition for PWR_PDCRB register *****************/ 6277 #define PWR_PDCRB_PB0_Pos (0U) 6278 #define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */ 6279 #define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Pin PB0 Pull-Down set */ 6280 #define PWR_PDCRB_PB1_Pos (1U) 6281 #define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */ 6282 #define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Pin PB1 Pull-Down set */ 6283 #define PWR_PDCRB_PB2_Pos (2U) 6284 #define PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */ 6285 #define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Pin PB2 Pull-Down set */ 6286 #define PWR_PDCRB_PB3_Pos (3U) 6287 #define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */ 6288 #define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Pin PB3 Pull-Down set */ 6289 #define PWR_PDCRB_PB5_Pos (5U) 6290 #define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */ 6291 #define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Pin PB5 Pull-Down set */ 6292 #define PWR_PDCRB_PB6_Pos (6U) 6293 #define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */ 6294 #define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Pin PB6 Pull-Down set */ 6295 #define PWR_PDCRB_PB7_Pos (7U) 6296 #define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */ 6297 #define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Pin PB7 Pull-Down set */ 6298 #define PWR_PDCRB_PB8_Pos (8U) 6299 #define PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */ 6300 #define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Pin PB8 Pull-Down set */ 6301 #define PWR_PDCRB_PB9_Pos (9U) 6302 #define PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */ 6303 #define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Pin PB9 Pull-Down set */ 6304 6305 /******************** Bit definition for PWR_PUCRC register *****************/ 6306 #define PWR_PUCRC_PC14_Pos (14U) 6307 #define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */ 6308 #define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Pin PC14 Pull-Up set */ 6309 #define PWR_PUCRC_PC15_Pos (15U) 6310 #define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */ 6311 #define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Pin PC15 Pull-Up set */ 6312 6313 /******************** Bit definition for PWR_PDCRC register *****************/ 6314 #define PWR_PDCRC_PC14_Pos (14U) 6315 #define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */ 6316 #define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Pin PC14 Pull-Down set */ 6317 #define PWR_PDCRC_PC15_Pos (15U) 6318 #define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */ 6319 #define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Pin PC15 Pull-Down set */ 6320 6321 /******************** Bit definition for PWR_PUCRE register *****************/ 6322 #define PWR_PUCRE_PE4_Pos (4U) 6323 #define PWR_PUCRE_PE4_Msk (0x1UL << PWR_PUCRE_PE4_Pos) /*!< 0x00000010 */ 6324 #define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Pin PE4 Pull-Up set */ 6325 6326 /******************** Bit definition for PWR_PDCRE register *****************/ 6327 #define PWR_PDCRE_PE4_Pos (4U) 6328 #define PWR_PDCRE_PE4_Msk (0x1UL << PWR_PDCRE_PE4_Pos) /*!< 0x00000010 */ 6329 #define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Pin PE4 Pull-Down set */ 6330 6331 /******************** Bit definition for PWR_PUCRH register *****************/ 6332 #define PWR_PUCRH_PH3_Pos (3U) 6333 #define PWR_PUCRH_PH3_Msk (0x1UL << PWR_PUCRH_PH3_Pos) /*!< 0x00000004 */ 6334 #define PWR_PUCRH_PH3 PWR_PUCRH_PH3_Msk /*!< Pin PH3 Pull-Up set */ 6335 6336 /******************** Bit definition for PWR_PDCRH register *****************/ 6337 #define PWR_PDCRH_PH3_Pos (3U) 6338 #define PWR_PDCRH_PH3_Msk (0x1UL << PWR_PDCRH_PH3_Pos) /*!< 0x00000004 */ 6339 #define PWR_PDCRH_PH3 PWR_PDCRH_PH3_Msk /*!< Pin PH3 Pull-Down set */ 6340 6341 /******************** Bit definition for PWR_C2CR1 register ********************/ 6342 #define PWR_C2CR1_LPMS_Pos (0U) 6343 #define PWR_C2CR1_LPMS_Msk (0x7UL << PWR_C2CR1_LPMS_Pos) /*!< 0x00000007 */ 6344 #define PWR_C2CR1_LPMS PWR_C2CR1_LPMS_Msk /*!< Low Power Mode Selection for CPU2 */ 6345 #define PWR_C2CR1_LPMS_0 (0x1U << PWR_C2CR1_LPMS_Pos) /*!< 0x00000001 */ 6346 #define PWR_C2CR1_LPMS_1 (0x2U << PWR_C2CR1_LPMS_Pos) /*!< 0x00000002 */ 6347 #define PWR_C2CR1_LPMS_2 (0x4U << PWR_C2CR1_LPMS_Pos) /*!< 0x00000004 */ 6348 6349 #define PWR_C2CR1_FPDR_Pos (4U) 6350 #define PWR_C2CR1_FPDR_Msk (0x1UL << PWR_C2CR1_FPDR_Pos) /*!< 0x00000010 */ 6351 #define PWR_C2CR1_FPDR PWR_C2CR1_FPDR_Msk /*!< Flash power down mode during LPrun for CPU2 */ 6352 6353 #define PWR_C2CR1_FPDS_Pos (5U) 6354 #define PWR_C2CR1_FPDS_Msk (0x1UL << PWR_C2CR1_FPDS_Pos) /*!< 0x00000020 */ 6355 #define PWR_C2CR1_FPDS PWR_C2CR1_FPDS_Msk /*!< Flash power down mode during LPsleep for CPU2 */ 6356 6357 #define PWR_C2CR1_BLEEWKUP_Pos (14U) 6358 #define PWR_C2CR1_BLEEWKUP_Msk (0x1UL << PWR_C2CR1_BLEEWKUP_Pos) /*!< 0x00008000 */ 6359 #define PWR_C2CR1_BLEEWKUP PWR_C2CR1_BLEEWKUP_Msk /*!< Radio BLE external wakeup signal */ 6360 6361 #define PWR_C2CR1_802EWKUP_Pos (15U) 6362 #define PWR_C2CR1_802EWKUP_Msk (0x1UL << PWR_C2CR1_802EWKUP_Pos) /*!< 0x00008000 */ 6363 #define PWR_C2CR1_802EWKUP PWR_C2CR1_802EWKUP_Msk /*!< Radio 802.15.4 external wakeup signal */ 6364 6365 /******************** Bit definition for PWR_C2CR3 register ********************/ 6366 #define PWR_C2CR3_EWUP_Pos (0U) 6367 #define PWR_C2CR3_EWUP_Msk (0x09UL << PWR_C2CR3_EWUP_Pos) /*!< 0x00000009 */ 6368 #define PWR_C2CR3_EWUP PWR_C2CR3_EWUP_Msk /*!< Enable all external Wake-Up lines for CPU2 */ 6369 #define PWR_C2CR3_EWUP1_Pos (0U) 6370 #define PWR_C2CR3_EWUP1_Msk (0x1UL << PWR_C2CR3_EWUP1_Pos) /*!< 0x00000001 */ 6371 #define PWR_C2CR3_EWUP1 PWR_C2CR3_EWUP1_Msk /*!< Enable external WKUP Pin 1 [line 0] for CPU2 */ 6372 #define PWR_C2CR3_EWUP4_Pos (3U) 6373 #define PWR_C2CR3_EWUP4_Msk (0x1UL << PWR_C2CR3_EWUP4_Pos) /*!< 0x00000008 */ 6374 #define PWR_C2CR3_EWUP4 PWR_C2CR3_EWUP4_Msk /*!< Enable external WKUP Pin 4 [line 3] for CPU2 */ 6375 6376 #define PWR_C2CR3_EBLEWUP_Pos (9U) 6377 #define PWR_C2CR3_EBLEWUP_Msk (0x1UL << PWR_C2CR3_EBLEWUP_Pos) /*!< 0x00000200 */ 6378 #define PWR_C2CR3_EBLEWUP PWR_C2CR3_EBLEWUP_Msk /*!< Enable BLE host wakeup interrupt for CPU2 */ 6379 #define PWR_C2CR3_E802WUP_Pos (10U) 6380 #define PWR_C2CR3_E802WUP_Msk (0x1UL << PWR_C2CR3_E802WUP_Pos) /*!< 0x00000400 */ 6381 #define PWR_C2CR3_E802WUP PWR_C2CR3_E802WUP_Msk /*!< Enable BLE host wakeup interrupt for CPU2 */ 6382 6383 #define PWR_C2CR3_APC_Pos (12U) 6384 #define PWR_C2CR3_APC_Msk (0x1UL << PWR_C2CR3_APC_Pos) /*!< 0x00001000 */ 6385 #define PWR_C2CR3_APC PWR_C2CR3_APC_Msk /*!< Apply pull-up and pull-down configuration for CPU2 */ 6386 6387 #define PWR_C2CR3_EIWUL_Pos (15U) 6388 #define PWR_C2CR3_EIWUL_Msk (0x1UL << PWR_C2CR3_EIWUL_Pos) /*!< 0x00008000 */ 6389 #define PWR_C2CR3_EIWUL PWR_C2CR3_EIWUL_Msk /*!< Internal Wake-Up line interrupt for CPU2 */ 6390 6391 /******************** Bit definition for PWR_EXTSCR register ********************/ 6392 #define PWR_EXTSCR_C1CSSF_Pos (0U) 6393 #define PWR_EXTSCR_C1CSSF_Msk (0x1UL << PWR_EXTSCR_C1CSSF_Pos) /*!< 0x00000001 */ 6394 #define PWR_EXTSCR_C1CSSF PWR_EXTSCR_C1CSSF_Msk /*!< Clear standby and stop flags for CPU1 */ 6395 #define PWR_EXTSCR_C2CSSF_Pos (1U) 6396 #define PWR_EXTSCR_C2CSSF_Msk (0x1UL << PWR_EXTSCR_C2CSSF_Pos) /*!< 0x00000002 */ 6397 #define PWR_EXTSCR_C2CSSF PWR_EXTSCR_C2CSSF_Msk /*!< Clear standby and stop flags for CPU2 */ 6398 #define PWR_EXTSCR_CCRPF_Pos (2U) 6399 #define PWR_EXTSCR_CCRPF_Msk (0x1UL << PWR_EXTSCR_CCRPF_Pos) /*!< 0x00000004 */ 6400 #define PWR_EXTSCR_CCRPF PWR_EXTSCR_CCRPF_Msk /*!< Clear critical radio system phase flag */ 6401 6402 #define PWR_EXTSCR_C1SBF_Pos (8U) 6403 #define PWR_EXTSCR_C1SBF_Msk (0x1UL << PWR_EXTSCR_C1SBF_Pos) /*!< 0x00000100 */ 6404 #define PWR_EXTSCR_C1SBF PWR_EXTSCR_C1SBF_Msk /*!< System standby flag for CPU1 */ 6405 #define PWR_EXTSCR_C1STOPF_Pos (9U) 6406 #define PWR_EXTSCR_C1STOPF_Msk (0x1UL << PWR_EXTSCR_C1STOPF_Pos) /*!< 0x00000200 */ 6407 #define PWR_EXTSCR_C1STOPF PWR_EXTSCR_C1STOPF_Msk /*!< System stop flag for CPU1 */ 6408 #define PWR_EXTSCR_C2SBF_Pos (10U) 6409 #define PWR_EXTSCR_C2SBF_Msk (0x1UL << PWR_EXTSCR_C2SBF_Pos) /*!< 0x00000400 */ 6410 #define PWR_EXTSCR_C2SBF PWR_EXTSCR_C2SBF_Msk /*!< System standby flag for CPU2 */ 6411 #define PWR_EXTSCR_C2STOPF_Pos (11U) 6412 #define PWR_EXTSCR_C2STOPF_Msk (0x1UL << PWR_EXTSCR_C2STOPF_Pos) /*!< 0x00000800 */ 6413 #define PWR_EXTSCR_C2STOPF PWR_EXTSCR_C2STOPF_Msk /*!< System stop flag for CPU2 */ 6414 6415 #define PWR_EXTSCR_CRPF_Pos (13U) 6416 #define PWR_EXTSCR_CRPF_Msk (0x1UL << PWR_EXTSCR_CRPF_Pos) /*!< 0x00002000 */ 6417 #define PWR_EXTSCR_CRPF PWR_EXTSCR_CRPF_Msk /*!< Critical radio system phase flag */ 6418 6419 #define PWR_EXTSCR_C1DS_Pos (14U) 6420 #define PWR_EXTSCR_C1DS_Msk (0x1UL << PWR_EXTSCR_C1DS_Pos) /*!< 0x00004000 */ 6421 #define PWR_EXTSCR_C1DS PWR_EXTSCR_C1DS_Msk /*!< CPU1 deepsleep mode flag */ 6422 #define PWR_EXTSCR_C2DS_Pos (15U) 6423 #define PWR_EXTSCR_C2DS_Msk (0x1UL << PWR_EXTSCR_C2DS_Pos) /*!< 0x00008000 */ 6424 #define PWR_EXTSCR_C2DS PWR_EXTSCR_C2DS_Msk /*!< CPU2 deepsleep mode flag */ 6425 6426 /******************************************************************************/ 6427 /* */ 6428 /* Reset and Clock Control */ 6429 /* */ 6430 /******************************************************************************/ 6431 /* 6432 * @brief Specific device feature definitions 6433 */ 6434 #define RCC_MCO3_SUPPORT 6435 #define RCC_LSCO3_SUPPORT 6436 6437 /******************** Bit definition for RCC_CR register *****************/ 6438 #define RCC_CR_MSION_Pos (0U) 6439 #define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000001 */ 6440 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed oscillator (MSI) clock enable */ 6441 #define RCC_CR_MSIRDY_Pos (1U) 6442 #define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000002 */ 6443 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed oscillator (MSI) clock ready flag */ 6444 #define RCC_CR_MSIPLLEN_Pos (2U) 6445 #define RCC_CR_MSIPLLEN_Msk (0x1UL << RCC_CR_MSIPLLEN_Pos) /*!< 0x00000004 */ 6446 #define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk /*!< Internal Multi Speed oscillator (MSI) PLL enable */ 6447 6448 /*!< MSIRANGE configuration : 12 frequency ranges available */ 6449 #define RCC_CR_MSIRANGE_Pos (4U) 6450 #define RCC_CR_MSIRANGE_Msk (0xFUL << RCC_CR_MSIRANGE_Pos) /*!< 0x000000F0 */ 6451 #define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk /*!< Internal Multi Speed oscillator (MSI) clock Range */ 6452 #define RCC_CR_MSIRANGE_0 (0x0U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000000 */ 6453 #define RCC_CR_MSIRANGE_1 (0x1U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000010 */ 6454 #define RCC_CR_MSIRANGE_2 (0x2U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000020 */ 6455 #define RCC_CR_MSIRANGE_3 (0x3U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000030 */ 6456 #define RCC_CR_MSIRANGE_4 (0x4U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000040 */ 6457 #define RCC_CR_MSIRANGE_5 (0x5U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000050 */ 6458 #define RCC_CR_MSIRANGE_6 (0x6U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000060 */ 6459 #define RCC_CR_MSIRANGE_7 (0x7U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000070 */ 6460 #define RCC_CR_MSIRANGE_8 (0x8U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000080 */ 6461 #define RCC_CR_MSIRANGE_9 (0x9U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000090 */ 6462 #define RCC_CR_MSIRANGE_10 (0xAU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000A0 */ 6463 #define RCC_CR_MSIRANGE_11 (0xBU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000B0 */ 6464 6465 #define RCC_CR_HSION_Pos (8U) 6466 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */ 6467 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */ 6468 #define RCC_CR_HSIKERON_Pos (9U) 6469 #define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */ 6470 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */ 6471 #define RCC_CR_HSIRDY_Pos (10U) 6472 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */ 6473 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */ 6474 #define RCC_CR_HSIASFS_Pos (11U) 6475 #define RCC_CR_HSIASFS_Msk (0x1UL << RCC_CR_HSIASFS_Pos) /*!< 0x00000800 */ 6476 #define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk /*!< HSI16 Automatic Start from Stop */ 6477 #define RCC_CR_HSIKERDY_Pos (12U) 6478 #define RCC_CR_HSIKERDY_Msk (0x1UL << RCC_CR_HSIKERDY_Pos) /*!< 0x00001000 */ 6479 #define RCC_CR_HSIKERDY RCC_CR_HSIKERDY_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel ready flag*/ 6480 6481 #define RCC_CR_HSEON_Pos (16U) 6482 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 6483 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */ 6484 #define RCC_CR_HSERDY_Pos (17U) 6485 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 6486 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */ 6487 #define RCC_CR_HSEBYP_Pos (18U) 6488 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 6489 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */ 6490 #define RCC_CR_CSSON_Pos (19U) 6491 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ 6492 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */ 6493 #define RCC_CR_HSEPRE_Pos (20U) 6494 #define RCC_CR_HSEPRE_Msk (0x1UL << RCC_CR_HSEPRE_Pos) /*!< 0x00100000 */ 6495 #define RCC_CR_HSEPRE RCC_CR_HSEPRE_Msk /*!< HSE sysclk prescaler */ 6496 6497 #define RCC_CR_PLLON_Pos (24U) 6498 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 6499 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */ 6500 #define RCC_CR_PLLRDY_Pos (25U) 6501 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 6502 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */ 6503 6504 /******************** Bit definition for RCC_ICSCR register ***************/ 6505 /*!< MSICAL configuration */ 6506 #define RCC_ICSCR_MSICAL_Pos (0U) 6507 #define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x000000FF */ 6508 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< MSICAL[7:0] bits */ 6509 #define RCC_ICSCR_MSICAL_0 (0x01U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000001 */ 6510 #define RCC_ICSCR_MSICAL_1 (0x02U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000002 */ 6511 #define RCC_ICSCR_MSICAL_2 (0x04U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000004 */ 6512 #define RCC_ICSCR_MSICAL_3 (0x08U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000008 */ 6513 #define RCC_ICSCR_MSICAL_4 (0x10U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000010 */ 6514 #define RCC_ICSCR_MSICAL_5 (0x20U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000020 */ 6515 #define RCC_ICSCR_MSICAL_6 (0x40U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000040 */ 6516 #define RCC_ICSCR_MSICAL_7 (0x80U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000080 */ 6517 6518 /*!< MSITRIM configuration */ 6519 #define RCC_ICSCR_MSITRIM_Pos (8U) 6520 #define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */ 6521 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< MSITRIM[7:0] bits */ 6522 #define RCC_ICSCR_MSITRIM_0 (0x01U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */ 6523 #define RCC_ICSCR_MSITRIM_1 (0x02U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */ 6524 #define RCC_ICSCR_MSITRIM_2 (0x04U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */ 6525 #define RCC_ICSCR_MSITRIM_3 (0x08U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */ 6526 #define RCC_ICSCR_MSITRIM_4 (0x10U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */ 6527 #define RCC_ICSCR_MSITRIM_5 (0x20U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */ 6528 #define RCC_ICSCR_MSITRIM_6 (0x40U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */ 6529 #define RCC_ICSCR_MSITRIM_7 (0x80U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */ 6530 6531 /*!< HSICAL configuration */ 6532 #define RCC_ICSCR_HSICAL_Pos (16U) 6533 #define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */ 6534 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */ 6535 #define RCC_ICSCR_HSICAL_0 (0x01U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */ 6536 #define RCC_ICSCR_HSICAL_1 (0x02U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */ 6537 #define RCC_ICSCR_HSICAL_2 (0x04U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */ 6538 #define RCC_ICSCR_HSICAL_3 (0x08U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */ 6539 #define RCC_ICSCR_HSICAL_4 (0x10U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */ 6540 #define RCC_ICSCR_HSICAL_5 (0x20U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */ 6541 #define RCC_ICSCR_HSICAL_6 (0x40U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */ 6542 #define RCC_ICSCR_HSICAL_7 (0x80U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */ 6543 6544 /*!< HSITRIM configuration */ 6545 #define RCC_ICSCR_HSITRIM_Pos (24U) 6546 #define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */ 6547 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */ 6548 #define RCC_ICSCR_HSITRIM_0 (0x01U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */ 6549 #define RCC_ICSCR_HSITRIM_1 (0x02U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */ 6550 #define RCC_ICSCR_HSITRIM_2 (0x04U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */ 6551 #define RCC_ICSCR_HSITRIM_3 (0x08U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */ 6552 #define RCC_ICSCR_HSITRIM_4 (0x10U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */ 6553 #define RCC_ICSCR_HSITRIM_5 (0x20U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */ 6554 #define RCC_ICSCR_HSITRIM_6 (0x40U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */ 6555 6556 /******************** Bit definition for RCC_CFGR register ******************/ 6557 /*!< SW configuration */ 6558 #define RCC_CFGR_SW_Pos (0U) 6559 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 6560 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 6561 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 6562 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 6563 6564 /*!< SWS configuration */ 6565 #define RCC_CFGR_SWS_Pos (2U) 6566 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 6567 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 6568 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 6569 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 6570 6571 /*!< HPRE configuration */ 6572 #define RCC_CFGR_HPRE_Pos (4U) 6573 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 6574 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 6575 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 6576 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 6577 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 6578 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 6579 6580 /*!< PPRE1 configuration */ 6581 #define RCC_CFGR_PPRE1_Pos (8U) 6582 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ 6583 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ 6584 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ 6585 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ 6586 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ 6587 6588 /*!< PPRE2 configuration */ 6589 #define RCC_CFGR_PPRE2_Pos (11U) 6590 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ 6591 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ 6592 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ 6593 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ 6594 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ 6595 6596 /*!< STOPWUCK configuration */ 6597 #define RCC_CFGR_STOPWUCK_Pos (15U) 6598 #define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */ 6599 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */ 6600 6601 /*!< HPREF configuration */ 6602 #define RCC_CFGR_HPREF_Pos (16U) 6603 #define RCC_CFGR_HPREF_Msk (0x1UL << RCC_CFGR_HPREF_Pos) /*!< 0x00010000 */ 6604 #define RCC_CFGR_HPREF RCC_CFGR_HPREF_Msk /*!< AHB prescaler flag */ 6605 6606 /*!< PPRE1F configuration */ 6607 #define RCC_CFGR_PPRE1F_Pos (17U) 6608 #define RCC_CFGR_PPRE1F_Msk (0x1UL << RCC_CFGR_PPRE1F_Pos) /*!< 0x00020000 */ 6609 #define RCC_CFGR_PPRE1F RCC_CFGR_PPRE1F_Msk /*!< CPU1 APB1 prescaler flag */ 6610 6611 /*!< PPRE2F configuration */ 6612 #define RCC_CFGR_PPRE2F_Pos (18U) 6613 #define RCC_CFGR_PPRE2F_Msk (0x1UL << RCC_CFGR_PPRE2F_Pos) /*!< 0x00040000 */ 6614 #define RCC_CFGR_PPRE2F RCC_CFGR_PPRE2F_Msk /*!< APB2 prescaler flag */ 6615 6616 /*!< MCOSEL configuration */ 6617 #define RCC_CFGR_MCOSEL_Pos (24U) 6618 #define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */ 6619 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */ 6620 #define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ 6621 #define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ 6622 #define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ 6623 #define RCC_CFGR_MCOSEL_3 (0x8U << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */ 6624 6625 /*!< MCOPRE configuration */ 6626 #define RCC_CFGR_MCOPRE_Pos (28U) 6627 #define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ 6628 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */ 6629 #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ 6630 #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ 6631 #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ 6632 6633 /******************** Bit definition for RCC_PLLCFGR register ***************/ 6634 #define RCC_PLLCFGR_PLLSRC_Pos (0U) 6635 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */ 6636 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk 6637 #define RCC_PLLCFGR_PLLSRC_0 (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */ 6638 #define RCC_PLLCFGR_PLLSRC_1 (0x2U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */ 6639 6640 #define RCC_PLLCFGR_PLLM_Pos (4U) 6641 #define RCC_PLLCFGR_PLLM_Msk (0x7UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */ 6642 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk 6643 #define RCC_PLLCFGR_PLLM_0 (0x1U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */ 6644 #define RCC_PLLCFGR_PLLM_1 (0x2U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */ 6645 #define RCC_PLLCFGR_PLLM_2 (0x4U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */ 6646 6647 #define RCC_PLLCFGR_PLLN_Pos (8U) 6648 #define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */ 6649 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk 6650 #define RCC_PLLCFGR_PLLN_0 (0x01U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */ 6651 #define RCC_PLLCFGR_PLLN_1 (0x02U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */ 6652 #define RCC_PLLCFGR_PLLN_2 (0x04U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */ 6653 #define RCC_PLLCFGR_PLLN_3 (0x08U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */ 6654 #define RCC_PLLCFGR_PLLN_4 (0x10U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */ 6655 #define RCC_PLLCFGR_PLLN_5 (0x20U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */ 6656 #define RCC_PLLCFGR_PLLN_6 (0x40U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */ 6657 6658 #define RCC_PLLCFGR_PLLPEN_Pos (16U) 6659 #define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */ 6660 #define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk 6661 #define RCC_PLLCFGR_PLLP_Pos (17U) 6662 #define RCC_PLLCFGR_PLLP_Msk (0x1FUL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x003E0000 */ 6663 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk 6664 #define RCC_PLLCFGR_PLLP_0 (0x01U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */ 6665 #define RCC_PLLCFGR_PLLP_1 (0x02U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00040000 */ 6666 #define RCC_PLLCFGR_PLLP_2 (0x04U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00080000 */ 6667 #define RCC_PLLCFGR_PLLP_3 (0x08U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00100000 */ 6668 #define RCC_PLLCFGR_PLLP_4 (0x10U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00200000 */ 6669 6670 #define RCC_PLLCFGR_PLLQEN_Pos (24U) 6671 #define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x01000000 */ 6672 #define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk 6673 #define RCC_PLLCFGR_PLLQ_Pos (25U) 6674 #define RCC_PLLCFGR_PLLQ_Msk (0x7UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0E000000 */ 6675 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk 6676 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */ 6677 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */ 6678 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */ 6679 6680 #define RCC_PLLCFGR_PLLREN_Pos (28U) 6681 #define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x10000000 */ 6682 #define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk 6683 #define RCC_PLLCFGR_PLLR_Pos (29U) 6684 #define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0xE0000000 */ 6685 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk 6686 #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */ 6687 #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */ 6688 #define RCC_PLLCFGR_PLLR_2 (0x4U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x80000000 */ 6689 6690 /******************** Bit definition for RCC_CIER register ******************/ 6691 #define RCC_CIER_LSI1RDYIE_Pos (0U) 6692 #define RCC_CIER_LSI1RDYIE_Msk (0x1UL << RCC_CIER_LSI1RDYIE_Pos) /*!< 0x00000001 */ 6693 #define RCC_CIER_LSI1RDYIE RCC_CIER_LSI1RDYIE_Msk 6694 #define RCC_CIER_LSERDYIE_Pos (1U) 6695 #define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ 6696 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk 6697 #define RCC_CIER_MSIRDYIE_Pos (2U) 6698 #define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */ 6699 #define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk 6700 #define RCC_CIER_HSIRDYIE_Pos (3U) 6701 #define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ 6702 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk 6703 #define RCC_CIER_HSERDYIE_Pos (4U) 6704 #define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ 6705 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk 6706 #define RCC_CIER_PLLRDYIE_Pos (5U) 6707 #define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */ 6708 #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk 6709 #define RCC_CIER_LSECSSIE_Pos (9U) 6710 #define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */ 6711 #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk 6712 #define RCC_CIER_HSI48RDYIE_Pos (10U) 6713 #define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000400 */ 6714 #define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk 6715 #define RCC_CIER_LSI2RDYIE_Pos (11U) 6716 #define RCC_CIER_LSI2RDYIE_Msk (0x1UL << RCC_CIER_LSI2RDYIE_Pos) /*!< 0x00000800 */ 6717 #define RCC_CIER_LSI2RDYIE RCC_CIER_LSI2RDYIE_Msk 6718 6719 6720 /******************** Bit definition for RCC_CIFR register ******************/ 6721 #define RCC_CIFR_LSI1RDYF_Pos (0U) 6722 #define RCC_CIFR_LSI1RDYF_Msk (0x1UL << RCC_CIFR_LSI1RDYF_Pos) /*!< 0x00000001 */ 6723 #define RCC_CIFR_LSI1RDYF RCC_CIFR_LSI1RDYF_Msk 6724 #define RCC_CIFR_LSERDYF_Pos (1U) 6725 #define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ 6726 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk 6727 #define RCC_CIFR_MSIRDYF_Pos (2U) 6728 #define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */ 6729 #define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk 6730 #define RCC_CIFR_HSIRDYF_Pos (3U) 6731 #define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ 6732 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk 6733 #define RCC_CIFR_HSERDYF_Pos (4U) 6734 #define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ 6735 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk 6736 #define RCC_CIFR_PLLRDYF_Pos (5U) 6737 #define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */ 6738 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk 6739 #define RCC_CIFR_CSSF_Pos (8U) 6740 #define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */ 6741 #define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk 6742 #define RCC_CIFR_LSECSSF_Pos (9U) 6743 #define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */ 6744 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk 6745 #define RCC_CIFR_HSI48RDYF_Pos (10U) 6746 #define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */ 6747 #define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk 6748 #define RCC_CIFR_LSI2RDYF_Pos (11U) 6749 #define RCC_CIFR_LSI2RDYF_Msk (0x1UL << RCC_CIFR_LSI2RDYF_Pos) /*!< 0x00000800 */ 6750 #define RCC_CIFR_LSI2RDYF RCC_CIFR_LSI2RDYF_Msk 6751 6752 /******************** Bit definition for RCC_CICR register ******************/ 6753 #define RCC_CICR_LSI1RDYC_Pos (0U) 6754 #define RCC_CICR_LSI1RDYC_Msk (0x1UL << RCC_CICR_LSI1RDYC_Pos) /*!< 0x00000001 */ 6755 #define RCC_CICR_LSI1RDYC RCC_CICR_LSI1RDYC_Msk 6756 #define RCC_CICR_LSERDYC_Pos (1U) 6757 #define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ 6758 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk 6759 #define RCC_CICR_MSIRDYC_Pos (2U) 6760 #define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */ 6761 #define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk 6762 #define RCC_CICR_HSIRDYC_Pos (3U) 6763 #define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ 6764 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk 6765 #define RCC_CICR_HSERDYC_Pos (4U) 6766 #define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ 6767 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk 6768 #define RCC_CICR_PLLRDYC_Pos (5U) 6769 #define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */ 6770 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk 6771 #define RCC_CICR_CSSC_Pos (8U) 6772 #define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */ 6773 #define RCC_CICR_CSSC RCC_CICR_CSSC_Msk 6774 #define RCC_CICR_LSECSSC_Pos (9U) 6775 #define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */ 6776 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk 6777 #define RCC_CICR_HSI48RDYC_Pos (10U) 6778 #define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */ 6779 #define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk 6780 #define RCC_CICR_LSI2RDYC_Pos (11U) 6781 #define RCC_CICR_LSI2RDYC_Msk (0x1UL << RCC_CICR_LSI2RDYC_Pos) /*!< 0x00000800 */ 6782 #define RCC_CICR_LSI2RDYC RCC_CICR_LSI2RDYC_Msk 6783 6784 /******************** Bit definition for RCC_AHB1RSTR register **************/ 6785 #define RCC_AHB1RSTR_DMA1RST_Pos (0U) 6786 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */ 6787 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk 6788 #define RCC_AHB1RSTR_DMAMUX1RST_Pos (2U) 6789 #define RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos) /*!< 0x00000004 */ 6790 #define RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk 6791 #define RCC_AHB1RSTR_CRCRST_Pos (12U) 6792 #define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ 6793 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk 6794 6795 /******************** Bit definition for RCC_AHB2RSTR register ***************/ 6796 #define RCC_AHB2RSTR_GPIOARST_Pos (0U) 6797 #define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */ 6798 #define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk 6799 #define RCC_AHB2RSTR_GPIOBRST_Pos (1U) 6800 #define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ 6801 #define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk 6802 #define RCC_AHB2RSTR_GPIOCRST_Pos (2U) 6803 #define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ 6804 #define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk 6805 #define RCC_AHB2RSTR_GPIOERST_Pos (4U) 6806 #define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */ 6807 #define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk 6808 #define RCC_AHB2RSTR_GPIOHRST_Pos (7U) 6809 #define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ 6810 #define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk 6811 #define RCC_AHB2RSTR_ADCRST_Pos (13U) 6812 #define RCC_AHB2RSTR_ADCRST_Msk (0x1UL << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */ 6813 #define RCC_AHB2RSTR_ADCRST RCC_AHB2RSTR_ADCRST_Msk 6814 6815 /******************** Bit definition for RCC_AHB3RSTR register ***************/ 6816 #define RCC_AHB3RSTR_PKARST_Pos (16U) 6817 #define RCC_AHB3RSTR_PKARST_Msk (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00010000 */ 6818 #define RCC_AHB3RSTR_PKARST RCC_AHB3RSTR_PKARST_Msk 6819 #define RCC_AHB3RSTR_AES2RST_Pos (17U) 6820 #define RCC_AHB3RSTR_AES2RST_Msk (0x1UL << RCC_AHB3RSTR_AES2RST_Pos) /*!< 0x00020000 */ 6821 #define RCC_AHB3RSTR_AES2RST RCC_AHB3RSTR_AES2RST_Msk 6822 #define RCC_AHB3RSTR_RNGRST_Pos (18U) 6823 #define RCC_AHB3RSTR_RNGRST_Msk (0x1UL << RCC_AHB3RSTR_RNGRST_Pos) /*!< 0x00040000 */ 6824 #define RCC_AHB3RSTR_RNGRST RCC_AHB3RSTR_RNGRST_Msk 6825 #define RCC_AHB3RSTR_HSEMRST_Pos (19U) 6826 #define RCC_AHB3RSTR_HSEMRST_Msk (0x1UL << RCC_AHB3RSTR_HSEMRST_Pos) /*!< 0x00080000 */ 6827 #define RCC_AHB3RSTR_HSEMRST RCC_AHB3RSTR_HSEMRST_Msk 6828 #define RCC_AHB3RSTR_IPCCRST_Pos (20U) 6829 #define RCC_AHB3RSTR_IPCCRST_Msk (0x1UL << RCC_AHB3RSTR_IPCCRST_Pos) /*!< 0x00100000 */ 6830 #define RCC_AHB3RSTR_IPCCRST RCC_AHB3RSTR_IPCCRST_Msk 6831 #define RCC_AHB3RSTR_FLASHRST_Pos (25U) 6832 #define RCC_AHB3RSTR_FLASHRST_Msk (0x1UL << RCC_AHB3RSTR_FLASHRST_Pos) /*!< 0x02000000 */ 6833 #define RCC_AHB3RSTR_FLASHRST RCC_AHB3RSTR_FLASHRST_Msk 6834 6835 /******************** Bit definition for RCC_APB1RSTR1 register **************/ 6836 #define RCC_APB1RSTR1_TIM2RST_Pos (0U) 6837 #define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */ 6838 #define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk 6839 #define RCC_APB1RSTR1_I2C1RST_Pos (21U) 6840 #define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */ 6841 #define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk 6842 #define RCC_APB1RSTR1_LPTIM1RST_Pos (31U) 6843 #define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */ 6844 #define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk 6845 6846 /******************** Bit definition for RCC_APB1RSTR2 register **************/ 6847 #define RCC_APB1RSTR2_LPTIM2RST_Pos (5U) 6848 #define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */ 6849 #define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk 6850 6851 /******************** Bit definition for RCC_APB2RSTR register **************/ 6852 #define RCC_APB2RSTR_TIM1RST_Pos (11U) 6853 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ 6854 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk 6855 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 6856 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ 6857 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk 6858 #define RCC_APB2RSTR_USART1RST_Pos (14U) 6859 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ 6860 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk 6861 #define RCC_APB2RSTR_TIM16RST_Pos (17U) 6862 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ 6863 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk 6864 #define RCC_APB2RSTR_TIM17RST_Pos (18U) 6865 #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ 6866 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk 6867 6868 /******************** Bit definition for RCC_APB3RSTR register **************/ 6869 #define RCC_APB3RSTR_RFRST_Pos (0U) 6870 #define RCC_APB3RSTR_RFRST_Msk (0x1UL << RCC_APB3RSTR_RFRST_Pos) /*!< 0x00000001 */ 6871 #define RCC_APB3RSTR_RFRST RCC_APB3RSTR_RFRST_Msk 6872 6873 /******************** Bit definition for RCC_AHB1ENR register ****************/ 6874 #define RCC_AHB1ENR_DMA1EN_Pos (0U) 6875 #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */ 6876 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk 6877 #define RCC_AHB1ENR_DMAMUX1EN_Pos (2U) 6878 #define RCC_AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos) /*!< 0x00000004 */ 6879 #define RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk 6880 #define RCC_AHB1ENR_CRCEN_Pos (12U) 6881 #define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ 6882 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk 6883 6884 /******************** Bit definition for RCC_AHB2ENR register ***************/ 6885 #define RCC_AHB2ENR_GPIOAEN_Pos (0U) 6886 #define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ 6887 #define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk 6888 #define RCC_AHB2ENR_GPIOBEN_Pos (1U) 6889 #define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ 6890 #define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk 6891 #define RCC_AHB2ENR_GPIOCEN_Pos (2U) 6892 #define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ 6893 #define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk 6894 #define RCC_AHB2ENR_GPIOEEN_Pos (4U) 6895 #define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */ 6896 #define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk 6897 #define RCC_AHB2ENR_GPIOHEN_Pos (7U) 6898 #define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ 6899 #define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk 6900 #define RCC_AHB2ENR_ADCEN_Pos (13U) 6901 #define RCC_AHB2ENR_ADCEN_Msk (0x1UL << RCC_AHB2ENR_ADCEN_Pos) /*!< 0x00002000 */ 6902 #define RCC_AHB2ENR_ADCEN RCC_AHB2ENR_ADCEN_Msk 6903 6904 /******************** Bit definition for RCC_AHB3ENR register ***************/ 6905 #define RCC_AHB3ENR_PKAEN_Pos (16U) 6906 #define RCC_AHB3ENR_PKAEN_Msk (0x1UL << RCC_AHB3ENR_PKAEN_Pos) /*!< 0x00010000 */ 6907 #define RCC_AHB3ENR_PKAEN RCC_AHB3ENR_PKAEN_Msk 6908 #define RCC_AHB3ENR_AES2EN_Pos (17U) 6909 #define RCC_AHB3ENR_AES2EN_Msk (0x1UL << RCC_AHB3ENR_AES2EN_Pos) /*!< 0x00020000 */ 6910 #define RCC_AHB3ENR_AES2EN RCC_AHB3ENR_AES2EN_Msk 6911 #define RCC_AHB3ENR_RNGEN_Pos (18U) 6912 #define RCC_AHB3ENR_RNGEN_Msk (0x1UL << RCC_AHB3ENR_RNGEN_Pos) /*!< 0x00040000 */ 6913 #define RCC_AHB3ENR_RNGEN RCC_AHB3ENR_RNGEN_Msk 6914 #define RCC_AHB3ENR_HSEMEN_Pos (19U) 6915 #define RCC_AHB3ENR_HSEMEN_Msk (0x1UL << RCC_AHB3ENR_HSEMEN_Pos) /*!< 0x00080000 */ 6916 #define RCC_AHB3ENR_HSEMEN RCC_AHB3ENR_HSEMEN_Msk 6917 #define RCC_AHB3ENR_IPCCEN_Pos (20U) 6918 #define RCC_AHB3ENR_IPCCEN_Msk (0x1UL << RCC_AHB3ENR_IPCCEN_Pos) /*!< 0x00100000 */ 6919 #define RCC_AHB3ENR_IPCCEN RCC_AHB3ENR_IPCCEN_Msk 6920 #define RCC_AHB3ENR_FLASHEN_Pos (25U) 6921 #define RCC_AHB3ENR_FLASHEN_Msk (0x1UL << RCC_AHB3ENR_FLASHEN_Pos) /*!< 0x02000000 */ 6922 #define RCC_AHB3ENR_FLASHEN RCC_AHB3ENR_FLASHEN_Msk 6923 6924 /******************** Bit definition for RCC_APB1ENR1 register **************/ 6925 #define RCC_APB1ENR1_TIM2EN_Pos (0U) 6926 #define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ 6927 #define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk 6928 #define RCC_APB1ENR1_RTCAPBEN_Pos (10U) 6929 #define RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos) /*!< 0x00000400 */ 6930 #define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk 6931 #define RCC_APB1ENR1_WWDGEN_Pos (11U) 6932 #define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ 6933 #define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk 6934 #define RCC_APB1ENR1_I2C1EN_Pos (21U) 6935 #define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */ 6936 #define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk 6937 #define RCC_APB1ENR1_LPTIM1EN_Pos (31U) 6938 #define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */ 6939 #define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk 6940 6941 /******************** Bit definition for RCC_APB1ENR2 register **************/ 6942 #define RCC_APB1ENR2_LPTIM2EN_Pos (5U) 6943 #define RCC_APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */ 6944 #define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk 6945 6946 /******************** Bit definition for RCC_APB2ENR register **************/ 6947 #define RCC_APB2ENR_TIM1EN_Pos (11U) 6948 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ 6949 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk 6950 #define RCC_APB2ENR_SPI1EN_Pos (12U) 6951 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 6952 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk 6953 #define RCC_APB2ENR_USART1EN_Pos (14U) 6954 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ 6955 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk 6956 #define RCC_APB2ENR_TIM16EN_Pos (17U) 6957 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ 6958 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk 6959 #define RCC_APB2ENR_TIM17EN_Pos (18U) 6960 #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ 6961 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk 6962 6963 /******************** Bit definition for RCC_AHB1SMENR register ****************/ 6964 #define RCC_AHB1SMENR_DMA1SMEN_Pos (0U) 6965 #define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */ 6966 #define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk 6967 #define RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U) 6968 #define RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos) /*!< 0x00000004 */ 6969 #define RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk 6970 #define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U) 6971 #define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */ 6972 #define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk 6973 #define RCC_AHB1SMENR_CRCSMEN_Pos (12U) 6974 #define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */ 6975 #define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk 6976 6977 /******************** Bit definition for RCC_AHB2SMENR register ***************/ 6978 #define RCC_AHB2SMENR_GPIOASMEN_Pos (0U) 6979 #define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */ 6980 #define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk 6981 #define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U) 6982 #define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */ 6983 #define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk 6984 #define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U) 6985 #define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */ 6986 #define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk 6987 #define RCC_AHB2SMENR_GPIOESMEN_Pos (4U) 6988 #define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */ 6989 #define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk 6990 #define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U) 6991 #define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */ 6992 #define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk 6993 #define RCC_AHB2SMENR_ADCSMEN_Pos (13U) 6994 #define RCC_AHB2SMENR_ADCSMEN_Msk (0x1UL << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */ 6995 #define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk 6996 6997 /******************** Bit definition for RCC_AHB3SMENR register ***************/ 6998 #define RCC_AHB3SMENR_PKASMEN_Pos (16U) 6999 #define RCC_AHB3SMENR_PKASMEN_Msk (0x1UL << RCC_AHB3SMENR_PKASMEN_Pos) /*!< 0x00010000 */ 7000 #define RCC_AHB3SMENR_PKASMEN RCC_AHB3SMENR_PKASMEN_Msk 7001 #define RCC_AHB3SMENR_AES2SMEN_Pos (17U) 7002 #define RCC_AHB3SMENR_AES2SMEN_Msk (0x1UL << RCC_AHB3SMENR_AES2SMEN_Pos) /*!< 0x00020000 */ 7003 #define RCC_AHB3SMENR_AES2SMEN RCC_AHB3SMENR_AES2SMEN_Msk 7004 #define RCC_AHB3SMENR_RNGSMEN_Pos (18U) 7005 #define RCC_AHB3SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB3SMENR_RNGSMEN_Pos) /*!< 0x00040000 */ 7006 #define RCC_AHB3SMENR_RNGSMEN RCC_AHB3SMENR_RNGSMEN_Msk 7007 #define RCC_AHB3SMENR_SRAM2SMEN_Pos (24U) 7008 #define RCC_AHB3SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB3SMENR_SRAM2SMEN_Pos) /*!< 0x01000000 */ 7009 #define RCC_AHB3SMENR_SRAM2SMEN RCC_AHB3SMENR_SRAM2SMEN_Msk 7010 #define RCC_AHB3SMENR_FLASHSMEN_Pos (25U) 7011 #define RCC_AHB3SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB3SMENR_FLASHSMEN_Pos) /*!< 0x02000000 */ 7012 #define RCC_AHB3SMENR_FLASHSMEN RCC_AHB3SMENR_FLASHSMEN_Msk 7013 7014 /******************** Bit definition for RCC_APB1SMENR1 register **************/ 7015 #define RCC_APB1SMENR1_TIM2SMEN_Pos (0U) 7016 #define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */ 7017 #define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk 7018 #define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U) 7019 #define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */ 7020 #define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk 7021 #define RCC_APB1SMENR1_WWDGSMEN_Pos (11U) 7022 #define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ 7023 #define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk 7024 #define RCC_APB1SMENR1_I2C1SMEN_Pos (21U) 7025 #define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */ 7026 #define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk 7027 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U) 7028 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */ 7029 #define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk 7030 7031 /******************** Bit definition for RCC_APB1SMENR2 register **************/ 7032 #define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U) 7033 #define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */ 7034 #define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk 7035 7036 /******************** Bit definition for RCC_APB2SMENR register **************/ 7037 #define RCC_APB2SMENR_TIM1SMEN_Pos (11U) 7038 #define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */ 7039 #define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk 7040 #define RCC_APB2SMENR_SPI1SMEN_Pos (12U) 7041 #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */ 7042 #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk 7043 #define RCC_APB2SMENR_USART1SMEN_Pos (14U) 7044 #define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */ 7045 #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk 7046 #define RCC_APB2SMENR_TIM16SMEN_Pos (17U) 7047 #define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */ 7048 #define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk 7049 #define RCC_APB2SMENR_TIM17SMEN_Pos (18U) 7050 #define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */ 7051 #define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk 7052 7053 /******************** Bit definition for RCC_CCIPR register ******************/ 7054 #define RCC_CCIPR_USART1SEL_Pos (0U) 7055 #define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */ 7056 #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk 7057 #define RCC_CCIPR_USART1SEL_0 (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */ 7058 #define RCC_CCIPR_USART1SEL_1 (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */ 7059 7060 #define RCC_CCIPR_I2C1SEL_Pos (12U) 7061 #define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */ 7062 #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk 7063 #define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */ 7064 #define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */ 7065 7066 #define RCC_CCIPR_LPTIM1SEL_Pos (18U) 7067 #define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */ 7068 #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk 7069 #define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */ 7070 #define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */ 7071 7072 #define RCC_CCIPR_LPTIM2SEL_Pos (20U) 7073 #define RCC_CCIPR_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */ 7074 #define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk 7075 #define RCC_CCIPR_LPTIM2SEL_0 (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */ 7076 #define RCC_CCIPR_LPTIM2SEL_1 (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */ 7077 7078 #define RCC_CCIPR_CLK48SEL_Pos (26U) 7079 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ 7080 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk 7081 #define RCC_CCIPR_CLK48SEL_0 (0x1U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */ 7082 #define RCC_CCIPR_CLK48SEL_1 (0x2U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */ 7083 7084 #define RCC_CCIPR_ADCSEL_Pos (28U) 7085 #define RCC_CCIPR_ADCSEL_Msk (0x3UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x30000000 */ 7086 #define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk 7087 #define RCC_CCIPR_ADCSEL_0 (0x1U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x10000000 */ 7088 #define RCC_CCIPR_ADCSEL_1 (0x2U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x20000000 */ 7089 7090 #define RCC_CCIPR_RNGSEL_Pos (30U) 7091 #define RCC_CCIPR_RNGSEL_Msk (0x3UL << RCC_CCIPR_RNGSEL_Pos) /*!< 0xC0000000 */ 7092 #define RCC_CCIPR_RNGSEL RCC_CCIPR_RNGSEL_Msk 7093 #define RCC_CCIPR_RNGSEL_0 (0x1U << RCC_CCIPR_RNGSEL_Pos) /*!< 0x40000000 */ 7094 #define RCC_CCIPR_RNGSEL_1 (0x2U << RCC_CCIPR_RNGSEL_Pos) /*!< 0x80000000 */ 7095 7096 /******************** Bit definition for RCC_BDCR register ******************/ 7097 #define RCC_BDCR_LSEON_Pos (0U) 7098 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ 7099 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk 7100 #define RCC_BDCR_LSERDY_Pos (1U) 7101 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ 7102 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk 7103 #define RCC_BDCR_LSEBYP_Pos (2U) 7104 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ 7105 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk 7106 7107 #define RCC_BDCR_LSEDRV_Pos (3U) 7108 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ 7109 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk 7110 #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ 7111 #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ 7112 7113 #define RCC_BDCR_LSECSSON_Pos (5U) 7114 #define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */ 7115 #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk 7116 #define RCC_BDCR_LSECSSD_Pos (6U) 7117 #define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */ 7118 #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk 7119 7120 #define RCC_BDCR_RTCSEL_Pos (8U) 7121 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ 7122 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk 7123 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ 7124 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ 7125 7126 #define RCC_BDCR_RTCEN_Pos (15U) 7127 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ 7128 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk 7129 7130 #define RCC_BDCR_BDRST_Pos (16U) 7131 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ 7132 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk 7133 7134 #define RCC_BDCR_LSCOEN_Pos (24U) 7135 #define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */ 7136 #define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk 7137 #define RCC_BDCR_LSCOSEL_Pos (25U) 7138 #define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */ 7139 #define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk 7140 7141 /******************** Bit definition for RCC_CSR register *******************/ 7142 #define RCC_CSR_LSI1ON_Pos (0U) 7143 #define RCC_CSR_LSI1ON_Msk (0x1UL << RCC_CSR_LSI1ON_Pos) /*!< 0x00000001 */ 7144 #define RCC_CSR_LSI1ON RCC_CSR_LSI1ON_Msk 7145 #define RCC_CSR_LSI1RDY_Pos (1U) 7146 #define RCC_CSR_LSI1RDY_Msk (0x1UL << RCC_CSR_LSI1RDY_Pos) /*!< 0x00000002 */ 7147 #define RCC_CSR_LSI1RDY RCC_CSR_LSI1RDY_Msk 7148 #define RCC_CSR_LSI2ON_Pos (2U) 7149 #define RCC_CSR_LSI2ON_Msk (0x1UL << RCC_CSR_LSI2ON_Pos) /*!< 0x00000004 */ 7150 #define RCC_CSR_LSI2ON RCC_CSR_LSI2ON_Msk 7151 #define RCC_CSR_LSI2RDY_Pos (3U) 7152 #define RCC_CSR_LSI2RDY_Msk (0x1UL << RCC_CSR_LSI2RDY_Pos) /*!< 0x00000008 */ 7153 #define RCC_CSR_LSI2RDY RCC_CSR_LSI2RDY_Msk 7154 #define RCC_CSR_LSI2TRIM_Pos (8U) 7155 #define RCC_CSR_LSI2TRIM_Msk (0xFUL << RCC_CSR_LSI2TRIM_Pos) /*!< 0x00000F00 */ 7156 #define RCC_CSR_LSI2TRIM RCC_CSR_LSI2TRIM_Msk 7157 #define RCC_CSR_LSI2TRIM_0 (0x1U << RCC_CSR_LSI2TRIM_Pos) /*!< 0x00000100 */ 7158 #define RCC_CSR_LSI2TRIM_1 (0x2U << RCC_CSR_LSI2TRIM_Pos) /*!< 0x00000200 */ 7159 #define RCC_CSR_LSI2TRIM_2 (0x4U << RCC_CSR_LSI2TRIM_Pos) /*!< 0x00000400 */ 7160 #define RCC_CSR_LSI2TRIM_3 (0x8U << RCC_CSR_LSI2TRIM_Pos) /*!< 0x00000800 */ 7161 #define RCC_CSR_RFWKPSEL_Pos (14U) 7162 #define RCC_CSR_RFWKPSEL_Msk (0x3UL << RCC_CSR_RFWKPSEL_Pos) /*!< 0x0000C000 */ 7163 #define RCC_CSR_RFWKPSEL RCC_CSR_RFWKPSEL_Msk 7164 #define RCC_CSR_RFWKPSEL_0 (0x1U << RCC_CSR_RFWKPSEL_Pos) /*!< 0x00004000 */ 7165 #define RCC_CSR_RFWKPSEL_1 (0x2U << RCC_CSR_RFWKPSEL_Pos) /*!< 0x00008000 */ 7166 #define RCC_CSR_RFRSTS_Pos (16U) 7167 #define RCC_CSR_RFRSTS_Msk (0x1UL << RCC_CSR_RFRSTS_Pos) /*!< 0x00010000 */ 7168 #define RCC_CSR_RFRSTS RCC_CSR_RFRSTS_Msk 7169 #define RCC_CSR_RMVF_Pos (23U) 7170 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ 7171 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk 7172 #define RCC_CSR_OBLRSTF_Pos (25U) 7173 #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ 7174 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk 7175 #define RCC_CSR_PINRSTF_Pos (26U) 7176 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 7177 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk 7178 #define RCC_CSR_BORRSTF_Pos (27U) 7179 #define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */ 7180 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk 7181 #define RCC_CSR_SFTRSTF_Pos (28U) 7182 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 7183 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk 7184 #define RCC_CSR_IWDGRSTF_Pos (29U) 7185 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 7186 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk 7187 #define RCC_CSR_WWDGRSTF_Pos (30U) 7188 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 7189 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk 7190 #define RCC_CSR_LPWRRSTF_Pos (31U) 7191 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 7192 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk 7193 7194 /******************** Bit definition for RCC_CRRCR register *******************/ 7195 #define RCC_CRRCR_HSI48ON_Pos (0U) 7196 #define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */ 7197 #define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk 7198 #define RCC_CRRCR_HSI48RDY_Pos (1U) 7199 #define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */ 7200 #define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk 7201 #define RCC_CRRCR_HSI48CAL_Pos (7U) 7202 #define RCC_CRRCR_HSI48CAL_Msk (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF80 */ 7203 #define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk 7204 #define RCC_CRRCR_HSI48CAL_0 (0x001U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */ 7205 #define RCC_CRRCR_HSI48CAL_1 (0x002U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */ 7206 #define RCC_CRRCR_HSI48CAL_2 (0x004U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */ 7207 #define RCC_CRRCR_HSI48CAL_3 (0x008U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000400 */ 7208 #define RCC_CRRCR_HSI48CAL_4 (0x010U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000800 */ 7209 #define RCC_CRRCR_HSI48CAL_5 (0x020U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00001000 */ 7210 #define RCC_CRRCR_HSI48CAL_6 (0x040U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00002000 */ 7211 #define RCC_CRRCR_HSI48CAL_7 (0x080U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00004000 */ 7212 #define RCC_CRRCR_HSI48CAL_8 (0x100U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00008000 */ 7213 7214 /******************** Bit definition for RCC_HSECR register *******************/ 7215 #define RCC_HSECR_UNLOCKED_Pos (0U) 7216 #define RCC_HSECR_UNLOCKED_Msk (0x1UL << RCC_HSECR_UNLOCKED_Pos) /*!< 0x00000001 */ 7217 #define RCC_HSECR_UNLOCKED RCC_HSECR_UNLOCKED_Msk 7218 7219 #define RCC_HSECR_HSES_Pos (3U) 7220 #define RCC_HSECR_HSES_Msk (0x1UL << RCC_HSECR_HSES_Pos) /*!< 0x00000008 */ 7221 #define RCC_HSECR_HSES RCC_HSECR_HSES_Msk 7222 7223 #define RCC_HSECR_HSEGMC_Pos (4U) 7224 #define RCC_HSECR_HSEGMC_Msk (0x7UL << RCC_HSECR_HSEGMC_Pos) /*!< 0x00000070 */ 7225 #define RCC_HSECR_HSEGMC RCC_HSECR_HSEGMC_Msk 7226 #define RCC_HSECR_HSEGMC0_Pos (4U) 7227 #define RCC_HSECR_HSEGMC0_Msk (0x1UL << RCC_HSECR_HSEGMC0_Pos) /*!< 0x00000010 */ 7228 #define RCC_HSECR_HSEGMC0 RCC_HSECR_HSEGMC0_Msk 7229 #define RCC_HSECR_HSEGMC1_Pos (5U) 7230 #define RCC_HSECR_HSEGMC1_Msk (0x1UL << RCC_HSECR_HSEGMC1_Pos) /*!< 0x00000020 */ 7231 #define RCC_HSECR_HSEGMC1 RCC_HSECR_HSEGMC1_Msk 7232 #define RCC_HSECR_HSEGMC2_Pos (6U) 7233 #define RCC_HSECR_HSEGMC2_Msk (0x1UL << RCC_HSECR_HSEGMC2_Pos) /*!< 0x00000040 */ 7234 #define RCC_HSECR_HSEGMC2 RCC_HSECR_HSEGMC2_Msk 7235 7236 #define RCC_HSECR_HSETUNE_Pos (8U) 7237 #define RCC_HSECR_HSETUNE_Msk (0x3FUL << RCC_HSECR_HSETUNE_Pos) /*!< 0x00003F00 */ 7238 #define RCC_HSECR_HSETUNE RCC_HSECR_HSETUNE_Msk 7239 #define RCC_HSECR_HSETUNE0_Pos (8U) 7240 #define RCC_HSECR_HSETUNE0_Msk (0x1UL << RCC_HSECR_HSETUNE0_Pos) /*!< 0x00000100 */ 7241 #define RCC_HSECR_HSETUNE0 RCC_HSECR_HSETUNE0_Msk 7242 #define RCC_HSECR_HSETUNE1_Pos (9U) 7243 #define RCC_HSECR_HSETUNE1_Msk (0x1UL << RCC_HSECR_HSETUNE1_Pos) /*!< 0x00000200 */ 7244 #define RCC_HSECR_HSETUNE1 RCC_HSECR_HSETUNE1_Msk 7245 #define RCC_HSECR_HSETUNE2_Pos (10U) 7246 #define RCC_HSECR_HSETUNE2_Msk (0x1UL << RCC_HSECR_HSETUNE2_Pos) /*!< 0x00000400 */ 7247 #define RCC_HSECR_HSETUNE2 RCC_HSECR_HSETUNE2_Msk 7248 #define RCC_HSECR_HSETUNE3_Pos (11U) 7249 #define RCC_HSECR_HSETUNE3_Msk (0x1UL << RCC_HSECR_HSETUNE3_Pos) /*!< 0x00000800 */ 7250 #define RCC_HSECR_HSETUNE3 RCC_HSECR_HSETUNE3_Msk 7251 #define RCC_HSECR_HSETUNE4_Pos (12U) 7252 #define RCC_HSECR_HSETUNE4_Msk (0x1UL << RCC_HSECR_HSETUNE4_Pos) /*!< 0x00001000 */ 7253 #define RCC_HSECR_HSETUNE4 RCC_HSECR_HSETUNE4_Msk 7254 #define RCC_HSECR_HSETUNE5_Pos (13U) 7255 #define RCC_HSECR_HSETUNE5_Msk (0x1UL << RCC_HSECR_HSETUNE5_Pos) /*!< 0x00002000 */ 7256 #define RCC_HSECR_HSETUNE5 RCC_HSECR_HSETUNE5_Msk 7257 7258 /******************** Bit definition for RCC_EXTCFGR register *******************/ 7259 #define RCC_EXTCFGR_SHDHPRE_Pos (0U) 7260 #define RCC_EXTCFGR_SHDHPRE_Msk (0xFUL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x0000000F */ 7261 #define RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_Msk 7262 #define RCC_EXTCFGR_SHDHPRE_0 (0x1U << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000001 */ 7263 #define RCC_EXTCFGR_SHDHPRE_1 (0x2U << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000002 */ 7264 #define RCC_EXTCFGR_SHDHPRE_2 (0x4U << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000004 */ 7265 #define RCC_EXTCFGR_SHDHPRE_3 (0x8U << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000008 */ 7266 7267 #define RCC_EXTCFGR_C2HPRE_Pos (4U) 7268 #define RCC_EXTCFGR_C2HPRE_Msk (0xFUL << RCC_EXTCFGR_C2HPRE_Pos) /*!< 0x000000F0 */ 7269 #define RCC_EXTCFGR_C2HPRE RCC_EXTCFGR_C2HPRE_Msk 7270 #define RCC_EXTCFGR_C2HPRE_0 (0x1U << RCC_EXTCFGR_C2HPRE_Pos) /*!< 0x00000010 */ 7271 #define RCC_EXTCFGR_C2HPRE_1 (0x2U << RCC_EXTCFGR_C2HPRE_Pos) /*!< 0x00000020 */ 7272 #define RCC_EXTCFGR_C2HPRE_2 (0x4U << RCC_EXTCFGR_C2HPRE_Pos) /*!< 0x00000040 */ 7273 #define RCC_EXTCFGR_C2HPRE_3 (0x8U << RCC_EXTCFGR_C2HPRE_Pos) /*!< 0x00000080 */ 7274 7275 #define RCC_EXTCFGR_SHDHPREF_Pos (16U) 7276 #define RCC_EXTCFGR_SHDHPREF_Msk (0x1UL << RCC_EXTCFGR_SHDHPREF_Pos) /*!< 0x00010000 */ 7277 #define RCC_EXTCFGR_SHDHPREF RCC_EXTCFGR_SHDHPREF_Msk 7278 #define RCC_EXTCFGR_C2HPREF_Pos (17U) 7279 #define RCC_EXTCFGR_C2HPREF_Msk (0x1UL << RCC_EXTCFGR_C2HPREF_Pos) /*!< 0x00020000 */ 7280 #define RCC_EXTCFGR_C2HPREF RCC_EXTCFGR_C2HPREF_Msk 7281 #define RCC_EXTCFGR_RFCSS_Pos (20U) 7282 #define RCC_EXTCFGR_RFCSS_Msk (0x1UL << RCC_EXTCFGR_RFCSS_Pos) /*!< 0x00100000 */ 7283 #define RCC_EXTCFGR_RFCSS RCC_EXTCFGR_RFCSS_Msk 7284 7285 /******************** Bit definition for RCC_C2AHB1ENR register ****************/ 7286 #define RCC_C2AHB1ENR_DMA1EN_Pos (0U) 7287 #define RCC_C2AHB1ENR_DMA1EN_Msk (0x1UL << RCC_C2AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */ 7288 #define RCC_C2AHB1ENR_DMA1EN RCC_C2AHB1ENR_DMA1EN_Msk 7289 #define RCC_C2AHB1ENR_DMAMUX1EN_Pos (2U) 7290 #define RCC_C2AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_C2AHB1ENR_DMAMUX1EN_Pos) /*!< 0x00000004 */ 7291 #define RCC_C2AHB1ENR_DMAMUX1EN RCC_C2AHB1ENR_DMAMUX1EN_Msk 7292 #define RCC_C2AHB1ENR_SRAM1EN_Pos (9U) 7293 #define RCC_C2AHB1ENR_SRAM1EN_Msk (0x1UL << RCC_C2AHB1ENR_SRAM1EN_Pos) /*!< 0x00000200 */ 7294 #define RCC_C2AHB1ENR_SRAM1EN RCC_C2AHB1ENR_SRAM1EN_Msk 7295 #define RCC_C2AHB1ENR_CRCEN_Pos (12U) 7296 #define RCC_C2AHB1ENR_CRCEN_Msk (0x1UL << RCC_C2AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ 7297 #define RCC_C2AHB1ENR_CRCEN RCC_C2AHB1ENR_CRCEN_Msk 7298 7299 /******************** Bit definition for RCC_C2AHB2ENR register ***************/ 7300 #define RCC_C2AHB2ENR_GPIOAEN_Pos (0U) 7301 #define RCC_C2AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_C2AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ 7302 #define RCC_C2AHB2ENR_GPIOAEN RCC_C2AHB2ENR_GPIOAEN_Msk 7303 #define RCC_C2AHB2ENR_GPIOBEN_Pos (1U) 7304 #define RCC_C2AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_C2AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ 7305 #define RCC_C2AHB2ENR_GPIOBEN RCC_C2AHB2ENR_GPIOBEN_Msk 7306 #define RCC_C2AHB2ENR_GPIOCEN_Pos (2U) 7307 #define RCC_C2AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_C2AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ 7308 #define RCC_C2AHB2ENR_GPIOCEN RCC_C2AHB2ENR_GPIOCEN_Msk 7309 #define RCC_C2AHB2ENR_GPIOEEN_Pos (4U) 7310 #define RCC_C2AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_C2AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */ 7311 #define RCC_C2AHB2ENR_GPIOEEN RCC_C2AHB2ENR_GPIOEEN_Msk 7312 #define RCC_C2AHB2ENR_GPIOHEN_Pos (7U) 7313 #define RCC_C2AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_C2AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ 7314 #define RCC_C2AHB2ENR_GPIOHEN RCC_C2AHB2ENR_GPIOHEN_Msk 7315 #define RCC_C2AHB2ENR_ADCEN_Pos (13U) 7316 #define RCC_C2AHB2ENR_ADCEN_Msk (0x1UL << RCC_C2AHB2ENR_ADCEN_Pos) /*!< 0x00002000 */ 7317 #define RCC_C2AHB2ENR_ADCEN RCC_C2AHB2ENR_ADCEN_Msk 7318 7319 /******************** Bit definition for RCC_C2AHB3ENR register ***************/ 7320 #define RCC_C2AHB3ENR_PKAEN_Pos (16U) 7321 #define RCC_C2AHB3ENR_PKAEN_Msk (0x1UL << RCC_C2AHB3ENR_PKAEN_Pos) /*!< 0x00010000 */ 7322 #define RCC_C2AHB3ENR_PKAEN RCC_C2AHB3ENR_PKAEN_Msk 7323 #define RCC_C2AHB3ENR_AES2EN_Pos (17U) 7324 #define RCC_C2AHB3ENR_AES2EN_Msk (0x1UL << RCC_C2AHB3ENR_AES2EN_Pos) /*!< 0x00020000 */ 7325 #define RCC_C2AHB3ENR_AES2EN RCC_C2AHB3ENR_AES2EN_Msk 7326 #define RCC_C2AHB3ENR_RNGEN_Pos (18U) 7327 #define RCC_C2AHB3ENR_RNGEN_Msk (0x1UL << RCC_C2AHB3ENR_RNGEN_Pos) /*!< 0x00040000 */ 7328 #define RCC_C2AHB3ENR_RNGEN RCC_C2AHB3ENR_RNGEN_Msk 7329 #define RCC_C2AHB3ENR_HSEMEN_Pos (19U) 7330 #define RCC_C2AHB3ENR_HSEMEN_Msk (0x1UL << RCC_C2AHB3ENR_HSEMEN_Pos) /*!< 0x00080000 */ 7331 #define RCC_C2AHB3ENR_HSEMEN RCC_C2AHB3ENR_HSEMEN_Msk 7332 #define RCC_C2AHB3ENR_IPCCEN_Pos (20U) 7333 #define RCC_C2AHB3ENR_IPCCEN_Msk (0x1UL << RCC_C2AHB3ENR_IPCCEN_Pos) /*!< 0x00100000 */ 7334 #define RCC_C2AHB3ENR_IPCCEN RCC_C2AHB3ENR_IPCCEN_Msk 7335 #define RCC_C2AHB3ENR_FLASHEN_Pos (25U) 7336 #define RCC_C2AHB3ENR_FLASHEN_Msk (0x1UL << RCC_C2AHB3ENR_FLASHEN_Pos) /*!< 0x02000000 */ 7337 #define RCC_C2AHB3ENR_FLASHEN RCC_C2AHB3ENR_FLASHEN_Msk 7338 7339 /******************** Bit definition for RCC_C2APB1ENR1 register **************/ 7340 #define RCC_C2APB1ENR1_TIM2EN_Pos (0U) 7341 #define RCC_C2APB1ENR1_TIM2EN_Msk (0x1UL << RCC_C2APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ 7342 #define RCC_C2APB1ENR1_TIM2EN RCC_C2APB1ENR1_TIM2EN_Msk 7343 #define RCC_C2APB1ENR1_RTCAPBEN_Pos (10U) 7344 #define RCC_C2APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_C2APB1ENR1_RTCAPBEN_Pos) /*!< 0x00000400 */ 7345 #define RCC_C2APB1ENR1_RTCAPBEN RCC_C2APB1ENR1_RTCAPBEN_Msk 7346 #define RCC_C2APB1ENR1_I2C1EN_Pos (21U) 7347 #define RCC_C2APB1ENR1_I2C1EN_Msk (0x1UL << RCC_C2APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */ 7348 #define RCC_C2APB1ENR1_I2C1EN RCC_C2APB1ENR1_I2C1EN_Msk 7349 #define RCC_C2APB1ENR1_LPTIM1EN_Pos (31U) 7350 #define RCC_C2APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_C2APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */ 7351 #define RCC_C2APB1ENR1_LPTIM1EN RCC_C2APB1ENR1_LPTIM1EN_Msk 7352 7353 /******************** Bit definition for RCC_C2APB1ENR2 register **************/ 7354 #define RCC_C2APB1ENR2_LPTIM2EN_Pos (5U) 7355 #define RCC_C2APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_C2APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */ 7356 #define RCC_C2APB1ENR2_LPTIM2EN RCC_C2APB1ENR2_LPTIM2EN_Msk 7357 7358 /******************** Bit definition for RCC_C2APB2ENR register **************/ 7359 #define RCC_C2APB2ENR_TIM1EN_Pos (11U) 7360 #define RCC_C2APB2ENR_TIM1EN_Msk (0x1UL << RCC_C2APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ 7361 #define RCC_C2APB2ENR_TIM1EN RCC_C2APB2ENR_TIM1EN_Msk 7362 #define RCC_C2APB2ENR_SPI1EN_Pos (12U) 7363 #define RCC_C2APB2ENR_SPI1EN_Msk (0x1UL << RCC_C2APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 7364 #define RCC_C2APB2ENR_SPI1EN RCC_C2APB2ENR_SPI1EN_Msk 7365 #define RCC_C2APB2ENR_USART1EN_Pos (14U) 7366 #define RCC_C2APB2ENR_USART1EN_Msk (0x1UL << RCC_C2APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ 7367 #define RCC_C2APB2ENR_USART1EN RCC_C2APB2ENR_USART1EN_Msk 7368 #define RCC_C2APB2ENR_TIM16EN_Pos (17U) 7369 #define RCC_C2APB2ENR_TIM16EN_Msk (0x1UL << RCC_C2APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ 7370 #define RCC_C2APB2ENR_TIM16EN RCC_C2APB2ENR_TIM16EN_Msk 7371 #define RCC_C2APB2ENR_TIM17EN_Pos (18U) 7372 #define RCC_C2APB2ENR_TIM17EN_Msk (0x1UL << RCC_C2APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ 7373 #define RCC_C2APB2ENR_TIM17EN RCC_C2APB2ENR_TIM17EN_Msk 7374 7375 /******************** Bit definition for RCC_C2APB3ENR register **************/ 7376 #define RCC_C2APB3ENR_BLEEN_Pos (0U) 7377 #define RCC_C2APB3ENR_BLEEN_Msk (0x1UL << RCC_C2APB3ENR_BLEEN_Pos) /*!< 0x00000001 */ 7378 #define RCC_C2APB3ENR_BLEEN RCC_C2APB3ENR_BLEEN_Msk 7379 #define RCC_C2APB3ENR_802EN_Pos (1U) 7380 #define RCC_C2APB3ENR_802EN_Msk (0x1UL << RCC_C2APB3ENR_802EN_Pos) /*!< x00000002U */ 7381 #define RCC_C2APB3ENR_802EN RCC_C2APB3ENR_802EN_Msk 7382 7383 /******************** Bit definition for RCC_C2AHB1SMENR register ****************/ 7384 #define RCC_C2AHB1SMENR_DMA1SMEN_Pos (0U) 7385 #define RCC_C2AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_C2AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */ 7386 #define RCC_C2AHB1SMENR_DMA1SMEN RCC_C2AHB1SMENR_DMA1SMEN_Msk 7387 #define RCC_C2AHB1SMENR_DMAMUX1SMEN_Pos (2U) 7388 #define RCC_C2AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_C2AHB1SMENR_DMAMUX1SMEN_Pos) /*!< 0x00000004 */ 7389 #define RCC_C2AHB1SMENR_DMAMUX1SMEN RCC_C2AHB1SMENR_DMAMUX1SMEN_Msk 7390 #define RCC_C2AHB1SMENR_SRAM1SMEN_Pos (9U) 7391 #define RCC_C2AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_C2AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */ 7392 #define RCC_C2AHB1SMENR_SRAM1SMEN RCC_C2AHB1SMENR_SRAM1SMEN_Msk 7393 #define RCC_C2AHB1SMENR_CRCSMEN_Pos (12U) 7394 #define RCC_C2AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_C2AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */ 7395 #define RCC_C2AHB1SMENR_CRCSMEN RCC_C2AHB1SMENR_CRCSMEN_Msk 7396 7397 /******************** Bit definition for RCC_C2AHB2SMENR register ***************/ 7398 #define RCC_C2AHB2SMENR_GPIOASMEN_Pos (0U) 7399 #define RCC_C2AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_C2AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */ 7400 #define RCC_C2AHB2SMENR_GPIOASMEN RCC_C2AHB2SMENR_GPIOASMEN_Msk 7401 #define RCC_C2AHB2SMENR_GPIOBSMEN_Pos (1U) 7402 #define RCC_C2AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_C2AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */ 7403 #define RCC_C2AHB2SMENR_GPIOBSMEN RCC_C2AHB2SMENR_GPIOBSMEN_Msk 7404 #define RCC_C2AHB2SMENR_GPIOCSMEN_Pos (2U) 7405 #define RCC_C2AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_C2AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */ 7406 #define RCC_C2AHB2SMENR_GPIOCSMEN RCC_C2AHB2SMENR_GPIOCSMEN_Msk 7407 #define RCC_C2AHB2SMENR_GPIOESMEN_Pos (4U) 7408 #define RCC_C2AHB2SMENR_GPIOESMEN_Msk (0x1UL << RCC_C2AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */ 7409 #define RCC_C2AHB2SMENR_GPIOESMEN RCC_C2AHB2SMENR_GPIOESMEN_Msk 7410 #define RCC_C2AHB2SMENR_GPIOHSMEN_Pos (7U) 7411 #define RCC_C2AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_C2AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */ 7412 #define RCC_C2AHB2SMENR_GPIOHSMEN RCC_C2AHB2SMENR_GPIOHSMEN_Msk 7413 #define RCC_C2AHB2SMENR_ADCSMEN_Pos (13U) 7414 #define RCC_C2AHB2SMENR_ADCSMEN_Msk (0x1UL << RCC_C2AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */ 7415 #define RCC_C2AHB2SMENR_ADCSMEN RCC_C2AHB2SMENR_ADCSMEN_Msk 7416 7417 /******************** Bit definition for RCC_C2AHB3SMENR register ***************/ 7418 #define RCC_C2AHB3SMENR_PKASMEN_Pos (16U) 7419 #define RCC_C2AHB3SMENR_PKASMEN_Msk (0x1UL << RCC_C2AHB3SMENR_PKASMEN_Pos) /*!< 0x00010000 */ 7420 #define RCC_C2AHB3SMENR_PKASMEN RCC_C2AHB3SMENR_PKASMEN_Msk 7421 #define RCC_C2AHB3SMENR_AES2SMEN_Pos (17U) 7422 #define RCC_C2AHB3SMENR_AES2SMEN_Msk (0x1UL << RCC_C2AHB3SMENR_AES2SMEN_Pos) /*!< 0x00020000 */ 7423 #define RCC_C2AHB3SMENR_AES2SMEN RCC_C2AHB3SMENR_AES2SMEN_Msk 7424 #define RCC_C2AHB3SMENR_RNGSMEN_Pos (18U) 7425 #define RCC_C2AHB3SMENR_RNGSMEN_Msk (0x1UL << RCC_C2AHB3SMENR_RNGSMEN_Pos) /*!< 0x00040000 */ 7426 #define RCC_C2AHB3SMENR_RNGSMEN RCC_C2AHB3SMENR_RNGSMEN_Msk 7427 #define RCC_C2AHB3SMENR_SRAM2SMEN_Pos (24U) 7428 #define RCC_C2AHB3SMENR_SRAM2SMEN_Msk (0x1UL << RCC_C2AHB3SMENR_SRAM2SMEN_Pos) /*!< 0x01000000 */ 7429 #define RCC_C2AHB3SMENR_SRAM2SMEN RCC_C2AHB3SMENR_SRAM2SMEN_Msk 7430 #define RCC_C2AHB3SMENR_FLASHSMEN_Pos (25U) 7431 #define RCC_C2AHB3SMENR_FLASHSMEN_Msk (0x1UL << RCC_C2AHB3SMENR_FLASHSMEN_Pos) /*!< 0x02000000 */ 7432 #define RCC_C2AHB3SMENR_FLASHSMEN RCC_C2AHB3SMENR_FLASHSMEN_Msk 7433 7434 /******************** Bit definition for RCC_C2APB1SMENR1 register **************/ 7435 #define RCC_C2APB1SMENR1_TIM2SMEN_Pos (0U) 7436 #define RCC_C2APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */ 7437 #define RCC_C2APB1SMENR1_TIM2SMEN RCC_C2APB1SMENR1_TIM2SMEN_Msk 7438 #define RCC_C2APB1SMENR1_RTCAPBSMEN_Pos (10U) 7439 #define RCC_C2APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_C2APB1SMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */ 7440 #define RCC_C2APB1SMENR1_RTCAPBSMEN RCC_C2APB1SMENR1_RTCAPBSMEN_Msk 7441 #define RCC_C2APB1SMENR1_I2C1SMEN_Pos (21U) 7442 #define RCC_C2APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */ 7443 #define RCC_C2APB1SMENR1_I2C1SMEN RCC_C2APB1SMENR1_I2C1SMEN_Msk 7444 #define RCC_C2APB1SMENR1_LPTIM1SMEN_Pos (31U) 7445 #define RCC_C2APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_C2APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */ 7446 #define RCC_C2APB1SMENR1_LPTIM1SMEN RCC_C2APB1SMENR1_LPTIM1SMEN_Msk 7447 7448 /******************** Bit definition for RCC_C2APB1SMENR2 register **************/ 7449 #define RCC_C2APB1SMENR2_LPTIM2SMEN_Pos (5U) 7450 #define RCC_C2APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_C2APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */ 7451 #define RCC_C2APB1SMENR2_LPTIM2SMEN RCC_C2APB1SMENR2_LPTIM2SMEN_Msk 7452 7453 /******************** Bit definition for RCC_C2APB2SMENR register **************/ 7454 #define RCC_C2APB2SMENR_TIM1SMEN_Pos (11U) 7455 #define RCC_C2APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */ 7456 #define RCC_C2APB2SMENR_TIM1SMEN RCC_C2APB2SMENR_TIM1SMEN_Msk 7457 #define RCC_C2APB2SMENR_SPI1SMEN_Pos (12U) 7458 #define RCC_C2APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */ 7459 #define RCC_C2APB2SMENR_SPI1SMEN RCC_C2APB2SMENR_SPI1SMEN_Msk 7460 #define RCC_C2APB2SMENR_USART1SMEN_Pos (14U) 7461 #define RCC_C2APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */ 7462 #define RCC_C2APB2SMENR_USART1SMEN RCC_C2APB2SMENR_USART1SMEN_Msk 7463 #define RCC_C2APB2SMENR_TIM16SMEN_Pos (17U) 7464 #define RCC_C2APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */ 7465 #define RCC_C2APB2SMENR_TIM16SMEN RCC_C2APB2SMENR_TIM16SMEN_Msk 7466 #define RCC_C2APB2SMENR_TIM17SMEN_Pos (18U) 7467 #define RCC_C2APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */ 7468 #define RCC_C2APB2SMENR_TIM17SMEN RCC_C2APB2SMENR_TIM17SMEN_Msk 7469 7470 /******************** Bit definition for RCC_C2APB3SMENR register **************/ 7471 #define RCC_C2APB3SMENR_BLESMEN_Pos (0U) 7472 #define RCC_C2APB3SMENR_BLESMEN_Msk (0x1UL << RCC_C2APB3SMENR_BLESMEN_Pos) /*!< 0x00000001 */ 7473 #define RCC_C2APB3SMENR_BLESMEN RCC_C2APB3SMENR_BLESMEN_Msk 7474 #define RCC_C2APB3SMENR_802SMEN_Pos (1U) 7475 #define RCC_C2APB3SMENR_802SMEN_Msk (0x1UL << RCC_C2APB3SMENR_802SMEN_Pos) /*!< 0x00000002 */ 7476 #define RCC_C2APB3SMENR_802SMEN RCC_C2APB3SMENR_802SMEN_Msk 7477 7478 /******************************************************************************/ 7479 /* */ 7480 /* RNG */ 7481 /* */ 7482 /******************************************************************************/ 7483 /******************** Bits definition for register *******************/ 7484 #define RNG_CR_RNGEN_Pos (2U) 7485 #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ 7486 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk 7487 #define RNG_CR_IE_Pos (3U) 7488 #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ 7489 #define RNG_CR_IE RNG_CR_IE_Msk 7490 #define RNG_CR_CED_Pos (5U) 7491 #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ 7492 #define RNG_CR_CED RNG_CR_CED_Msk 7493 7494 /******************** Bits definition for RNG_SR register *******************/ 7495 #define RNG_SR_DRDY_Pos (0U) 7496 #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ 7497 #define RNG_SR_DRDY RNG_SR_DRDY_Msk 7498 #define RNG_SR_CECS_Pos (1U) 7499 #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ 7500 #define RNG_SR_CECS RNG_SR_CECS_Msk 7501 #define RNG_SR_SECS_Pos (2U) 7502 #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ 7503 #define RNG_SR_SECS RNG_SR_SECS_Msk 7504 #define RNG_SR_CEIS_Pos (5U) 7505 #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ 7506 #define RNG_SR_CEIS RNG_SR_CEIS_Msk 7507 #define RNG_SR_SEIS_Pos (6U) 7508 #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ 7509 #define RNG_SR_SEIS RNG_SR_SEIS_Msk 7510 7511 /******************************************************************************/ 7512 /* */ 7513 /* Real-Time Clock (RTC) */ 7514 /* */ 7515 /******************************************************************************/ 7516 /* 7517 * @brief Specific device feature definitions 7518 */ 7519 #define RTC_TAMPER2_SUPPORT 7520 #define RTC_WAKEUP_SUPPORT 7521 #define RTC_BACKUP_SUPPORT 7522 #define RTC_CPU2_SUPPORT_D 7523 #define RTC_INTERNALTS_SUPPORT 7524 7525 /******************** Bits definition for RTC_TR register *******************/ 7526 #define RTC_TR_PM_Pos (22U) 7527 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ 7528 #define RTC_TR_PM RTC_TR_PM_Msk /*!< AM/PM notation */ 7529 #define RTC_TR_HT_Pos (20U) 7530 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ 7531 #define RTC_TR_HT RTC_TR_HT_Msk /*!< Hour tens in BCD format */ 7532 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */ 7533 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */ 7534 #define RTC_TR_HU_Pos (16U) 7535 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ 7536 #define RTC_TR_HU RTC_TR_HU_Msk /*!< Hour units in BCD format */ 7537 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */ 7538 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */ 7539 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */ 7540 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */ 7541 #define RTC_TR_MNT_Pos (12U) 7542 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ 7543 #define RTC_TR_MNT RTC_TR_MNT_Msk /*!< Minute tens in BCD format */ 7544 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */ 7545 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */ 7546 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */ 7547 #define RTC_TR_MNU_Pos (8U) 7548 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ 7549 #define RTC_TR_MNU RTC_TR_MNU_Msk /*!< Minute unit in BCD format */ 7550 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */ 7551 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */ 7552 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */ 7553 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */ 7554 #define RTC_TR_ST_Pos (4U) 7555 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ 7556 #define RTC_TR_ST RTC_TR_ST_Msk /*!< Second tens in BCD format */ 7557 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */ 7558 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */ 7559 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */ 7560 #define RTC_TR_SU_Pos (0U) 7561 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ 7562 #define RTC_TR_SU RTC_TR_SU_Msk /*!< Second units in BCD format */ 7563 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */ 7564 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */ 7565 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */ 7566 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */ 7567 7568 /******************** Bits definition for RTC_DR register *******************/ 7569 #define RTC_DR_YT_Pos (20U) 7570 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ 7571 #define RTC_DR_YT RTC_DR_YT_Msk /*!< Year tens in BCD format */ 7572 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */ 7573 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */ 7574 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */ 7575 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */ 7576 #define RTC_DR_YU_Pos (16U) 7577 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ 7578 #define RTC_DR_YU RTC_DR_YU_Msk /*!< Years units in BCD format */ 7579 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */ 7580 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */ 7581 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */ 7582 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */ 7583 #define RTC_DR_WDU_Pos (13U) 7584 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ 7585 #define RTC_DR_WDU RTC_DR_WDU_Msk /*!< Week day units */ 7586 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */ 7587 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */ 7588 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */ 7589 #define RTC_DR_MT_Pos (12U) 7590 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ 7591 #define RTC_DR_MT RTC_DR_MT_Msk /*!< Month tens in BCD format */ 7592 #define RTC_DR_MU_Pos (8U) 7593 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ 7594 #define RTC_DR_MU RTC_DR_MU_Msk /*!< Month units in BCD format */ 7595 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */ 7596 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */ 7597 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */ 7598 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */ 7599 #define RTC_DR_DT_Pos (4U) 7600 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ 7601 #define RTC_DR_DT RTC_DR_DT_Msk /*!< Date tens in BCD format */ 7602 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */ 7603 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */ 7604 #define RTC_DR_DU_Pos (0U) 7605 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ 7606 #define RTC_DR_DU RTC_DR_DU_Msk /*!< Date units in BCD format */ 7607 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */ 7608 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */ 7609 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */ 7610 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */ 7611 7612 /******************** Bits definition for RTC_CR register *******************/ 7613 #define RTC_CR_ITSE_Pos (24U) 7614 #define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ 7615 #define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!< Timestamp on internal event enable */ 7616 #define RTC_CR_COE_Pos (23U) 7617 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ 7618 #define RTC_CR_COE RTC_CR_COE_Msk /*!< Calibration output enable */ 7619 #define RTC_CR_OSEL_Pos (21U) 7620 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ 7621 #define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< Output selection */ 7622 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ 7623 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ 7624 #define RTC_CR_POL_Pos (20U) 7625 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ 7626 #define RTC_CR_POL RTC_CR_POL_Msk /*!< Ouput polarity */ 7627 #define RTC_CR_COSEL_Pos (19U) 7628 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ 7629 #define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration ouput selection */ 7630 #define RTC_CR_BKP_Pos (18U) 7631 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ 7632 #define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */ 7633 #define RTC_CR_SUB1H_Pos (17U) 7634 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ 7635 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< Subtract 1 hour (winter time change) */ 7636 #define RTC_CR_ADD1H_Pos (16U) 7637 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ 7638 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< Add 1 hour (summer time change) */ 7639 #define RTC_CR_TSIE_Pos (15U) 7640 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ 7641 #define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Time-stamp interrupt enable */ 7642 #define RTC_CR_WUTIE_Pos (14U) 7643 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ 7644 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wakeup timer interrupt enable */ 7645 #define RTC_CR_ALRBIE_Pos (13U) 7646 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ 7647 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< Alarm B interrupt enable */ 7648 #define RTC_CR_ALRAIE_Pos (12U) 7649 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ 7650 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< Alarm A interrupt enable */ 7651 #define RTC_CR_TSE_Pos (11U) 7652 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ 7653 #define RTC_CR_TSE RTC_CR_TSE_Msk /*!< Timestamp on RTC TS input edge enable */ 7654 #define RTC_CR_WUTE_Pos (10U) 7655 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ 7656 #define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wakeup timer enable */ 7657 #define RTC_CR_ALRBE_Pos (9U) 7658 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ 7659 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< Alarm B enable */ 7660 #define RTC_CR_ALRAE_Pos (8U) 7661 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ 7662 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< Alarm A enable */ 7663 #define RTC_CR_FMT_Pos (6U) 7664 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ 7665 #define RTC_CR_FMT RTC_CR_FMT_Msk /*!< Hour AM/PM or 24H format */ 7666 #define RTC_CR_BYPSHAD_Pos (5U) 7667 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ 7668 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< Bypass the shadow registers */ 7669 #define RTC_CR_REFCKON_Pos (4U) 7670 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ 7671 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< RTC_REFIN reference clock detection enable (50 or 60 Hz) */ 7672 #define RTC_CR_TSEDGE_Pos (3U) 7673 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ 7674 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge */ 7675 #define RTC_CR_WUCKSEL_Pos (0U) 7676 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ 7677 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< Wakekup clock selection */ 7678 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ 7679 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ 7680 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ 7681 7682 /******************** Bits definition for RTC_ISR register ******************/ 7683 #define RTC_ISR_ITSF_Pos (17U) 7684 #define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */ 7685 #define RTC_ISR_ITSF RTC_ISR_ITSF_Msk /*!< Internal timestamp flag */ 7686 #define RTC_ISR_RECALPF_Pos (16U) 7687 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ 7688 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< Recalibration pending flag */ 7689 #define RTC_ISR_TAMP2F_Pos (14U) 7690 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ 7691 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< RTC_TAMP2 detection flag */ 7692 #define RTC_ISR_TSOVF_Pos (12U) 7693 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ 7694 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< Timestamp overflow flag */ 7695 #define RTC_ISR_TSF_Pos (11U) 7696 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ 7697 #define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< Timestamp flag */ 7698 #define RTC_ISR_WUTF_Pos (10U) 7699 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ 7700 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< Wakeup timer flag */ 7701 #define RTC_ISR_ALRBF_Pos (9U) 7702 #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ 7703 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< Alarm B flag */ 7704 #define RTC_ISR_ALRAF_Pos (8U) 7705 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ 7706 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< Alarm A flag */ 7707 #define RTC_ISR_INIT_Pos (7U) 7708 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ 7709 #define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< Initialization mode */ 7710 #define RTC_ISR_INITF_Pos (6U) 7711 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ 7712 #define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< Initialization flag */ 7713 #define RTC_ISR_RSF_Pos (5U) 7714 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ 7715 #define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< Registers synchronization flag */ 7716 #define RTC_ISR_INITS_Pos (4U) 7717 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ 7718 #define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< Initialization status flag */ 7719 #define RTC_ISR_SHPF_Pos (3U) 7720 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ 7721 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< Shift operation pending */ 7722 #define RTC_ISR_WUTWF_Pos (2U) 7723 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ 7724 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< Wakeup timer write flag */ 7725 #define RTC_ISR_ALRBWF_Pos (1U) 7726 #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ 7727 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< Alarm B write flag */ 7728 #define RTC_ISR_ALRAWF_Pos (0U) 7729 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ 7730 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< Alarm A write flag */ 7731 7732 /******************** Bits definition for RTC_PRER register *****************/ 7733 #define RTC_PRER_PREDIV_A_Pos (16U) 7734 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ 7735 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< Asynchronous prescaler factor */ 7736 #define RTC_PRER_PREDIV_S_Pos (0U) 7737 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ 7738 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< Synchronous prescaler factor */ 7739 7740 /******************** Bits definition for RTC_WUTR register *****************/ 7741 #define RTC_WUTR_WUT_Pos (0U) 7742 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ 7743 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wakeup auto-reload value bits */ 7744 7745 /******************** Bits definition for RTC_ALRMAR register ***************/ 7746 #define RTC_ALRMAR_MSK4_Pos (31U) 7747 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ 7748 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< Alarm A date mask */ 7749 #define RTC_ALRMAR_WDSEL_Pos (30U) 7750 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ 7751 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< Alarm A week day selection */ 7752 #define RTC_ALRMAR_DT_Pos (28U) 7753 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ 7754 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< Alarm A date tens in BCD format */ 7755 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ 7756 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ 7757 #define RTC_ALRMAR_DU_Pos (24U) 7758 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ 7759 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< Alarm A date units in BCD format */ 7760 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ 7761 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ 7762 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ 7763 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ 7764 #define RTC_ALRMAR_MSK3_Pos (23U) 7765 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ 7766 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< Alarm A hours mask */ 7767 #define RTC_ALRMAR_PM_Pos (22U) 7768 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ 7769 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< Alarm A AM/PM or 24H format */ 7770 #define RTC_ALRMAR_HT_Pos (20U) 7771 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ 7772 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< Alarm A hour tens in BCD format */ 7773 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ 7774 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ 7775 #define RTC_ALRMAR_HU_Pos (16U) 7776 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ 7777 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< Alarm A hour units in BCD format */ 7778 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ 7779 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ 7780 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ 7781 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ 7782 #define RTC_ALRMAR_MSK2_Pos (15U) 7783 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ 7784 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< Alarm A minutes mask */ 7785 #define RTC_ALRMAR_MNT_Pos (12U) 7786 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ 7787 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< Alarm A minute tens in BCD format */ 7788 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ 7789 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ 7790 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ 7791 #define RTC_ALRMAR_MNU_Pos (8U) 7792 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ 7793 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< Alarm A minute units in BCD format */ 7794 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ 7795 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ 7796 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ 7797 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ 7798 #define RTC_ALRMAR_MSK1_Pos (7U) 7799 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ 7800 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< Alarm A seconds mask */ 7801 #define RTC_ALRMAR_ST_Pos (4U) 7802 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ 7803 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< Alarm A second tens in BCD format */ 7804 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ 7805 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ 7806 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ 7807 #define RTC_ALRMAR_SU_Pos (0U) 7808 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ 7809 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< Alarm A second units in BCD format */ 7810 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ 7811 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ 7812 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ 7813 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ 7814 7815 /******************** Bits definition for RTC_ALRMBR register ***************/ 7816 #define RTC_ALRMBR_MSK4_Pos (31U) 7817 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ 7818 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< Alarm B date mask */ 7819 #define RTC_ALRMBR_WDSEL_Pos (30U) 7820 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ 7821 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< Alarm B week day selection */ 7822 #define RTC_ALRMBR_DT_Pos (28U) 7823 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ 7824 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< Alarm B data tens in BCD format */ 7825 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ 7826 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ 7827 #define RTC_ALRMBR_DU_Pos (24U) 7828 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ 7829 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< Alarm B data units or day in BCD format */ 7830 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ 7831 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ 7832 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ 7833 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ 7834 #define RTC_ALRMBR_MSK3_Pos (23U) 7835 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ 7836 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< Alarm B hour mask */ 7837 #define RTC_ALRMBR_PM_Pos (22U) 7838 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ 7839 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< Alarm B AM/PM or 24H format */ 7840 #define RTC_ALRMBR_HT_Pos (20U) 7841 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ 7842 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< Alarm B hour tens in BCD format */ 7843 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ 7844 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ 7845 #define RTC_ALRMBR_HU_Pos (16U) 7846 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ 7847 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< Alarm B hour units in BCD format */ 7848 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ 7849 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ 7850 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ 7851 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ 7852 #define RTC_ALRMBR_MSK2_Pos (15U) 7853 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ 7854 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< Alarm B minutes mask */ 7855 #define RTC_ALRMBR_MNT_Pos (12U) 7856 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ 7857 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< Alarm B minute tens in BCD format */ 7858 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ 7859 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ 7860 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ 7861 #define RTC_ALRMBR_MNU_Pos (8U) 7862 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ 7863 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< Alarm B minute units in BCD format */ 7864 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ 7865 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ 7866 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ 7867 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ 7868 #define RTC_ALRMBR_MSK1_Pos (7U) 7869 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ 7870 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< Alarm B seconds mask */ 7871 #define RTC_ALRMBR_ST_Pos (4U) 7872 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ 7873 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< Alarm B second tens in BCD format */ 7874 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ 7875 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ 7876 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ 7877 #define RTC_ALRMBR_SU_Pos (0U) 7878 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ 7879 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< Alarm B second units in BCD format */ 7880 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ 7881 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ 7882 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ 7883 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ 7884 7885 /******************** Bits definition for RTC_WPR register ******************/ 7886 #define RTC_WPR_KEY_Pos (0U) 7887 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ 7888 #define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< Write protection key */ 7889 7890 /******************** Bits definition for RTC_SSR register ******************/ 7891 #define RTC_SSR_SS_Pos (0U) 7892 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ 7893 #define RTC_SSR_SS RTC_SSR_SS_Msk /*!< Sub second value */ 7894 7895 /******************** Bits definition for RTC_SHIFTR register ***************/ 7896 #define RTC_SHIFTR_SUBFS_Pos (0U) 7897 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ 7898 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Substract a fraction of a second */ 7899 #define RTC_SHIFTR_ADD1S_Pos (31U) 7900 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ 7901 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< Add on second */ 7902 7903 /******************** Bits definition for RTC_TSTR register *****************/ 7904 #define RTC_TSTR_PM_Pos (22U) 7905 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ 7906 #define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< Timestamp AM/PM or 24H format */ 7907 #define RTC_TSTR_HT_Pos (20U) 7908 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ 7909 #define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< Timestamp hour tens in BCD format */ 7910 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ 7911 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ 7912 #define RTC_TSTR_HU_Pos (16U) 7913 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ 7914 #define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< Timestamp hour units in BCD format */ 7915 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ 7916 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ 7917 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ 7918 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ 7919 #define RTC_TSTR_MNT_Pos (12U) 7920 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ 7921 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< Timestamp minute tens in BCD format */ 7922 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ 7923 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ 7924 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ 7925 #define RTC_TSTR_MNU_Pos (8U) 7926 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ 7927 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< Timestamp minute units in BCD format */ 7928 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ 7929 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ 7930 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ 7931 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ 7932 #define RTC_TSTR_ST_Pos (4U) 7933 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ 7934 #define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< Timestamp second tens in BCD format */ 7935 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ 7936 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ 7937 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ 7938 #define RTC_TSTR_SU_Pos (0U) 7939 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ 7940 #define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< Timestamp second units in BCD format */ 7941 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ 7942 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ 7943 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ 7944 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ 7945 7946 /******************** Bits definition for RTC_TSDR register *****************/ 7947 #define RTC_TSDR_WDU_Pos (13U) 7948 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ 7949 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Timestamp week day units */ 7950 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ 7951 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ 7952 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ 7953 #define RTC_TSDR_MT_Pos (12U) 7954 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ 7955 #define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< Timestamp month tens in BCD format */ 7956 #define RTC_TSDR_MU_Pos (8U) 7957 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ 7958 #define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< Timestamp month units in BCD format */ 7959 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ 7960 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ 7961 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ 7962 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ 7963 #define RTC_TSDR_DT_Pos (4U) 7964 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ 7965 #define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< Timestamp date tens in BCD format */ 7966 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ 7967 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ 7968 #define RTC_TSDR_DU_Pos (0U) 7969 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ 7970 #define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< Timestamp date units in BCD format */ 7971 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ 7972 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ 7973 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ 7974 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ 7975 7976 /******************** Bits definition for RTC_TSSSR register ****************/ 7977 #define RTC_TSSSR_SS_Pos (0U) 7978 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ 7979 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Timestamp sub second value */ 7980 7981 /******************** Bits definition for RTC_CALR register *****************/ 7982 #define RTC_CALR_CALP_Pos (15U) 7983 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ 7984 #define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< Increase frequency of RTC 488.5 ppm */ 7985 #define RTC_CALR_CALW8_Pos (14U) 7986 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ 7987 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< Use a 8-second calibration cycle period */ 7988 #define RTC_CALR_CALW16_Pos (13U) 7989 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ 7990 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< Use a 16-second calibration cycle period */ 7991 #define RTC_CALR_CALM_Pos (0U) 7992 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ 7993 #define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< Calibration minus */ 7994 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ 7995 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ 7996 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ 7997 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ 7998 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ 7999 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ 8000 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ 8001 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ 8002 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ 8003 8004 /******************** Bits definition for RTC_TAMPCR register ****************/ 8005 #define RTC_TAMPCR_TAMP2MF_Pos (21U) 8006 #define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */ 8007 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< Tamper 2 generates a trigger event */ 8008 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U) 8009 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */ 8010 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< Tamper 2 no erase backup registers */ 8011 #define RTC_TAMPCR_TAMP2IE_Pos (19U) 8012 #define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */ 8013 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< Tamper 2 interrupt enable */ 8014 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U) 8015 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ 8016 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< RTC_TAMPx pull-up disable */ 8017 #define RTC_TAMPCR_TAMPPRCH_Pos (13U) 8018 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ 8019 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< RTC_TAMPx precharge duration */ 8020 #define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ 8021 #define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ 8022 #define RTC_TAMPCR_TAMPFLT_Pos (11U) 8023 #define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ 8024 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< RTC_TAMPx filter count */ 8025 #define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ 8026 #define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ 8027 #define RTC_TAMPCR_TAMPFREQ_Pos (8U) 8028 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ 8029 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< Tamper sampling frequency */ 8030 #define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ 8031 #define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ 8032 #define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ 8033 #define RTC_TAMPCR_TAMPTS_Pos (7U) 8034 #define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ 8035 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< Activate timestamp on tamper detection event */ 8036 #define RTC_TAMPCR_TAMP2TRG_Pos (4U) 8037 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ 8038 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< Active level for RTC_TAMP2 input */ 8039 #define RTC_TAMPCR_TAMP2E_Pos (3U) 8040 #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ 8041 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< RTC_TAMP2 detection enable */ 8042 #define RTC_TAMPCR_TAMPIE_Pos (2U) 8043 #define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ 8044 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< Tampers interrupt enable */ 8045 8046 /******************** Bits definition for RTC_ALRMASSR register *************/ 8047 #define RTC_ALRMASSR_MASKSS_Pos (24U) 8048 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ 8049 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk /*!< Alarm A mask the most-significant bits starting at this bit */ 8050 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ 8051 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ 8052 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ 8053 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ 8054 #define RTC_ALRMASSR_SS_Pos (0U) /*!< Alarm A sub seconds value*/ 8055 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ 8056 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk 8057 8058 /******************** Bits definition for RTC_ALRMBSSR register *************/ 8059 #define RTC_ALRMBSSR_MASKSS_Pos (24U) 8060 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ 8061 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk /*!< Alarm B mask the most-significant bits starting at this bit */ 8062 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ 8063 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ 8064 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ 8065 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ 8066 #define RTC_ALRMBSSR_SS_Pos (0U) /*!< Alarm B sub seconds value*/ 8067 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ 8068 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk 8069 8070 /******************** Bits definition for RTC_OR register ****************/ 8071 #define RTC_OR_OUT_RMP_Pos (1U) 8072 #define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */ 8073 #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< RTC_OUT remap */ 8074 #define RTC_OR_ALARMOUTTYPE_Pos (0U) 8075 #define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */ 8076 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< RTC_ALARM on PC13 output type */ 8077 8078 /******************** Bits definition for RTC_BKP0R register ****************/ 8079 #define RTC_BKP0R_Pos (0U) 8080 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ 8081 #define RTC_BKP0R RTC_BKP0R_Msk /*!< RTC backup register 0 */ 8082 8083 /******************** Bits definition for RTC_BKP1R register ****************/ 8084 #define RTC_BKP1R_Pos (0U) 8085 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ 8086 #define RTC_BKP1R RTC_BKP1R_Msk /*!< RTC backup register 1 */ 8087 8088 /******************** Bits definition for RTC_BKP2R register ****************/ 8089 #define RTC_BKP2R_Pos (0U) 8090 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ 8091 #define RTC_BKP2R RTC_BKP2R_Msk /*!< RTC backup register 2 */ 8092 8093 /******************** Bits definition for RTC_BKP3R register ****************/ 8094 #define RTC_BKP3R_Pos (0U) 8095 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ 8096 #define RTC_BKP3R RTC_BKP3R_Msk /*!< RTC backup register 3 */ 8097 8098 /******************** Bits definition for RTC_BKP4R register ****************/ 8099 #define RTC_BKP4R_Pos (0U) 8100 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ 8101 #define RTC_BKP4R RTC_BKP4R_Msk /*!< RTC backup register 4 */ 8102 8103 /******************** Bits definition for RTC_BKP5R register ****************/ 8104 #define RTC_BKP5R_Pos (0U) 8105 #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */ 8106 #define RTC_BKP5R RTC_BKP5R_Msk /*!< RTC backup register 5 */ 8107 8108 /******************** Bits definition for RTC_BKP6R register ****************/ 8109 #define RTC_BKP6R_Pos (0U) 8110 #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */ 8111 #define RTC_BKP6R RTC_BKP6R_Msk /*!< RTC backup register 6 */ 8112 8113 /******************** Bits definition for RTC_BKP7R register ****************/ 8114 #define RTC_BKP7R_Pos (0U) 8115 #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */ 8116 #define RTC_BKP7R RTC_BKP7R_Msk /*!< RTC backup register 7 */ 8117 8118 /******************** Bits definition for RTC_BKP8R register ****************/ 8119 #define RTC_BKP8R_Pos (0U) 8120 #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */ 8121 #define RTC_BKP8R RTC_BKP8R_Msk /*!< RTC backup register 8 */ 8122 8123 /******************** Bits definition for RTC_BKP9R register ****************/ 8124 #define RTC_BKP9R_Pos (0U) 8125 #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */ 8126 #define RTC_BKP9R RTC_BKP9R_Msk /*!< RTC backup register 9 */ 8127 8128 /******************** Bits definition for RTC_BKP10R register ***************/ 8129 #define RTC_BKP10R_Pos (0U) 8130 #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */ 8131 #define RTC_BKP10R RTC_BKP10R_Msk /*!< RTC backup register 10 */ 8132 8133 /******************** Bits definition for RTC_BKP11R register ***************/ 8134 #define RTC_BKP11R_Pos (0U) 8135 #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */ 8136 #define RTC_BKP11R RTC_BKP11R_Msk /*!< RTC backup register 11 */ 8137 8138 /******************** Bits definition for RTC_BKP12R register ***************/ 8139 #define RTC_BKP12R_Pos (0U) 8140 #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */ 8141 #define RTC_BKP12R RTC_BKP12R_Msk /*!< RTC backup register 12 */ 8142 8143 /******************** Bits definition for RTC_BKP13R register ***************/ 8144 #define RTC_BKP13R_Pos (0U) 8145 #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */ 8146 #define RTC_BKP13R RTC_BKP13R_Msk /*!< RTC backup register 13 */ 8147 8148 /******************** Bits definition for RTC_BKP14R register ***************/ 8149 #define RTC_BKP14R_Pos (0U) 8150 #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */ 8151 #define RTC_BKP14R RTC_BKP14R_Msk /*!< RTC backup register 14 */ 8152 8153 /******************** Bits definition for RTC_BKP15R register ***************/ 8154 #define RTC_BKP15R_Pos (0U) 8155 #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */ 8156 #define RTC_BKP15R RTC_BKP15R_Msk /*!< RTC backup register 15 */ 8157 8158 /******************** Bits definition for RTC_BKP16R register ***************/ 8159 #define RTC_BKP16R_Pos (0U) 8160 #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */ 8161 #define RTC_BKP16R RTC_BKP16R_Msk /*!< RTC backup register 16 */ 8162 8163 /******************** Bits definition for RTC_BKP17R register ***************/ 8164 #define RTC_BKP17R_Pos (0U) 8165 #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */ 8166 #define RTC_BKP17R RTC_BKP17R_Msk /*!< RTC backup register 17 */ 8167 8168 /******************** Bits definition for RTC_BKP18R register ***************/ 8169 #define RTC_BKP18R_Pos (0U) 8170 #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */ 8171 #define RTC_BKP18R RTC_BKP18R_Msk /*!< RTC backup register 18 */ 8172 8173 /******************** Bits definition for RTC_BKP19R register ***************/ 8174 #define RTC_BKP19R_Pos (0U) 8175 #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */ 8176 #define RTC_BKP19R RTC_BKP19R_Msk /*!< RTC backup register 19 */ 8177 8178 /******************** Number of backup registers ******************************/ 8179 #define RTC_BKP_NUMBER (20U) 8180 8181 /******************************************************************************/ 8182 /* */ 8183 /* Serial Peripheral Interface (SPI) */ 8184 /* */ 8185 /******************************************************************************/ 8186 /******************* Bit definition for SPI_CR1 register ********************/ 8187 #define SPI_CR1_CPHA_Pos (0U) 8188 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 8189 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */ 8190 #define SPI_CR1_CPOL_Pos (1U) 8191 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 8192 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */ 8193 #define SPI_CR1_MSTR_Pos (2U) 8194 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 8195 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */ 8196 8197 #define SPI_CR1_BR_Pos (3U) 8198 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 8199 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */ 8200 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 8201 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 8202 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 8203 8204 #define SPI_CR1_SPE_Pos (6U) 8205 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 8206 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */ 8207 #define SPI_CR1_LSBFIRST_Pos (7U) 8208 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 8209 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */ 8210 #define SPI_CR1_SSI_Pos (8U) 8211 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 8212 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */ 8213 #define SPI_CR1_SSM_Pos (9U) 8214 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 8215 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */ 8216 #define SPI_CR1_RXONLY_Pos (10U) 8217 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 8218 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */ 8219 #define SPI_CR1_CRCL_Pos (11U) 8220 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ 8221 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */ 8222 #define SPI_CR1_CRCNEXT_Pos (12U) 8223 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 8224 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */ 8225 #define SPI_CR1_CRCEN_Pos (13U) 8226 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 8227 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */ 8228 #define SPI_CR1_BIDIOE_Pos (14U) 8229 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 8230 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */ 8231 #define SPI_CR1_BIDIMODE_Pos (15U) 8232 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 8233 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */ 8234 8235 /******************* Bit definition for SPI_CR2 register ********************/ 8236 #define SPI_CR2_RXDMAEN_Pos (0U) 8237 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 8238 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 8239 #define SPI_CR2_TXDMAEN_Pos (1U) 8240 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 8241 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 8242 #define SPI_CR2_SSOE_Pos (2U) 8243 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 8244 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 8245 #define SPI_CR2_NSSP_Pos (3U) 8246 #define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */ 8247 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */ 8248 #define SPI_CR2_FRF_Pos (4U) 8249 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ 8250 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ 8251 #define SPI_CR2_ERRIE_Pos (5U) 8252 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 8253 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 8254 #define SPI_CR2_RXNEIE_Pos (6U) 8255 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 8256 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 8257 #define SPI_CR2_TXEIE_Pos (7U) 8258 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 8259 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 8260 #define SPI_CR2_DS_Pos (8U) 8261 #define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */ 8262 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */ 8263 #define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */ 8264 #define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */ 8265 #define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */ 8266 #define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */ 8267 #define SPI_CR2_FRXTH_Pos (12U) 8268 #define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */ 8269 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */ 8270 #define SPI_CR2_LDMARX_Pos (13U) 8271 #define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */ 8272 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */ 8273 #define SPI_CR2_LDMATX_Pos (14U) 8274 #define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */ 8275 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */ 8276 8277 /******************** Bit definition for SPI_SR register ********************/ 8278 #define SPI_SR_RXNE_Pos (0U) 8279 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 8280 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 8281 #define SPI_SR_TXE_Pos (1U) 8282 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 8283 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 8284 #define SPI_SR_CRCERR_Pos (4U) 8285 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 8286 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 8287 #define SPI_SR_MODF_Pos (5U) 8288 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 8289 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 8290 #define SPI_SR_OVR_Pos (6U) 8291 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 8292 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 8293 #define SPI_SR_BSY_Pos (7U) 8294 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 8295 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 8296 #define SPI_SR_FRE_Pos (8U) 8297 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */ 8298 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ 8299 #define SPI_SR_FRLVL_Pos (9U) 8300 #define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */ 8301 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */ 8302 #define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */ 8303 #define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */ 8304 #define SPI_SR_FTLVL_Pos (11U) 8305 #define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */ 8306 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */ 8307 #define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */ 8308 #define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */ 8309 8310 /******************** Bit definition for SPI_DR register ********************/ 8311 #define SPI_DR_DR_Pos (0U) 8312 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ 8313 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */ 8314 8315 /******************* Bit definition for SPI_CRCPR register ******************/ 8316 #define SPI_CRCPR_CRCPOLY_Pos (0U) 8317 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ 8318 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */ 8319 8320 /****************** Bit definition for SPI_RXCRCR register ******************/ 8321 #define SPI_RXCRCR_RXCRC_Pos (0U) 8322 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ 8323 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */ 8324 8325 /****************** Bit definition for SPI_TXCRCR register ******************/ 8326 #define SPI_TXCRCR_TXCRC_Pos (0U) 8327 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ 8328 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */ 8329 8330 /******************************************************************************/ 8331 /* */ 8332 /* SYSCFG */ 8333 /* */ 8334 /******************************************************************************/ 8335 /***************** Bit definition for SYSCFG_MEMRMP register (SYSCFG memory remap register) ***********************************/ 8336 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U) 8337 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */ 8338 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ 8339 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */ 8340 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */ 8341 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */ 8342 8343 /***************** Bit definition for SYSCFG_CFGR1 register (SYSCFG configuration register 1) ****************************************************************/ 8344 #define SYSCFG_CFGR1_BOOSTEN_Pos (8U) 8345 #define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */ 8346 #define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */ 8347 #define SYSCFG_CFGR1_ANASWVDD_Pos (9U) 8348 #define SYSCFG_CFGR1_ANASWVDD_Msk (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos) /*!< 0x00000200 */ 8349 #define SYSCFG_CFGR1_ANASWVDD SYSCFG_CFGR1_ANASWVDD_Msk /*!< I/O analog switch voltage selection */ 8350 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U) 8351 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */ 8352 #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< Fast-mode Plus (Fm+) driving capability activation on PB6 */ 8353 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U) 8354 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */ 8355 #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< Fast-mode Plus (Fm+) driving capability activation on PB7 */ 8356 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U) 8357 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */ 8358 #define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< Fast-mode Plus (Fm+) driving capability activation on PB8 */ 8359 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U) 8360 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */ 8361 #define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< Fast-mode Plus (Fm+) driving capability activation on PB9 */ 8362 #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U) 8363 #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */ 8364 #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast-mode Plus (Fm+) driving capability activation */ 8365 #define SYSCFG_CFGR1_FPU_IE_Pos (26U) 8366 #define SYSCFG_CFGR1_FPU_IE_Msk (0x3FUL << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0xFC000000 */ 8367 #define SYSCFG_CFGR1_FPU_IE SYSCFG_CFGR1_FPU_IE_Msk /*!< Cortex M4 Floating Point Unit interrupts enable bits */ 8368 #define SYSCFG_CFGR1_FPU_IE_0 (0x01U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x04000000 */ 8369 #define SYSCFG_CFGR1_FPU_IE_1 (0x02U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x08000000 */ 8370 #define SYSCFG_CFGR1_FPU_IE_2 (0x04U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x10000000 */ 8371 #define SYSCFG_CFGR1_FPU_IE_3 (0x08U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x20000000 */ 8372 #define SYSCFG_CFGR1_FPU_IE_4 (0x10U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x40000000 */ 8373 #define SYSCFG_CFGR1_FPU_IE_5 (0x20U << SYSCFG_CFGR1_FPU_IE_Pos) /*!< 0x80000000 */ 8374 8375 /***************** Bit definition for SYSCFG_EXTICR1 register (External interrupt configuration register 1) ********************************/ 8376 #define SYSCFG_EXTICR1_EXTI0_Pos (0U) 8377 #define SYSCFG_EXTICR1_EXTI0_Msk (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */ 8378 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< External Interrupt Line 0 configuration */ 8379 #define SYSCFG_EXTICR1_EXTI1_Pos (4U) 8380 #define SYSCFG_EXTICR1_EXTI1_Msk (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x00000070 */ 8381 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< External Interrupt Line 1 configuration */ 8382 #define SYSCFG_EXTICR1_EXTI2_Pos (8U) 8383 #define SYSCFG_EXTICR1_EXTI2_Msk (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000700 */ 8384 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< External Interrupt Line 2 configuration */ 8385 #define SYSCFG_EXTICR1_EXTI3_Pos (12U) 8386 #define SYSCFG_EXTICR1_EXTI3_Msk (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x00007000 */ 8387 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< External Interrupt Line 3 configuration */ 8388 8389 /** 8390 * @brief External Interrupt Line 0 Source Input configuration 8391 */ 8392 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000UL) /*!< PA[0] pin */ 8393 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001UL) /*!< PB[0] pin */ 8394 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002UL) /*!< PC[0] pin */ 8395 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003UL) /*!< PD[0] pin */ 8396 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004UL) /*!< PE[0] pin */ 8397 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000007UL) /*!< PH[0] pin */ 8398 8399 /** 8400 * @brief External Interrupt Line 1 Source Input configuration 8401 */ 8402 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000UL) /*!< PA[1] pin */ 8403 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010UL) /*!< PB[1] pin */ 8404 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020UL) /*!< PC[1] pin */ 8405 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030UL) /*!< PD[1] pin */ 8406 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040UL) /*!< PE[1] pin */ 8407 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000070UL) /*!< PH[1] pin */ 8408 8409 /** 8410 * @brief External Interrupt Line 2 Source Input configuration 8411 */ 8412 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000UL) /*!< PA[2] pin */ 8413 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100UL) /*!< PB[2] pin */ 8414 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200UL) /*!< PC[2] pin */ 8415 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300UL) /*!< PD[2] pin */ 8416 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400UL) /*!< PE[2] pin */ 8417 8418 /** 8419 * @brief External Interrupt Line 3 Source Input configuration 8420 */ 8421 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000UL) /*!< PA[3] pin */ 8422 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000UL) /*!< PB[3] pin */ 8423 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000UL) /*!< PC[3] pin */ 8424 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000UL) /*!< PD[3] pin */ 8425 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000UL) /*!< PE[3] pin */ 8426 #define SYSCFG_EXTICR1_EXTI3_PH (0x00007000UL) /*!< PH[3] pin */ 8427 8428 /***************** Bit definition for SYSCFG_EXTICR2 register (External interrupt configuration register 2) ********************************/ 8429 #define SYSCFG_EXTICR2_EXTI4_Pos (0U) 8430 #define SYSCFG_EXTICR2_EXTI4_Msk (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */ 8431 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< External Interrupt Line 4 configuration */ 8432 #define SYSCFG_EXTICR2_EXTI5_Pos (4U) 8433 #define SYSCFG_EXTICR2_EXTI5_Msk (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x00000070 */ 8434 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< External Interrupt Line 5 configuration */ 8435 #define SYSCFG_EXTICR2_EXTI6_Pos (8U) 8436 #define SYSCFG_EXTICR2_EXTI6_Msk (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000700 */ 8437 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< External Interrupt Line 6 configuration */ 8438 #define SYSCFG_EXTICR2_EXTI7_Pos (12U) 8439 #define SYSCFG_EXTICR2_EXTI7_Msk (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x00007000 */ 8440 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< External Interrupt Line 7 configuration */ 8441 8442 /** 8443 * @brief External Interrupt Line 4 Source Input configuration 8444 */ 8445 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000UL) /*!< PA[4] pin */ 8446 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001UL) /*!< PB[4] pin */ 8447 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002UL) /*!< PC[4] pin */ 8448 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003UL) /*!< PD[4] pin */ 8449 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004UL) /*!< PE[4] pin */ 8450 8451 /** 8452 * @brief External Interrupt Line 5 Source Input configuration 8453 */ 8454 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000UL) /*!< PA[5] pin */ 8455 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010UL) /*!< PB[5] pin */ 8456 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020UL) /*!< PC[5] pin */ 8457 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030UL) /*!< PD[5] pin */ 8458 8459 /** 8460 * @brief External Interrupt Line 6 Source Input configuration 8461 */ 8462 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000UL) /*!< PA[6] pin */ 8463 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100UL) /*!< PB[6] pin */ 8464 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200UL) /*!< PC[6] pin */ 8465 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300UL) /*!< PD[6] pin */ 8466 8467 /** 8468 * @brief External Interrupt Line 7 Source Input configuration 8469 */ 8470 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000UL) /*!< PA[7] pin */ 8471 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000UL) /*!< PB[7] pin */ 8472 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000UL) /*!< PC[7] pin */ 8473 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000UL) /*!< PD[7] pin */ 8474 8475 /***************** Bit definition for SYSCFG_EXTICR3 register (External interrupt configuration register 3) ********************************/ 8476 #define SYSCFG_EXTICR3_EXTI8_Pos (0U) 8477 #define SYSCFG_EXTICR3_EXTI8_Msk (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */ 8478 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< External Interrupt Line 8 configuration */ 8479 #define SYSCFG_EXTICR3_EXTI9_Pos (4U) 8480 #define SYSCFG_EXTICR3_EXTI9_Msk (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x00000070 */ 8481 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< External Interrupt Line 9 configuration */ 8482 #define SYSCFG_EXTICR3_EXTI10_Pos (8U) 8483 #define SYSCFG_EXTICR3_EXTI10_Msk (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000700 */ 8484 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< External Interrupt Line 10 configuration */ 8485 #define SYSCFG_EXTICR3_EXTI11_Pos (12U) 8486 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ 8487 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< External Interrupt Line 11 configuration */ 8488 8489 /** 8490 * @brief External Interrupt Line 8 Source Input configuration 8491 */ 8492 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000UL) /*!< PA[8] pin */ 8493 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001UL) /*!< PB[8] pin */ 8494 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002UL) /*!< PC[8] pin */ 8495 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003UL) /*!< PD[8] pin */ 8496 8497 /** 8498 * @brief External Interrupt Line 9 Source Input configuration 8499 */ 8500 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000UL) /*!< PA[9] pin */ 8501 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010UL) /*!< PB[9] pin */ 8502 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020UL) /*!< PC[9] pin */ 8503 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030UL) /*!< PD[9] pin */ 8504 8505 /** 8506 * @brief External Interrupt Line 10 Source Input configuration 8507 */ 8508 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000UL) /*!< PA[10] pin */ 8509 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100UL) /*!< PB[10] pin */ 8510 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200UL) /*!< PC[10] pin */ 8511 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300UL) /*!< PD[10] pin */ 8512 8513 /** 8514 * @brief External Interrupt Line 11 Source Input configuration 8515 */ 8516 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000UL) /*!< PA[11] pin */ 8517 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000UL) /*!< PB[11] pin */ 8518 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000UL) /*!< PC[11] pin */ 8519 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000UL) /*!< PD[11] pin */ 8520 8521 /***************** Bit definition for SYSCFG_EXTICR4 register (External interrupt configuration register 4) *********************************/ 8522 #define SYSCFG_EXTICR4_EXTI12_Pos (0U) 8523 #define SYSCFG_EXTICR4_EXTI12_Msk (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */ 8524 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< External Interrupt Line 12 configuration */ 8525 #define SYSCFG_EXTICR4_EXTI13_Pos (4U) 8526 #define SYSCFG_EXTICR4_EXTI13_Msk (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */ 8527 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< External Interrupt Line 13 configuration */ 8528 #define SYSCFG_EXTICR4_EXTI14_Pos (8U) 8529 #define SYSCFG_EXTICR4_EXTI14_Msk (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */ 8530 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< External Interrupt Line 14 configuration */ 8531 #define SYSCFG_EXTICR4_EXTI15_Pos (12U) 8532 #define SYSCFG_EXTICR4_EXTI15_Msk (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */ 8533 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< External Interrupt Line 15 configuration */ 8534 8535 /** 8536 * @brief External Interrupt Line 12 Source Input configuration 8537 */ 8538 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000UL) /*!< PA[12] pin */ 8539 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001UL) /*!< PB[12] pin */ 8540 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002UL) /*!< PC[12] pin */ 8541 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003UL) /*!< PD[12] pin */ 8542 8543 /** 8544 * @brief External Interrupt Line 13 Source Input configuration 8545 */ 8546 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000UL) /*!< PA[13] pin */ 8547 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010UL) /*!< PB[13] pin */ 8548 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020UL) /*!< PC[13] pin */ 8549 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030UL) /*!< PD[13] pin */ 8550 8551 /** 8552 * @brief External Interrupt Line 14 Source Input configuration 8553 */ 8554 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000UL) /*!< PA[14] pin */ 8555 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100UL) /*!< PB[14] pin */ 8556 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200UL) /*!< PC[14] pin */ 8557 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300UL) /*!< PD[14] pin */ 8558 8559 /** 8560 * @brief External Interrupt Line 15 Source Input configuration 8561 */ 8562 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000UL) /*!< PA[15] pin */ 8563 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000UL) /*!< PB[15] pin */ 8564 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000UL) /*!< PC[15] pin */ 8565 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000UL) /*!< PD[15] pin */ 8566 8567 /***************** Bit definition for SYSCFG_SCSR register (SYSCFG SRAM2 control and status register) *********************************************************/ 8568 #define SYSCFG_SCSR_SRAM2ER_Pos (0U) 8569 #define SYSCFG_SCSR_SRAM2ER_Msk (0x1UL << SYSCFG_SCSR_SRAM2ER_Pos) /*!< 0x00000001 */ 8570 #define SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk /*!< SRAM2 and PKA RAM Erase */ 8571 #define SYSCFG_SCSR_SRAM2BSY_Pos (1U) 8572 #define SYSCFG_SCSR_SRAM2BSY_Msk (0x1UL << SYSCFG_SCSR_SRAM2BSY_Pos) /*!< 0x00000002 */ 8573 #define SYSCFG_SCSR_SRAM2BSY SYSCFG_SCSR_SRAM2BSY_Msk /*!< SRAM2 and PKA RAM busy by erase operation */ 8574 #define SYSCFG_SCSR_C2RFD_Pos (31U) 8575 #define SYSCFG_SCSR_C2RFD_Msk (0x1UL << SYSCFG_SCSR_C2RFD_Pos) /*!< 0x80000000 */ 8576 #define SYSCFG_SCSR_C2RFD SYSCFG_SCSR_C2RFD_Msk /*!< CPU2 SRAM fetch (execution) disable */ 8577 8578 /***************** Bit definition for SYSCFG_CFGR2 register (SYSCFG configuration register 2) *****************************************************************/ 8579 #define SYSCFG_CFGR2_CLL_Pos (0U) 8580 #define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */ 8581 #define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Cortex M4 LOCKUP (hardfault) output enable */ 8582 #define SYSCFG_CFGR2_SPL_Pos (1U) 8583 #define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */ 8584 #define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM2 Parity Lock */ 8585 #define SYSCFG_CFGR2_PVDL_Pos (2U) 8586 #define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */ 8587 #define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */ 8588 #define SYSCFG_CFGR2_ECCL_Pos (3U) 8589 #define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */ 8590 #define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock */ 8591 #define SYSCFG_CFGR2_SPF_Pos (8U) 8592 #define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */ 8593 #define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM2 Parity Lock */ 8594 8595 /***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/ 8596 #define SYSCFG_SWPR1_PAGE0_Pos (0U) 8597 #define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */ 8598 #define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 � 0x200303FF) */ 8599 #define SYSCFG_SWPR1_PAGE1_Pos (1U) 8600 #define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */ 8601 #define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 � 0x200307FF) */ 8602 #define SYSCFG_SWPR1_PAGE2_Pos (2U) 8603 #define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */ 8604 #define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 � 0x20030BFF) */ 8605 #define SYSCFG_SWPR1_PAGE3_Pos (3U) 8606 #define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */ 8607 #define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 � 0x20030FFF) */ 8608 #define SYSCFG_SWPR1_PAGE4_Pos (4U) 8609 #define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */ 8610 #define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 � 0x200313FF) */ 8611 #define SYSCFG_SWPR1_PAGE5_Pos (5U) 8612 #define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */ 8613 #define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 � 0x200317FF) */ 8614 #define SYSCFG_SWPR1_PAGE6_Pos (6U) 8615 #define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */ 8616 #define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 � 0x20031BFF) */ 8617 #define SYSCFG_SWPR1_PAGE7_Pos (7U) 8618 #define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */ 8619 #define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 � 0x20031FFF) */ 8620 #define SYSCFG_SWPR1_PAGE8_Pos (8U) 8621 #define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */ 8622 #define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 � 0x200323FF) */ 8623 #define SYSCFG_SWPR1_PAGE9_Pos (9U) 8624 #define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */ 8625 #define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 � 0x200327FF) */ 8626 #define SYSCFG_SWPR1_PAGE10_Pos (10U) 8627 #define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */ 8628 #define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 � 0x20032BFF) */ 8629 #define SYSCFG_SWPR1_PAGE11_Pos (11U) 8630 #define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */ 8631 #define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 � 0x20032FFF) */ 8632 #define SYSCFG_SWPR1_PAGE12_Pos (12U) 8633 #define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */ 8634 #define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 � 0x200333FF) */ 8635 #define SYSCFG_SWPR1_PAGE13_Pos (13U) 8636 #define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */ 8637 #define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 � 0x200337FF) */ 8638 #define SYSCFG_SWPR1_PAGE14_Pos (14U) 8639 #define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */ 8640 #define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 � 0x20033BFF) */ 8641 #define SYSCFG_SWPR1_PAGE15_Pos (15U) 8642 #define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */ 8643 #define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 � 0x20033FFF) */ 8644 #define SYSCFG_SWPR1_PAGE16_Pos (16U) 8645 #define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */ 8646 #define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 � 0x200343FF) */ 8647 #define SYSCFG_SWPR1_PAGE17_Pos (17U) 8648 #define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */ 8649 #define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 � 0x200347FF) */ 8650 #define SYSCFG_SWPR1_PAGE18_Pos (18U) 8651 #define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */ 8652 #define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 � 0x20034BFF) */ 8653 #define SYSCFG_SWPR1_PAGE19_Pos (19U) 8654 #define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */ 8655 #define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 � 0x20034FFF) */ 8656 #define SYSCFG_SWPR1_PAGE20_Pos (20U) 8657 #define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */ 8658 #define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 � 0x200353FF) */ 8659 #define SYSCFG_SWPR1_PAGE21_Pos (21U) 8660 #define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */ 8661 #define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 � 0x200357FF) */ 8662 #define SYSCFG_SWPR1_PAGE22_Pos (22U) 8663 #define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */ 8664 #define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 � 0x20035BFF) */ 8665 #define SYSCFG_SWPR1_PAGE23_Pos (23U) 8666 #define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */ 8667 #define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 � 0x20035FFF) */ 8668 #define SYSCFG_SWPR1_PAGE24_Pos (24U) 8669 #define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */ 8670 #define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 � 0x200363FF) */ 8671 #define SYSCFG_SWPR1_PAGE25_Pos (25U) 8672 #define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */ 8673 #define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 � 0x200367FF) */ 8674 #define SYSCFG_SWPR1_PAGE26_Pos (26U) 8675 #define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */ 8676 #define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 � 0x20036BFF) */ 8677 #define SYSCFG_SWPR1_PAGE27_Pos (27U) 8678 #define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */ 8679 #define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 � 0x20036FFF) */ 8680 #define SYSCFG_SWPR1_PAGE28_Pos (28U) 8681 #define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */ 8682 #define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 � 0x200373FF) */ 8683 #define SYSCFG_SWPR1_PAGE29_Pos (29U) 8684 #define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */ 8685 #define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 � 0x200377FF) */ 8686 #define SYSCFG_SWPR1_PAGE30_Pos (30U) 8687 #define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */ 8688 #define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 � 0x20037BFF) */ 8689 #define SYSCFG_SWPR1_PAGE31_Pos (31U) 8690 #define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */ 8691 #define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 � 0x20037FFF) */ 8692 8693 /***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/ 8694 #define SYSCFG_SKR_KEY_Pos (0U) 8695 #define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */ 8696 #define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< SRAM2 write protection key for software erase */ 8697 8698 /***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/ 8699 #define SYSCFG_SWPR2_PAGE32_Pos (0U) 8700 #define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */ 8701 #define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 � 0x200383FF) */ 8702 #define SYSCFG_SWPR2_PAGE33_Pos (1U) 8703 #define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */ 8704 #define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 � 0x200387FF) */ 8705 #define SYSCFG_SWPR2_PAGE34_Pos (2U) 8706 #define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */ 8707 #define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 � 0x20038bFF) */ 8708 #define SYSCFG_SWPR2_PAGE35_Pos (3U) 8709 #define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */ 8710 #define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 � 0x20038FFF) */ 8711 #define SYSCFG_SWPR2_PAGE36_Pos (4U) 8712 #define SYSCFG_SWPR2_PAGE36_Msk (0x1UL << SYSCFG_SWPR2_PAGE36_Pos) /*!< 0x00000010 */ 8713 #define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 � 0x200393FF) */ 8714 #define SYSCFG_SWPR2_PAGE37_Pos (5U) 8715 #define SYSCFG_SWPR2_PAGE37_Msk (0x1UL << SYSCFG_SWPR2_PAGE37_Pos) /*!< 0x00000020 */ 8716 #define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 � 0x200397FF) */ 8717 #define SYSCFG_SWPR2_PAGE38_Pos (6U) 8718 #define SYSCFG_SWPR2_PAGE38_Msk (0x1UL << SYSCFG_SWPR2_PAGE38_Pos) /*!< 0x00000040 */ 8719 #define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 � 0x20039BFF) */ 8720 #define SYSCFG_SWPR2_PAGE39_Pos (7U) 8721 #define SYSCFG_SWPR2_PAGE39_Msk (0x1UL << SYSCFG_SWPR2_PAGE39_Pos) /*!< 0x00000080 */ 8722 #define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 � 0x20039FFF) */ 8723 #define SYSCFG_SWPR2_PAGE40_Pos (8U) 8724 #define SYSCFG_SWPR2_PAGE40_Msk (0x1UL << SYSCFG_SWPR2_PAGE40_Pos) /*!< 0x00000100 */ 8725 #define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 � 0x2003A3FF) */ 8726 #define SYSCFG_SWPR2_PAGE41_Pos (9U) 8727 #define SYSCFG_SWPR2_PAGE41_Msk (0x1UL << SYSCFG_SWPR2_PAGE41_Pos) /*!< 0x00000200 */ 8728 #define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 � 0x2003A7FF) */ 8729 #define SYSCFG_SWPR2_PAGE42_Pos (10U) 8730 #define SYSCFG_SWPR2_PAGE42_Msk (0x1UL << SYSCFG_SWPR2_PAGE42_Pos) /*!< 0x00000400 */ 8731 #define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 � 0x2003ABFF) */ 8732 #define SYSCFG_SWPR2_PAGE43_Pos (11U) 8733 #define SYSCFG_SWPR2_PAGE43_Msk (0x1UL << SYSCFG_SWPR2_PAGE43_Pos) /*!< 0x00000800 */ 8734 #define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 � 0x2003AFFF) */ 8735 #define SYSCFG_SWPR2_PAGE44_Pos (12U) 8736 #define SYSCFG_SWPR2_PAGE44_Msk (0x1UL << SYSCFG_SWPR2_PAGE44_Pos) /*!< 0x00001000 */ 8737 #define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 � 0x2003B3FF) */ 8738 #define SYSCFG_SWPR2_PAGE45_Pos (13U) 8739 #define SYSCFG_SWPR2_PAGE45_Msk (0x1UL << SYSCFG_SWPR2_PAGE45_Pos) /*!< 0x00002000 */ 8740 #define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 � 0x2003B7FF) */ 8741 #define SYSCFG_SWPR2_PAGE46_Pos (14U) 8742 #define SYSCFG_SWPR2_PAGE46_Msk (0x1UL << SYSCFG_SWPR2_PAGE46_Pos) /*!< 0x00004000 */ 8743 #define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 � 0x2003BBFF) */ 8744 #define SYSCFG_SWPR2_PAGE47_Pos (15U) 8745 #define SYSCFG_SWPR2_PAGE47_Msk (0x1UL << SYSCFG_SWPR2_PAGE47_Pos) /*!< 0x00008000 */ 8746 #define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 � 0x2003BFFF) */ 8747 #define SYSCFG_SWPR2_PAGE48_Pos (16U) 8748 #define SYSCFG_SWPR2_PAGE48_Msk (0x1UL << SYSCFG_SWPR2_PAGE48_Pos) /*!< 0x00010000 */ 8749 #define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 � 0x2003C3FF) */ 8750 #define SYSCFG_SWPR2_PAGE49_Pos (17U) 8751 #define SYSCFG_SWPR2_PAGE49_Msk (0x1UL << SYSCFG_SWPR2_PAGE49_Pos) /*!< 0x00020000 */ 8752 #define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 � 0x2003C7FF) */ 8753 #define SYSCFG_SWPR2_PAGE50_Pos (18U) 8754 #define SYSCFG_SWPR2_PAGE50_Msk (0x1UL << SYSCFG_SWPR2_PAGE50_Pos) /*!< 0x00040000 */ 8755 #define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 � 0x2003CBFF) */ 8756 #define SYSCFG_SWPR2_PAGE51_Pos (19U) 8757 #define SYSCFG_SWPR2_PAGE51_Msk (0x1UL << SYSCFG_SWPR2_PAGE51_Pos) /*!< 0x00080000 */ 8758 #define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 � 0x2003CFFF) */ 8759 #define SYSCFG_SWPR2_PAGE52_Pos (20U) 8760 #define SYSCFG_SWPR2_PAGE52_Msk (0x1UL << SYSCFG_SWPR2_PAGE52_Pos) /*!< 0x00100000 */ 8761 #define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 � 0x2003D3FF) */ 8762 #define SYSCFG_SWPR2_PAGE53_Pos (21U) 8763 #define SYSCFG_SWPR2_PAGE53_Msk (0x1UL << SYSCFG_SWPR2_PAGE53_Pos) /*!< 0x00200000 */ 8764 #define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 � 0x2003D7FF) */ 8765 #define SYSCFG_SWPR2_PAGE54_Pos (22U) 8766 #define SYSCFG_SWPR2_PAGE54_Msk (0x1UL << SYSCFG_SWPR2_PAGE54_Pos) /*!< 0x00400000 */ 8767 #define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 � 0x2003DBFF) */ 8768 #define SYSCFG_SWPR2_PAGE55_Pos (23U) 8769 #define SYSCFG_SWPR2_PAGE55_Msk (0x1UL << SYSCFG_SWPR2_PAGE55_Pos) /*!< 0x00800000 */ 8770 #define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 � 0x2003DFFF) */ 8771 #define SYSCFG_SWPR2_PAGE56_Pos (24U) 8772 #define SYSCFG_SWPR2_PAGE56_Msk (0x1UL << SYSCFG_SWPR2_PAGE56_Pos) /*!< 0x01000000 */ 8773 #define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 � 0x2003E3FF) */ 8774 #define SYSCFG_SWPR2_PAGE57_Pos (25U) 8775 #define SYSCFG_SWPR2_PAGE57_Msk (0x1UL << SYSCFG_SWPR2_PAGE57_Pos) /*!< 0x02000000 */ 8776 #define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 � 0x2003E7FF) */ 8777 #define SYSCFG_SWPR2_PAGE58_Pos (26U) 8778 #define SYSCFG_SWPR2_PAGE58_Msk (0x1UL << SYSCFG_SWPR2_PAGE58_Pos) /*!< 0x04000000 */ 8779 #define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 � 0x2003EBFF) */ 8780 #define SYSCFG_SWPR2_PAGE59_Pos (27U) 8781 #define SYSCFG_SWPR2_PAGE59_Msk (0x1UL << SYSCFG_SWPR2_PAGE59_Pos) /*!< 0x08000000 */ 8782 #define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 � 0x2003EFFF) */ 8783 #define SYSCFG_SWPR2_PAGE60_Pos (28U) 8784 #define SYSCFG_SWPR2_PAGE60_Msk (0x1UL << SYSCFG_SWPR2_PAGE60_Pos) /*!< 0x10000000 */ 8785 #define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 � 0x2003F3FF) */ 8786 #define SYSCFG_SWPR2_PAGE61_Pos (29U) 8787 #define SYSCFG_SWPR2_PAGE61_Msk (0x1UL << SYSCFG_SWPR2_PAGE61_Pos) /*!< 0x20000000 */ 8788 #define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 � 0x2003F7FF) */ 8789 #define SYSCFG_SWPR2_PAGE62_Pos (30U) 8790 #define SYSCFG_SWPR2_PAGE62_Msk (0x1UL << SYSCFG_SWPR2_PAGE62_Pos) /*!< 0x40000000 */ 8791 #define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 � 0x2003FBFF) */ 8792 #define SYSCFG_SWPR2_PAGE63_Pos (31U) 8793 #define SYSCFG_SWPR2_PAGE63_Msk (0x1UL << SYSCFG_SWPR2_PAGE63_Pos) /*!< 0x80000000 */ 8794 #define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 � 0x2003FFFF) */ 8795 8796 /***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/ 8797 #define SYSCFG_IMR1_TIM1IM_Pos (13U) 8798 #define SYSCFG_IMR1_TIM1IM_Msk (0x1UL << SYSCFG_IMR1_TIM1IM_Pos) /*!< 0x00002000 */ 8799 #define SYSCFG_IMR1_TIM1IM SYSCFG_IMR1_TIM1IM_Msk /*!< Enabling of interrupt from Timer 1 to CPU1 */ 8800 #define SYSCFG_IMR1_TIM16IM_Pos (14U) 8801 #define SYSCFG_IMR1_TIM16IM_Msk (0x1UL << SYSCFG_IMR1_TIM16IM_Pos) /*!< 0x00004000 */ 8802 #define SYSCFG_IMR1_TIM16IM SYSCFG_IMR1_TIM16IM_Msk /*!< Enabling of interrupt from Timer 16 to CPU1 */ 8803 #define SYSCFG_IMR1_TIM17IM_Pos (15U) 8804 #define SYSCFG_IMR1_TIM17IM_Msk (0x1UL << SYSCFG_IMR1_TIM17IM_Pos) /*!< 0x00008000 */ 8805 #define SYSCFG_IMR1_TIM17IM SYSCFG_IMR1_TIM17IM_Msk /*!< Enabling of interrupt from Timer 17 to CPU1 */ 8806 #define SYSCFG_IMR1_EXTI5IM_Pos (21U) 8807 #define SYSCFG_IMR1_EXTI5IM_Msk (0x1UL << SYSCFG_IMR1_EXTI5IM_Pos) /*!< 0x00200000 */ 8808 #define SYSCFG_IMR1_EXTI5IM SYSCFG_IMR1_EXTI5IM_Msk /*!< Enabling of interrupt from External Interrupt Line 5 to CPU1 */ 8809 #define SYSCFG_IMR1_EXTI6IM_Pos (22U) 8810 #define SYSCFG_IMR1_EXTI6IM_Msk (0x1UL << SYSCFG_IMR1_EXTI6IM_Pos) /*!< 0x00400000 */ 8811 #define SYSCFG_IMR1_EXTI6IM SYSCFG_IMR1_EXTI6IM_Msk /*!< Enabling of interrupt from External Interrupt Line 6 to CPU1 */ 8812 #define SYSCFG_IMR1_EXTI7IM_Pos (23U) 8813 #define SYSCFG_IMR1_EXTI7IM_Msk (0x1UL << SYSCFG_IMR1_EXTI7IM_Pos) /*!< 0x00800000 */ 8814 #define SYSCFG_IMR1_EXTI7IM SYSCFG_IMR1_EXTI7IM_Msk /*!< Enabling of interrupt from External Interrupt Line 7 to CPU1 */ 8815 #define SYSCFG_IMR1_EXTI8IM_Pos (24U) 8816 #define SYSCFG_IMR1_EXTI8IM_Msk (0x1UL << SYSCFG_IMR1_EXTI8IM_Pos) /*!< 0x01000000 */ 8817 #define SYSCFG_IMR1_EXTI8IM SYSCFG_IMR1_EXTI8IM_Msk /*!< Enabling of interrupt from External Interrupt Line 8 to CPU1 */ 8818 #define SYSCFG_IMR1_EXTI9IM_Pos (25U) 8819 #define SYSCFG_IMR1_EXTI9IM_Msk (0x1UL << SYSCFG_IMR1_EXTI9IM_Pos) /*!< 0x02000000 */ 8820 #define SYSCFG_IMR1_EXTI9IM SYSCFG_IMR1_EXTI9IM_Msk /*!< Enabling of interrupt from External Interrupt Line 9 to CPU1 */ 8821 #define SYSCFG_IMR1_EXTI10IM_Pos (26U) 8822 #define SYSCFG_IMR1_EXTI10IM_Msk (0x1UL << SYSCFG_IMR1_EXTI10IM_Pos) /*!< 0x04000000 */ 8823 #define SYSCFG_IMR1_EXTI10IM SYSCFG_IMR1_EXTI10IM_Msk /*!< Enabling of interrupt from External Interrupt Line 10 to CPU1 */ 8824 #define SYSCFG_IMR1_EXTI11IM_Pos (27U) 8825 #define SYSCFG_IMR1_EXTI11IM_Msk (0x1UL << SYSCFG_IMR1_EXTI11IM_Pos) /*!< 0x08000000 */ 8826 #define SYSCFG_IMR1_EXTI11IM SYSCFG_IMR1_EXTI11IM_Msk /*!< Enabling of interrupt from External Interrupt Line 11 to CPU1 */ 8827 #define SYSCFG_IMR1_EXTI12IM_Pos (28U) 8828 #define SYSCFG_IMR1_EXTI12IM_Msk (0x1UL << SYSCFG_IMR1_EXTI12IM_Pos) /*!< 0x10000000 */ 8829 #define SYSCFG_IMR1_EXTI12IM SYSCFG_IMR1_EXTI12IM_Msk /*!< Enabling of interrupt from External Interrupt Line 12 to CPU1 */ 8830 #define SYSCFG_IMR1_EXTI13IM_Pos (29U) 8831 #define SYSCFG_IMR1_EXTI13IM_Msk (0x1UL << SYSCFG_IMR1_EXTI13IM_Pos) /*!< 0x20000000 */ 8832 #define SYSCFG_IMR1_EXTI13IM SYSCFG_IMR1_EXTI13IM_Msk /*!< Enabling of interrupt from External Interrupt Line 13 to CPU1 */ 8833 #define SYSCFG_IMR1_EXTI14IM_Pos (30U) 8834 #define SYSCFG_IMR1_EXTI14IM_Msk (0x1UL << SYSCFG_IMR1_EXTI14IM_Pos) /*!< 0x40000000 */ 8835 #define SYSCFG_IMR1_EXTI14IM SYSCFG_IMR1_EXTI14IM_Msk /*!< Enabling of interrupt from External Interrupt Line 14 to CPU1 */ 8836 #define SYSCFG_IMR1_EXTI15IM_Pos (31U) 8837 #define SYSCFG_IMR1_EXTI15IM_Msk (0x1UL << SYSCFG_IMR1_EXTI15IM_Pos) /*!< 0x80000000 */ 8838 #define SYSCFG_IMR1_EXTI15IM SYSCFG_IMR1_EXTI15IM_Msk /*!< Enabling of interrupt from External Interrupt Line 15 to CPU1 */ 8839 8840 /***************** Bit definition for SYSCFG_IMR2 register (Interrupt masks control and status register on CPU1 - part 2) *******************************************/ 8841 #define SYSCFG_IMR2_PVM3IM_Pos (18U) 8842 #define SYSCFG_IMR2_PVM3IM_Msk (0x1UL << SYSCFG_IMR2_PVM3IM_Pos) /*!< 0x00040000 */ 8843 #define SYSCFG_IMR2_PVM3IM SYSCFG_IMR2_PVM3IM_Msk /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU1 */ 8844 #define SYSCFG_IMR2_PVDIM_Pos (20U) 8845 #define SYSCFG_IMR2_PVDIM_Msk (0x1UL << SYSCFG_IMR2_PVDIM_Pos) /*!< 0x00100000 */ 8846 #define SYSCFG_IMR2_PVDIM SYSCFG_IMR2_PVDIM_Msk /*!< Enabling of interrupt from Power Voltage Detector to CPU1 */ 8847 8848 /***************** Bit definition for SYSCFG_C2IMR1 register (Interrupt masks control and status register on CPU2 - part 1) *******************************************/ 8849 #define SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM_Pos (0U) 8850 #define SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM_Msk (0x1UL << SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM_Pos) /*!< 0x00000001 */ 8851 #define SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM_Msk /* !< Enabling of interrupt from RTC TimeStamp, RTC Tampers 8852 and LSE Clock Security System to CPU2 */ 8853 #define SYSCFG_C2IMR1_RTCWKUPIM_Pos (3U) 8854 #define SYSCFG_C2IMR1_RTCWKUPIM_Msk (0x1UL << SYSCFG_C2IMR1_RTCWKUPIM_Pos) /*!< 0x00000008 */ 8855 #define SYSCFG_C2IMR1_RTCWKUPIM SYSCFG_C2IMR1_RTCWKUPIM_Msk /*!< Enabling of interrupt from RTC Wakeup to CPU2 */ 8856 #define SYSCFG_C2IMR1_RTCALARMIM_Pos (4U) 8857 #define SYSCFG_C2IMR1_RTCALARMIM_Msk (0x1UL << SYSCFG_C2IMR1_RTCALARMIM_Pos) /*!< 0x00000010 */ 8858 #define SYSCFG_C2IMR1_RTCALARMIM SYSCFG_C2IMR1_RTCALARMIM_Msk /*!< Enabling of interrupt from RTC Alarms to CPU2 */ 8859 #define SYSCFG_C2IMR1_RCCIM_Pos (5U) 8860 #define SYSCFG_C2IMR1_RCCIM_Msk (0x1UL << SYSCFG_C2IMR1_RCCIM_Pos) /*!< 0x00000020 */ 8861 #define SYSCFG_C2IMR1_RCCIM SYSCFG_C2IMR1_RCCIM_Msk /*!< Enabling of interrupt from RCC to CPU2 */ 8862 #define SYSCFG_C2IMR1_FLASHIM_Pos (6U) 8863 #define SYSCFG_C2IMR1_FLASHIM_Msk (0x1UL << SYSCFG_C2IMR1_FLASHIM_Pos) /*!< 0x00000040 */ 8864 #define SYSCFG_C2IMR1_FLASHIM SYSCFG_C2IMR1_FLASHIM_Msk /*!< Enabling of interrupt from FLASH to CPU2 */ 8865 #define SYSCFG_C2IMR1_PKAIM_Pos (8U) 8866 #define SYSCFG_C2IMR1_PKAIM_Msk (0x1UL << SYSCFG_C2IMR1_PKAIM_Pos) /*!< 0x00000100 */ 8867 #define SYSCFG_C2IMR1_PKAIM SYSCFG_C2IMR1_PKAIM_Msk /*!< Enabling of interrupt from Public Key Accelerator to CPU2 */ 8868 #define SYSCFG_C2IMR1_RNGIM_Pos (9U) 8869 #define SYSCFG_C2IMR1_RNGIM_Msk (0x1UL << SYSCFG_C2IMR1_RNGIM_Pos) /*!< 0x00000200 */ 8870 #define SYSCFG_C2IMR1_RNGIM SYSCFG_C2IMR1_RNGIM_Msk /*!< Enabling of interrupt from Random Number Generator to CPU2 */ 8871 #define SYSCFG_C2IMR1_ADCIM_Pos (12U) 8872 #define SYSCFG_C2IMR1_ADCIM_Msk (0x1UL << SYSCFG_C2IMR1_ADCIM_Pos) /*!< 0x00001000 */ 8873 #define SYSCFG_C2IMR1_ADCIM SYSCFG_C2IMR1_ADCIM_Msk /*!< Enabling of interrupt from Analog Digital Converter to CPU2 */ 8874 #define SYSCFG_C2IMR1_EXTI0IM_Pos (16U) 8875 #define SYSCFG_C2IMR1_EXTI0IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI0IM_Pos) /*!< 0x00010000 */ 8876 #define SYSCFG_C2IMR1_EXTI0IM SYSCFG_C2IMR1_EXTI0IM_Msk /*!< Enabling of interrupt from External Interrupt Line 0 to CPU2 */ 8877 #define SYSCFG_C2IMR1_EXTI1IM_Pos (17U) 8878 #define SYSCFG_C2IMR1_EXTI1IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI1IM_Pos) /*!< 0x00020000 */ 8879 #define SYSCFG_C2IMR1_EXTI1IM SYSCFG_C2IMR1_EXTI1IM_Msk /*!< Enabling of interrupt from External Interrupt Line 1 to CPU2 */ 8880 #define SYSCFG_C2IMR1_EXTI2IM_Pos (18U) 8881 #define SYSCFG_C2IMR1_EXTI2IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI2IM_Pos) /*!< 0x00040000 */ 8882 #define SYSCFG_C2IMR1_EXTI2IM SYSCFG_C2IMR1_EXTI2IM_Msk /*!< Enabling of interrupt from External Interrupt Line 2 to CPU2 */ 8883 #define SYSCFG_C2IMR1_EXTI3IM_Pos (19U) 8884 #define SYSCFG_C2IMR1_EXTI3IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI3IM_Pos) /*!< 0x00080000 */ 8885 #define SYSCFG_C2IMR1_EXTI3IM SYSCFG_C2IMR1_EXTI3IM_Msk /*!< Enabling of interrupt from External Interrupt Line 3 to CPU2 */ 8886 #define SYSCFG_C2IMR1_EXTI4IM_Pos (20U) 8887 #define SYSCFG_C2IMR1_EXTI4IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI4IM_Pos) /*!< 0x00100000 */ 8888 #define SYSCFG_C2IMR1_EXTI4IM SYSCFG_C2IMR1_EXTI4IM_Msk /*!< Enabling of interrupt from External Interrupt Line 4 to CPU2 */ 8889 #define SYSCFG_C2IMR1_EXTI5IM_Pos (21U) 8890 #define SYSCFG_C2IMR1_EXTI5IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI5IM_Pos) /*!< 0x00200000 */ 8891 #define SYSCFG_C2IMR1_EXTI5IM SYSCFG_C2IMR1_EXTI5IM_Msk /*!< Enabling of interrupt from External Interrupt Line 5 to CPU2 */ 8892 #define SYSCFG_C2IMR1_EXTI6IM_Pos (22U) 8893 #define SYSCFG_C2IMR1_EXTI6IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI6IM_Pos) /*!< 0x00400000 */ 8894 #define SYSCFG_C2IMR1_EXTI6IM SYSCFG_C2IMR1_EXTI6IM_Msk /*!< Enabling of interrupt from External Interrupt Line 6 to CPU2 */ 8895 #define SYSCFG_C2IMR1_EXTI7IM_Pos (23U) 8896 #define SYSCFG_C2IMR1_EXTI7IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI7IM_Pos) /*!< 0x00800000 */ 8897 #define SYSCFG_C2IMR1_EXTI7IM SYSCFG_C2IMR1_EXTI7IM_Msk /*!< Enabling of interrupt from External Interrupt Line 7 to CPU2 */ 8898 #define SYSCFG_C2IMR1_EXTI8IM_Pos (24U) 8899 #define SYSCFG_C2IMR1_EXTI8IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI8IM_Pos) /*!< 0x01000000 */ 8900 #define SYSCFG_C2IMR1_EXTI8IM SYSCFG_C2IMR1_EXTI8IM_Msk /*!< Enabling of interrupt from External Interrupt Line 8 to CPU2 */ 8901 #define SYSCFG_C2IMR1_EXTI9IM_Pos (25U) 8902 #define SYSCFG_C2IMR1_EXTI9IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI9IM_Pos) /*!< 0x02000000 */ 8903 #define SYSCFG_C2IMR1_EXTI9IM SYSCFG_C2IMR1_EXTI9IM_Msk /*!< Enabling of interrupt from External Interrupt Line 9 to CPU2 */ 8904 #define SYSCFG_C2IMR1_EXTI10IM_Pos (26U) 8905 #define SYSCFG_C2IMR1_EXTI10IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI10IM_Pos) /*!< 0x04000000 */ 8906 #define SYSCFG_C2IMR1_EXTI10IM SYSCFG_C2IMR1_EXTI10IM_Msk /*!< Enabling of interrupt from External Interrupt Line 10 to CPU2 */ 8907 #define SYSCFG_C2IMR1_EXTI11IM_Pos (27U) 8908 #define SYSCFG_C2IMR1_EXTI11IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI11IM_Pos) /*!< 0x08000000 */ 8909 #define SYSCFG_C2IMR1_EXTI11IM SYSCFG_C2IMR1_EXTI11IM_Msk /*!< Enabling of interrupt from External Interrupt Line 11 to CPU2 */ 8910 #define SYSCFG_C2IMR1_EXTI12IM_Pos (28U) 8911 #define SYSCFG_C2IMR1_EXTI12IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI12IM_Pos) /*!< 0x10000000 */ 8912 #define SYSCFG_C2IMR1_EXTI12IM SYSCFG_C2IMR1_EXTI12IM_Msk /*!< Enabling of interrupt from External Interrupt Line 12 to CPU2 */ 8913 #define SYSCFG_C2IMR1_EXTI13IM_Pos (29U) 8914 #define SYSCFG_C2IMR1_EXTI13IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI13IM_Pos) /*!< 0x20000000 */ 8915 #define SYSCFG_C2IMR1_EXTI13IM SYSCFG_C2IMR1_EXTI13IM_Msk /*!< Enabling of interrupt from External Interrupt Line 13 to CPU2 */ 8916 #define SYSCFG_C2IMR1_EXTI14IM_Pos (30U) 8917 #define SYSCFG_C2IMR1_EXTI14IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI14IM_Pos) /*!< 0x40000000 */ 8918 #define SYSCFG_C2IMR1_EXTI14IM SYSCFG_C2IMR1_EXTI14IM_Msk /*!< Enabling of interrupt from External Interrupt Line 14 to CPU2 */ 8919 #define SYSCFG_C2IMR1_EXTI15IM_Pos (31U) 8920 #define SYSCFG_C2IMR1_EXTI15IM_Msk (0x1UL << SYSCFG_C2IMR1_EXTI15IM_Pos) /*!< 0x80000000 */ 8921 #define SYSCFG_C2IMR1_EXTI15IM SYSCFG_C2IMR1_EXTI15IM_Msk /*!< Enabling of interrupt from External Interrupt Line 15 to CPU2 */ 8922 8923 /***************** Bit definition for SYSCFG_C2IMR2 register (Interrupt masks control and status register on CPU2 - part 2) *******************************************/ 8924 #define SYSCFG_C2IMR2_DMA1CH1IM_Pos (0U) 8925 #define SYSCFG_C2IMR2_DMA1CH1IM_Msk (0x1UL << SYSCFG_C2IMR2_DMA1CH1IM_Pos) /*!< 0x00000001 */ 8926 #define SYSCFG_C2IMR2_DMA1CH1IM SYSCFG_C2IMR2_DMA1CH1IM_Msk /*!< Enabling of interrupt from DMA1 Channel 1 to CPU2 */ 8927 #define SYSCFG_C2IMR2_DMA1CH2IM_Pos (1U) 8928 #define SYSCFG_C2IMR2_DMA1CH2IM_Msk (0x1UL << SYSCFG_C2IMR2_DMA1CH2IM_Pos) /*!< 0x00000002 */ 8929 #define SYSCFG_C2IMR2_DMA1CH2IM SYSCFG_C2IMR2_DMA1CH2IM_Msk /*!< Enabling of interrupt from DMA1 Channel 2 to CPU2 */ 8930 #define SYSCFG_C2IMR2_DMA1CH3IM_Pos (2U) 8931 #define SYSCFG_C2IMR2_DMA1CH3IM_Msk (0x1UL << SYSCFG_C2IMR2_DMA1CH3IM_Pos) /*!< 0x00000004 */ 8932 #define SYSCFG_C2IMR2_DMA1CH3IM SYSCFG_C2IMR2_DMA1CH3IM_Msk /*!< Enabling of interrupt from DMA1 Channel 3 to CPU2 */ 8933 #define SYSCFG_C2IMR2_DMA1CH4IM_Pos (3U) 8934 #define SYSCFG_C2IMR2_DMA1CH4IM_Msk (0x1UL << SYSCFG_C2IMR2_DMA1CH4IM_Pos) /*!< 0x00000008 */ 8935 #define SYSCFG_C2IMR2_DMA1CH4IM SYSCFG_C2IMR2_DMA1CH4IM_Msk /*!< Enabling of interrupt from DMA1 Channel 4 to CPU2 */ 8936 #define SYSCFG_C2IMR2_DMA1CH5IM_Pos (4U) 8937 #define SYSCFG_C2IMR2_DMA1CH5IM_Msk (0x1UL << SYSCFG_C2IMR2_DMA1CH5IM_Pos) /*!< 0x00000010 */ 8938 #define SYSCFG_C2IMR2_DMA1CH5IM SYSCFG_C2IMR2_DMA1CH5IM_Msk /*!< Enabling of interrupt from DMA1 Channel 5 to CPU2 */ 8939 #define SYSCFG_C2IMR2_DMA1CH6IM_Pos (5U) 8940 #define SYSCFG_C2IMR2_DMA1CH6IM_Msk (0x1UL << SYSCFG_C2IMR2_DMA1CH6IM_Pos) /*!< 0x00000020 */ 8941 #define SYSCFG_C2IMR2_DMA1CH6IM SYSCFG_C2IMR2_DMA1CH6IM_Msk /*!< Enabling of interrupt from DMA1 Channel 6 to CPU2 */ 8942 #define SYSCFG_C2IMR2_DMA1CH7IM_Pos (6U) 8943 #define SYSCFG_C2IMR2_DMA1CH7IM_Msk (0x1UL << SYSCFG_C2IMR2_DMA1CH7IM_Pos) /*!< 0x00000040 */ 8944 #define SYSCFG_C2IMR2_DMA1CH7IM SYSCFG_C2IMR2_DMA1CH7IM_Msk /*!< Enabling of interrupt from DMA1 Channel 7 to CPU2 */ 8945 #define SYSCFG_C2IMR2_DMAMUX1IM_Pos (15U) 8946 #define SYSCFG_C2IMR2_DMAMUX1IM_Msk (0x1UL << SYSCFG_C2IMR2_DMAMUX1IM_Pos) /*!< 0x00008000 */ 8947 #define SYSCFG_C2IMR2_DMAMUX1IM SYSCFG_C2IMR2_DMAMUX1IM_Msk /*!< Enabling of interrupt from DMAMUX1 to CPU2 */ 8948 #define SYSCFG_C2IMR2_PVM3IM_Pos (18U) 8949 #define SYSCFG_C2IMR2_PVM3IM_Msk (0x1UL << SYSCFG_C2IMR2_PVM3IM_Pos) /*!< 0x00040000 */ 8950 #define SYSCFG_C2IMR2_PVM3IM SYSCFG_C2IMR2_PVM3IM_Msk /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU2 */ 8951 #define SYSCFG_C2IMR2_PVDIM_Pos (20U) 8952 #define SYSCFG_C2IMR2_PVDIM_Msk (0x1UL << SYSCFG_C2IMR2_PVDIM_Pos) /*!< 0x00100000 */ 8953 #define SYSCFG_C2IMR2_PVDIM SYSCFG_C2IMR2_PVDIM_Msk /*!< Enabling of interrupt from Power Voltage Detector to CPU2 */ 8954 #define SYSCFG_C2IMR2_TSCIM_Pos (21U) 8955 #define SYSCFG_C2IMR2_TSCIM_Msk (0x1UL << SYSCFG_C2IMR2_TSCIM_Pos) /*!< 0x00200000 */ 8956 #define SYSCFG_C2IMR2_TSCIM SYSCFG_C2IMR2_TSCIM_Msk /*!< Enabling of interrupt from Touch Sensing Controller to CPU2 */ 8957 8958 /***************** Bit definition for SYSCFG_SIPCR register (SYSCFG secure IP control register) *****************************************************************************/ 8959 #define SYSCFG_SIPCR_SAES2_Pos (1U) 8960 #define SYSCFG_SIPCR_SAES2_Msk (0x1UL << SYSCFG_SIPCR_SAES2_Pos) /*!< 0x00000002 */ 8961 #define SYSCFG_SIPCR_SAES2 SYSCFG_SIPCR_SAES2_Msk /*!< Enabling the security access of Advanced Encryption Standard 2 */ 8962 #define SYSCFG_SIPCR_SPKA_Pos (2U) 8963 #define SYSCFG_SIPCR_SPKA_Msk (0x1UL << SYSCFG_SIPCR_SPKA_Pos) /*!< 0x00000004 */ 8964 #define SYSCFG_SIPCR_SPKA SYSCFG_SIPCR_SPKA_Msk /*!< Enabling the security access of Public Key Accelerator */ 8965 #define SYSCFG_SIPCR_SRNG_Pos (3U) 8966 #define SYSCFG_SIPCR_SRNG_Msk (0x1UL << SYSCFG_SIPCR_SRNG_Pos) /*!< 0x00000008 */ 8967 #define SYSCFG_SIPCR_SRNG SYSCFG_SIPCR_SRNG_Msk /*!< Enabling the security access of Random Number Generator */ 8968 8969 /******************************************************************************/ 8970 /* */ 8971 /* TIM */ 8972 /* */ 8973 /******************************************************************************/ 8974 /******************* Bit definition for TIM_CR1 register ********************/ 8975 #define TIM_CR1_CEN_Pos (0U) 8976 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 8977 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 8978 #define TIM_CR1_UDIS_Pos (1U) 8979 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 8980 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 8981 #define TIM_CR1_URS_Pos (2U) 8982 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 8983 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 8984 #define TIM_CR1_OPM_Pos (3U) 8985 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 8986 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 8987 #define TIM_CR1_DIR_Pos (4U) 8988 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 8989 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 8990 8991 #define TIM_CR1_CMS_Pos (5U) 8992 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 8993 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 8994 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 8995 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 8996 8997 #define TIM_CR1_ARPE_Pos (7U) 8998 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 8999 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 9000 9001 #define TIM_CR1_CKD_Pos (8U) 9002 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 9003 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 9004 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 9005 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 9006 9007 #define TIM_CR1_UIFREMAP_Pos (11U) 9008 #define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */ 9009 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */ 9010 9011 /******************* Bit definition for TIM_CR2 register ********************/ 9012 #define TIM_CR2_CCPC_Pos (0U) 9013 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ 9014 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ 9015 #define TIM_CR2_CCUS_Pos (2U) 9016 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ 9017 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ 9018 #define TIM_CR2_CCDS_Pos (3U) 9019 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 9020 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 9021 9022 #define TIM_CR2_MMS_Pos (4U) 9023 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 9024 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 9025 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 9026 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 9027 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 9028 9029 #define TIM_CR2_TI1S_Pos (7U) 9030 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 9031 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 9032 #define TIM_CR2_OIS1_Pos (8U) 9033 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ 9034 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ 9035 #define TIM_CR2_OIS1N_Pos (9U) 9036 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ 9037 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ 9038 #define TIM_CR2_OIS2_Pos (10U) 9039 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ 9040 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ 9041 #define TIM_CR2_OIS2N_Pos (11U) 9042 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ 9043 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ 9044 #define TIM_CR2_OIS3_Pos (12U) 9045 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ 9046 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ 9047 #define TIM_CR2_OIS3N_Pos (13U) 9048 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ 9049 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ 9050 #define TIM_CR2_OIS4_Pos (14U) 9051 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ 9052 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ 9053 #define TIM_CR2_OIS5_Pos (16U) 9054 #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ 9055 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */ 9056 #define TIM_CR2_OIS6_Pos (18U) 9057 #define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */ 9058 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */ 9059 9060 #define TIM_CR2_MMS2_Pos (20U) 9061 #define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */ 9062 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 9063 #define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */ 9064 #define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */ 9065 #define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */ 9066 #define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */ 9067 9068 /******************* Bit definition for TIM_SMCR register *******************/ 9069 #define TIM_SMCR_SMS_Pos (0U) 9070 #define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */ 9071 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 9072 #define TIM_SMCR_SMS_0 (0x00001U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 9073 #define TIM_SMCR_SMS_1 (0x00002U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 9074 #define TIM_SMCR_SMS_2 (0x00004U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 9075 #define TIM_SMCR_SMS_3 (0x10000U << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */ 9076 9077 #define TIM_SMCR_OCCS_Pos (3U) 9078 #define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ 9079 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ 9080 9081 #define TIM_SMCR_TS_Pos (4U) 9082 #define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */ 9083 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 9084 #define TIM_SMCR_TS_0 (0x00001U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 9085 #define TIM_SMCR_TS_1 (0x00002U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 9086 #define TIM_SMCR_TS_2 (0x00004U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 9087 #define TIM_SMCR_TS_3 (0x10000U << TIM_SMCR_TS_Pos) /*!< 0x00100000 */ 9088 #define TIM_SMCR_TS_4 (0x20000U << TIM_SMCR_TS_Pos) /*!< 0x00200000 */ 9089 9090 #define TIM_SMCR_MSM_Pos (7U) 9091 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 9092 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 9093 9094 #define TIM_SMCR_ETF_Pos (8U) 9095 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 9096 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 9097 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 9098 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 9099 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 9100 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 9101 9102 #define TIM_SMCR_ETPS_Pos (12U) 9103 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 9104 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 9105 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 9106 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 9107 9108 #define TIM_SMCR_ECE_Pos (14U) 9109 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 9110 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 9111 #define TIM_SMCR_ETP_Pos (15U) 9112 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 9113 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 9114 9115 /******************* Bit definition for TIM_DIER register *******************/ 9116 #define TIM_DIER_UIE_Pos (0U) 9117 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 9118 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 9119 #define TIM_DIER_CC1IE_Pos (1U) 9120 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 9121 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 9122 #define TIM_DIER_CC2IE_Pos (2U) 9123 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 9124 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 9125 #define TIM_DIER_CC3IE_Pos (3U) 9126 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 9127 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 9128 #define TIM_DIER_CC4IE_Pos (4U) 9129 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 9130 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 9131 #define TIM_DIER_COMIE_Pos (5U) 9132 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ 9133 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ 9134 #define TIM_DIER_TIE_Pos (6U) 9135 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 9136 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 9137 #define TIM_DIER_BIE_Pos (7U) 9138 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ 9139 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ 9140 #define TIM_DIER_UDE_Pos (8U) 9141 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 9142 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 9143 #define TIM_DIER_CC1DE_Pos (9U) 9144 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 9145 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 9146 #define TIM_DIER_CC2DE_Pos (10U) 9147 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 9148 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 9149 #define TIM_DIER_CC3DE_Pos (11U) 9150 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 9151 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 9152 #define TIM_DIER_CC4DE_Pos (12U) 9153 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 9154 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 9155 #define TIM_DIER_COMDE_Pos (13U) 9156 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ 9157 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ 9158 #define TIM_DIER_TDE_Pos (14U) 9159 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 9160 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 9161 9162 /******************** Bit definition for TIM_SR register ********************/ 9163 #define TIM_SR_UIF_Pos (0U) 9164 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 9165 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 9166 #define TIM_SR_CC1IF_Pos (1U) 9167 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 9168 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 9169 #define TIM_SR_CC2IF_Pos (2U) 9170 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 9171 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 9172 #define TIM_SR_CC3IF_Pos (3U) 9173 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 9174 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 9175 #define TIM_SR_CC4IF_Pos (4U) 9176 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 9177 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 9178 #define TIM_SR_COMIF_Pos (5U) 9179 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ 9180 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ 9181 #define TIM_SR_TIF_Pos (6U) 9182 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 9183 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 9184 #define TIM_SR_BIF_Pos (7U) 9185 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */ 9186 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ 9187 #define TIM_SR_B2IF_Pos (8U) 9188 #define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */ 9189 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */ 9190 #define TIM_SR_CC1OF_Pos (9U) 9191 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 9192 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 9193 #define TIM_SR_CC2OF_Pos (10U) 9194 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 9195 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 9196 #define TIM_SR_CC3OF_Pos (11U) 9197 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 9198 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 9199 #define TIM_SR_CC4OF_Pos (12U) 9200 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 9201 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 9202 #define TIM_SR_SBIF_Pos (13U) 9203 #define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */ 9204 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */ 9205 #define TIM_SR_CC5IF_Pos (16U) 9206 #define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */ 9207 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */ 9208 #define TIM_SR_CC6IF_Pos (17U) 9209 #define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */ 9210 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */ 9211 9212 9213 /******************* Bit definition for TIM_EGR register ********************/ 9214 #define TIM_EGR_UG_Pos (0U) 9215 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 9216 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 9217 #define TIM_EGR_CC1G_Pos (1U) 9218 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 9219 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 9220 #define TIM_EGR_CC2G_Pos (2U) 9221 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 9222 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 9223 #define TIM_EGR_CC3G_Pos (3U) 9224 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 9225 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 9226 #define TIM_EGR_CC4G_Pos (4U) 9227 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 9228 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 9229 #define TIM_EGR_COMG_Pos (5U) 9230 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ 9231 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ 9232 #define TIM_EGR_TG_Pos (6U) 9233 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 9234 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 9235 #define TIM_EGR_BG_Pos (7U) 9236 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */ 9237 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ 9238 #define TIM_EGR_B2G_Pos (8U) 9239 #define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */ 9240 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */ 9241 9242 9243 /****************** Bit definition for TIM_CCMR1 register *******************/ 9244 #define TIM_CCMR1_CC1S_Pos (0U) 9245 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 9246 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 9247 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 9248 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 9249 9250 #define TIM_CCMR1_OC1FE_Pos (2U) 9251 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 9252 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 9253 #define TIM_CCMR1_OC1PE_Pos (3U) 9254 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 9255 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 9256 9257 #define TIM_CCMR1_OC1M_Pos (4U) 9258 #define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */ 9259 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 9260 #define TIM_CCMR1_OC1M_0 (0x0001U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 9261 #define TIM_CCMR1_OC1M_1 (0x0002U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 9262 #define TIM_CCMR1_OC1M_2 (0x0004U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 9263 #define TIM_CCMR1_OC1M_3 (0x1000U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */ 9264 9265 #define TIM_CCMR1_OC1CE_Pos (7U) 9266 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 9267 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */ 9268 9269 #define TIM_CCMR1_CC2S_Pos (8U) 9270 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 9271 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 9272 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 9273 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 9274 9275 #define TIM_CCMR1_OC2FE_Pos (10U) 9276 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 9277 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 9278 #define TIM_CCMR1_OC2PE_Pos (11U) 9279 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 9280 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 9281 9282 #define TIM_CCMR1_OC2M_Pos (12U) 9283 #define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */ 9284 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 9285 #define TIM_CCMR1_OC2M_0 (0x0001U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 9286 #define TIM_CCMR1_OC2M_1 (0x0002U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 9287 #define TIM_CCMR1_OC2M_2 (0x0004U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 9288 #define TIM_CCMR1_OC2M_3 (0x1000U << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */ 9289 9290 #define TIM_CCMR1_OC2CE_Pos (15U) 9291 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 9292 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 9293 9294 /*----------------------------------------------------------------------------*/ 9295 #define TIM_CCMR1_IC1PSC_Pos (2U) 9296 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 9297 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 9298 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 9299 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 9300 9301 #define TIM_CCMR1_IC1F_Pos (4U) 9302 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 9303 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 9304 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 9305 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 9306 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 9307 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 9308 9309 #define TIM_CCMR1_IC2PSC_Pos (10U) 9310 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 9311 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 9312 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 9313 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 9314 9315 #define TIM_CCMR1_IC2F_Pos (12U) 9316 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 9317 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 9318 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 9319 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 9320 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 9321 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 9322 9323 /****************** Bit definition for TIM_CCMR2 register *******************/ 9324 #define TIM_CCMR2_CC3S_Pos (0U) 9325 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 9326 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 9327 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 9328 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 9329 9330 #define TIM_CCMR2_OC3FE_Pos (2U) 9331 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 9332 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 9333 #define TIM_CCMR2_OC3PE_Pos (3U) 9334 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 9335 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 9336 9337 #define TIM_CCMR2_OC3M_Pos (4U) 9338 #define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */ 9339 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 9340 #define TIM_CCMR2_OC3M_0 (0x0001U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 9341 #define TIM_CCMR2_OC3M_1 (0x0002U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 9342 #define TIM_CCMR2_OC3M_2 (0x0004U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 9343 #define TIM_CCMR2_OC3M_3 (0x1000U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */ 9344 9345 #define TIM_CCMR2_OC3CE_Pos (7U) 9346 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 9347 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 9348 9349 #define TIM_CCMR2_CC4S_Pos (8U) 9350 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 9351 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 9352 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 9353 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 9354 9355 #define TIM_CCMR2_OC4FE_Pos (10U) 9356 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 9357 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 9358 #define TIM_CCMR2_OC4PE_Pos (11U) 9359 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 9360 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 9361 9362 #define TIM_CCMR2_OC4M_Pos (12U) 9363 #define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */ 9364 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 9365 #define TIM_CCMR2_OC4M_0 (0x0001U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 9366 #define TIM_CCMR2_OC4M_1 (0x0002U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 9367 #define TIM_CCMR2_OC4M_2 (0x0004U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 9368 #define TIM_CCMR2_OC4M_3 (0x1000U << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */ 9369 9370 #define TIM_CCMR2_OC4CE_Pos (15U) 9371 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 9372 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 9373 9374 /*----------------------------------------------------------------------------*/ 9375 #define TIM_CCMR2_IC3PSC_Pos (2U) 9376 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 9377 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 9378 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 9379 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 9380 9381 #define TIM_CCMR2_IC3F_Pos (4U) 9382 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 9383 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 9384 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 9385 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 9386 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 9387 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 9388 9389 #define TIM_CCMR2_IC4PSC_Pos (10U) 9390 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 9391 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 9392 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 9393 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 9394 9395 #define TIM_CCMR2_IC4F_Pos (12U) 9396 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 9397 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 9398 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 9399 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 9400 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 9401 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 9402 9403 /****************** Bit definition for TIM_CCMR3 register *******************/ 9404 #define TIM_CCMR3_OC5FE_Pos (2U) 9405 #define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */ 9406 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */ 9407 #define TIM_CCMR3_OC5PE_Pos (3U) 9408 #define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */ 9409 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */ 9410 9411 #define TIM_CCMR3_OC5M_Pos (4U) 9412 #define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */ 9413 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */ 9414 #define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */ 9415 #define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */ 9416 #define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */ 9417 #define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */ 9418 9419 #define TIM_CCMR3_OC5CE_Pos (7U) 9420 #define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */ 9421 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */ 9422 9423 #define TIM_CCMR3_OC6FE_Pos (10U) 9424 #define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */ 9425 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */ 9426 #define TIM_CCMR3_OC6PE_Pos (11U) 9427 #define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */ 9428 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */ 9429 9430 #define TIM_CCMR3_OC6M_Pos (12U) 9431 #define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */ 9432 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */ 9433 #define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */ 9434 #define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */ 9435 #define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */ 9436 #define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */ 9437 9438 #define TIM_CCMR3_OC6CE_Pos (15U) 9439 #define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */ 9440 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */ 9441 9442 /******************* Bit definition for TIM_CCER register *******************/ 9443 #define TIM_CCER_CC1E_Pos (0U) 9444 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 9445 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 9446 #define TIM_CCER_CC1P_Pos (1U) 9447 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 9448 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 9449 #define TIM_CCER_CC1NE_Pos (2U) 9450 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ 9451 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ 9452 #define TIM_CCER_CC1NP_Pos (3U) 9453 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 9454 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 9455 #define TIM_CCER_CC2E_Pos (4U) 9456 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 9457 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 9458 #define TIM_CCER_CC2P_Pos (5U) 9459 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 9460 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 9461 #define TIM_CCER_CC2NE_Pos (6U) 9462 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ 9463 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ 9464 #define TIM_CCER_CC2NP_Pos (7U) 9465 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 9466 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 9467 #define TIM_CCER_CC3E_Pos (8U) 9468 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 9469 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 9470 #define TIM_CCER_CC3P_Pos (9U) 9471 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 9472 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 9473 #define TIM_CCER_CC3NE_Pos (10U) 9474 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ 9475 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ 9476 #define TIM_CCER_CC3NP_Pos (11U) 9477 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 9478 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 9479 #define TIM_CCER_CC4E_Pos (12U) 9480 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 9481 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 9482 #define TIM_CCER_CC4P_Pos (13U) 9483 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 9484 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 9485 #define TIM_CCER_CC4NP_Pos (15U) 9486 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ 9487 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ 9488 #define TIM_CCER_CC5E_Pos (16U) 9489 #define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */ 9490 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */ 9491 #define TIM_CCER_CC5P_Pos (17U) 9492 #define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */ 9493 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */ 9494 #define TIM_CCER_CC6E_Pos (20U) 9495 #define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */ 9496 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */ 9497 #define TIM_CCER_CC6P_Pos (21U) 9498 #define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */ 9499 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */ 9500 9501 /******************* Bit definition for TIM_CNT register ********************/ 9502 #define TIM_CNT_CNT_Pos (0U) 9503 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ 9504 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 9505 #define TIM_CNT_UIFCPY_Pos (31U) 9506 #define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */ 9507 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */ 9508 9509 /******************* Bit definition for TIM_PSC register ********************/ 9510 #define TIM_PSC_PSC_Pos (0U) 9511 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 9512 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 9513 9514 /******************* Bit definition for TIM_ARR register ********************/ 9515 #define TIM_ARR_ARR_Pos (0U) 9516 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ 9517 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */ 9518 9519 /******************* Bit definition for TIM_RCR register ********************/ 9520 #define TIM_RCR_REP_Pos (0U) 9521 #define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */ 9522 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ 9523 9524 /******************* Bit definition for TIM_CCR1 register *******************/ 9525 #define TIM_CCR1_CCR1_Pos (0U) 9526 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 9527 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 9528 9529 /******************* Bit definition for TIM_CCR2 register *******************/ 9530 #define TIM_CCR2_CCR2_Pos (0U) 9531 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 9532 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 9533 9534 /******************* Bit definition for TIM_CCR3 register *******************/ 9535 #define TIM_CCR3_CCR3_Pos (0U) 9536 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 9537 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 9538 9539 /******************* Bit definition for TIM_CCR4 register *******************/ 9540 #define TIM_CCR4_CCR4_Pos (0U) 9541 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 9542 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 9543 9544 /******************* Bit definition for TIM_CCR5 register *******************/ 9545 #define TIM_CCR5_CCR5_Pos (0U) 9546 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ 9547 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ 9548 #define TIM_CCR5_GC5C1_Pos (29U) 9549 #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ 9550 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */ 9551 #define TIM_CCR5_GC5C2_Pos (30U) 9552 #define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */ 9553 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */ 9554 #define TIM_CCR5_GC5C3_Pos (31U) 9555 #define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */ 9556 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */ 9557 9558 /******************* Bit definition for TIM_CCR6 register *******************/ 9559 #define TIM_CCR6_CCR6_Pos (0U) 9560 #define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */ 9561 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */ 9562 9563 /******************* Bit definition for TIM_BDTR register *******************/ 9564 #define TIM_BDTR_DTG_Pos (0U) 9565 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ 9566 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ 9567 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ 9568 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ 9569 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ 9570 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ 9571 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ 9572 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ 9573 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ 9574 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ 9575 9576 #define TIM_BDTR_LOCK_Pos (8U) 9577 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ 9578 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ 9579 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ 9580 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ 9581 9582 #define TIM_BDTR_OSSI_Pos (10U) 9583 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ 9584 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ 9585 #define TIM_BDTR_OSSR_Pos (11U) 9586 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ 9587 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ 9588 #define TIM_BDTR_BKE_Pos (12U) 9589 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ 9590 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */ 9591 #define TIM_BDTR_BKP_Pos (13U) 9592 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ 9593 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */ 9594 #define TIM_BDTR_AOE_Pos (14U) 9595 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ 9596 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ 9597 #define TIM_BDTR_MOE_Pos (15U) 9598 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ 9599 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ 9600 9601 #define TIM_BDTR_BKF_Pos (16U) 9602 #define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */ 9603 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */ 9604 #define TIM_BDTR_BK2F_Pos (20U) 9605 #define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */ 9606 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */ 9607 9608 #define TIM_BDTR_BK2E_Pos (24U) 9609 #define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */ 9610 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */ 9611 #define TIM_BDTR_BK2P_Pos (25U) 9612 #define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */ 9613 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */ 9614 9615 #define TIM_BDTR_BKDSRM_Pos (26U) 9616 #define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */ 9617 #define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */ 9618 #define TIM_BDTR_BK2DSRM_Pos (27U) 9619 #define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */ 9620 #define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */ 9621 9622 #define TIM_BDTR_BKBID_Pos (28U) 9623 #define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */ 9624 #define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break BIDirectional */ 9625 #define TIM_BDTR_BK2BID_Pos (29U) 9626 #define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */ 9627 #define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 BIDirectional */ 9628 9629 /******************* Bit definition for TIM_DCR register ********************/ 9630 #define TIM_DCR_DBA_Pos (0U) 9631 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 9632 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 9633 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 9634 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 9635 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 9636 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 9637 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 9638 9639 #define TIM_DCR_DBL_Pos (8U) 9640 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 9641 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 9642 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 9643 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 9644 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 9645 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 9646 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 9647 9648 /******************* Bit definition for TIM_DMAR register *******************/ 9649 #define TIM_DMAR_DMAB_Pos (0U) 9650 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 9651 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 9652 9653 /******************* Bit definition for TIM1_OR register *******************/ 9654 #define TIM1_OR_ETR_ADC1_RMP_Pos (0U) 9655 #define TIM1_OR_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */ 9656 #define TIM1_OR_ETR_ADC1_RMP TIM1_OR_ETR_ADC1_RMP_Msk /*!< TIM1_ETR_ADC1 remapping capability*/ 9657 #define TIM1_OR_ETR_ADC1_RMP_0 (0x1U << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */ 9658 #define TIM1_OR_ETR_ADC1_RMP_1 (0x2U << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */ 9659 #define TIM1_OR_TI1_RMP_Pos (4U) 9660 #define TIM1_OR_TI1_RMP_Msk (0x1UL << TIM1_OR_TI1_RMP_Pos) /*!< 0x00000010 */ 9661 #define TIM1_OR_TI1_RMP TIM1_OR_TI1_RMP_Msk /*!< Input Capture 1 remap*/ 9662 9663 /******************* Bit definition for TIM2_OR register *******************/ 9664 #define TIM2_OR_TI4_RMP_Pos (2U) 9665 #define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x0000000C */ 9666 #define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!< TI4 RMA[1:0]Input capture 4 remap*/ 9667 #define TIM2_OR_TI4_RMP_0 (0x1U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000004 */ 9668 #define TIM2_OR_TI4_RMP_1 (0x2U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */ 9669 #define TIM2_OR_ETR_RMP_Pos (1U) 9670 #define TIM2_OR_ETR_RMP_Msk (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */ 9671 #define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!< External trigger remap*/ 9672 #define TIM2_OR_ITR1_RMP_Pos (0U) 9673 #define TIM2_OR_ITR1_RMP_Msk (0x1UL << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000001 */ 9674 #define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk /*!< Internal trigger remap*/ 9675 9676 /******************* Bit definition for TIM16_OR register ******************/ 9677 #define TIM16_OR_TI1_RMP_Pos (0U) 9678 #define TIM16_OR_TI1_RMP_Msk (0x3UL << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000003 */ 9679 #define TIM16_OR_TI1_RMP TIM16_OR_TI1_RMP_Msk /*!<Timer 16 input 1 connection. */ 9680 #define TIM16_OR_TI1_RMP_0 (0x1U << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000001 */ 9681 #define TIM16_OR_TI1_RMP_1 (0x2U << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000002 */ 9682 9683 /******************* Bit definition for TIM17_OR register ******************/ 9684 #define TIM17_OR_TI1_RMP_Pos (0U) 9685 #define TIM17_OR_TI1_RMP_Msk (0x3UL << TIM17_OR_TI1_RMP_Pos) /*!< 0x00000003 */ 9686 #define TIM17_OR_TI1_RMP TIM17_OR_TI1_RMP_Msk /*!<Timer 17 input 1 connection. */ 9687 #define TIM17_OR_TI1_RMP_0 (0x1U << TIM17_OR_TI1_RMP_Pos) /*!< 0x00000001 */ 9688 #define TIM17_OR_TI1_RMP_1 (0x2U << TIM17_OR_TI1_RMP_Pos) /*!< 0x00000002 */ 9689 9690 /******************* Bit definition for TIM1_AF1 register *******************/ 9691 #define TIM1_AF1_BKINE_Pos (0U) 9692 #define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */ 9693 #define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */ 9694 #define TIM1_AF1_BKINP_Pos (9U) 9695 #define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */ 9696 #define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */ 9697 #define TIM1_AF1_ETRSEL_Pos (14U) 9698 #define TIM1_AF1_ETRSEL_Msk (0x7UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0001C000 */ 9699 #define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */ 9700 #define TIM1_AF1_ETRSEL_0 (0x1U << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */ 9701 #define TIM1_AF1_ETRSEL_1 (0x2U << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */ 9702 #define TIM1_AF1_ETRSEL_2 (0x4U << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */ 9703 9704 /******************* Bit definition for TIM2_AF1 register *******************/ 9705 #define TIM2_AF1_ETRSEL_Pos (14U) 9706 #define TIM2_AF1_ETRSEL_Msk (0x7UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x0001C000 */ 9707 #define TIM2_AF1_ETRSEL (0x00001C000) /*!< External trigger source selection */ 9708 #define TIM2_AF1_ETRSEL_0 (0x000004000) /*!< Bit_0 */ 9709 #define TIM2_AF1_ETRSEL_1 (0x000008000) /*!< Bit_1 */ 9710 #define TIM2_AF1_ETRSEL_2 (0x000010000) /*!< Bit_2 */ 9711 9712 /******************* Bit definition for TIM16_AF1 register *******************/ 9713 #define TIM16_AF1_BKINE_Pos (0U) 9714 #define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos) /*!< 0x00000001 */ 9715 #define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk /*!<BRK BKIN input enable */ 9716 #define TIM16_AF1_BKINP_Pos (9U) 9717 #define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos) /*!< 0x00000200 */ 9718 #define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk /*!<BRK BKIN2 input polarity */ 9719 9720 /******************* Bit definition for TIM17_AF1 register *******************/ 9721 #define TIM17_AF1_BKINE_Pos (0U) 9722 #define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos) /*!< 0x00000001 */ 9723 #define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk /*!<BRK BKIN input enable */ 9724 #define TIM17_AF1_BKINP_Pos (9U) 9725 #define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos) /*!< 0x00000200 */ 9726 #define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk /*!<BRK BKIN2 input polarity */ 9727 9728 /******************* Bit definition for TIM1_AF2 register *******************/ 9729 #define TIM1_AF2_BK2INE_Pos (0U) 9730 #define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */ 9731 #define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN2 input enable */ 9732 #define TIM1_AF2_BK2INP_Pos (9U) 9733 #define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */ 9734 #define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */ 9735 9736 /******************************************************************************/ 9737 /* */ 9738 /* Low Power Timer (LPTTIM) */ 9739 /* */ 9740 /******************************************************************************/ 9741 /****************** Bit definition for LPTIM_ISR register *******************/ 9742 #define LPTIM_ISR_CMPM_Pos (0U) 9743 #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */ 9744 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */ 9745 #define LPTIM_ISR_ARRM_Pos (1U) 9746 #define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */ 9747 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */ 9748 #define LPTIM_ISR_EXTTRIG_Pos (2U) 9749 #define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */ 9750 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */ 9751 #define LPTIM_ISR_CMPOK_Pos (3U) 9752 #define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */ 9753 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */ 9754 #define LPTIM_ISR_ARROK_Pos (4U) 9755 #define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */ 9756 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */ 9757 #define LPTIM_ISR_UP_Pos (5U) 9758 #define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */ 9759 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */ 9760 #define LPTIM_ISR_DOWN_Pos (6U) 9761 #define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */ 9762 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */ 9763 9764 /****************** Bit definition for LPTIM_ICR register *******************/ 9765 #define LPTIM_ICR_CMPMCF_Pos (0U) 9766 #define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */ 9767 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */ 9768 #define LPTIM_ICR_ARRMCF_Pos (1U) 9769 #define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */ 9770 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */ 9771 #define LPTIM_ICR_EXTTRIGCF_Pos (2U) 9772 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */ 9773 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */ 9774 #define LPTIM_ICR_CMPOKCF_Pos (3U) 9775 #define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */ 9776 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */ 9777 #define LPTIM_ICR_ARROKCF_Pos (4U) 9778 #define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */ 9779 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */ 9780 #define LPTIM_ICR_UPCF_Pos (5U) 9781 #define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */ 9782 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */ 9783 #define LPTIM_ICR_DOWNCF_Pos (6U) 9784 #define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */ 9785 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */ 9786 9787 /****************** Bit definition for LPTIM_IER register ********************/ 9788 #define LPTIM_IER_CMPMIE_Pos (0U) 9789 #define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */ 9790 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */ 9791 #define LPTIM_IER_ARRMIE_Pos (1U) 9792 #define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */ 9793 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */ 9794 #define LPTIM_IER_EXTTRIGIE_Pos (2U) 9795 #define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */ 9796 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */ 9797 #define LPTIM_IER_CMPOKIE_Pos (3U) 9798 #define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */ 9799 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */ 9800 #define LPTIM_IER_ARROKIE_Pos (4U) 9801 #define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */ 9802 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */ 9803 #define LPTIM_IER_UPIE_Pos (5U) 9804 #define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */ 9805 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */ 9806 #define LPTIM_IER_DOWNIE_Pos (6U) 9807 #define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */ 9808 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */ 9809 9810 /****************** Bit definition for LPTIM_CFGR register *******************/ 9811 #define LPTIM_CFGR_CKSEL_Pos (0U) 9812 #define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */ 9813 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */ 9814 9815 #define LPTIM_CFGR_CKPOL_Pos (1U) 9816 #define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */ 9817 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */ 9818 #define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */ 9819 #define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */ 9820 9821 #define LPTIM_CFGR_CKFLT_Pos (3U) 9822 #define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */ 9823 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */ 9824 #define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */ 9825 #define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */ 9826 9827 #define LPTIM_CFGR_TRGFLT_Pos (6U) 9828 #define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */ 9829 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */ 9830 #define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */ 9831 #define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */ 9832 9833 #define LPTIM_CFGR_PRESC_Pos (9U) 9834 #define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */ 9835 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */ 9836 #define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */ 9837 #define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */ 9838 #define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */ 9839 9840 #define LPTIM_CFGR_TRIGSEL_Pos (13U) 9841 #define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */ 9842 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */ 9843 #define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */ 9844 #define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */ 9845 #define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */ 9846 9847 #define LPTIM_CFGR_TRIGEN_Pos (17U) 9848 #define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */ 9849 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */ 9850 #define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */ 9851 #define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */ 9852 9853 #define LPTIM_CFGR_TIMOUT_Pos (19U) 9854 #define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */ 9855 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timeout enable */ 9856 #define LPTIM_CFGR_WAVE_Pos (20U) 9857 #define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */ 9858 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */ 9859 #define LPTIM_CFGR_WAVPOL_Pos (21U) 9860 #define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */ 9861 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */ 9862 #define LPTIM_CFGR_PRELOAD_Pos (22U) 9863 #define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */ 9864 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */ 9865 #define LPTIM_CFGR_COUNTMODE_Pos (23U) 9866 #define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */ 9867 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */ 9868 #define LPTIM_CFGR_ENC_Pos (24U) 9869 #define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */ 9870 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */ 9871 9872 /****************** Bit definition for LPTIM_CR register ********************/ 9873 #define LPTIM_CR_ENABLE_Pos (0U) 9874 #define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */ 9875 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */ 9876 #define LPTIM_CR_SNGSTRT_Pos (1U) 9877 #define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */ 9878 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */ 9879 #define LPTIM_CR_CNTSTRT_Pos (2U) 9880 #define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */ 9881 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */ 9882 #define LPTIM_CR_COUNTRST_Pos (3U) 9883 #define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */ 9884 #define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */ 9885 #define LPTIM_CR_RSTARE_Pos (4U) 9886 #define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */ 9887 #define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */ 9888 9889 /****************** Bit definition for LPTIM_CMP register *******************/ 9890 #define LPTIM_CMP_CMP_Pos (0U) 9891 #define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */ 9892 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */ 9893 9894 /****************** Bit definition for LPTIM_ARR register *******************/ 9895 #define LPTIM_ARR_ARR_Pos (0U) 9896 #define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */ 9897 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */ 9898 9899 /****************** Bit definition for LPTIM_CNT register *******************/ 9900 #define LPTIM_CNT_CNT_Pos (0U) 9901 #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */ 9902 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */ 9903 9904 /****************** Bit definition for LPTIM_OR register *******************/ 9905 #define LPTIM_OR_OR_Pos (0U) 9906 #define LPTIM_OR_OR_Msk (0x3UL << LPTIM_OR_OR_Pos) /*!< 0x00000003 */ 9907 #define LPTIM_OR_OR LPTIM_OR_OR_Msk /*!< OR[1:0] bits (Remap selection) */ 9908 #define LPTIM_OR_OR_0 (0x1U << LPTIM_OR_OR_Pos) /*!< 0x00000001 */ 9909 #define LPTIM_OR_OR_1 (0x2U << LPTIM_OR_OR_Pos) /*!< 0x00000002 */ 9910 9911 /******************************************************************************/ 9912 /* */ 9913 /* Inter-Processor Communication Controller (IPCC) */ 9914 /* */ 9915 /******************************************************************************/ 9916 9917 /********************** Bit definition for IPCC_C1CR register ***************/ 9918 #define IPCC_C1CR_RXOIE_Pos (0U) 9919 #define IPCC_C1CR_RXOIE_Msk (0x1UL << IPCC_C1CR_RXOIE_Pos) /*!< 0x00000001 */ 9920 #define IPCC_C1CR_RXOIE IPCC_C1CR_RXOIE_Msk /*!< Processor M4 Receive channel occupied interrupt enable */ 9921 #define IPCC_C1CR_TXFIE_Pos (16U) 9922 #define IPCC_C1CR_TXFIE_Msk (0x1UL << IPCC_C1CR_TXFIE_Pos) /*!< 0x00010000 */ 9923 #define IPCC_C1CR_TXFIE IPCC_C1CR_TXFIE_Msk /*!< Processor M4 Transmit channel free interrupt enable */ 9924 9925 /********************** Bit definition for IPCC_C1MR register **************/ 9926 #define IPCC_C1MR_CH1OM_Pos (0U) 9927 #define IPCC_C1MR_CH1OM_Msk (0x1UL << IPCC_C1MR_CH1OM_Pos) /*!< 0x00000001 */ 9928 #define IPCC_C1MR_CH1OM IPCC_C1MR_CH1OM_Msk /*!< M4 Channel1 occupied interrupt mask */ 9929 #define IPCC_C1MR_CH2OM_Pos (1U) 9930 #define IPCC_C1MR_CH2OM_Msk (0x1UL << IPCC_C1MR_CH2OM_Pos) /*!< 0x00000002 */ 9931 #define IPCC_C1MR_CH2OM IPCC_C1MR_CH2OM_Msk /*!< M4 Channel2 occupied interrupt mask */ 9932 #define IPCC_C1MR_CH3OM_Pos (2U) 9933 #define IPCC_C1MR_CH3OM_Msk (0x1UL << IPCC_C1MR_CH3OM_Pos) /*!< 0x00000004 */ 9934 #define IPCC_C1MR_CH3OM IPCC_C1MR_CH3OM_Msk /*!< M4 Channel3 occupied interrupt mask */ 9935 #define IPCC_C1MR_CH4OM_Pos (3U) 9936 #define IPCC_C1MR_CH4OM_Msk (0x1UL << IPCC_C1MR_CH4OM_Pos) /*!< 0x00000008 */ 9937 #define IPCC_C1MR_CH4OM IPCC_C1MR_CH4OM_Msk /*!< M4 Channel4 occupied interrupt mask */ 9938 #define IPCC_C1MR_CH5OM_Pos (4U) 9939 #define IPCC_C1MR_CH5OM_Msk (0x1UL << IPCC_C1MR_CH5OM_Pos) /*!< 0x00000010 */ 9940 #define IPCC_C1MR_CH5OM IPCC_C1MR_CH5OM_Msk /*!< M4 Channel5 occupied interrupt mask */ 9941 #define IPCC_C1MR_CH6OM_Pos (5U) 9942 #define IPCC_C1MR_CH6OM_Msk (0x1UL << IPCC_C1MR_CH6OM_Pos) /*!< 0x00000020 */ 9943 #define IPCC_C1MR_CH6OM IPCC_C1MR_CH6OM_Msk /*!< M4 Channel6 occupied interrupt mask */ 9944 9945 #define IPCC_C1MR_CH1FM_Pos (16U) 9946 #define IPCC_C1MR_CH1FM_Msk (0x1UL << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */ 9947 #define IPCC_C1MR_CH1FM IPCC_C1MR_CH1FM_Msk /*!< M4 Transmit Channel1 free interrupt mask */ 9948 #define IPCC_C1MR_CH2FM_Pos (17U) 9949 #define IPCC_C1MR_CH2FM_Msk (0x1UL << IPCC_C1MR_CH2FM_Pos) /*!< 0x00020000 */ 9950 #define IPCC_C1MR_CH2FM IPCC_C1MR_CH2FM_Msk /*!< M4 Transmit Channel2 free interrupt mask */ 9951 #define IPCC_C1MR_CH3FM_Pos (18U) 9952 #define IPCC_C1MR_CH3FM_Msk (0x1UL << IPCC_C1MR_CH3FM_Pos) /*!< 0x00040000 */ 9953 #define IPCC_C1MR_CH3FM IPCC_C1MR_CH3FM_Msk /*!< M4 Transmit Channel3 free interrupt mask */ 9954 #define IPCC_C1MR_CH4FM_Pos (19U) 9955 #define IPCC_C1MR_CH4FM_Msk (0x1UL << IPCC_C1MR_CH4FM_Pos) /*!< 0x00080000 */ 9956 #define IPCC_C1MR_CH4FM IPCC_C1MR_CH4FM_Msk /*!< M4 Transmit Channel4 free interrupt mask */ 9957 #define IPCC_C1MR_CH5FM_Pos (20U) 9958 #define IPCC_C1MR_CH5FM_Msk (0x1UL << IPCC_C1MR_CH5FM_Pos) /*!< 0x00100000 */ 9959 #define IPCC_C1MR_CH5FM IPCC_C1MR_CH5FM_Msk /*!< M4 Transmit Channel5 free interrupt mask */ 9960 #define IPCC_C1MR_CH6FM_Pos (21U) 9961 #define IPCC_C1MR_CH6FM_Msk (0x1UL << IPCC_C1MR_CH6FM_Pos) /*!< 0x00200000 */ 9962 #define IPCC_C1MR_CH6FM IPCC_C1MR_CH6FM_Msk /*!< M4 Transmit Channel6 free interrupt mask */ 9963 9964 /********************** Bit definition for IPCC_C1SCR register ***************/ 9965 #define IPCC_C1SCR_CH1C_Pos (0U) 9966 #define IPCC_C1SCR_CH1C_Msk (0x1UL << IPCC_C1SCR_CH1C_Pos) /*!< 0x00000001 */ 9967 #define IPCC_C1SCR_CH1C IPCC_C1SCR_CH1C_Msk /*!< M4 receive Channel1 status clear */ 9968 #define IPCC_C1SCR_CH2C_Pos (1U) 9969 #define IPCC_C1SCR_CH2C_Msk (0x1UL << IPCC_C1SCR_CH2C_Pos) /*!< 0x00000002 */ 9970 #define IPCC_C1SCR_CH2C IPCC_C1SCR_CH2C_Msk /*!< M4 receive Channel2 status clear */ 9971 #define IPCC_C1SCR_CH3C_Pos (2U) 9972 #define IPCC_C1SCR_CH3C_Msk (0x1UL << IPCC_C1SCR_CH3C_Pos) /*!< 0x00000004 */ 9973 #define IPCC_C1SCR_CH3C IPCC_C1SCR_CH3C_Msk /*!< M4 receive Channel3 status clear */ 9974 #define IPCC_C1SCR_CH4C_Pos (3U) 9975 #define IPCC_C1SCR_CH4C_Msk (0x1UL << IPCC_C1SCR_CH4C_Pos) /*!< 0x00000008 */ 9976 #define IPCC_C1SCR_CH4C IPCC_C1SCR_CH4C_Msk /*!< M4 receive Channel4 status clear */ 9977 #define IPCC_C1SCR_CH5C_Pos (4U) 9978 #define IPCC_C1SCR_CH5C_Msk (0x1UL << IPCC_C1SCR_CH5C_Pos) /*!< 0x00000010 */ 9979 #define IPCC_C1SCR_CH5C IPCC_C1SCR_CH5C_Msk /*!< M4 receive Channel5 status clear */ 9980 #define IPCC_C1SCR_CH6C_Pos (5U) 9981 #define IPCC_C1SCR_CH6C_Msk (0x1UL << IPCC_C1SCR_CH6C_Pos) /*!< 0x00000020 */ 9982 #define IPCC_C1SCR_CH6C IPCC_C1SCR_CH6C_Msk /*!< M4 receive Channel6 status clear */ 9983 9984 #define IPCC_C1SCR_CH1S_Pos (16U) 9985 #define IPCC_C1SCR_CH1S_Msk (0x1UL << IPCC_C1SCR_CH1S_Pos) /*!< 0x00010000 */ 9986 #define IPCC_C1SCR_CH1S IPCC_C1SCR_CH1S_Msk /*!< M4 transmit Channel1 status set */ 9987 #define IPCC_C1SCR_CH2S_Pos (17U) 9988 #define IPCC_C1SCR_CH2S_Msk (0x1UL << IPCC_C1SCR_CH2S_Pos) /*!< 0x00020000 */ 9989 #define IPCC_C1SCR_CH2S IPCC_C1SCR_CH2S_Msk /*!< M4 transmit Channel2 status set */ 9990 #define IPCC_C1SCR_CH3S_Pos (18U) 9991 #define IPCC_C1SCR_CH3S_Msk (0x1UL << IPCC_C1SCR_CH3S_Pos) /*!< 0x00040000 */ 9992 #define IPCC_C1SCR_CH3S IPCC_C1SCR_CH3S_Msk /*!< M4 transmit Channel3 status set */ 9993 #define IPCC_C1SCR_CH4S_Pos (19U) 9994 #define IPCC_C1SCR_CH4S_Msk (0x1UL << IPCC_C1SCR_CH4S_Pos) /*!< 0x00080000 */ 9995 #define IPCC_C1SCR_CH4S IPCC_C1SCR_CH4S_Msk /*!< M4 transmit Channel4 status set */ 9996 #define IPCC_C1SCR_CH5S_Pos (20U) 9997 #define IPCC_C1SCR_CH5S_Msk (0x1UL << IPCC_C1SCR_CH5S_Pos) /*!< 0x00100000 */ 9998 #define IPCC_C1SCR_CH5S IPCC_C1SCR_CH5S_Msk /*!< M4 transmit Channel5 status set */ 9999 #define IPCC_C1SCR_CH6S_Pos (21U) 10000 #define IPCC_C1SCR_CH6S_Msk (0x1UL << IPCC_C1SCR_CH6S_Pos) /*!< 0x00200000 */ 10001 #define IPCC_C1SCR_CH6S IPCC_C1SCR_CH6S_Msk /*!< M4 transmit Channel6 status set */ 10002 10003 /********************** Bit definition for IPCC_C1TOC2SR register ***************/ 10004 #define IPCC_C1TOC2SR_CH1F_Pos (0U) 10005 #define IPCC_C1TOC2SR_CH1F_Msk (0x1UL << IPCC_C1TOC2SR_CH1F_Pos) /*!< 0x00000001 */ 10006 #define IPCC_C1TOC2SR_CH1F IPCC_C1TOC2SR_CH1F_Msk /*!< M4 transmit to M4 receive Channel1 status flag before masking */ 10007 #define IPCC_C1TOC2SR_CH2F_Pos (1U) 10008 #define IPCC_C1TOC2SR_CH2F_Msk (0x1UL << IPCC_C1TOC2SR_CH2F_Pos) /*!< 0x00000002 */ 10009 #define IPCC_C1TOC2SR_CH2F IPCC_C1TOC2SR_CH2F_Msk /*!< M4 transmit to M4 receive Channel2 status flag before masking */ 10010 #define IPCC_C1TOC2SR_CH3F_Pos (2U) 10011 #define IPCC_C1TOC2SR_CH3F_Msk (0x1UL << IPCC_C1TOC2SR_CH3F_Pos) /*!< 0x00000004 */ 10012 #define IPCC_C1TOC2SR_CH3F IPCC_C1TOC2SR_CH3F_Msk /*!< M4 transmit to M4 receive Channel3 status flag before masking */ 10013 #define IPCC_C1TOC2SR_CH4F_Pos (3U) 10014 #define IPCC_C1TOC2SR_CH4F_Msk (0x1UL << IPCC_C1TOC2SR_CH4F_Pos) /*!< 0x00000008 */ 10015 #define IPCC_C1TOC2SR_CH4F IPCC_C1TOC2SR_CH4F_Msk /*!< M4 transmit to M4 receive Channel4 status flag before masking */ 10016 #define IPCC_C1TOC2SR_CH5F_Pos (4U) 10017 #define IPCC_C1TOC2SR_CH5F_Msk (0x1UL << IPCC_C1TOC2SR_CH5F_Pos) /*!< 0x00000010 */ 10018 #define IPCC_C1TOC2SR_CH5F IPCC_C1TOC2SR_CH5F_Msk /*!< M4 transmit to M4 receive Channel5 status flag before masking */ 10019 #define IPCC_C1TOC2SR_CH6F_Pos (5U) 10020 #define IPCC_C1TOC2SR_CH6F_Msk (0x1UL << IPCC_C1TOC2SR_CH6F_Pos) /*!< 0x00000020 */ 10021 #define IPCC_C1TOC2SR_CH6F IPCC_C1TOC2SR_CH6F_Msk /*!< M4 transmit to M4 receive Channel6 status flag before masking */ 10022 10023 /********************** Bit definition for IPCC_C2CR register ***************/ 10024 #define IPCC_C2CR_RXOIE_Pos (0U) 10025 #define IPCC_C2CR_RXOIE_Msk (0x1UL << IPCC_C2CR_RXOIE_Pos) /*!< 0x00000001 */ 10026 #define IPCC_C2CR_RXOIE IPCC_C2CR_RXOIE_Msk /*!< Processor M0+ Receive channel occupied interrupt enable */ 10027 #define IPCC_C2CR_TXFIE_Pos (16U) 10028 #define IPCC_C2CR_TXFIE_Msk (0x1UL << IPCC_C2CR_TXFIE_Pos) /*!< 0x00010000 */ 10029 #define IPCC_C2CR_TXFIE IPCC_C2CR_TXFIE_Msk /*!< Processor M0+ Transmit channel free interrupt enable */ 10030 10031 /********************** Bit definition for IPCC_C2MR register ***************/ 10032 #define IPCC_C2MR_CH1OM_Pos (0U) 10033 #define IPCC_C2MR_CH1OM_Msk (0x1UL << IPCC_C2MR_CH1OM_Pos) /*!< 0x00000001 */ 10034 #define IPCC_C2MR_CH1OM IPCC_C2MR_CH1OM_Msk /*!< M0+ Channel1 occupied interrupt mask */ 10035 #define IPCC_C2MR_CH2OM_Pos (1U) 10036 #define IPCC_C2MR_CH2OM_Msk (0x1UL << IPCC_C2MR_CH2OM_Pos) /*!< 0x00000002 */ 10037 #define IPCC_C2MR_CH2OM IPCC_C2MR_CH2OM_Msk /*!< M0+ Channel2 occupied interrupt mask */ 10038 #define IPCC_C2MR_CH3OM_Pos (2U) 10039 #define IPCC_C2MR_CH3OM_Msk (0x1UL << IPCC_C2MR_CH3OM_Pos) /*!< 0x00000004 */ 10040 #define IPCC_C2MR_CH3OM IPCC_C2MR_CH3OM_Msk /*!< M0+ Channel3 occupied interrupt mask */ 10041 #define IPCC_C2MR_CH4OM_Pos (3U) 10042 #define IPCC_C2MR_CH4OM_Msk (0x1UL << IPCC_C2MR_CH4OM_Pos) /*!< 0x00000008 */ 10043 #define IPCC_C2MR_CH4OM IPCC_C2MR_CH4OM_Msk /*!< M0+ Channel4 occupied interrupt mask */ 10044 #define IPCC_C2MR_CH5OM_Pos (4U) 10045 #define IPCC_C2MR_CH5OM_Msk (0x1UL << IPCC_C2MR_CH5OM_Pos) /*!< 0x00000010 */ 10046 #define IPCC_C2MR_CH5OM IPCC_C2MR_CH5OM_Msk /*!< M0+ Channel5 occupied interrupt mask */ 10047 #define IPCC_C2MR_CH6OM_Pos (5U) 10048 #define IPCC_C2MR_CH6OM_Msk (0x1UL << IPCC_C2MR_CH6OM_Pos) /*!< 0x00000020 */ 10049 #define IPCC_C2MR_CH6OM IPCC_C2MR_CH6OM_Msk /*!< M0+ Channel6 occupied interrupt mask */ 10050 10051 #define IPCC_C2MR_CH1FM_Pos (16U) 10052 #define IPCC_C2MR_CH1FM_Msk (0x1UL << IPCC_C2MR_CH1FM_Pos) /*!< 0x00010000 */ 10053 #define IPCC_C2MR_CH1FM IPCC_C2MR_CH1FM_Msk /*!< M0+ Transmit Channel1 free interrupt mask */ 10054 #define IPCC_C2MR_CH2FM_Pos (17U) 10055 #define IPCC_C2MR_CH2FM_Msk (0x1UL << IPCC_C2MR_CH2FM_Pos) /*!< 0x00020000 */ 10056 #define IPCC_C2MR_CH2FM IPCC_C2MR_CH2FM_Msk /*!< M0+ Transmit Channel2 free interrupt mask */ 10057 #define IPCC_C2MR_CH3FM_Pos (18U) 10058 #define IPCC_C2MR_CH3FM_Msk (0x1UL << IPCC_C2MR_CH3FM_Pos) /*!< 0x00040000 */ 10059 #define IPCC_C2MR_CH3FM IPCC_C2MR_CH3FM_Msk /*!< M0+ Transmit Channel3 free interrupt mask */ 10060 #define IPCC_C2MR_CH4FM_Pos (19U) 10061 #define IPCC_C2MR_CH4FM_Msk (0x1UL << IPCC_C2MR_CH4FM_Pos) /*!< 0x00080000 */ 10062 #define IPCC_C2MR_CH4FM IPCC_C2MR_CH4FM_Msk /*!< M0+ Transmit Channel4 free interrupt mask */ 10063 #define IPCC_C2MR_CH5FM_Pos (20U) 10064 #define IPCC_C2MR_CH5FM_Msk (0x1UL << IPCC_C2MR_CH5FM_Pos) /*!< 0x00100000 */ 10065 #define IPCC_C2MR_CH5FM IPCC_C2MR_CH5FM_Msk /*!< M0+ Transmit Channel5 free interrupt mask */ 10066 #define IPCC_C2MR_CH6FM_Pos (21U) 10067 #define IPCC_C2MR_CH6FM_Msk (0x1UL << IPCC_C2MR_CH6FM_Pos) /*!< 0x00200000 */ 10068 #define IPCC_C2MR_CH6FM IPCC_C2MR_CH6FM_Msk /*!< M0+ Transmit Channel6 free interrupt mask */ 10069 10070 /********************** Bit definition for IPCC_C2SCR register ***************/ 10071 #define IPCC_C2SCR_CH1C_Pos (0U) 10072 #define IPCC_C2SCR_CH1C_Msk (0x1UL << IPCC_C2SCR_CH1C_Pos) /*!< 0x00000001 */ 10073 #define IPCC_C2SCR_CH1C IPCC_C2SCR_CH1C_Msk /*!< M0+ receive Channel1 status clear */ 10074 #define IPCC_C2SCR_CH2C_Pos (1U) 10075 #define IPCC_C2SCR_CH2C_Msk (0x1UL << IPCC_C2SCR_CH2C_Pos) /*!< 0x00000002 */ 10076 #define IPCC_C2SCR_CH2C IPCC_C2SCR_CH2C_Msk /*!< M0+ receive Channel2 status clear */ 10077 #define IPCC_C2SCR_CH3C_Pos (2U) 10078 #define IPCC_C2SCR_CH3C_Msk (0x1UL << IPCC_C2SCR_CH3C_Pos) /*!< 0x00000004 */ 10079 #define IPCC_C2SCR_CH3C IPCC_C2SCR_CH3C_Msk /*!< M0+ receive Channel3 status clear */ 10080 #define IPCC_C2SCR_CH4C_Pos (3U) 10081 #define IPCC_C2SCR_CH4C_Msk (0x1UL << IPCC_C2SCR_CH4C_Pos) /*!< 0x00000008 */ 10082 #define IPCC_C2SCR_CH4C IPCC_C2SCR_CH4C_Msk /*!< M0+ receive Channel4 status clear */ 10083 #define IPCC_C2SCR_CH5C_Pos (4U) 10084 #define IPCC_C2SCR_CH5C_Msk (0x1UL << IPCC_C2SCR_CH5C_Pos) /*!< 0x00000010 */ 10085 #define IPCC_C2SCR_CH5C IPCC_C2SCR_CH5C_Msk /*!< M0+ receive Channel5 status clear */ 10086 #define IPCC_C2SCR_CH6C_Pos (5U) 10087 #define IPCC_C2SCR_CH6C_Msk (0x1UL << IPCC_C2SCR_CH6C_Pos) /*!< 0x00000020 */ 10088 #define IPCC_C2SCR_CH6C IPCC_C2SCR_CH6C_Msk /*!< M0+ receive Channel6 status clear */ 10089 10090 #define IPCC_C2SCR_CH1S_Pos (16U) 10091 #define IPCC_C2SCR_CH1S_Msk (0x1UL << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */ 10092 #define IPCC_C2SCR_CH1S IPCC_C2SCR_CH1S_Msk /*!< M0+ transmit Channel1 status set */ 10093 #define IPCC_C2SCR_CH2S_Pos (17U) 10094 #define IPCC_C2SCR_CH2S_Msk (0x1UL << IPCC_C2SCR_CH2S_Pos) /*!< 0x00020000 */ 10095 #define IPCC_C2SCR_CH2S IPCC_C2SCR_CH2S_Msk /*!< M0+ transmit Channel2 status set */ 10096 #define IPCC_C2SCR_CH3S_Pos (18U) 10097 #define IPCC_C2SCR_CH3S_Msk (0x1UL << IPCC_C2SCR_CH3S_Pos) /*!< 0x00040000 */ 10098 #define IPCC_C2SCR_CH3S IPCC_C2SCR_CH3S_Msk /*!< M0+ transmit Channel3 status set */ 10099 #define IPCC_C2SCR_CH4S_Pos (19U) 10100 #define IPCC_C2SCR_CH4S_Msk (0x1UL << IPCC_C2SCR_CH4S_Pos) /*!< 0x00080000 */ 10101 #define IPCC_C2SCR_CH4S IPCC_C2SCR_CH4S_Msk /*!< M0+ transmit Channel4 status set */ 10102 #define IPCC_C2SCR_CH5S_Pos (20U) 10103 #define IPCC_C2SCR_CH5S_Msk (0x1UL << IPCC_C2SCR_CH5S_Pos) /*!< 0x00100000 */ 10104 #define IPCC_C2SCR_CH5S IPCC_C2SCR_CH5S_Msk /*!< M0+ transmit Channel5 status set */ 10105 #define IPCC_C2SCR_CH6S_Pos (21U) 10106 #define IPCC_C2SCR_CH6S_Msk (0x1UL << IPCC_C2SCR_CH6S_Pos) /*!< 0x00200000 */ 10107 #define IPCC_C2SCR_CH6S IPCC_C2SCR_CH6S_Msk /*!< M0+ transmit Channel6 status set */ 10108 10109 /********************** Bit definition for IPCC_C2TOC1SR register ***************/ 10110 #define IPCC_C2TOC1SR_CH1F_Pos (0U) 10111 #define IPCC_C2TOC1SR_CH1F_Msk (0x1UL << IPCC_C2TOC1SR_CH1F_Pos) /*!< 0x00000001 */ 10112 #define IPCC_C2TOC1SR_CH1F IPCC_C2TOC1SR_CH1F_Msk /*!< M0+ transmit to M0 receive Channel1 status flag before masking */ 10113 #define IPCC_C2TOC1SR_CH2F_Pos (1U) 10114 #define IPCC_C2TOC1SR_CH2F_Msk (0x1UL << IPCC_C2TOC1SR_CH2F_Pos) /*!< 0x00000002 */ 10115 #define IPCC_C2TOC1SR_CH2F IPCC_C2TOC1SR_CH2F_Msk /*!< M0+ transmit to M0 receive Channel2 status flag before masking */ 10116 #define IPCC_C2TOC1SR_CH3F_Pos (2U) 10117 #define IPCC_C2TOC1SR_CH3F_Msk (0x1UL << IPCC_C2TOC1SR_CH3F_Pos) /*!< 0x00000004 */ 10118 #define IPCC_C2TOC1SR_CH3F IPCC_C2TOC1SR_CH3F_Msk /*!< M0+ transmit to M0 receive Channel3 status flag before masking */ 10119 #define IPCC_C2TOC1SR_CH4F_Pos (3U) 10120 #define IPCC_C2TOC1SR_CH4F_Msk (0x1UL << IPCC_C2TOC1SR_CH4F_Pos) /*!< 0x00000008 */ 10121 #define IPCC_C2TOC1SR_CH4F IPCC_C2TOC1SR_CH4F_Msk /*!< M0+ transmit to M0 receive Channel4 status flag before masking */ 10122 #define IPCC_C2TOC1SR_CH5F_Pos (4U) 10123 #define IPCC_C2TOC1SR_CH5F_Msk (0x1UL << IPCC_C2TOC1SR_CH5F_Pos) /*!< 0x00000010 */ 10124 #define IPCC_C2TOC1SR_CH5F IPCC_C2TOC1SR_CH5F_Msk /*!< M0+ transmit to M0 receive Channel5 status flag before masking */ 10125 #define IPCC_C2TOC1SR_CH6F_Pos (5U) 10126 #define IPCC_C2TOC1SR_CH6F_Msk (0x1UL << IPCC_C2TOC1SR_CH6F_Pos) /*!< 0x00000020 */ 10127 #define IPCC_C2TOC1SR_CH6F IPCC_C2TOC1SR_CH6F_Msk /*!< M0+ transmit to M0 receive Channel6 status flag before masking */ 10128 10129 /********************** Bit definition for IPCC_C1CR register ***************/ 10130 #define IPCC_CR_RXOIE_Pos IPCC_C1CR_RXOIE_Pos 10131 #define IPCC_CR_RXOIE_Msk IPCC_C1CR_RXOIE_Msk 10132 #define IPCC_CR_RXOIE IPCC_C1CR_RXOIE 10133 #define IPCC_CR_TXFIE_Pos IPCC_C1CR_TXFIE_Pos 10134 #define IPCC_CR_TXFIE_Msk IPCC_C1CR_TXFIE_Msk 10135 #define IPCC_CR_TXFIE IPCC_C1CR_TXFIE 10136 10137 /********************** Bit definition for IPCC_C1MR register **************/ 10138 #define IPCC_MR_CH1OM_Pos IPCC_C1MR_CH1OM_Pos 10139 #define IPCC_MR_CH1OM_Msk IPCC_C1MR_CH1OM_Msk 10140 #define IPCC_MR_CH1OM IPCC_C1MR_CH1OM 10141 #define IPCC_MR_CH2OM_Pos IPCC_C1MR_CH2OM_Pos 10142 #define IPCC_MR_CH2OM_Msk IPCC_C1MR_CH2OM_Msk 10143 #define IPCC_MR_CH2OM IPCC_C1MR_CH2OM 10144 #define IPCC_MR_CH3OM_Pos IPCC_C1MR_CH3OM_Pos 10145 #define IPCC_MR_CH3OM_Msk IPCC_C1MR_CH3OM_Msk 10146 #define IPCC_MR_CH3OM IPCC_C1MR_CH3OM 10147 #define IPCC_MR_CH4OM_Pos IPCC_C1MR_CH4OM_Pos 10148 #define IPCC_MR_CH4OM_Msk IPCC_C1MR_CH4OM_Msk 10149 #define IPCC_MR_CH4OM IPCC_C1MR_CH4OM 10150 #define IPCC_MR_CH5OM_Pos IPCC_C1MR_CH5OM_Pos 10151 #define IPCC_MR_CH5OM_Msk IPCC_C1MR_CH5OM_Msk 10152 #define IPCC_MR_CH5OM IPCC_C1MR_CH5OM 10153 #define IPCC_MR_CH6OM_Pos IPCC_C1MR_CH6OM_Pos 10154 #define IPCC_MR_CH6OM_Msk IPCC_C1MR_CH6OM_Msk 10155 #define IPCC_MR_CH6OM IPCC_C1MR_CH6OM 10156 10157 #define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos 10158 #define IPCC_MR_CH1FM_Msk IPCC_C1MR_CH1FM_Msk 10159 #define IPCC_MR_CH1FM IPCC_C1MR_CH1FM 10160 #define IPCC_MR_CH2FM_Pos IPCC_C1MR_CH2FM_Pos 10161 #define IPCC_MR_CH2FM_Msk IPCC_C1MR_CH2FM_Msk 10162 #define IPCC_MR_CH2FM IPCC_C1MR_CH2FM 10163 #define IPCC_MR_CH3FM_Pos IPCC_C1MR_CH3FM_Pos 10164 #define IPCC_MR_CH3FM_Msk IPCC_C1MR_CH3FM_Msk 10165 #define IPCC_MR_CH3FM IPCC_C1MR_CH3FM 10166 #define IPCC_MR_CH4FM_Pos IPCC_C1MR_CH4FM_Pos 10167 #define IPCC_MR_CH4FM_Msk IPCC_C1MR_CH4FM_Msk 10168 #define IPCC_MR_CH4FM IPCC_C1MR_CH4FM 10169 #define IPCC_MR_CH5FM_Pos IPCC_C1MR_CH5FM_Pos 10170 #define IPCC_MR_CH5FM_Msk IPCC_C1MR_CH5FM_Msk 10171 #define IPCC_MR_CH5FM IPCC_C1MR_CH5FM 10172 #define IPCC_MR_CH6FM_Pos IPCC_C1MR_CH6FM_Pos 10173 #define IPCC_MR_CH6FM_Msk IPCC_C1MR_CH6FM_Msk 10174 #define IPCC_MR_CH6FM IPCC_C1MR_CH6FM 10175 10176 /********************** Bit definition for IPCC_C1SCR register ***************/ 10177 #define IPCC_SCR_CH1C_Pos IPCC_C1SCR_CH1C_Pos 10178 #define IPCC_SCR_CH1C_Msk IPCC_C1SCR_CH1C_Msk 10179 #define IPCC_SCR_CH1C IPCC_C1SCR_CH1C 10180 #define IPCC_SCR_CH2C_Pos IPCC_C1SCR_CH2C_Pos 10181 #define IPCC_SCR_CH2C_Msk IPCC_C1SCR_CH2C_Msk 10182 #define IPCC_SCR_CH2C IPCC_C1SCR_CH2C 10183 #define IPCC_SCR_CH3C_Pos IPCC_C1SCR_CH3C_Pos 10184 #define IPCC_SCR_CH3C_Msk IPCC_C1SCR_CH3C_Msk 10185 #define IPCC_SCR_CH3C IPCC_C1SCR_CH3C 10186 #define IPCC_SCR_CH4C_Pos IPCC_C1SCR_CH4C_Pos 10187 #define IPCC_SCR_CH4C_Msk IPCC_C1SCR_CH4C_Msk 10188 #define IPCC_SCR_CH4C IPCC_C1SCR_CH4C 10189 #define IPCC_SCR_CH5C_Pos IPCC_C1SCR_CH5C_Pos 10190 #define IPCC_SCR_CH5C_Msk IPCC_C1SCR_CH5C_Msk 10191 #define IPCC_SCR_CH5C IPCC_C1SCR_CH5C 10192 #define IPCC_SCR_CH6C_Pos IPCC_C1SCR_CH6C_Pos 10193 #define IPCC_SCR_CH6C_Msk IPCC_C1SCR_CH6C_Msk 10194 #define IPCC_SCR_CH6C IPCC_C1SCR_CH6C 10195 10196 #define IPCC_SCR_CH1S_Pos IPCC_C1SCR_CH1S_Pos 10197 #define IPCC_SCR_CH1S_Msk IPCC_C1SCR_CH1S_Msk 10198 #define IPCC_SCR_CH1S IPCC_C1SCR_CH1S 10199 #define IPCC_SCR_CH2S_Pos IPCC_C1SCR_CH2S_Pos 10200 #define IPCC_SCR_CH2S_Msk IPCC_C1SCR_CH2S_Msk 10201 #define IPCC_SCR_CH2S IPCC_C1SCR_CH2S 10202 #define IPCC_SCR_CH3S_Pos IPCC_C1SCR_CH3S_Pos 10203 #define IPCC_SCR_CH3S_Msk IPCC_C1SCR_CH3S_Msk 10204 #define IPCC_SCR_CH3S IPCC_C1SCR_CH3S 10205 #define IPCC_SCR_CH4S_Pos IPCC_C1SCR_CH4S_Pos 10206 #define IPCC_SCR_CH4S_Msk IPCC_C1SCR_CH4S_Msk 10207 #define IPCC_SCR_CH4S IPCC_C1SCR_CH4S 10208 #define IPCC_SCR_CH5S_Pos IPCC_C1SCR_CH5S_Pos 10209 #define IPCC_SCR_CH5S_Msk IPCC_C1SCR_CH5S_Msk 10210 #define IPCC_SCR_CH5S IPCC_C1SCR_CH5S 10211 #define IPCC_SCR_CH6S_Pos IPCC_C1SCR_CH6S_Pos 10212 #define IPCC_SCR_CH6S_Msk IPCC_C1SCR_CH6S_Msk 10213 #define IPCC_SCR_CH6S IPCC_C1SCR_CH6S 10214 10215 /********************** Bit definition for IPCC_C1TOC2SR register ***************/ 10216 #define IPCC_SR_CH1F_Pos IPCC_C1TOC2SR_CH1F_Pos 10217 #define IPCC_SR_CH1F_Msk IPCC_C1TOC2SR_CH1F_Msk 10218 #define IPCC_SR_CH1F IPCC_C1TOC2SR_CH1F 10219 #define IPCC_SR_CH2F_Pos IPCC_C1TOC2SR_CH2F_Pos 10220 #define IPCC_SR_CH2F_Msk IPCC_C1TOC2SR_CH2F_Msk 10221 #define IPCC_SR_CH2F IPCC_C1TOC2SR_CH2F 10222 #define IPCC_SR_CH3F_Pos IPCC_C1TOC2SR_CH3F_Pos 10223 #define IPCC_SR_CH3F_Msk IPCC_C1TOC2SR_CH3F_Msk 10224 #define IPCC_SR_CH3F IPCC_C1TOC2SR_CH3F 10225 #define IPCC_SR_CH4F_Pos IPCC_C1TOC2SR_CH4F_Pos 10226 #define IPCC_SR_CH4F_Msk IPCC_C1TOC2SR_CH4F_Msk 10227 #define IPCC_SR_CH4F IPCC_C1TOC2SR_CH4F 10228 #define IPCC_SR_CH5F_Pos IPCC_C1TOC2SR_CH5F_Pos 10229 #define IPCC_SR_CH5F_Msk IPCC_C1TOC2SR_CH5F_Msk 10230 #define IPCC_SR_CH5F IPCC_C1TOC2SR_CH5F 10231 #define IPCC_SR_CH6F_Pos IPCC_C1TOC2SR_CH6F_Pos 10232 #define IPCC_SR_CH6F_Msk IPCC_C1TOC2SR_CH6F_Msk 10233 #define IPCC_SR_CH6F IPCC_C1TOC2SR_CH6F 10234 10235 /******************** Number of IPCC channels ******************************/ 10236 #define IPCC_CHANNEL_NUMBER 6U 10237 10238 /******************************************************************************/ 10239 /* */ 10240 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 10241 /* */ 10242 /******************************************************************************/ 10243 /****************** Bit definition for USART_CR1 register *******************/ 10244 #define USART_CR1_UE_Pos (0U) 10245 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */ 10246 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 10247 #define USART_CR1_UESM_Pos (1U) 10248 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */ 10249 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */ 10250 #define USART_CR1_RE_Pos (2U) 10251 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ 10252 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 10253 #define USART_CR1_TE_Pos (3U) 10254 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ 10255 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 10256 #define USART_CR1_IDLEIE_Pos (4U) 10257 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 10258 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 10259 #define USART_CR1_RXNEIE_Pos (5U) 10260 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ 10261 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ 10262 #define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos 10263 #define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk /*!< 0x00000020 */ 10264 #define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */ 10265 #define USART_CR1_TCIE_Pos (6U) 10266 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 10267 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 10268 #define USART_CR1_TXEIE_Pos (7U) 10269 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 10270 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */ 10271 #define USART_CR1_TXEIE_TXFNFIE_Pos (7U) 10272 #define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 10273 #define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE /*!< TXE and TX FIFO Not Full Interrupt Enable */ 10274 #define USART_CR1_PEIE_Pos (8U) 10275 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 10276 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 10277 #define USART_CR1_PS_Pos (9U) 10278 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ 10279 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 10280 #define USART_CR1_PCE_Pos (10U) 10281 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 10282 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 10283 #define USART_CR1_WAKE_Pos (11U) 10284 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 10285 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */ 10286 #define USART_CR1_M0_Pos (12U) 10287 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */ 10288 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */ 10289 #define USART_CR1_MME_Pos (13U) 10290 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */ 10291 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */ 10292 #define USART_CR1_CMIE_Pos (14U) 10293 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */ 10294 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */ 10295 #define USART_CR1_OVER8_Pos (15U) 10296 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 10297 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */ 10298 #define USART_CR1_DEDT_Pos (16U) 10299 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */ 10300 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ 10301 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */ 10302 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */ 10303 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */ 10304 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */ 10305 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */ 10306 #define USART_CR1_DEAT_Pos (21U) 10307 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */ 10308 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ 10309 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */ 10310 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */ 10311 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */ 10312 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */ 10313 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */ 10314 #define USART_CR1_RTOIE_Pos (26U) 10315 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */ 10316 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out Interrupt Enable */ 10317 #define USART_CR1_EOBIE_Pos (27U) 10318 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */ 10319 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block Interrupt Enable */ 10320 #define USART_CR1_M1_Pos (28U) 10321 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */ 10322 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */ 10323 #define USART_CR1_M (uint32_t)(USART_CR1_M1 | USART_CR1_M0) /*!< Word length */ 10324 #define USART_CR1_FIFOEN_Pos (29U) 10325 #define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */ 10326 #define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */ 10327 #define USART_CR1_TXFEIE_Pos (30U) 10328 #define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */ 10329 #define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TX FIFO Empty Interrupt Enable */ 10330 #define USART_CR1_RXFFIE_Pos (31U) 10331 #define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */ 10332 #define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RX FIFO Full Interrupt Enable */ 10333 10334 /****************** Bit definition for USART_CR2 register *******************/ 10335 #define USART_CR2_SLVEN_Pos (0U) 10336 #define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */ 10337 #define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */ 10338 #define USART_CR2_DIS_NSS_Pos (3U) 10339 #define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */ 10340 #define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Slave Select (NSS) pin management */ 10341 #define USART_CR2_ADDM7_Pos (4U) 10342 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */ 10343 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */ 10344 #define USART_CR2_LBDL_Pos (5U) 10345 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 10346 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ 10347 #define USART_CR2_LBDIE_Pos (6U) 10348 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 10349 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ 10350 #define USART_CR2_LBCL_Pos (8U) 10351 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 10352 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 10353 #define USART_CR2_CPHA_Pos (9U) 10354 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 10355 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 10356 #define USART_CR2_CPOL_Pos (10U) 10357 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 10358 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 10359 #define USART_CR2_CLKEN_Pos (11U) 10360 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 10361 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 10362 #define USART_CR2_STOP_Pos (12U) 10363 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 10364 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 10365 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 10366 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 10367 #define USART_CR2_LINEN_Pos (14U) 10368 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 10369 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ 10370 #define USART_CR2_SWAP_Pos (15U) 10371 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */ 10372 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */ 10373 #define USART_CR2_RXINV_Pos (16U) 10374 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */ 10375 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */ 10376 #define USART_CR2_TXINV_Pos (17U) 10377 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */ 10378 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */ 10379 #define USART_CR2_DATAINV_Pos (18U) 10380 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */ 10381 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */ 10382 #define USART_CR2_MSBFIRST_Pos (19U) 10383 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */ 10384 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */ 10385 #define USART_CR2_ABREN_Pos (20U) 10386 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */ 10387 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/ 10388 #define USART_CR2_ABRMODE_Pos (21U) 10389 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */ 10390 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ 10391 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */ 10392 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */ 10393 #define USART_CR2_RTOEN_Pos (23U) 10394 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */ 10395 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */ 10396 #define USART_CR2_ADD_Pos (24U) 10397 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */ 10398 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 10399 10400 /****************** Bit definition for USART_CR3 register *******************/ 10401 #define USART_CR3_EIE_Pos (0U) 10402 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 10403 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 10404 #define USART_CR3_IREN_Pos (1U) 10405 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 10406 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ 10407 #define USART_CR3_IRLP_Pos (2U) 10408 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 10409 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ 10410 #define USART_CR3_HDSEL_Pos (3U) 10411 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 10412 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 10413 #define USART_CR3_NACK_Pos (4U) 10414 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 10415 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */ 10416 #define USART_CR3_SCEN_Pos (5U) 10417 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 10418 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */ 10419 #define USART_CR3_DMAR_Pos (6U) 10420 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 10421 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 10422 #define USART_CR3_DMAT_Pos (7U) 10423 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 10424 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 10425 #define USART_CR3_RTSE_Pos (8U) 10426 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 10427 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 10428 #define USART_CR3_CTSE_Pos (9U) 10429 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 10430 #define USART_CR3_CTSE USART_CR3_CTSE_Msk 10431 #define USART_CR3_CTSIE_Pos (10U) 10432 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 10433 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 10434 #define USART_CR3_ONEBIT_Pos (11U) 10435 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 10436 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ 10437 #define USART_CR3_OVRDIS_Pos (12U) 10438 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */ 10439 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */ 10440 #define USART_CR3_DDRE_Pos (13U) 10441 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */ 10442 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */ 10443 #define USART_CR3_DEM_Pos (14U) 10444 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */ 10445 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */ 10446 #define USART_CR3_DEP_Pos (15U) 10447 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */ 10448 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */ 10449 #define USART_CR3_SCARCNT_Pos (17U) 10450 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */ 10451 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ 10452 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */ 10453 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */ 10454 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */ 10455 #define USART_CR3_WUS_Pos (20U) 10456 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */ 10457 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ 10458 #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */ 10459 #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */ 10460 #define USART_CR3_WUFIE_Pos (22U) 10461 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */ 10462 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */ 10463 #define USART_CR3_TXFTIE_Pos (23U) 10464 #define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */ 10465 #define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TX FIFO Threshold Interrupt Enable */ 10466 #define USART_CR3_TCBGTIE_Pos (24U) 10467 #define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */ 10468 #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */ 10469 #define USART_CR3_RXFTCFG_Pos (25U) 10470 #define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */ 10471 #define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RX FIFO Threshold Configuration */ 10472 #define USART_CR3_RXFTCFG_0 (0x1U << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */ 10473 #define USART_CR3_RXFTCFG_1 (0x2U << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */ 10474 #define USART_CR3_RXFTCFG_2 (0x4U << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */ 10475 #define USART_CR3_RXFTIE_Pos (28U) 10476 #define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */ 10477 #define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RX FIFO Threshold Interrupt Enable */ 10478 #define USART_CR3_TXFTCFG_Pos (29U) 10479 #define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */ 10480 #define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TX FIFO Threshold configuration */ 10481 #define USART_CR3_TXFTCFG_0 (0x1U << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */ 10482 #define USART_CR3_TXFTCFG_1 (0x2U << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */ 10483 #define USART_CR3_TXFTCFG_2 (0x4U << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */ 10484 10485 /****************** Bit definition for USART_BRR register *******************/ 10486 #define USART_BRR_BRR ((uint16_t)0xFFFF) /*!< USART Baud rate register [15:0] */ 10487 10488 /****************** Bit definition for USART_GTPR register ******************/ 10489 #define USART_GTPR_PSC_Pos (0U) 10490 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 10491 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 10492 #define USART_GTPR_GT_Pos (8U) 10493 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 10494 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */ 10495 10496 /******************* Bit definition for USART_RTOR register *****************/ 10497 #define USART_RTOR_RTO_Pos (0U) 10498 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */ 10499 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Timeout Value */ 10500 #define USART_RTOR_BLEN_Pos (24U) 10501 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */ 10502 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */ 10503 10504 /******************* Bit definition for USART_RQR register ******************/ 10505 #define USART_RQR_ABRRQ_Pos (0U) 10506 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */ 10507 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */ 10508 #define USART_RQR_SBKRQ_Pos (1U) 10509 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */ 10510 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */ 10511 #define USART_RQR_MMRQ_Pos (2U) 10512 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */ 10513 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */ 10514 #define USART_RQR_RXFRQ_Pos (3U) 10515 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */ 10516 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */ 10517 #define USART_RQR_TXFRQ_Pos (4U) 10518 #define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */ 10519 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit Data flush Request */ 10520 10521 /******************* Bit definition for USART_ISR register ******************/ 10522 #define USART_ISR_PE_Pos (0U) 10523 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */ 10524 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */ 10525 #define USART_ISR_FE_Pos (1U) 10526 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */ 10527 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */ 10528 #define USART_ISR_NE_Pos (2U) 10529 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */ 10530 #define USART_ISR_NE USART_ISR_NE_Msk /*!< START bit Noise Error detection Flag */ 10531 #define USART_ISR_ORE_Pos (3U) 10532 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */ 10533 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */ 10534 #define USART_ISR_IDLE_Pos (4U) 10535 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */ 10536 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */ 10537 #define USART_ISR_RXNE_Pos (5U) 10538 #define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */ 10539 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */ 10540 #define USART_ISR_RXNE_RXFNE_Pos USART_ISR_RXNE_Pos 10541 #define USART_ISR_RXNE_RXFNE_Msk USART_ISR_RXNE_Msk /*!< 0x00000020 */ 10542 #define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_Msk /*!< Read Data Register or RX FIFO Not Empty */ 10543 #define USART_ISR_TC_Pos (6U) 10544 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */ 10545 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */ 10546 #define USART_ISR_TXE_Pos (7U) 10547 #define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */ 10548 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */ 10549 #define USART_ISR_TXE_TXFNF_Pos USART_ISR_TXE_Pos 10550 #define USART_ISR_TXE_TXFNF_Msk USART_ISR_TXE_Msk /*!< 0x00000080 */ 10551 #define USART_ISR_TXE_TXFNF USART_ISR_TXE_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */ 10552 #define USART_ISR_LBDF_Pos (8U) 10553 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */ 10554 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */ 10555 #define USART_ISR_CTSIF_Pos (9U) 10556 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */ 10557 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt Flag */ 10558 #define USART_ISR_CTS_Pos (10U) 10559 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */ 10560 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS Flag */ 10561 #define USART_ISR_RTOF_Pos (11U) 10562 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */ 10563 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Timeout */ 10564 #define USART_ISR_EOBF_Pos (12U) 10565 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */ 10566 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */ 10567 #define USART_ISR_UDR_Pos (13U) 10568 #define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */ 10569 #define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI Slave Underrun error Flag */ 10570 #define USART_ISR_ABRE_Pos (14U) 10571 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */ 10572 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */ 10573 #define USART_ISR_ABRF_Pos (15U) 10574 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */ 10575 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */ 10576 #define USART_ISR_BUSY_Pos (16U) 10577 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */ 10578 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */ 10579 #define USART_ISR_CMF_Pos (17U) 10580 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */ 10581 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */ 10582 #define USART_ISR_SBKF_Pos (18U) 10583 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */ 10584 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */ 10585 #define USART_ISR_RWU_Pos (19U) 10586 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */ 10587 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */ 10588 #define USART_ISR_WUF_Pos (20U) 10589 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */ 10590 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */ 10591 #define USART_ISR_TEACK_Pos (21U) 10592 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */ 10593 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */ 10594 #define USART_ISR_REACK_Pos (22U) 10595 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */ 10596 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */ 10597 #define USART_ISR_TXFE_Pos (23U) 10598 #define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */ 10599 #define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TX FIFO Empty Flag */ 10600 #define USART_ISR_RXFF_Pos (24U) 10601 #define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */ 10602 #define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RX FIFO Full Flag */ 10603 #define USART_ISR_TCBGT_Pos (25U) 10604 #define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */ 10605 #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time completion */ 10606 #define USART_ISR_RXFT_Pos (26U) 10607 #define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */ 10608 #define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RX FIFO Threshold Flag */ 10609 #define USART_ISR_TXFT_Pos (27U) 10610 #define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */ 10611 #define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TX FIFO Threshold Flag */ 10612 10613 /******************* Bit definition for USART_ICR register ******************/ 10614 #define USART_ICR_PECF_Pos (0U) 10615 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */ 10616 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */ 10617 #define USART_ICR_FECF_Pos (1U) 10618 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */ 10619 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */ 10620 #define USART_ICR_NECF_Pos (2U) 10621 #define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */ 10622 #define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */ 10623 #define USART_ICR_ORECF_Pos (3U) 10624 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */ 10625 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */ 10626 #define USART_ICR_IDLECF_Pos (4U) 10627 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */ 10628 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */ 10629 #define USART_ICR_TXFECF_Pos (5U) 10630 #define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */ 10631 #define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TX FIFO Empty Clear Flag */ 10632 #define USART_ICR_TCCF_Pos (6U) 10633 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */ 10634 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */ 10635 #define USART_ICR_TCBGTCF_Pos (7U) 10636 #define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */ 10637 #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */ 10638 #define USART_ICR_LBDCF_Pos (8U) 10639 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */ 10640 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */ 10641 #define USART_ICR_CTSCF_Pos (9U) 10642 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */ 10643 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */ 10644 #define USART_ICR_RTOCF_Pos (11U) 10645 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */ 10646 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */ 10647 #define USART_ICR_EOBCF_Pos (12U) 10648 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */ 10649 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */ 10650 #define USART_ICR_UDRCF_Pos (13U) 10651 #define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */ 10652 #define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */ 10653 #define USART_ICR_CMCF_Pos (17U) 10654 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */ 10655 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */ 10656 #define USART_ICR_WUCF_Pos (20U) 10657 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */ 10658 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */ 10659 10660 /******************* Bit definition for USART_RDR register ******************/ 10661 #define USART_RDR_RDR_Pos (0U) 10662 #define USART_RDR_RDR_Msk (0x01FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */ 10663 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */ 10664 10665 /******************* Bit definition for USART_TDR register ******************/ 10666 #define USART_TDR_TDR_Pos (0U) 10667 #define USART_TDR_TDR_Msk (0x01FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */ 10668 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */ 10669 10670 /******************* Bit definition for USART_PRESC register ******************/ 10671 #define USART_PRESC_PRESCALER_Pos (0U) 10672 #define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */ 10673 #define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */ 10674 #define USART_PRESC_PRESCALER_0 (0x1U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */ 10675 #define USART_PRESC_PRESCALER_1 (0x2U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */ 10676 #define USART_PRESC_PRESCALER_2 (0x4U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */ 10677 #define USART_PRESC_PRESCALER_3 (0x8U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */ 10678 10679 /******************************************************************************/ 10680 /* */ 10681 /* VREFBUF */ 10682 /* */ 10683 /******************************************************************************/ 10684 /******************* Bit definition for VREFBUF_CSR register ****************/ 10685 #define VREFBUF_CSR_ENVR_Pos (0U) 10686 #define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ 10687 #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */ 10688 #define VREFBUF_CSR_HIZ_Pos (1U) 10689 #define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */ 10690 #define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */ 10691 #define VREFBUF_CSR_VRS_Pos (2U) 10692 #define VREFBUF_CSR_VRS_Msk (0x1UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000004 */ 10693 #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ 10694 #define VREFBUF_CSR_VRR_Pos (3U) 10695 #define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */ 10696 #define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */ 10697 10698 /******************* Bit definition for VREFBUF_CCR register ******************/ 10699 #define VREFBUF_CCR_TRIM_Pos (0U) 10700 #define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */ 10701 #define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */ 10702 10703 /******************************************************************************/ 10704 /* */ 10705 /* Window WATCHDOG */ 10706 /* */ 10707 /******************************************************************************/ 10708 /******************* Bit definition for WWDG_CR register ********************/ 10709 #define WWDG_CR_T_Pos (0U) 10710 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ 10711 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ 10712 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */ 10713 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */ 10714 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */ 10715 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */ 10716 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */ 10717 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */ 10718 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */ 10719 10720 #define WWDG_CR_WDGA_Pos (7U) 10721 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 10722 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */ 10723 10724 /******************* Bit definition for WWDG_CFR register *******************/ 10725 #define WWDG_CFR_W_Pos (0U) 10726 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 10727 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */ 10728 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 10729 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 10730 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 10731 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 10732 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 10733 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 10734 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 10735 10736 #define WWDG_CFR_WDGTB_Pos (11U) 10737 #define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */ 10738 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */ 10739 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */ 10740 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */ 10741 #define WWDG_CFR_WDGTB_2 (0x4U << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */ 10742 10743 #define WWDG_CFR_EWI_Pos (9U) 10744 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 10745 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */ 10746 10747 /******************* Bit definition for WWDG_SR register ********************/ 10748 #define WWDG_SR_EWIF_Pos (0U) 10749 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 10750 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */ 10751 10752 /******************************************************************************/ 10753 /* */ 10754 /* Debug MCU */ 10755 /* */ 10756 /******************************************************************************/ 10757 /******************** Bit definition for DBGMCU_IDCODE register *************/ 10758 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 10759 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 10760 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk 10761 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 10762 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 10763 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk 10764 10765 /******************** Bit definition for DBGMCU_CR register *****************/ 10766 #define DBGMCU_CR_DBG_SLEEP_Pos (0U) 10767 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ 10768 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk 10769 #define DBGMCU_CR_DBG_STOP_Pos (1U) 10770 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 10771 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk 10772 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 10773 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 10774 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk 10775 #define DBGMCU_CR_TRACE_IOEN_Pos (5U) 10776 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ 10777 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk 10778 #define DBGMCU_CR_TRGOEN_Pos (28U) 10779 #define DBGMCU_CR_TRGOEN_Msk (0x1UL << DBGMCU_CR_TRGOEN_Pos) /*!< 0x10000000 */ 10780 #define DBGMCU_CR_TRGOEN DBGMCU_CR_TRGOEN_Msk 10781 10782 /******************** Bit definition for DBGMCU_APB1FZR1 register ***********/ 10783 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) 10784 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ 10785 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk 10786 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U) 10787 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ 10788 #define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk 10789 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U) 10790 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ 10791 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk 10792 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U) 10793 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ 10794 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk 10795 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U) 10796 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ 10797 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk 10798 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U) 10799 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */ 10800 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk 10801 10802 /******************** Bit definition for DBGMCU_C2APB1FZR1 register ***********/ 10803 #define DBGMCU_C2APB1FZR1_DBG_TIM2_STOP_Pos (0U) 10804 #define DBGMCU_C2APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_C2APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ 10805 #define DBGMCU_C2APB1FZR1_DBG_TIM2_STOP DBGMCU_C2APB1FZR1_DBG_TIM2_STOP_Msk 10806 #define DBGMCU_C2APB1FZR1_DBG_RTC_STOP_Pos (10U) 10807 #define DBGMCU_C2APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_C2APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ 10808 #define DBGMCU_C2APB1FZR1_DBG_RTC_STOP DBGMCU_C2APB1FZR1_DBG_RTC_STOP_Msk 10809 #define DBGMCU_C2APB1FZR1_DBG_IWDG_STOP_Pos (12U) 10810 #define DBGMCU_C2APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_C2APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ 10811 #define DBGMCU_C2APB1FZR1_DBG_IWDG_STOP DBGMCU_C2APB1FZR1_DBG_IWDG_STOP_Msk 10812 #define DBGMCU_C2APB1FZR1_DBG_I2C1_STOP_Pos (21U) 10813 #define DBGMCU_C2APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_C2APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ 10814 #define DBGMCU_C2APB1FZR1_DBG_I2C1_STOP DBGMCU_C2APB1FZR1_DBG_I2C1_STOP_Msk 10815 #define DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP_Pos (31U) 10816 #define DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */ 10817 #define DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP_Msk 10818 10819 /******************** Bit definition for DBGMCU_APB1FZR2 register ***********/ 10820 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U) 10821 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */ 10822 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk 10823 10824 /******************** Bit definition for DBGMCU_C2APB1FZR2 register ***********/ 10825 #define DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP_Pos (5U) 10826 #define DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */ 10827 #define DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP_Msk 10828 10829 /******************** Bit definition for DBGMCU_APB2FZR register ************/ 10830 #define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) 10831 #define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos) /*!< 0x000000800 */ 10832 #define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk 10833 #define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U) 10834 #define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ 10835 #define DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk 10836 #define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos (18U) 10837 #define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ 10838 #define DBGMCU_APB2FZR_DBG_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk 10839 10840 /******************** Bit definition for DBGMCU_C2APB2FZR register ************/ 10841 #define DBGMCU_C2APB2FZR_DBG_TIM1_STOP_Pos (11U) 10842 #define DBGMCU_C2APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_C2APB2FZR_DBG_TIM1_STOP_Pos) /*!< 0x000000800 */ 10843 #define DBGMCU_C2APB2FZR_DBG_TIM1_STOP DBGMCU_C2APB2FZR_DBG_TIM1_STOP_Msk 10844 #define DBGMCU_C2APB2FZR_DBG_TIM16_STOP_Pos (17U) 10845 #define DBGMCU_C2APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_C2APB2FZR_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ 10846 #define DBGMCU_C2APB2FZR_DBG_TIM16_STOP DBGMCU_C2APB2FZR_DBG_TIM16_STOP_Msk 10847 #define DBGMCU_C2APB2FZR_DBG_TIM17_STOP_Pos (18U) 10848 #define DBGMCU_C2APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_C2APB2FZR_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ 10849 #define DBGMCU_C2APB2FZR_DBG_TIM17_STOP DBGMCU_C2APB2FZR_DBG_TIM17_STOP_Msk 10850 10851 /** @addtogroup Exported_macros 10852 * @{ 10853 */ 10854 10855 10856 /*********************** UART Instances : Asynchronous mode *******************/ 10857 #define IS_UART_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 10858 10859 /*********************** UART Instances : FIFO mode ***************************/ 10860 #define IS_UART_FIFO_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 10861 10862 /*********************** UART Instances : SPI Slave mode **********************/ 10863 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 10864 10865 /*********************** USART Instances : Synchronous mode *******************/ 10866 #define IS_USART_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 10867 10868 /*********************** USART Instances : Auto Baud Rate detection ***********/ 10869 10870 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 10871 10872 /*********************** UART Instances : Half-Duplex mode ********************/ 10873 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 10874 10875 /*********************** UART Instances : LIN mode ****************************/ 10876 #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 10877 10878 /*********************** UART Instances : Wake-up from Stop mode **************/ 10879 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 10880 10881 /*********************** UART Instances : Hardware Flow control ***************/ 10882 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 10883 10884 /*********************** UART Instances : Smard card mode *********************/ 10885 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 10886 10887 /*********************** UART Instances : Driver Enable ***********************/ 10888 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 10889 10890 /*********************** UART Instances : IRDA mode ***************************/ 10891 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1) 10892 10893 /******************** LPUART Instance *****************************************/ 10894 #define IS_LPUART_INSTANCE(INSTANCE) (0) 10895 10896 /******************************* ADC Instances ********************************/ 10897 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 10898 10899 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON) 10900 10901 /******************************* AES Instances ********************************/ 10902 #define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES2) 10903 10904 /******************************* CRC Instances ********************************/ 10905 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 10906 10907 /******************************** DMA Instances *******************************/ 10908 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 10909 ((INSTANCE) == DMA1_Channel2) || \ 10910 ((INSTANCE) == DMA1_Channel3) || \ 10911 ((INSTANCE) == DMA1_Channel4) || \ 10912 ((INSTANCE) == DMA1_Channel5) || \ 10913 ((INSTANCE) == DMA1_Channel6) || \ 10914 ((INSTANCE) == DMA1_Channel7)) 10915 10916 /******************************** DMAMUX Instances ****************************/ 10917 #define IS_DMAMUX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMAMUX1) 10918 10919 #define IS_DMAMUX_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \ 10920 ((INSTANCE) == DMAMUX1_RequestGenerator1) || \ 10921 ((INSTANCE) == DMAMUX1_RequestGenerator2) || \ 10922 ((INSTANCE) == DMAMUX1_RequestGenerator3)) 10923 10924 /******************************* GPIO Instances *******************************/ 10925 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 10926 ((INSTANCE) == GPIOB) || \ 10927 ((INSTANCE) == GPIOC) || \ 10928 ((INSTANCE) == GPIOE) || \ 10929 ((INSTANCE) == GPIOH)) 10930 10931 /******************************* GPIO AF Instances ****************************/ 10932 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 10933 10934 /**************************** GPIO Lock Instances *****************************/ 10935 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 10936 10937 /******************************** I2C Instances *******************************/ 10938 #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1) 10939 10940 /****************** I2C Instances : wakeup capability from stop modes *********/ 10941 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) 10942 10943 /******************************* SMBUS Instances ******************************/ 10944 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) 10945 10946 /******************************* IPCC Instances ********************************/ 10947 #define IS_IPCC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IPCC) 10948 10949 /******************************** HSEM Instances *******************************/ 10950 #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) 10951 10952 #define HSEM_CPU1_COREID (0x00000004UL)/* Semaphore Core ID */ 10953 #define HSEM_CPU2_COREID (0x00000008UL)/* Semaphore Core ID */ 10954 10955 #define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ 10956 #define HSEM_SEMID_MAX (31U) /* HSEM ID Max */ 10957 10958 #define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ 10959 #define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ 10960 10961 #define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ 10962 #define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ 10963 10964 /******************************** PKA Instances *******************************/ 10965 #define IS_PKA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PKA) 10966 10967 /******************************* RNG Instances ********************************/ 10968 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) 10969 10970 /****************************** RTC Instances *********************************/ 10971 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 10972 10973 /******************************** SPI Instances *******************************/ 10974 #define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1) 10975 10976 /****************** LPTIM Instances : All supported instances *****************/ 10977 #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \ 10978 ((INSTANCE) == LPTIM2)) 10979 10980 /****************** LPTIM Instances : Encoder mode ****************************/ 10981 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1) 10982 10983 /****************** TIM Instances : All supported instances *******************/ 10984 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 10985 ((INSTANCE) == TIM2) || \ 10986 ((INSTANCE) == TIM16) || \ 10987 ((INSTANCE) == TIM17)) 10988 10989 /****************************** IWDG Instances ********************************/ 10990 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 10991 10992 /****************************** WWDG Instances ********************************/ 10993 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 10994 10995 /****************** TIM Instances : supporting 32 bits counter ****************/ 10996 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2) 10997 10998 /****************** TIM Instances : supporting the break function *************/ 10999 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11000 ((INSTANCE) == TIM16) || \ 11001 ((INSTANCE) == TIM17)) 11002 11003 /************** TIM Instances : supporting Break source selection *************/ 11004 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11005 ((INSTANCE) == TIM16) || \ 11006 ((INSTANCE) == TIM17)) 11007 11008 /****************** TIM Instances : supporting 2 break inputs *****************/ 11009 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 11010 11011 /************* TIM Instances : at least 1 capture/compare channel *************/ 11012 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11013 ((INSTANCE) == TIM2) || \ 11014 ((INSTANCE) == TIM16) || \ 11015 ((INSTANCE) == TIM17)) 11016 11017 /************ TIM Instances : at least 2 capture/compare channels *************/ 11018 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11019 ((INSTANCE) == TIM2)) 11020 11021 /************ TIM Instances : at least 3 capture/compare channels *************/ 11022 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11023 ((INSTANCE) == TIM2)) 11024 11025 /************ TIM Instances : at least 4 capture/compare channels *************/ 11026 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11027 ((INSTANCE) == TIM2)) 11028 11029 /****************** TIM Instances : at least 5 capture/compare channels *******/ 11030 #define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 11031 11032 /****************** TIM Instances : at least 6 capture/compare channels *******/ 11033 #define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 11034 11035 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ 11036 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 11037 11038 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ 11039 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11040 ((INSTANCE) == TIM2) || \ 11041 ((INSTANCE) == TIM16) || \ 11042 ((INSTANCE) == TIM17)) 11043 11044 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ 11045 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11046 ((INSTANCE) == TIM2) || \ 11047 ((INSTANCE) == TIM16) || \ 11048 ((INSTANCE) == TIM17)) 11049 11050 /******************** TIM Instances : DMA burst feature ***********************/ 11051 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11052 ((INSTANCE) == TIM2) || \ 11053 ((INSTANCE) == TIM16) || \ 11054 ((INSTANCE) == TIM17)) 11055 11056 /******************* TIM Instances : Timer input selection ********************/ 11057 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11058 ((INSTANCE) == TIM2) || \ 11059 ((INSTANCE) == TIM16) || \ 11060 ((INSTANCE) == TIM17)) 11061 11062 /******************* TIM Instances : output(s) available **********************/ 11063 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 11064 ((((INSTANCE) == TIM1) && \ 11065 (((CHANNEL) == TIM_CHANNEL_1) || \ 11066 ((CHANNEL) == TIM_CHANNEL_2) || \ 11067 ((CHANNEL) == TIM_CHANNEL_3) || \ 11068 ((CHANNEL) == TIM_CHANNEL_4) || \ 11069 ((CHANNEL) == TIM_CHANNEL_5) || \ 11070 ((CHANNEL) == TIM_CHANNEL_6))) \ 11071 || \ 11072 (((INSTANCE) == TIM2) && \ 11073 (((CHANNEL) == TIM_CHANNEL_1) || \ 11074 ((CHANNEL) == TIM_CHANNEL_2) || \ 11075 ((CHANNEL) == TIM_CHANNEL_3) || \ 11076 ((CHANNEL) == TIM_CHANNEL_4))) \ 11077 || \ 11078 (((INSTANCE) == TIM16) && \ 11079 (((CHANNEL) == TIM_CHANNEL_1))) \ 11080 || \ 11081 (((INSTANCE) == TIM17) && \ 11082 (((CHANNEL) == TIM_CHANNEL_1)))) 11083 11084 /****************** TIM Instances : supporting complementary output(s) ********/ 11085 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ 11086 ((((INSTANCE) == TIM1) && \ 11087 (((CHANNEL) == TIM_CHANNEL_1) || \ 11088 ((CHANNEL) == TIM_CHANNEL_2) || \ 11089 ((CHANNEL) == TIM_CHANNEL_3))) \ 11090 || \ 11091 (((INSTANCE) == TIM17) && \ 11092 ((CHANNEL) == TIM_CHANNEL_1)) \ 11093 || \ 11094 (((INSTANCE) == TIM16) && \ 11095 ((CHANNEL) == TIM_CHANNEL_1))) 11096 11097 11098 /****************** TIM Instances : supporting clock division *****************/ 11099 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11100 ((INSTANCE) == TIM2) || \ 11101 ((INSTANCE) == TIM16) || \ 11102 ((INSTANCE) == TIM17)) 11103 11104 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ 11105 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11106 ((INSTANCE) == TIM2)) 11107 11108 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ 11109 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11110 ((INSTANCE) == TIM2)) 11111 11112 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ 11113 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11114 ((INSTANCE) == TIM2)) 11115 11116 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ 11117 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11118 ((INSTANCE) == TIM2)) 11119 11120 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/ 11121 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 11122 11123 /****************** TIM Instances : supporting commutation event generation ***/ 11124 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 11125 11126 /****************** TIM Instances : supporting counting mode selection ********/ 11127 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11128 ((INSTANCE) == TIM2)) 11129 11130 /****************** TIM Instances : supporting encoder interface **************/ 11131 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11132 ((INSTANCE) == TIM2)) 11133 11134 /****************** TIM Instances : supporting Hall sensor interface **********/ 11135 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11136 ((INSTANCE) == TIM2)) 11137 11138 /**************** TIM Instances : external trigger input available ************/ 11139 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11140 ((INSTANCE) == TIM2)) 11141 11142 /************* TIM Instances : supporting ETR source selection ***************/ 11143 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11144 ((INSTANCE) == TIM2)) 11145 11146 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ 11147 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11148 ((INSTANCE) == TIM2)) 11149 11150 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ 11151 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11152 ((INSTANCE) == TIM2)) 11153 11154 /****************** TIM Instances : supporting OCxREF clear *******************/ 11155 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11156 ((INSTANCE) == TIM2)) 11157 11158 /****************** TIM Instances : remapping capability **********************/ 11159 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11160 ((INSTANCE) == TIM2) || \ 11161 ((INSTANCE) == TIM16) || \ 11162 ((INSTANCE) == TIM17)) 11163 11164 /****************** TIM Instances : supporting repetition counter *************/ 11165 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11166 ((INSTANCE) == TIM16) || \ 11167 ((INSTANCE) == TIM17)) 11168 11169 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ 11170 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 11171 11172 /******************* TIM Instances : Timer input XOR function *****************/ 11173 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 11174 ((INSTANCE) == TIM2)) 11175 11176 /************ TIM Instances : Advanced timers ********************************/ 11177 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)) 11178 11179 /** 11180 * @} 11181 */ 11182 11183 /** 11184 * @} 11185 */ 11186 11187 /** 11188 * @} 11189 */ 11190 11191 #ifdef __cplusplus 11192 } 11193 #endif /* __cplusplus */ 11194 11195 #endif /* __STM32WB50xx_H */ 11196 11197 /** 11198 * @} 11199 */ 11200 11201 /** 11202 * @} 11203 */ 11204 11205 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 11206