1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 @verbatim
33 ==============================================================================
34 ##### TIMER Generic features #####
35 ==============================================================================
36 [..] The Timer features include:
37 (#) 16-bit up, down, up/down auto-reload counter.
38 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
39 counter clock frequency either by any factor between 1 and 65536.
40 (#) Up to 4 independent channels for:
41 (++) Input Capture
42 (++) Output Compare
43 (++) PWM generation (Edge and Center-aligned Mode)
44 (++) One-pulse mode output
45 (#) Synchronization circuit to control the timer with external signals and to interconnect
46 several timers together.
47 (#) Supports incremental encoder for positioning purposes
48
49 ##### How to use this driver #####
50 ==============================================================================
51 [..]
52 (#) Initialize the TIM low level resources by implementing the following functions
53 depending on the selected feature:
54 (++) Time Base : HAL_TIM_Base_MspInit()
55 (++) Input Capture : HAL_TIM_IC_MspInit()
56 (++) Output Compare : HAL_TIM_OC_MspInit()
57 (++) PWM generation : HAL_TIM_PWM_MspInit()
58 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
59 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
60
61 (#) Initialize the TIM low level resources :
62 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
63 (##) TIM pins configuration
64 (+++) Enable the clock for the TIM GPIOs using the following function:
65 __HAL_RCC_GPIOx_CLK_ENABLE();
66 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
67
68 (#) The external Clock can be configured, if needed (the default clock is the
69 internal clock from the APBx), using the following function:
70 HAL_TIM_ConfigClockSource, the clock configuration should be done before
71 any start function.
72
73 (#) Configure the TIM in the desired functioning mode using one of the
74 Initialization function of this driver:
75 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
76 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
77 Output Compare signal.
78 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
79 PWM signal.
80 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
81 external signal.
82 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
83 in One Pulse Mode.
84 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
85
86 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
87 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
88 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
89 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
90 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
91 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
92 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
93
94 (#) The DMA Burst is managed with the two following functions:
95 HAL_TIM_DMABurst_WriteStart()
96 HAL_TIM_DMABurst_ReadStart()
97
98 *** Callback registration ***
99 =============================================
100
101 [..]
102 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
103 allows the user to configure dynamically the driver callbacks.
104
105 [..]
106 Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
107 @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
108 the Callback ID and a pointer to the user callback function.
109
110 [..]
111 Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
112 weak function.
113 @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
114 and the Callback ID.
115
116 [..]
117 These functions allow to register/unregister following callbacks:
118 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
119 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
120 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
121 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
122 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
123 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
124 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
125 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
126 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
127 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
128 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
129 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
130 (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
131 (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
132 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
133 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
134 (+) TriggerCallback : TIM Trigger Callback.
135 (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
136 (+) IC_CaptureCallback : TIM Input Capture Callback.
137 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
138 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
139 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
140 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
141 (+) ErrorCallback : TIM Error Callback.
142 (+) CommutationCallback : TIM Commutation Callback.
143 (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
144 (+) BreakCallback : TIM Break Callback.
145 (+) Break2Callback : TIM Break2 Callback.
146
147 [..]
148 By default, after the Init and when the state is HAL_TIM_STATE_RESET
149 all interrupt callbacks are set to the corresponding weak functions:
150 examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
151
152 [..]
153 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
154 functionalities in the Init / DeInit only when these callbacks are null
155 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
156 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
157
158 [..]
159 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
160 Exception done MspInit / MspDeInit that can be registered / unregistered
161 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
162 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
163 In that case first register the MspInit/MspDeInit user callbacks
164 using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
165
166 [..]
167 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
168 not defined, the callback registration feature is not available and all callbacks
169 are set to the corresponding weak functions.
170
171 @endverbatim
172 ******************************************************************************
173 * @attention
174 *
175 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
176 * All rights reserved.</center></h2>
177 *
178 * This software component is licensed by ST under BSD 3-Clause license,
179 * the "License"; You may not use this file except in compliance with the
180 * License. You may obtain a copy of the License at:
181 * opensource.org/licenses/BSD-3-Clause
182 *
183 ******************************************************************************
184 */
185
186 /* Includes ------------------------------------------------------------------*/
187 #include "stm32l4xx_hal.h"
188
189 /** @addtogroup STM32L4xx_HAL_Driver
190 * @{
191 */
192
193 /** @defgroup TIM TIM
194 * @brief TIM HAL module driver
195 * @{
196 */
197
198 #ifdef HAL_TIM_MODULE_ENABLED
199
200 /* Private typedef -----------------------------------------------------------*/
201 /* Private define ------------------------------------------------------------*/
202 /* Private macros ------------------------------------------------------------*/
203 /* Private variables ---------------------------------------------------------*/
204 /* Private function prototypes -----------------------------------------------*/
205 /** @addtogroup TIM_Private_Functions
206 * @{
207 */
208 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
209 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
210 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
211 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
212 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
213 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
214 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
215 uint32_t TIM_ICFilter);
216 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
217 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
218 uint32_t TIM_ICFilter);
219 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
220 uint32_t TIM_ICFilter);
221 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
222 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
223 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
224 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
225 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
226 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
227 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
228 TIM_SlaveConfigTypeDef *sSlaveConfig);
229 /**
230 * @}
231 */
232 /* Exported functions --------------------------------------------------------*/
233
234 /** @defgroup TIM_Exported_Functions TIM Exported Functions
235 * @{
236 */
237
238 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
239 * @brief Time Base functions
240 *
241 @verbatim
242 ==============================================================================
243 ##### Time Base functions #####
244 ==============================================================================
245 [..]
246 This section provides functions allowing to:
247 (+) Initialize and configure the TIM base.
248 (+) De-initialize the TIM base.
249 (+) Start the Time Base.
250 (+) Stop the Time Base.
251 (+) Start the Time Base and enable interrupt.
252 (+) Stop the Time Base and disable interrupt.
253 (+) Start the Time Base and enable DMA transfer.
254 (+) Stop the Time Base and disable DMA transfer.
255
256 @endverbatim
257 * @{
258 */
259 /**
260 * @brief Initializes the TIM Time base Unit according to the specified
261 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
262 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
263 * requires a timer reset to avoid unexpected direction
264 * due to DIR bit readonly in center aligned mode.
265 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
266 * @param htim TIM Base handle
267 * @retval HAL status
268 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)269 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
270 {
271 /* Check the TIM handle allocation */
272 if (htim == NULL)
273 {
274 return HAL_ERROR;
275 }
276
277 /* Check the parameters */
278 assert_param(IS_TIM_INSTANCE(htim->Instance));
279 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
280 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
281 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
282
283 if (htim->State == HAL_TIM_STATE_RESET)
284 {
285 /* Allocate lock resource and initialize it */
286 htim->Lock = HAL_UNLOCKED;
287
288 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
289 /* Reset interrupt callbacks to legacy weak callbacks */
290 TIM_ResetCallback(htim);
291
292 if (htim->Base_MspInitCallback == NULL)
293 {
294 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
295 }
296 /* Init the low level hardware : GPIO, CLOCK, NVIC */
297 htim->Base_MspInitCallback(htim);
298 #else
299 /* Init the low level hardware : GPIO, CLOCK, NVIC */
300 HAL_TIM_Base_MspInit(htim);
301 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
302 }
303
304 /* Set the TIM state */
305 htim->State = HAL_TIM_STATE_BUSY;
306
307 /* Set the Time Base configuration */
308 TIM_Base_SetConfig(htim->Instance, &htim->Init);
309
310 /* Initialize the DMA burst operation state */
311 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
312
313 /* Initialize the TIM channels state */
314 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
315 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
316
317 /* Initialize the TIM state*/
318 htim->State = HAL_TIM_STATE_READY;
319
320 return HAL_OK;
321 }
322
323 /**
324 * @brief DeInitializes the TIM Base peripheral
325 * @param htim TIM Base handle
326 * @retval HAL status
327 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)328 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
329 {
330 /* Check the parameters */
331 assert_param(IS_TIM_INSTANCE(htim->Instance));
332
333 htim->State = HAL_TIM_STATE_BUSY;
334
335 /* Disable the TIM Peripheral Clock */
336 __HAL_TIM_DISABLE(htim);
337
338 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
339 if (htim->Base_MspDeInitCallback == NULL)
340 {
341 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
342 }
343 /* DeInit the low level hardware */
344 htim->Base_MspDeInitCallback(htim);
345 #else
346 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
347 HAL_TIM_Base_MspDeInit(htim);
348 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
349
350 /* Change the DMA burst operation state */
351 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
352
353 /* Change the TIM channels state */
354 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
355 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
356
357 /* Change TIM state */
358 htim->State = HAL_TIM_STATE_RESET;
359
360 /* Release Lock */
361 __HAL_UNLOCK(htim);
362
363 return HAL_OK;
364 }
365
366 /**
367 * @brief Initializes the TIM Base MSP.
368 * @param htim TIM Base handle
369 * @retval None
370 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)371 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
372 {
373 /* Prevent unused argument(s) compilation warning */
374 UNUSED(htim);
375
376 /* NOTE : This function should not be modified, when the callback is needed,
377 the HAL_TIM_Base_MspInit could be implemented in the user file
378 */
379 }
380
381 /**
382 * @brief DeInitializes TIM Base MSP.
383 * @param htim TIM Base handle
384 * @retval None
385 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)386 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
387 {
388 /* Prevent unused argument(s) compilation warning */
389 UNUSED(htim);
390
391 /* NOTE : This function should not be modified, when the callback is needed,
392 the HAL_TIM_Base_MspDeInit could be implemented in the user file
393 */
394 }
395
396
397 /**
398 * @brief Starts the TIM Base generation.
399 * @param htim TIM Base handle
400 * @retval HAL status
401 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)402 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
403 {
404 uint32_t tmpsmcr;
405
406 /* Check the parameters */
407 assert_param(IS_TIM_INSTANCE(htim->Instance));
408
409 /* Check the TIM state */
410 if (htim->State != HAL_TIM_STATE_READY)
411 {
412 return HAL_ERROR;
413 }
414
415 /* Set the TIM state */
416 htim->State = HAL_TIM_STATE_BUSY;
417
418 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
419 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
420 {
421 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
422 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
423 {
424 __HAL_TIM_ENABLE(htim);
425 }
426 }
427 else
428 {
429 __HAL_TIM_ENABLE(htim);
430 }
431
432 /* Return function status */
433 return HAL_OK;
434 }
435
436 /**
437 * @brief Stops the TIM Base generation.
438 * @param htim TIM Base handle
439 * @retval HAL status
440 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)441 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
442 {
443 /* Check the parameters */
444 assert_param(IS_TIM_INSTANCE(htim->Instance));
445
446 /* Disable the Peripheral */
447 __HAL_TIM_DISABLE(htim);
448
449 /* Set the TIM state */
450 htim->State = HAL_TIM_STATE_READY;
451
452 /* Return function status */
453 return HAL_OK;
454 }
455
456 /**
457 * @brief Starts the TIM Base generation in interrupt mode.
458 * @param htim TIM Base handle
459 * @retval HAL status
460 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)461 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
462 {
463 uint32_t tmpsmcr;
464
465 /* Check the parameters */
466 assert_param(IS_TIM_INSTANCE(htim->Instance));
467
468 /* Check the TIM state */
469 if (htim->State != HAL_TIM_STATE_READY)
470 {
471 return HAL_ERROR;
472 }
473
474 /* Set the TIM state */
475 htim->State = HAL_TIM_STATE_BUSY;
476
477 /* Enable the TIM Update interrupt */
478 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
479
480 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
481 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
482 {
483 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
484 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
485 {
486 __HAL_TIM_ENABLE(htim);
487 }
488 }
489 else
490 {
491 __HAL_TIM_ENABLE(htim);
492 }
493
494 /* Return function status */
495 return HAL_OK;
496 }
497
498 /**
499 * @brief Stops the TIM Base generation in interrupt mode.
500 * @param htim TIM Base handle
501 * @retval HAL status
502 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)503 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
504 {
505 /* Check the parameters */
506 assert_param(IS_TIM_INSTANCE(htim->Instance));
507
508 /* Disable the TIM Update interrupt */
509 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
510
511 /* Disable the Peripheral */
512 __HAL_TIM_DISABLE(htim);
513
514 /* Set the TIM state */
515 htim->State = HAL_TIM_STATE_READY;
516
517 /* Return function status */
518 return HAL_OK;
519 }
520
521 /**
522 * @brief Starts the TIM Base generation in DMA mode.
523 * @param htim TIM Base handle
524 * @param pData The source Buffer address.
525 * @param Length The length of data to be transferred from memory to peripheral.
526 * @retval HAL status
527 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,uint32_t * pData,uint16_t Length)528 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
529 {
530 uint32_t tmpsmcr;
531
532 /* Check the parameters */
533 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
534
535 /* Set the TIM state */
536 if (htim->State == HAL_TIM_STATE_BUSY)
537 {
538 return HAL_BUSY;
539 }
540 else if (htim->State == HAL_TIM_STATE_READY)
541 {
542 if ((pData == NULL) && (Length > 0U))
543 {
544 return HAL_ERROR;
545 }
546 else
547 {
548 htim->State = HAL_TIM_STATE_BUSY;
549 }
550 }
551 else
552 {
553 return HAL_ERROR;
554 }
555
556 /* Set the DMA Period elapsed callbacks */
557 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
558 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
559
560 /* Set the DMA error callback */
561 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
562
563 /* Enable the DMA channel */
564 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
565 {
566 return HAL_ERROR;
567 }
568
569 /* Enable the TIM Update DMA request */
570 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
571
572 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
573 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
574 {
575 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
576 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
577 {
578 __HAL_TIM_ENABLE(htim);
579 }
580 }
581 else
582 {
583 __HAL_TIM_ENABLE(htim);
584 }
585
586 /* Return function status */
587 return HAL_OK;
588 }
589
590 /**
591 * @brief Stops the TIM Base generation in DMA mode.
592 * @param htim TIM Base handle
593 * @retval HAL status
594 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)595 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
596 {
597 /* Check the parameters */
598 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
599
600 /* Disable the TIM Update DMA request */
601 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
602
603 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
604
605 /* Disable the Peripheral */
606 __HAL_TIM_DISABLE(htim);
607
608 /* Set the TIM state */
609 htim->State = HAL_TIM_STATE_READY;
610
611 /* Return function status */
612 return HAL_OK;
613 }
614
615 /**
616 * @}
617 */
618
619 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
620 * @brief TIM Output Compare functions
621 *
622 @verbatim
623 ==============================================================================
624 ##### TIM Output Compare functions #####
625 ==============================================================================
626 [..]
627 This section provides functions allowing to:
628 (+) Initialize and configure the TIM Output Compare.
629 (+) De-initialize the TIM Output Compare.
630 (+) Start the TIM Output Compare.
631 (+) Stop the TIM Output Compare.
632 (+) Start the TIM Output Compare and enable interrupt.
633 (+) Stop the TIM Output Compare and disable interrupt.
634 (+) Start the TIM Output Compare and enable DMA transfer.
635 (+) Stop the TIM Output Compare and disable DMA transfer.
636
637 @endverbatim
638 * @{
639 */
640 /**
641 * @brief Initializes the TIM Output Compare according to the specified
642 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
643 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
644 * requires a timer reset to avoid unexpected direction
645 * due to DIR bit readonly in center aligned mode.
646 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
647 * @param htim TIM Output Compare handle
648 * @retval HAL status
649 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)650 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
651 {
652 /* Check the TIM handle allocation */
653 if (htim == NULL)
654 {
655 return HAL_ERROR;
656 }
657
658 /* Check the parameters */
659 assert_param(IS_TIM_INSTANCE(htim->Instance));
660 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
661 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
662 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
663
664 if (htim->State == HAL_TIM_STATE_RESET)
665 {
666 /* Allocate lock resource and initialize it */
667 htim->Lock = HAL_UNLOCKED;
668
669 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
670 /* Reset interrupt callbacks to legacy weak callbacks */
671 TIM_ResetCallback(htim);
672
673 if (htim->OC_MspInitCallback == NULL)
674 {
675 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
676 }
677 /* Init the low level hardware : GPIO, CLOCK, NVIC */
678 htim->OC_MspInitCallback(htim);
679 #else
680 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
681 HAL_TIM_OC_MspInit(htim);
682 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
683 }
684
685 /* Set the TIM state */
686 htim->State = HAL_TIM_STATE_BUSY;
687
688 /* Init the base time for the Output Compare */
689 TIM_Base_SetConfig(htim->Instance, &htim->Init);
690
691 /* Initialize the DMA burst operation state */
692 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
693
694 /* Initialize the TIM channels state */
695 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
696 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
697
698 /* Initialize the TIM state*/
699 htim->State = HAL_TIM_STATE_READY;
700
701 return HAL_OK;
702 }
703
704 /**
705 * @brief DeInitializes the TIM peripheral
706 * @param htim TIM Output Compare handle
707 * @retval HAL status
708 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)709 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
710 {
711 /* Check the parameters */
712 assert_param(IS_TIM_INSTANCE(htim->Instance));
713
714 htim->State = HAL_TIM_STATE_BUSY;
715
716 /* Disable the TIM Peripheral Clock */
717 __HAL_TIM_DISABLE(htim);
718
719 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
720 if (htim->OC_MspDeInitCallback == NULL)
721 {
722 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
723 }
724 /* DeInit the low level hardware */
725 htim->OC_MspDeInitCallback(htim);
726 #else
727 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
728 HAL_TIM_OC_MspDeInit(htim);
729 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
730
731 /* Change the DMA burst operation state */
732 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
733
734 /* Change the TIM channels state */
735 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
736 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
737
738 /* Change TIM state */
739 htim->State = HAL_TIM_STATE_RESET;
740
741 /* Release Lock */
742 __HAL_UNLOCK(htim);
743
744 return HAL_OK;
745 }
746
747 /**
748 * @brief Initializes the TIM Output Compare MSP.
749 * @param htim TIM Output Compare handle
750 * @retval None
751 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)752 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
753 {
754 /* Prevent unused argument(s) compilation warning */
755 UNUSED(htim);
756
757 /* NOTE : This function should not be modified, when the callback is needed,
758 the HAL_TIM_OC_MspInit could be implemented in the user file
759 */
760 }
761
762 /**
763 * @brief DeInitializes TIM Output Compare MSP.
764 * @param htim TIM Output Compare handle
765 * @retval None
766 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)767 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
768 {
769 /* Prevent unused argument(s) compilation warning */
770 UNUSED(htim);
771
772 /* NOTE : This function should not be modified, when the callback is needed,
773 the HAL_TIM_OC_MspDeInit could be implemented in the user file
774 */
775 }
776
777 /**
778 * @brief Starts the TIM Output Compare signal generation.
779 * @param htim TIM Output Compare handle
780 * @param Channel TIM Channel to be enabled
781 * This parameter can be one of the following values:
782 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
783 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
784 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
785 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
786 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
787 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
788 * @retval HAL status
789 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)790 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
791 {
792 uint32_t tmpsmcr;
793
794 /* Check the parameters */
795 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
796
797 /* Check the TIM channel state */
798 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
799 {
800 return HAL_ERROR;
801 }
802
803 /* Set the TIM channel state */
804 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
805
806 /* Enable the Output compare channel */
807 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
808
809 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
810 {
811 /* Enable the main output */
812 __HAL_TIM_MOE_ENABLE(htim);
813 }
814
815 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
816 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
817 {
818 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
819 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
820 {
821 __HAL_TIM_ENABLE(htim);
822 }
823 }
824 else
825 {
826 __HAL_TIM_ENABLE(htim);
827 }
828
829 /* Return function status */
830 return HAL_OK;
831 }
832
833 /**
834 * @brief Stops the TIM Output Compare signal generation.
835 * @param htim TIM Output Compare handle
836 * @param Channel TIM Channel to be disabled
837 * This parameter can be one of the following values:
838 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
839 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
840 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
841 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
842 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
843 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
844 * @retval HAL status
845 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)846 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
847 {
848 /* Check the parameters */
849 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
850
851 /* Disable the Output compare channel */
852 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
853
854 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
855 {
856 /* Disable the Main Output */
857 __HAL_TIM_MOE_DISABLE(htim);
858 }
859
860 /* Disable the Peripheral */
861 __HAL_TIM_DISABLE(htim);
862
863 /* Set the TIM channel state */
864 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
865
866 /* Return function status */
867 return HAL_OK;
868 }
869
870 /**
871 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
872 * @param htim TIM Output Compare handle
873 * @param Channel TIM Channel to be enabled
874 * This parameter can be one of the following values:
875 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
876 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
877 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
878 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
879 * @retval HAL status
880 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)881 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
882 {
883 uint32_t tmpsmcr;
884
885 /* Check the parameters */
886 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
887
888 /* Check the TIM channel state */
889 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
890 {
891 return HAL_ERROR;
892 }
893
894 /* Set the TIM channel state */
895 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
896
897 switch (Channel)
898 {
899 case TIM_CHANNEL_1:
900 {
901 /* Enable the TIM Capture/Compare 1 interrupt */
902 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
903 break;
904 }
905
906 case TIM_CHANNEL_2:
907 {
908 /* Enable the TIM Capture/Compare 2 interrupt */
909 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
910 break;
911 }
912
913 case TIM_CHANNEL_3:
914 {
915 /* Enable the TIM Capture/Compare 3 interrupt */
916 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
917 break;
918 }
919
920 case TIM_CHANNEL_4:
921 {
922 /* Enable the TIM Capture/Compare 4 interrupt */
923 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
924 break;
925 }
926
927 default:
928 break;
929 }
930
931 /* Enable the Output compare channel */
932 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
933
934 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
935 {
936 /* Enable the main output */
937 __HAL_TIM_MOE_ENABLE(htim);
938 }
939
940 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
941 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
942 {
943 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
944 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
945 {
946 __HAL_TIM_ENABLE(htim);
947 }
948 }
949 else
950 {
951 __HAL_TIM_ENABLE(htim);
952 }
953
954 /* Return function status */
955 return HAL_OK;
956 }
957
958 /**
959 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
960 * @param htim TIM Output Compare handle
961 * @param Channel TIM Channel to be disabled
962 * This parameter can be one of the following values:
963 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
964 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
965 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
966 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
967 * @retval HAL status
968 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)969 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
970 {
971 /* Check the parameters */
972 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
973
974 switch (Channel)
975 {
976 case TIM_CHANNEL_1:
977 {
978 /* Disable the TIM Capture/Compare 1 interrupt */
979 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
980 break;
981 }
982
983 case TIM_CHANNEL_2:
984 {
985 /* Disable the TIM Capture/Compare 2 interrupt */
986 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
987 break;
988 }
989
990 case TIM_CHANNEL_3:
991 {
992 /* Disable the TIM Capture/Compare 3 interrupt */
993 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
994 break;
995 }
996
997 case TIM_CHANNEL_4:
998 {
999 /* Disable the TIM Capture/Compare 4 interrupt */
1000 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1001 break;
1002 }
1003
1004 default:
1005 break;
1006 }
1007
1008 /* Disable the Output compare channel */
1009 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1010
1011 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1012 {
1013 /* Disable the Main Output */
1014 __HAL_TIM_MOE_DISABLE(htim);
1015 }
1016
1017 /* Disable the Peripheral */
1018 __HAL_TIM_DISABLE(htim);
1019
1020 /* Set the TIM channel state */
1021 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1022
1023 /* Return function status */
1024 return HAL_OK;
1025 }
1026
1027 /**
1028 * @brief Starts the TIM Output Compare signal generation in DMA mode.
1029 * @param htim TIM Output Compare handle
1030 * @param Channel TIM Channel to be enabled
1031 * This parameter can be one of the following values:
1032 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1033 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1034 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1035 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1036 * @param pData The source Buffer address.
1037 * @param Length The length of data to be transferred from memory to TIM peripheral
1038 * @retval HAL status
1039 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)1040 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1041 {
1042 uint32_t tmpsmcr;
1043
1044 /* Check the parameters */
1045 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1046
1047 /* Set the TIM channel state */
1048 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1049 {
1050 return HAL_BUSY;
1051 }
1052 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1053 {
1054 if ((pData == NULL) && (Length > 0U))
1055 {
1056 return HAL_ERROR;
1057 }
1058 else
1059 {
1060 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1061 }
1062 }
1063 else
1064 {
1065 return HAL_ERROR;
1066 }
1067
1068 switch (Channel)
1069 {
1070 case TIM_CHANNEL_1:
1071 {
1072 /* Set the DMA compare callbacks */
1073 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1074 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1075
1076 /* Set the DMA error callback */
1077 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1078
1079 /* Enable the DMA channel */
1080 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
1081 {
1082 return HAL_ERROR;
1083 }
1084
1085 /* Enable the TIM Capture/Compare 1 DMA request */
1086 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1087 break;
1088 }
1089
1090 case TIM_CHANNEL_2:
1091 {
1092 /* Set the DMA compare callbacks */
1093 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1094 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1095
1096 /* Set the DMA error callback */
1097 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1098
1099 /* Enable the DMA channel */
1100 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
1101 {
1102 return HAL_ERROR;
1103 }
1104
1105 /* Enable the TIM Capture/Compare 2 DMA request */
1106 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1107 break;
1108 }
1109
1110 case TIM_CHANNEL_3:
1111 {
1112 /* Set the DMA compare callbacks */
1113 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1114 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1115
1116 /* Set the DMA error callback */
1117 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1118
1119 /* Enable the DMA channel */
1120 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
1121 {
1122 return HAL_ERROR;
1123 }
1124 /* Enable the TIM Capture/Compare 3 DMA request */
1125 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1126 break;
1127 }
1128
1129 case TIM_CHANNEL_4:
1130 {
1131 /* Set the DMA compare callbacks */
1132 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1133 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1134
1135 /* Set the DMA error callback */
1136 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1137
1138 /* Enable the DMA channel */
1139 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
1140 {
1141 return HAL_ERROR;
1142 }
1143 /* Enable the TIM Capture/Compare 4 DMA request */
1144 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1145 break;
1146 }
1147
1148 default:
1149 break;
1150 }
1151
1152 /* Enable the Output compare channel */
1153 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1154
1155 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1156 {
1157 /* Enable the main output */
1158 __HAL_TIM_MOE_ENABLE(htim);
1159 }
1160
1161 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1162 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1163 {
1164 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1165 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1166 {
1167 __HAL_TIM_ENABLE(htim);
1168 }
1169 }
1170 else
1171 {
1172 __HAL_TIM_ENABLE(htim);
1173 }
1174
1175 /* Return function status */
1176 return HAL_OK;
1177 }
1178
1179 /**
1180 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1181 * @param htim TIM Output Compare handle
1182 * @param Channel TIM Channel to be disabled
1183 * This parameter can be one of the following values:
1184 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1185 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1186 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1187 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1188 * @retval HAL status
1189 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1190 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1191 {
1192 /* Check the parameters */
1193 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1194
1195 switch (Channel)
1196 {
1197 case TIM_CHANNEL_1:
1198 {
1199 /* Disable the TIM Capture/Compare 1 DMA request */
1200 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1201 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1202 break;
1203 }
1204
1205 case TIM_CHANNEL_2:
1206 {
1207 /* Disable the TIM Capture/Compare 2 DMA request */
1208 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1209 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1210 break;
1211 }
1212
1213 case TIM_CHANNEL_3:
1214 {
1215 /* Disable the TIM Capture/Compare 3 DMA request */
1216 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1217 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1218 break;
1219 }
1220
1221 case TIM_CHANNEL_4:
1222 {
1223 /* Disable the TIM Capture/Compare 4 interrupt */
1224 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1225 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1226 break;
1227 }
1228
1229 default:
1230 break;
1231 }
1232
1233 /* Disable the Output compare channel */
1234 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1235
1236 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1237 {
1238 /* Disable the Main Output */
1239 __HAL_TIM_MOE_DISABLE(htim);
1240 }
1241
1242 /* Disable the Peripheral */
1243 __HAL_TIM_DISABLE(htim);
1244
1245 /* Set the TIM channel state */
1246 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1247
1248 /* Return function status */
1249 return HAL_OK;
1250 }
1251
1252 /**
1253 * @}
1254 */
1255
1256 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1257 * @brief TIM PWM functions
1258 *
1259 @verbatim
1260 ==============================================================================
1261 ##### TIM PWM functions #####
1262 ==============================================================================
1263 [..]
1264 This section provides functions allowing to:
1265 (+) Initialize and configure the TIM PWM.
1266 (+) De-initialize the TIM PWM.
1267 (+) Start the TIM PWM.
1268 (+) Stop the TIM PWM.
1269 (+) Start the TIM PWM and enable interrupt.
1270 (+) Stop the TIM PWM and disable interrupt.
1271 (+) Start the TIM PWM and enable DMA transfer.
1272 (+) Stop the TIM PWM and disable DMA transfer.
1273
1274 @endverbatim
1275 * @{
1276 */
1277 /**
1278 * @brief Initializes the TIM PWM Time Base according to the specified
1279 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1280 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1281 * requires a timer reset to avoid unexpected direction
1282 * due to DIR bit readonly in center aligned mode.
1283 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1284 * @param htim TIM PWM handle
1285 * @retval HAL status
1286 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1287 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1288 {
1289 /* Check the TIM handle allocation */
1290 if (htim == NULL)
1291 {
1292 return HAL_ERROR;
1293 }
1294
1295 /* Check the parameters */
1296 assert_param(IS_TIM_INSTANCE(htim->Instance));
1297 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1298 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1299 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1300
1301 if (htim->State == HAL_TIM_STATE_RESET)
1302 {
1303 /* Allocate lock resource and initialize it */
1304 htim->Lock = HAL_UNLOCKED;
1305
1306 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1307 /* Reset interrupt callbacks to legacy weak callbacks */
1308 TIM_ResetCallback(htim);
1309
1310 if (htim->PWM_MspInitCallback == NULL)
1311 {
1312 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1313 }
1314 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1315 htim->PWM_MspInitCallback(htim);
1316 #else
1317 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1318 HAL_TIM_PWM_MspInit(htim);
1319 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1320 }
1321
1322 /* Set the TIM state */
1323 htim->State = HAL_TIM_STATE_BUSY;
1324
1325 /* Init the base time for the PWM */
1326 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1327
1328 /* Initialize the DMA burst operation state */
1329 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1330
1331 /* Initialize the TIM channels state */
1332 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1333 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1334
1335 /* Initialize the TIM state*/
1336 htim->State = HAL_TIM_STATE_READY;
1337
1338 return HAL_OK;
1339 }
1340
1341 /**
1342 * @brief DeInitializes the TIM peripheral
1343 * @param htim TIM PWM handle
1344 * @retval HAL status
1345 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1346 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1347 {
1348 /* Check the parameters */
1349 assert_param(IS_TIM_INSTANCE(htim->Instance));
1350
1351 htim->State = HAL_TIM_STATE_BUSY;
1352
1353 /* Disable the TIM Peripheral Clock */
1354 __HAL_TIM_DISABLE(htim);
1355
1356 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1357 if (htim->PWM_MspDeInitCallback == NULL)
1358 {
1359 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1360 }
1361 /* DeInit the low level hardware */
1362 htim->PWM_MspDeInitCallback(htim);
1363 #else
1364 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1365 HAL_TIM_PWM_MspDeInit(htim);
1366 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1367
1368 /* Change the DMA burst operation state */
1369 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1370
1371 /* Change the TIM channels state */
1372 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1373 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1374
1375 /* Change TIM state */
1376 htim->State = HAL_TIM_STATE_RESET;
1377
1378 /* Release Lock */
1379 __HAL_UNLOCK(htim);
1380
1381 return HAL_OK;
1382 }
1383
1384 /**
1385 * @brief Initializes the TIM PWM MSP.
1386 * @param htim TIM PWM handle
1387 * @retval None
1388 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1389 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1390 {
1391 /* Prevent unused argument(s) compilation warning */
1392 UNUSED(htim);
1393
1394 /* NOTE : This function should not be modified, when the callback is needed,
1395 the HAL_TIM_PWM_MspInit could be implemented in the user file
1396 */
1397 }
1398
1399 /**
1400 * @brief DeInitializes TIM PWM MSP.
1401 * @param htim TIM PWM handle
1402 * @retval None
1403 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1404 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1405 {
1406 /* Prevent unused argument(s) compilation warning */
1407 UNUSED(htim);
1408
1409 /* NOTE : This function should not be modified, when the callback is needed,
1410 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1411 */
1412 }
1413
1414 /**
1415 * @brief Starts the PWM signal generation.
1416 * @param htim TIM handle
1417 * @param Channel TIM Channels to be enabled
1418 * This parameter can be one of the following values:
1419 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1420 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1421 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1422 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1423 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1424 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1425 * @retval HAL status
1426 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1427 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1428 {
1429 uint32_t tmpsmcr;
1430
1431 /* Check the parameters */
1432 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1433
1434 /* Check the TIM channel state */
1435 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1436 {
1437 return HAL_ERROR;
1438 }
1439
1440 /* Set the TIM channel state */
1441 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1442
1443 /* Enable the Capture compare channel */
1444 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1445
1446 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1447 {
1448 /* Enable the main output */
1449 __HAL_TIM_MOE_ENABLE(htim);
1450 }
1451
1452 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1453 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1454 {
1455 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1456 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1457 {
1458 __HAL_TIM_ENABLE(htim);
1459 }
1460 }
1461 else
1462 {
1463 __HAL_TIM_ENABLE(htim);
1464 }
1465
1466 /* Return function status */
1467 return HAL_OK;
1468 }
1469
1470 /**
1471 * @brief Stops the PWM signal generation.
1472 * @param htim TIM PWM handle
1473 * @param Channel TIM Channels to be disabled
1474 * This parameter can be one of the following values:
1475 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1476 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1477 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1478 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1479 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1480 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1481 * @retval HAL status
1482 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1483 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1484 {
1485 /* Check the parameters */
1486 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1487
1488 /* Disable the Capture compare channel */
1489 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1490
1491 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1492 {
1493 /* Disable the Main Output */
1494 __HAL_TIM_MOE_DISABLE(htim);
1495 }
1496
1497 /* Disable the Peripheral */
1498 __HAL_TIM_DISABLE(htim);
1499
1500 /* Set the TIM channel state */
1501 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1502
1503 /* Return function status */
1504 return HAL_OK;
1505 }
1506
1507 /**
1508 * @brief Starts the PWM signal generation in interrupt mode.
1509 * @param htim TIM PWM handle
1510 * @param Channel TIM Channel to be enabled
1511 * This parameter can be one of the following values:
1512 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1513 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1514 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1515 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1516 * @retval HAL status
1517 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1518 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1519 {
1520 uint32_t tmpsmcr;
1521 /* Check the parameters */
1522 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1523
1524 /* Check the TIM channel state */
1525 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1526 {
1527 return HAL_ERROR;
1528 }
1529
1530 /* Set the TIM channel state */
1531 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1532
1533 switch (Channel)
1534 {
1535 case TIM_CHANNEL_1:
1536 {
1537 /* Enable the TIM Capture/Compare 1 interrupt */
1538 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1539 break;
1540 }
1541
1542 case TIM_CHANNEL_2:
1543 {
1544 /* Enable the TIM Capture/Compare 2 interrupt */
1545 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1546 break;
1547 }
1548
1549 case TIM_CHANNEL_3:
1550 {
1551 /* Enable the TIM Capture/Compare 3 interrupt */
1552 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1553 break;
1554 }
1555
1556 case TIM_CHANNEL_4:
1557 {
1558 /* Enable the TIM Capture/Compare 4 interrupt */
1559 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1560 break;
1561 }
1562
1563 default:
1564 break;
1565 }
1566
1567 /* Enable the Capture compare channel */
1568 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1569
1570 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1571 {
1572 /* Enable the main output */
1573 __HAL_TIM_MOE_ENABLE(htim);
1574 }
1575
1576 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1577 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1578 {
1579 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1580 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1581 {
1582 __HAL_TIM_ENABLE(htim);
1583 }
1584 }
1585 else
1586 {
1587 __HAL_TIM_ENABLE(htim);
1588 }
1589
1590 /* Return function status */
1591 return HAL_OK;
1592 }
1593
1594 /**
1595 * @brief Stops the PWM signal generation in interrupt mode.
1596 * @param htim TIM PWM handle
1597 * @param Channel TIM Channels to be disabled
1598 * This parameter can be one of the following values:
1599 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1600 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1601 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1602 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1603 * @retval HAL status
1604 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1605 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1606 {
1607 /* Check the parameters */
1608 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1609
1610 switch (Channel)
1611 {
1612 case TIM_CHANNEL_1:
1613 {
1614 /* Disable the TIM Capture/Compare 1 interrupt */
1615 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1616 break;
1617 }
1618
1619 case TIM_CHANNEL_2:
1620 {
1621 /* Disable the TIM Capture/Compare 2 interrupt */
1622 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1623 break;
1624 }
1625
1626 case TIM_CHANNEL_3:
1627 {
1628 /* Disable the TIM Capture/Compare 3 interrupt */
1629 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1630 break;
1631 }
1632
1633 case TIM_CHANNEL_4:
1634 {
1635 /* Disable the TIM Capture/Compare 4 interrupt */
1636 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1637 break;
1638 }
1639
1640 default:
1641 break;
1642 }
1643
1644 /* Disable the Capture compare channel */
1645 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1646
1647 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1648 {
1649 /* Disable the Main Output */
1650 __HAL_TIM_MOE_DISABLE(htim);
1651 }
1652
1653 /* Disable the Peripheral */
1654 __HAL_TIM_DISABLE(htim);
1655
1656 /* Set the TIM channel state */
1657 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1658
1659 /* Return function status */
1660 return HAL_OK;
1661 }
1662
1663 /**
1664 * @brief Starts the TIM PWM signal generation in DMA mode.
1665 * @param htim TIM PWM handle
1666 * @param Channel TIM Channels to be enabled
1667 * This parameter can be one of the following values:
1668 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1669 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1670 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1671 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1672 * @param pData The source Buffer address.
1673 * @param Length The length of data to be transferred from memory to TIM peripheral
1674 * @retval HAL status
1675 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)1676 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1677 {
1678 uint32_t tmpsmcr;
1679
1680 /* Check the parameters */
1681 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1682
1683 /* Set the TIM channel state */
1684 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1685 {
1686 return HAL_BUSY;
1687 }
1688 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1689 {
1690 if ((pData == NULL) && (Length > 0U))
1691 {
1692 return HAL_ERROR;
1693 }
1694 else
1695 {
1696 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1697 }
1698 }
1699 else
1700 {
1701 return HAL_ERROR;
1702 }
1703
1704 switch (Channel)
1705 {
1706 case TIM_CHANNEL_1:
1707 {
1708 /* Set the DMA compare callbacks */
1709 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1710 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1711
1712 /* Set the DMA error callback */
1713 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1714
1715 /* Enable the DMA channel */
1716 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
1717 {
1718 return HAL_ERROR;
1719 }
1720
1721 /* Enable the TIM Capture/Compare 1 DMA request */
1722 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1723 break;
1724 }
1725
1726 case TIM_CHANNEL_2:
1727 {
1728 /* Set the DMA compare callbacks */
1729 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1730 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1731
1732 /* Set the DMA error callback */
1733 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1734
1735 /* Enable the DMA channel */
1736 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
1737 {
1738 return HAL_ERROR;
1739 }
1740 /* Enable the TIM Capture/Compare 2 DMA request */
1741 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1742 break;
1743 }
1744
1745 case TIM_CHANNEL_3:
1746 {
1747 /* Set the DMA compare callbacks */
1748 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1749 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1750
1751 /* Set the DMA error callback */
1752 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1753
1754 /* Enable the DMA channel */
1755 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
1756 {
1757 return HAL_ERROR;
1758 }
1759 /* Enable the TIM Output Capture/Compare 3 request */
1760 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1761 break;
1762 }
1763
1764 case TIM_CHANNEL_4:
1765 {
1766 /* Set the DMA compare callbacks */
1767 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1768 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1769
1770 /* Set the DMA error callback */
1771 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1772
1773 /* Enable the DMA channel */
1774 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
1775 {
1776 return HAL_ERROR;
1777 }
1778 /* Enable the TIM Capture/Compare 4 DMA request */
1779 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1780 break;
1781 }
1782
1783 default:
1784 break;
1785 }
1786
1787 /* Enable the Capture compare channel */
1788 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1789
1790 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1791 {
1792 /* Enable the main output */
1793 __HAL_TIM_MOE_ENABLE(htim);
1794 }
1795
1796 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1797 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1798 {
1799 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1800 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1801 {
1802 __HAL_TIM_ENABLE(htim);
1803 }
1804 }
1805 else
1806 {
1807 __HAL_TIM_ENABLE(htim);
1808 }
1809
1810 /* Return function status */
1811 return HAL_OK;
1812 }
1813
1814 /**
1815 * @brief Stops the TIM PWM signal generation in DMA mode.
1816 * @param htim TIM PWM handle
1817 * @param Channel TIM Channels to be disabled
1818 * This parameter can be one of the following values:
1819 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1820 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1821 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1822 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1823 * @retval HAL status
1824 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1825 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1826 {
1827 /* Check the parameters */
1828 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1829
1830 switch (Channel)
1831 {
1832 case TIM_CHANNEL_1:
1833 {
1834 /* Disable the TIM Capture/Compare 1 DMA request */
1835 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1836 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1837 break;
1838 }
1839
1840 case TIM_CHANNEL_2:
1841 {
1842 /* Disable the TIM Capture/Compare 2 DMA request */
1843 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1844 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1845 break;
1846 }
1847
1848 case TIM_CHANNEL_3:
1849 {
1850 /* Disable the TIM Capture/Compare 3 DMA request */
1851 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1852 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1853 break;
1854 }
1855
1856 case TIM_CHANNEL_4:
1857 {
1858 /* Disable the TIM Capture/Compare 4 interrupt */
1859 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1860 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1861 break;
1862 }
1863
1864 default:
1865 break;
1866 }
1867
1868 /* Disable the Capture compare channel */
1869 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1870
1871 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1872 {
1873 /* Disable the Main Output */
1874 __HAL_TIM_MOE_DISABLE(htim);
1875 }
1876
1877 /* Disable the Peripheral */
1878 __HAL_TIM_DISABLE(htim);
1879
1880 /* Set the TIM channel state */
1881 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1882
1883 /* Return function status */
1884 return HAL_OK;
1885 }
1886
1887 /**
1888 * @}
1889 */
1890
1891 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1892 * @brief TIM Input Capture functions
1893 *
1894 @verbatim
1895 ==============================================================================
1896 ##### TIM Input Capture functions #####
1897 ==============================================================================
1898 [..]
1899 This section provides functions allowing to:
1900 (+) Initialize and configure the TIM Input Capture.
1901 (+) De-initialize the TIM Input Capture.
1902 (+) Start the TIM Input Capture.
1903 (+) Stop the TIM Input Capture.
1904 (+) Start the TIM Input Capture and enable interrupt.
1905 (+) Stop the TIM Input Capture and disable interrupt.
1906 (+) Start the TIM Input Capture and enable DMA transfer.
1907 (+) Stop the TIM Input Capture and disable DMA transfer.
1908
1909 @endverbatim
1910 * @{
1911 */
1912 /**
1913 * @brief Initializes the TIM Input Capture Time base according to the specified
1914 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1915 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1916 * requires a timer reset to avoid unexpected direction
1917 * due to DIR bit readonly in center aligned mode.
1918 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1919 * @param htim TIM Input Capture handle
1920 * @retval HAL status
1921 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)1922 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1923 {
1924 /* Check the TIM handle allocation */
1925 if (htim == NULL)
1926 {
1927 return HAL_ERROR;
1928 }
1929
1930 /* Check the parameters */
1931 assert_param(IS_TIM_INSTANCE(htim->Instance));
1932 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1933 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1934 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1935
1936 if (htim->State == HAL_TIM_STATE_RESET)
1937 {
1938 /* Allocate lock resource and initialize it */
1939 htim->Lock = HAL_UNLOCKED;
1940
1941 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1942 /* Reset interrupt callbacks to legacy weak callbacks */
1943 TIM_ResetCallback(htim);
1944
1945 if (htim->IC_MspInitCallback == NULL)
1946 {
1947 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
1948 }
1949 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1950 htim->IC_MspInitCallback(htim);
1951 #else
1952 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1953 HAL_TIM_IC_MspInit(htim);
1954 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1955 }
1956
1957 /* Set the TIM state */
1958 htim->State = HAL_TIM_STATE_BUSY;
1959
1960 /* Init the base time for the input capture */
1961 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1962
1963 /* Initialize the DMA burst operation state */
1964 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1965
1966 /* Initialize the TIM channels state */
1967 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1968 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1969
1970 /* Initialize the TIM state*/
1971 htim->State = HAL_TIM_STATE_READY;
1972
1973 return HAL_OK;
1974 }
1975
1976 /**
1977 * @brief DeInitializes the TIM peripheral
1978 * @param htim TIM Input Capture handle
1979 * @retval HAL status
1980 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)1981 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
1982 {
1983 /* Check the parameters */
1984 assert_param(IS_TIM_INSTANCE(htim->Instance));
1985
1986 htim->State = HAL_TIM_STATE_BUSY;
1987
1988 /* Disable the TIM Peripheral Clock */
1989 __HAL_TIM_DISABLE(htim);
1990
1991 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1992 if (htim->IC_MspDeInitCallback == NULL)
1993 {
1994 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
1995 }
1996 /* DeInit the low level hardware */
1997 htim->IC_MspDeInitCallback(htim);
1998 #else
1999 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
2000 HAL_TIM_IC_MspDeInit(htim);
2001 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2002
2003 /* Change the DMA burst operation state */
2004 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2005
2006 /* Change the TIM channels state */
2007 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2008 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2009
2010 /* Change TIM state */
2011 htim->State = HAL_TIM_STATE_RESET;
2012
2013 /* Release Lock */
2014 __HAL_UNLOCK(htim);
2015
2016 return HAL_OK;
2017 }
2018
2019 /**
2020 * @brief Initializes the TIM Input Capture MSP.
2021 * @param htim TIM Input Capture handle
2022 * @retval None
2023 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)2024 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
2025 {
2026 /* Prevent unused argument(s) compilation warning */
2027 UNUSED(htim);
2028
2029 /* NOTE : This function should not be modified, when the callback is needed,
2030 the HAL_TIM_IC_MspInit could be implemented in the user file
2031 */
2032 }
2033
2034 /**
2035 * @brief DeInitializes TIM Input Capture MSP.
2036 * @param htim TIM handle
2037 * @retval None
2038 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)2039 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
2040 {
2041 /* Prevent unused argument(s) compilation warning */
2042 UNUSED(htim);
2043
2044 /* NOTE : This function should not be modified, when the callback is needed,
2045 the HAL_TIM_IC_MspDeInit could be implemented in the user file
2046 */
2047 }
2048
2049 /**
2050 * @brief Starts the TIM Input Capture measurement.
2051 * @param htim TIM Input Capture handle
2052 * @param Channel TIM Channels to be enabled
2053 * This parameter can be one of the following values:
2054 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2055 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2056 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2057 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2058 * @retval HAL status
2059 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2060 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2061 {
2062 uint32_t tmpsmcr;
2063 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2064 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2065
2066 /* Check the parameters */
2067 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2068
2069 /* Check the TIM channel state */
2070 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2071 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2072 {
2073 return HAL_ERROR;
2074 }
2075
2076 /* Set the TIM channel state */
2077 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2078 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2079
2080 /* Enable the Input Capture channel */
2081 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2082
2083 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2084 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2085 {
2086 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2087 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2088 {
2089 __HAL_TIM_ENABLE(htim);
2090 }
2091 }
2092 else
2093 {
2094 __HAL_TIM_ENABLE(htim);
2095 }
2096
2097 /* Return function status */
2098 return HAL_OK;
2099 }
2100
2101 /**
2102 * @brief Stops the TIM Input Capture measurement.
2103 * @param htim TIM Input Capture handle
2104 * @param Channel TIM Channels to be disabled
2105 * This parameter can be one of the following values:
2106 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2107 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2108 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2109 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2110 * @retval HAL status
2111 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2112 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2113 {
2114 /* Check the parameters */
2115 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2116
2117 /* Disable the Input Capture channel */
2118 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2119
2120 /* Disable the Peripheral */
2121 __HAL_TIM_DISABLE(htim);
2122
2123 /* Set the TIM channel state */
2124 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2125 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2126
2127 /* Return function status */
2128 return HAL_OK;
2129 }
2130
2131 /**
2132 * @brief Starts the TIM Input Capture measurement in interrupt mode.
2133 * @param htim TIM Input Capture handle
2134 * @param Channel TIM Channels to be enabled
2135 * This parameter can be one of the following values:
2136 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2137 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2138 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2139 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2140 * @retval HAL status
2141 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2142 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2143 {
2144 uint32_t tmpsmcr;
2145 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2146 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2147
2148 /* Check the parameters */
2149 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2150
2151 /* Check the TIM channel state */
2152 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2153 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2154 {
2155 return HAL_ERROR;
2156 }
2157
2158 /* Set the TIM channel state */
2159 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2160 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2161
2162 switch (Channel)
2163 {
2164 case TIM_CHANNEL_1:
2165 {
2166 /* Enable the TIM Capture/Compare 1 interrupt */
2167 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2168 break;
2169 }
2170
2171 case TIM_CHANNEL_2:
2172 {
2173 /* Enable the TIM Capture/Compare 2 interrupt */
2174 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2175 break;
2176 }
2177
2178 case TIM_CHANNEL_3:
2179 {
2180 /* Enable the TIM Capture/Compare 3 interrupt */
2181 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
2182 break;
2183 }
2184
2185 case TIM_CHANNEL_4:
2186 {
2187 /* Enable the TIM Capture/Compare 4 interrupt */
2188 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
2189 break;
2190 }
2191
2192 default:
2193 break;
2194 }
2195 /* Enable the Input Capture channel */
2196 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2197
2198 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2199 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2200 {
2201 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2202 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2203 {
2204 __HAL_TIM_ENABLE(htim);
2205 }
2206 }
2207 else
2208 {
2209 __HAL_TIM_ENABLE(htim);
2210 }
2211
2212 /* Return function status */
2213 return HAL_OK;
2214 }
2215
2216 /**
2217 * @brief Stops the TIM Input Capture measurement in interrupt mode.
2218 * @param htim TIM Input Capture handle
2219 * @param Channel TIM Channels to be disabled
2220 * This parameter can be one of the following values:
2221 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2222 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2223 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2224 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2225 * @retval HAL status
2226 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2227 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2228 {
2229 /* Check the parameters */
2230 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2231
2232 switch (Channel)
2233 {
2234 case TIM_CHANNEL_1:
2235 {
2236 /* Disable the TIM Capture/Compare 1 interrupt */
2237 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2238 break;
2239 }
2240
2241 case TIM_CHANNEL_2:
2242 {
2243 /* Disable the TIM Capture/Compare 2 interrupt */
2244 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2245 break;
2246 }
2247
2248 case TIM_CHANNEL_3:
2249 {
2250 /* Disable the TIM Capture/Compare 3 interrupt */
2251 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2252 break;
2253 }
2254
2255 case TIM_CHANNEL_4:
2256 {
2257 /* Disable the TIM Capture/Compare 4 interrupt */
2258 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2259 break;
2260 }
2261
2262 default:
2263 break;
2264 }
2265
2266 /* Disable the Input Capture channel */
2267 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2268
2269 /* Disable the Peripheral */
2270 __HAL_TIM_DISABLE(htim);
2271
2272 /* Set the TIM channel state */
2273 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2274 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2275
2276 /* Return function status */
2277 return HAL_OK;
2278 }
2279
2280 /**
2281 * @brief Starts the TIM Input Capture measurement in DMA mode.
2282 * @param htim TIM Input Capture handle
2283 * @param Channel TIM Channels to be enabled
2284 * This parameter can be one of the following values:
2285 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2286 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2287 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2288 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2289 * @param pData The destination Buffer address.
2290 * @param Length The length of data to be transferred from TIM peripheral to memory.
2291 * @retval HAL status
2292 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2293 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2294 {
2295 uint32_t tmpsmcr;
2296 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2297 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2298
2299 /* Check the parameters */
2300 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2301 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2302
2303 /* Set the TIM channel state */
2304 if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
2305 || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
2306 {
2307 return HAL_BUSY;
2308 }
2309 else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
2310 && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
2311 {
2312 if ((pData == NULL) && (Length > 0U))
2313 {
2314 return HAL_ERROR;
2315 }
2316 else
2317 {
2318 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2319 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2320 }
2321 }
2322 else
2323 {
2324 return HAL_ERROR;
2325 }
2326
2327 switch (Channel)
2328 {
2329 case TIM_CHANNEL_1:
2330 {
2331 /* Set the DMA capture callbacks */
2332 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2333 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2334
2335 /* Set the DMA error callback */
2336 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2337
2338 /* Enable the DMA channel */
2339 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
2340 {
2341 return HAL_ERROR;
2342 }
2343 /* Enable the TIM Capture/Compare 1 DMA request */
2344 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2345 break;
2346 }
2347
2348 case TIM_CHANNEL_2:
2349 {
2350 /* Set the DMA capture callbacks */
2351 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2352 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2353
2354 /* Set the DMA error callback */
2355 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2356
2357 /* Enable the DMA channel */
2358 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
2359 {
2360 return HAL_ERROR;
2361 }
2362 /* Enable the TIM Capture/Compare 2 DMA request */
2363 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2364 break;
2365 }
2366
2367 case TIM_CHANNEL_3:
2368 {
2369 /* Set the DMA capture callbacks */
2370 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2371 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2372
2373 /* Set the DMA error callback */
2374 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2375
2376 /* Enable the DMA channel */
2377 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
2378 {
2379 return HAL_ERROR;
2380 }
2381 /* Enable the TIM Capture/Compare 3 DMA request */
2382 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2383 break;
2384 }
2385
2386 case TIM_CHANNEL_4:
2387 {
2388 /* Set the DMA capture callbacks */
2389 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2390 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2391
2392 /* Set the DMA error callback */
2393 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2394
2395 /* Enable the DMA channel */
2396 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
2397 {
2398 return HAL_ERROR;
2399 }
2400 /* Enable the TIM Capture/Compare 4 DMA request */
2401 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2402 break;
2403 }
2404
2405 default:
2406 break;
2407 }
2408
2409 /* Enable the Input Capture channel */
2410 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2411
2412 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2413 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2414 {
2415 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2416 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2417 {
2418 __HAL_TIM_ENABLE(htim);
2419 }
2420 }
2421 else
2422 {
2423 __HAL_TIM_ENABLE(htim);
2424 }
2425
2426 /* Return function status */
2427 return HAL_OK;
2428 }
2429
2430 /**
2431 * @brief Stops the TIM Input Capture measurement in DMA mode.
2432 * @param htim TIM Input Capture handle
2433 * @param Channel TIM Channels to be disabled
2434 * This parameter can be one of the following values:
2435 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2436 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2437 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2438 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2439 * @retval HAL status
2440 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2441 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2442 {
2443 /* Check the parameters */
2444 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2445 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2446
2447 /* Disable the Input Capture channel */
2448 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2449
2450 switch (Channel)
2451 {
2452 case TIM_CHANNEL_1:
2453 {
2454 /* Disable the TIM Capture/Compare 1 DMA request */
2455 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2456 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2457 break;
2458 }
2459
2460 case TIM_CHANNEL_2:
2461 {
2462 /* Disable the TIM Capture/Compare 2 DMA request */
2463 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2464 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2465 break;
2466 }
2467
2468 case TIM_CHANNEL_3:
2469 {
2470 /* Disable the TIM Capture/Compare 3 DMA request */
2471 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2472 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2473 break;
2474 }
2475
2476 case TIM_CHANNEL_4:
2477 {
2478 /* Disable the TIM Capture/Compare 4 DMA request */
2479 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2480 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2481 break;
2482 }
2483
2484 default:
2485 break;
2486 }
2487
2488 /* Disable the Peripheral */
2489 __HAL_TIM_DISABLE(htim);
2490
2491 /* Set the TIM channel state */
2492 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2493 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2494
2495 /* Return function status */
2496 return HAL_OK;
2497 }
2498 /**
2499 * @}
2500 */
2501
2502 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2503 * @brief TIM One Pulse functions
2504 *
2505 @verbatim
2506 ==============================================================================
2507 ##### TIM One Pulse functions #####
2508 ==============================================================================
2509 [..]
2510 This section provides functions allowing to:
2511 (+) Initialize and configure the TIM One Pulse.
2512 (+) De-initialize the TIM One Pulse.
2513 (+) Start the TIM One Pulse.
2514 (+) Stop the TIM One Pulse.
2515 (+) Start the TIM One Pulse and enable interrupt.
2516 (+) Stop the TIM One Pulse and disable interrupt.
2517 (+) Start the TIM One Pulse and enable DMA transfer.
2518 (+) Stop the TIM One Pulse and disable DMA transfer.
2519
2520 @endverbatim
2521 * @{
2522 */
2523 /**
2524 * @brief Initializes the TIM One Pulse Time Base according to the specified
2525 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2526 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2527 * requires a timer reset to avoid unexpected direction
2528 * due to DIR bit readonly in center aligned mode.
2529 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2530 * @note When the timer instance is initialized in One Pulse mode, timer
2531 * channels 1 and channel 2 are reserved and cannot be used for other
2532 * purpose.
2533 * @param htim TIM One Pulse handle
2534 * @param OnePulseMode Select the One pulse mode.
2535 * This parameter can be one of the following values:
2536 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2537 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2538 * @retval HAL status
2539 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2540 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2541 {
2542 /* Check the TIM handle allocation */
2543 if (htim == NULL)
2544 {
2545 return HAL_ERROR;
2546 }
2547
2548 /* Check the parameters */
2549 assert_param(IS_TIM_INSTANCE(htim->Instance));
2550 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2551 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2552 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2553 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2554
2555 if (htim->State == HAL_TIM_STATE_RESET)
2556 {
2557 /* Allocate lock resource and initialize it */
2558 htim->Lock = HAL_UNLOCKED;
2559
2560 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2561 /* Reset interrupt callbacks to legacy weak callbacks */
2562 TIM_ResetCallback(htim);
2563
2564 if (htim->OnePulse_MspInitCallback == NULL)
2565 {
2566 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2567 }
2568 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2569 htim->OnePulse_MspInitCallback(htim);
2570 #else
2571 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2572 HAL_TIM_OnePulse_MspInit(htim);
2573 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2574 }
2575
2576 /* Set the TIM state */
2577 htim->State = HAL_TIM_STATE_BUSY;
2578
2579 /* Configure the Time base in the One Pulse Mode */
2580 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2581
2582 /* Reset the OPM Bit */
2583 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2584
2585 /* Configure the OPM Mode */
2586 htim->Instance->CR1 |= OnePulseMode;
2587
2588 /* Initialize the DMA burst operation state */
2589 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2590
2591 /* Initialize the TIM channels state */
2592 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2593 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2594 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2595 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2596
2597 /* Initialize the TIM state*/
2598 htim->State = HAL_TIM_STATE_READY;
2599
2600 return HAL_OK;
2601 }
2602
2603 /**
2604 * @brief DeInitializes the TIM One Pulse
2605 * @param htim TIM One Pulse handle
2606 * @retval HAL status
2607 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2608 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2609 {
2610 /* Check the parameters */
2611 assert_param(IS_TIM_INSTANCE(htim->Instance));
2612
2613 htim->State = HAL_TIM_STATE_BUSY;
2614
2615 /* Disable the TIM Peripheral Clock */
2616 __HAL_TIM_DISABLE(htim);
2617
2618 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2619 if (htim->OnePulse_MspDeInitCallback == NULL)
2620 {
2621 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2622 }
2623 /* DeInit the low level hardware */
2624 htim->OnePulse_MspDeInitCallback(htim);
2625 #else
2626 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2627 HAL_TIM_OnePulse_MspDeInit(htim);
2628 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2629
2630 /* Change the DMA burst operation state */
2631 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2632
2633 /* Set the TIM channel state */
2634 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2635 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2636 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2637 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2638
2639 /* Change TIM state */
2640 htim->State = HAL_TIM_STATE_RESET;
2641
2642 /* Release Lock */
2643 __HAL_UNLOCK(htim);
2644
2645 return HAL_OK;
2646 }
2647
2648 /**
2649 * @brief Initializes the TIM One Pulse MSP.
2650 * @param htim TIM One Pulse handle
2651 * @retval None
2652 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2653 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2654 {
2655 /* Prevent unused argument(s) compilation warning */
2656 UNUSED(htim);
2657
2658 /* NOTE : This function should not be modified, when the callback is needed,
2659 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2660 */
2661 }
2662
2663 /**
2664 * @brief DeInitializes TIM One Pulse MSP.
2665 * @param htim TIM One Pulse handle
2666 * @retval None
2667 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2668 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2669 {
2670 /* Prevent unused argument(s) compilation warning */
2671 UNUSED(htim);
2672
2673 /* NOTE : This function should not be modified, when the callback is needed,
2674 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2675 */
2676 }
2677
2678 /**
2679 * @brief Starts the TIM One Pulse signal generation.
2680 * @param htim TIM One Pulse handle
2681 * @param OutputChannel TIM Channels to be enabled
2682 * This parameter can be one of the following values:
2683 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2684 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2685 * @retval HAL status
2686 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2687 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2688 {
2689 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2690 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2691 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2692 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2693
2694 /* Prevent unused argument(s) compilation warning */
2695 UNUSED(OutputChannel);
2696
2697 /* Check the TIM channels state */
2698 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2699 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2700 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2701 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2702 {
2703 return HAL_ERROR;
2704 }
2705
2706 /* Set the TIM channels state */
2707 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2708 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2709 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2710 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2711
2712 /* Enable the Capture compare and the Input Capture channels
2713 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2714 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2715 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2716 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2717
2718 No need to enable the counter, it's enabled automatically by hardware
2719 (the counter starts in response to a stimulus and generate a pulse */
2720
2721 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2722 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2723
2724 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2725 {
2726 /* Enable the main output */
2727 __HAL_TIM_MOE_ENABLE(htim);
2728 }
2729
2730 /* Return function status */
2731 return HAL_OK;
2732 }
2733
2734 /**
2735 * @brief Stops the TIM One Pulse signal generation.
2736 * @param htim TIM One Pulse handle
2737 * @param OutputChannel TIM Channels to be disable
2738 * This parameter can be one of the following values:
2739 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2740 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2741 * @retval HAL status
2742 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2743 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2744 {
2745 /* Prevent unused argument(s) compilation warning */
2746 UNUSED(OutputChannel);
2747
2748 /* Disable the Capture compare and the Input Capture channels
2749 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2750 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2751 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2752 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2753
2754 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2755 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2756
2757 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2758 {
2759 /* Disable the Main Output */
2760 __HAL_TIM_MOE_DISABLE(htim);
2761 }
2762
2763 /* Disable the Peripheral */
2764 __HAL_TIM_DISABLE(htim);
2765
2766 /* Set the TIM channels state */
2767 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2768 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2769 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2770 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2771
2772 /* Return function status */
2773 return HAL_OK;
2774 }
2775
2776 /**
2777 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2778 * @param htim TIM One Pulse handle
2779 * @param OutputChannel TIM Channels to be enabled
2780 * This parameter can be one of the following values:
2781 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2782 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2783 * @retval HAL status
2784 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2785 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2786 {
2787 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2788 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2789 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2790 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2791
2792 /* Prevent unused argument(s) compilation warning */
2793 UNUSED(OutputChannel);
2794
2795 /* Check the TIM channels state */
2796 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2797 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2798 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2799 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2800 {
2801 return HAL_ERROR;
2802 }
2803
2804 /* Set the TIM channels state */
2805 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2806 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2807 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2808 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2809
2810 /* Enable the Capture compare and the Input Capture channels
2811 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2812 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2813 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2814 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2815
2816 No need to enable the counter, it's enabled automatically by hardware
2817 (the counter starts in response to a stimulus and generate a pulse */
2818
2819 /* Enable the TIM Capture/Compare 1 interrupt */
2820 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2821
2822 /* Enable the TIM Capture/Compare 2 interrupt */
2823 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2824
2825 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2826 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2827
2828 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2829 {
2830 /* Enable the main output */
2831 __HAL_TIM_MOE_ENABLE(htim);
2832 }
2833
2834 /* Return function status */
2835 return HAL_OK;
2836 }
2837
2838 /**
2839 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2840 * @param htim TIM One Pulse handle
2841 * @param OutputChannel TIM Channels to be enabled
2842 * This parameter can be one of the following values:
2843 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2844 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2845 * @retval HAL status
2846 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2847 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2848 {
2849 /* Prevent unused argument(s) compilation warning */
2850 UNUSED(OutputChannel);
2851
2852 /* Disable the TIM Capture/Compare 1 interrupt */
2853 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2854
2855 /* Disable the TIM Capture/Compare 2 interrupt */
2856 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2857
2858 /* Disable the Capture compare and the Input Capture channels
2859 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2860 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2861 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2862 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2863 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2864 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2865
2866 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2867 {
2868 /* Disable the Main Output */
2869 __HAL_TIM_MOE_DISABLE(htim);
2870 }
2871
2872 /* Disable the Peripheral */
2873 __HAL_TIM_DISABLE(htim);
2874
2875 /* Set the TIM channels state */
2876 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2877 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2878 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2879 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2880
2881 /* Return function status */
2882 return HAL_OK;
2883 }
2884
2885 /**
2886 * @}
2887 */
2888
2889 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
2890 * @brief TIM Encoder functions
2891 *
2892 @verbatim
2893 ==============================================================================
2894 ##### TIM Encoder functions #####
2895 ==============================================================================
2896 [..]
2897 This section provides functions allowing to:
2898 (+) Initialize and configure the TIM Encoder.
2899 (+) De-initialize the TIM Encoder.
2900 (+) Start the TIM Encoder.
2901 (+) Stop the TIM Encoder.
2902 (+) Start the TIM Encoder and enable interrupt.
2903 (+) Stop the TIM Encoder and disable interrupt.
2904 (+) Start the TIM Encoder and enable DMA transfer.
2905 (+) Stop the TIM Encoder and disable DMA transfer.
2906
2907 @endverbatim
2908 * @{
2909 */
2910 /**
2911 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
2912 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2913 * requires a timer reset to avoid unexpected direction
2914 * due to DIR bit readonly in center aligned mode.
2915 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
2916 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
2917 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
2918 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
2919 * @note When the timer instance is initialized in Encoder mode, timer
2920 * channels 1 and channel 2 are reserved and cannot be used for other
2921 * purpose.
2922 * @param htim TIM Encoder Interface handle
2923 * @param sConfig TIM Encoder Interface configuration structure
2924 * @retval HAL status
2925 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,TIM_Encoder_InitTypeDef * sConfig)2926 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
2927 {
2928 uint32_t tmpsmcr;
2929 uint32_t tmpccmr1;
2930 uint32_t tmpccer;
2931
2932 /* Check the TIM handle allocation */
2933 if (htim == NULL)
2934 {
2935 return HAL_ERROR;
2936 }
2937
2938 /* Check the parameters */
2939 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
2940 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2941 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2942 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2943 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
2944 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
2945 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
2946 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
2947 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
2948 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
2949 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
2950 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
2951 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
2952
2953 if (htim->State == HAL_TIM_STATE_RESET)
2954 {
2955 /* Allocate lock resource and initialize it */
2956 htim->Lock = HAL_UNLOCKED;
2957
2958 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2959 /* Reset interrupt callbacks to legacy weak callbacks */
2960 TIM_ResetCallback(htim);
2961
2962 if (htim->Encoder_MspInitCallback == NULL)
2963 {
2964 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
2965 }
2966 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2967 htim->Encoder_MspInitCallback(htim);
2968 #else
2969 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2970 HAL_TIM_Encoder_MspInit(htim);
2971 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2972 }
2973
2974 /* Set the TIM state */
2975 htim->State = HAL_TIM_STATE_BUSY;
2976
2977 /* Reset the SMS and ECE bits */
2978 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
2979
2980 /* Configure the Time base in the Encoder Mode */
2981 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2982
2983 /* Get the TIMx SMCR register value */
2984 tmpsmcr = htim->Instance->SMCR;
2985
2986 /* Get the TIMx CCMR1 register value */
2987 tmpccmr1 = htim->Instance->CCMR1;
2988
2989 /* Get the TIMx CCER register value */
2990 tmpccer = htim->Instance->CCER;
2991
2992 /* Set the encoder Mode */
2993 tmpsmcr |= sConfig->EncoderMode;
2994
2995 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
2996 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
2997 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
2998
2999 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
3000 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
3001 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
3002 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
3003 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
3004
3005 /* Set the TI1 and the TI2 Polarities */
3006 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
3007 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
3008 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
3009
3010 /* Write to TIMx SMCR */
3011 htim->Instance->SMCR = tmpsmcr;
3012
3013 /* Write to TIMx CCMR1 */
3014 htim->Instance->CCMR1 = tmpccmr1;
3015
3016 /* Write to TIMx CCER */
3017 htim->Instance->CCER = tmpccer;
3018
3019 /* Initialize the DMA burst operation state */
3020 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
3021
3022 /* Set the TIM channels state */
3023 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3024 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3025 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3026 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3027
3028 /* Initialize the TIM state*/
3029 htim->State = HAL_TIM_STATE_READY;
3030
3031 return HAL_OK;
3032 }
3033
3034
3035 /**
3036 * @brief DeInitializes the TIM Encoder interface
3037 * @param htim TIM Encoder Interface handle
3038 * @retval HAL status
3039 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)3040 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
3041 {
3042 /* Check the parameters */
3043 assert_param(IS_TIM_INSTANCE(htim->Instance));
3044
3045 htim->State = HAL_TIM_STATE_BUSY;
3046
3047 /* Disable the TIM Peripheral Clock */
3048 __HAL_TIM_DISABLE(htim);
3049
3050 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3051 if (htim->Encoder_MspDeInitCallback == NULL)
3052 {
3053 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
3054 }
3055 /* DeInit the low level hardware */
3056 htim->Encoder_MspDeInitCallback(htim);
3057 #else
3058 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
3059 HAL_TIM_Encoder_MspDeInit(htim);
3060 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3061
3062 /* Change the DMA burst operation state */
3063 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
3064
3065 /* Set the TIM channels state */
3066 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3067 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3068 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3069 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3070
3071 /* Change TIM state */
3072 htim->State = HAL_TIM_STATE_RESET;
3073
3074 /* Release Lock */
3075 __HAL_UNLOCK(htim);
3076
3077 return HAL_OK;
3078 }
3079
3080 /**
3081 * @brief Initializes the TIM Encoder Interface MSP.
3082 * @param htim TIM Encoder Interface handle
3083 * @retval None
3084 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)3085 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
3086 {
3087 /* Prevent unused argument(s) compilation warning */
3088 UNUSED(htim);
3089
3090 /* NOTE : This function should not be modified, when the callback is needed,
3091 the HAL_TIM_Encoder_MspInit could be implemented in the user file
3092 */
3093 }
3094
3095 /**
3096 * @brief DeInitializes TIM Encoder Interface MSP.
3097 * @param htim TIM Encoder Interface handle
3098 * @retval None
3099 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)3100 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
3101 {
3102 /* Prevent unused argument(s) compilation warning */
3103 UNUSED(htim);
3104
3105 /* NOTE : This function should not be modified, when the callback is needed,
3106 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
3107 */
3108 }
3109
3110 /**
3111 * @brief Starts the TIM Encoder Interface.
3112 * @param htim TIM Encoder Interface handle
3113 * @param Channel TIM Channels to be enabled
3114 * This parameter can be one of the following values:
3115 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3116 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3117 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3118 * @retval HAL status
3119 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)3120 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
3121 {
3122 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3123 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3124 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3125 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3126
3127 /* Check the parameters */
3128 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3129
3130 /* Set the TIM channel(s) state */
3131 if (Channel == TIM_CHANNEL_1)
3132 {
3133 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3134 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3135 {
3136 return HAL_ERROR;
3137 }
3138 else
3139 {
3140 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3141 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3142 }
3143 }
3144 else if (Channel == TIM_CHANNEL_2)
3145 {
3146 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3147 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3148 {
3149 return HAL_ERROR;
3150 }
3151 else
3152 {
3153 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3154 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3155 }
3156 }
3157 else
3158 {
3159 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3160 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3161 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3162 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3163 {
3164 return HAL_ERROR;
3165 }
3166 else
3167 {
3168 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3169 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3170 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3171 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3172 }
3173 }
3174
3175 /* Enable the encoder interface channels */
3176 switch (Channel)
3177 {
3178 case TIM_CHANNEL_1:
3179 {
3180 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3181 break;
3182 }
3183
3184 case TIM_CHANNEL_2:
3185 {
3186 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3187 break;
3188 }
3189
3190 default :
3191 {
3192 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3193 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3194 break;
3195 }
3196 }
3197 /* Enable the Peripheral */
3198 __HAL_TIM_ENABLE(htim);
3199
3200 /* Return function status */
3201 return HAL_OK;
3202 }
3203
3204 /**
3205 * @brief Stops the TIM Encoder Interface.
3206 * @param htim TIM Encoder Interface handle
3207 * @param Channel TIM Channels to be disabled
3208 * This parameter can be one of the following values:
3209 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3210 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3211 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3212 * @retval HAL status
3213 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)3214 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
3215 {
3216 /* Check the parameters */
3217 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3218
3219 /* Disable the Input Capture channels 1 and 2
3220 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3221 switch (Channel)
3222 {
3223 case TIM_CHANNEL_1:
3224 {
3225 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3226 break;
3227 }
3228
3229 case TIM_CHANNEL_2:
3230 {
3231 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3232 break;
3233 }
3234
3235 default :
3236 {
3237 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3238 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3239 break;
3240 }
3241 }
3242
3243 /* Disable the Peripheral */
3244 __HAL_TIM_DISABLE(htim);
3245
3246 /* Set the TIM channel(s) state */
3247 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3248 {
3249 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3250 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3251 }
3252 else
3253 {
3254 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3255 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3256 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3257 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3258 }
3259
3260 /* Return function status */
3261 return HAL_OK;
3262 }
3263
3264 /**
3265 * @brief Starts the TIM Encoder Interface in interrupt mode.
3266 * @param htim TIM Encoder Interface handle
3267 * @param Channel TIM Channels to be enabled
3268 * This parameter can be one of the following values:
3269 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3270 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3271 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3272 * @retval HAL status
3273 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3274 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3275 {
3276 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3277 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3278 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3279 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3280
3281 /* Check the parameters */
3282 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3283
3284 /* Set the TIM channel(s) state */
3285 if (Channel == TIM_CHANNEL_1)
3286 {
3287 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3288 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3289 {
3290 return HAL_ERROR;
3291 }
3292 else
3293 {
3294 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3295 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3296 }
3297 }
3298 else if (Channel == TIM_CHANNEL_2)
3299 {
3300 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3301 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3302 {
3303 return HAL_ERROR;
3304 }
3305 else
3306 {
3307 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3308 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3309 }
3310 }
3311 else
3312 {
3313 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3314 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3315 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3316 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3317 {
3318 return HAL_ERROR;
3319 }
3320 else
3321 {
3322 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3323 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3324 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3325 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3326 }
3327 }
3328
3329 /* Enable the encoder interface channels */
3330 /* Enable the capture compare Interrupts 1 and/or 2 */
3331 switch (Channel)
3332 {
3333 case TIM_CHANNEL_1:
3334 {
3335 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3336 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3337 break;
3338 }
3339
3340 case TIM_CHANNEL_2:
3341 {
3342 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3343 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3344 break;
3345 }
3346
3347 default :
3348 {
3349 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3350 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3351 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3352 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3353 break;
3354 }
3355 }
3356
3357 /* Enable the Peripheral */
3358 __HAL_TIM_ENABLE(htim);
3359
3360 /* Return function status */
3361 return HAL_OK;
3362 }
3363
3364 /**
3365 * @brief Stops the TIM Encoder Interface in interrupt mode.
3366 * @param htim TIM Encoder Interface handle
3367 * @param Channel TIM Channels to be disabled
3368 * This parameter can be one of the following values:
3369 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3370 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3371 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3372 * @retval HAL status
3373 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3374 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3375 {
3376 /* Check the parameters */
3377 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3378
3379 /* Disable the Input Capture channels 1 and 2
3380 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3381 if (Channel == TIM_CHANNEL_1)
3382 {
3383 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3384
3385 /* Disable the capture compare Interrupts 1 */
3386 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3387 }
3388 else if (Channel == TIM_CHANNEL_2)
3389 {
3390 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3391
3392 /* Disable the capture compare Interrupts 2 */
3393 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3394 }
3395 else
3396 {
3397 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3398 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3399
3400 /* Disable the capture compare Interrupts 1 and 2 */
3401 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3402 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3403 }
3404
3405 /* Disable the Peripheral */
3406 __HAL_TIM_DISABLE(htim);
3407
3408 /* Set the TIM channel(s) state */
3409 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3410 {
3411 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3412 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3413 }
3414 else
3415 {
3416 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3417 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3418 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3419 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3420 }
3421
3422 /* Return function status */
3423 return HAL_OK;
3424 }
3425
3426 /**
3427 * @brief Starts the TIM Encoder Interface in DMA mode.
3428 * @param htim TIM Encoder Interface handle
3429 * @param Channel TIM Channels to be enabled
3430 * This parameter can be one of the following values:
3431 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3432 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3433 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3434 * @param pData1 The destination Buffer address for IC1.
3435 * @param pData2 The destination Buffer address for IC2.
3436 * @param Length The length of data to be transferred from TIM peripheral to memory.
3437 * @retval HAL status
3438 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)3439 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
3440 uint32_t *pData2, uint16_t Length)
3441 {
3442 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3443 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3444 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3445 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3446
3447 /* Check the parameters */
3448 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3449
3450 /* Set the TIM channel(s) state */
3451 if (Channel == TIM_CHANNEL_1)
3452 {
3453 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3454 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
3455 {
3456 return HAL_BUSY;
3457 }
3458 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3459 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
3460 {
3461 if ((pData1 == NULL) && (Length > 0U))
3462 {
3463 return HAL_ERROR;
3464 }
3465 else
3466 {
3467 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3468 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3469 }
3470 }
3471 else
3472 {
3473 return HAL_ERROR;
3474 }
3475 }
3476 else if (Channel == TIM_CHANNEL_2)
3477 {
3478 if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3479 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3480 {
3481 return HAL_BUSY;
3482 }
3483 else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3484 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3485 {
3486 if ((pData2 == NULL) && (Length > 0U))
3487 {
3488 return HAL_ERROR;
3489 }
3490 else
3491 {
3492 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3493 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3494 }
3495 }
3496 else
3497 {
3498 return HAL_ERROR;
3499 }
3500 }
3501 else
3502 {
3503 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3504 || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3505 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3506 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3507 {
3508 return HAL_BUSY;
3509 }
3510 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3511 && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3512 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3513 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3514 {
3515 if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
3516 {
3517 return HAL_ERROR;
3518 }
3519 else
3520 {
3521 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3522 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3523 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3524 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3525 }
3526 }
3527 else
3528 {
3529 return HAL_ERROR;
3530 }
3531 }
3532
3533 switch (Channel)
3534 {
3535 case TIM_CHANNEL_1:
3536 {
3537 /* Set the DMA capture callbacks */
3538 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3539 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3540
3541 /* Set the DMA error callback */
3542 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3543
3544 /* Enable the DMA channel */
3545 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
3546 {
3547 return HAL_ERROR;
3548 }
3549 /* Enable the TIM Input Capture DMA request */
3550 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3551
3552 /* Enable the Peripheral */
3553 __HAL_TIM_ENABLE(htim);
3554
3555 /* Enable the Capture compare channel */
3556 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3557 break;
3558 }
3559
3560 case TIM_CHANNEL_2:
3561 {
3562 /* Set the DMA capture callbacks */
3563 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3564 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3565
3566 /* Set the DMA error callback */
3567 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3568 /* Enable the DMA channel */
3569 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
3570 {
3571 return HAL_ERROR;
3572 }
3573 /* Enable the TIM Input Capture DMA request */
3574 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3575
3576 /* Enable the Peripheral */
3577 __HAL_TIM_ENABLE(htim);
3578
3579 /* Enable the Capture compare channel */
3580 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3581 break;
3582 }
3583
3584 case TIM_CHANNEL_ALL:
3585 {
3586 /* Set the DMA capture callbacks */
3587 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3588 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3589
3590 /* Set the DMA error callback */
3591 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3592
3593 /* Enable the DMA channel */
3594 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
3595 {
3596 return HAL_ERROR;
3597 }
3598
3599 /* Set the DMA capture callbacks */
3600 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3601 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3602
3603 /* Set the DMA error callback */
3604 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3605
3606 /* Enable the DMA channel */
3607 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
3608 {
3609 return HAL_ERROR;
3610 }
3611 /* Enable the Peripheral */
3612 __HAL_TIM_ENABLE(htim);
3613
3614 /* Enable the Capture compare channel */
3615 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3616 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3617
3618 /* Enable the TIM Input Capture DMA request */
3619 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3620 /* Enable the TIM Input Capture DMA request */
3621 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3622 break;
3623 }
3624
3625 default:
3626 break;
3627 }
3628
3629 /* Return function status */
3630 return HAL_OK;
3631 }
3632
3633 /**
3634 * @brief Stops the TIM Encoder Interface in DMA mode.
3635 * @param htim TIM Encoder Interface handle
3636 * @param Channel TIM Channels to be enabled
3637 * This parameter can be one of the following values:
3638 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3639 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3640 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3641 * @retval HAL status
3642 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3643 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3644 {
3645 /* Check the parameters */
3646 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3647
3648 /* Disable the Input Capture channels 1 and 2
3649 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3650 if (Channel == TIM_CHANNEL_1)
3651 {
3652 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3653
3654 /* Disable the capture compare DMA Request 1 */
3655 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3656 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3657 }
3658 else if (Channel == TIM_CHANNEL_2)
3659 {
3660 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3661
3662 /* Disable the capture compare DMA Request 2 */
3663 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3664 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3665 }
3666 else
3667 {
3668 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3669 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3670
3671 /* Disable the capture compare DMA Request 1 and 2 */
3672 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3673 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3674 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3675 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3676 }
3677
3678 /* Disable the Peripheral */
3679 __HAL_TIM_DISABLE(htim);
3680
3681 /* Set the TIM channel(s) state */
3682 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3683 {
3684 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3685 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3686 }
3687 else
3688 {
3689 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3690 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3691 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3692 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3693 }
3694
3695 /* Return function status */
3696 return HAL_OK;
3697 }
3698
3699 /**
3700 * @}
3701 */
3702 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3703 * @brief TIM IRQ handler management
3704 *
3705 @verbatim
3706 ==============================================================================
3707 ##### IRQ handler management #####
3708 ==============================================================================
3709 [..]
3710 This section provides Timer IRQ handler function.
3711
3712 @endverbatim
3713 * @{
3714 */
3715 /**
3716 * @brief This function handles TIM interrupts requests.
3717 * @param htim TIM handle
3718 * @retval None
3719 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3720 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3721 {
3722 /* Capture compare 1 event */
3723 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
3724 {
3725 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
3726 {
3727 {
3728 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
3729 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3730
3731 /* Input capture event */
3732 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3733 {
3734 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3735 htim->IC_CaptureCallback(htim);
3736 #else
3737 HAL_TIM_IC_CaptureCallback(htim);
3738 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3739 }
3740 /* Output compare event */
3741 else
3742 {
3743 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3744 htim->OC_DelayElapsedCallback(htim);
3745 htim->PWM_PulseFinishedCallback(htim);
3746 #else
3747 HAL_TIM_OC_DelayElapsedCallback(htim);
3748 HAL_TIM_PWM_PulseFinishedCallback(htim);
3749 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3750 }
3751 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3752 }
3753 }
3754 }
3755 /* Capture compare 2 event */
3756 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
3757 {
3758 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
3759 {
3760 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
3761 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3762 /* Input capture event */
3763 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3764 {
3765 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3766 htim->IC_CaptureCallback(htim);
3767 #else
3768 HAL_TIM_IC_CaptureCallback(htim);
3769 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3770 }
3771 /* Output compare event */
3772 else
3773 {
3774 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3775 htim->OC_DelayElapsedCallback(htim);
3776 htim->PWM_PulseFinishedCallback(htim);
3777 #else
3778 HAL_TIM_OC_DelayElapsedCallback(htim);
3779 HAL_TIM_PWM_PulseFinishedCallback(htim);
3780 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3781 }
3782 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3783 }
3784 }
3785 /* Capture compare 3 event */
3786 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
3787 {
3788 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
3789 {
3790 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
3791 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3792 /* Input capture event */
3793 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3794 {
3795 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3796 htim->IC_CaptureCallback(htim);
3797 #else
3798 HAL_TIM_IC_CaptureCallback(htim);
3799 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3800 }
3801 /* Output compare event */
3802 else
3803 {
3804 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3805 htim->OC_DelayElapsedCallback(htim);
3806 htim->PWM_PulseFinishedCallback(htim);
3807 #else
3808 HAL_TIM_OC_DelayElapsedCallback(htim);
3809 HAL_TIM_PWM_PulseFinishedCallback(htim);
3810 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3811 }
3812 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3813 }
3814 }
3815 /* Capture compare 4 event */
3816 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
3817 {
3818 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
3819 {
3820 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
3821 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3822 /* Input capture event */
3823 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3824 {
3825 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3826 htim->IC_CaptureCallback(htim);
3827 #else
3828 HAL_TIM_IC_CaptureCallback(htim);
3829 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3830 }
3831 /* Output compare event */
3832 else
3833 {
3834 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3835 htim->OC_DelayElapsedCallback(htim);
3836 htim->PWM_PulseFinishedCallback(htim);
3837 #else
3838 HAL_TIM_OC_DelayElapsedCallback(htim);
3839 HAL_TIM_PWM_PulseFinishedCallback(htim);
3840 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3841 }
3842 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3843 }
3844 }
3845 /* TIM Update event */
3846 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
3847 {
3848 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
3849 {
3850 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
3851 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3852 htim->PeriodElapsedCallback(htim);
3853 #else
3854 HAL_TIM_PeriodElapsedCallback(htim);
3855 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3856 }
3857 }
3858 /* TIM Break input event */
3859 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
3860 {
3861 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
3862 {
3863 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
3864 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3865 htim->BreakCallback(htim);
3866 #else
3867 HAL_TIMEx_BreakCallback(htim);
3868 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3869 }
3870 }
3871 /* TIM Break2 input event */
3872 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
3873 {
3874 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
3875 {
3876 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
3877 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3878 htim->Break2Callback(htim);
3879 #else
3880 HAL_TIMEx_Break2Callback(htim);
3881 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3882 }
3883 }
3884 /* TIM Trigger detection event */
3885 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
3886 {
3887 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
3888 {
3889 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
3890 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3891 htim->TriggerCallback(htim);
3892 #else
3893 HAL_TIM_TriggerCallback(htim);
3894 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3895 }
3896 }
3897 /* TIM commutation event */
3898 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
3899 {
3900 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
3901 {
3902 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
3903 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3904 htim->CommutationCallback(htim);
3905 #else
3906 HAL_TIMEx_CommutCallback(htim);
3907 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3908 }
3909 }
3910 }
3911
3912 /**
3913 * @}
3914 */
3915
3916 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
3917 * @brief TIM Peripheral Control functions
3918 *
3919 @verbatim
3920 ==============================================================================
3921 ##### Peripheral Control functions #####
3922 ==============================================================================
3923 [..]
3924 This section provides functions allowing to:
3925 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
3926 (+) Configure External Clock source.
3927 (+) Configure Complementary channels, break features and dead time.
3928 (+) Configure Master and the Slave synchronization.
3929 (+) Configure the DMA Burst Mode.
3930
3931 @endverbatim
3932 * @{
3933 */
3934
3935 /**
3936 * @brief Initializes the TIM Output Compare Channels according to the specified
3937 * parameters in the TIM_OC_InitTypeDef.
3938 * @param htim TIM Output Compare handle
3939 * @param sConfig TIM Output Compare configuration structure
3940 * @param Channel TIM Channels to configure
3941 * This parameter can be one of the following values:
3942 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3943 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3944 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3945 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3946 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
3947 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
3948 * @retval HAL status
3949 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OC_InitTypeDef * sConfig,uint32_t Channel)3950 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
3951 TIM_OC_InitTypeDef *sConfig,
3952 uint32_t Channel)
3953 {
3954 /* Check the parameters */
3955 assert_param(IS_TIM_CHANNELS(Channel));
3956 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
3957 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3958
3959 /* Process Locked */
3960 __HAL_LOCK(htim);
3961
3962 switch (Channel)
3963 {
3964 case TIM_CHANNEL_1:
3965 {
3966 /* Check the parameters */
3967 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3968
3969 /* Configure the TIM Channel 1 in Output Compare */
3970 TIM_OC1_SetConfig(htim->Instance, sConfig);
3971 break;
3972 }
3973
3974 case TIM_CHANNEL_2:
3975 {
3976 /* Check the parameters */
3977 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3978
3979 /* Configure the TIM Channel 2 in Output Compare */
3980 TIM_OC2_SetConfig(htim->Instance, sConfig);
3981 break;
3982 }
3983
3984 case TIM_CHANNEL_3:
3985 {
3986 /* Check the parameters */
3987 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3988
3989 /* Configure the TIM Channel 3 in Output Compare */
3990 TIM_OC3_SetConfig(htim->Instance, sConfig);
3991 break;
3992 }
3993
3994 case TIM_CHANNEL_4:
3995 {
3996 /* Check the parameters */
3997 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3998
3999 /* Configure the TIM Channel 4 in Output Compare */
4000 TIM_OC4_SetConfig(htim->Instance, sConfig);
4001 break;
4002 }
4003
4004 case TIM_CHANNEL_5:
4005 {
4006 /* Check the parameters */
4007 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4008
4009 /* Configure the TIM Channel 5 in Output Compare */
4010 TIM_OC5_SetConfig(htim->Instance, sConfig);
4011 break;
4012 }
4013
4014 case TIM_CHANNEL_6:
4015 {
4016 /* Check the parameters */
4017 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4018
4019 /* Configure the TIM Channel 6 in Output Compare */
4020 TIM_OC6_SetConfig(htim->Instance, sConfig);
4021 break;
4022 }
4023
4024 default:
4025 break;
4026 }
4027
4028 __HAL_UNLOCK(htim);
4029
4030 return HAL_OK;
4031 }
4032
4033 /**
4034 * @brief Initializes the TIM Input Capture Channels according to the specified
4035 * parameters in the TIM_IC_InitTypeDef.
4036 * @param htim TIM IC handle
4037 * @param sConfig TIM Input Capture configuration structure
4038 * @param Channel TIM Channel to configure
4039 * This parameter can be one of the following values:
4040 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4041 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4042 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4043 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4044 * @retval HAL status
4045 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,TIM_IC_InitTypeDef * sConfig,uint32_t Channel)4046 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
4047 {
4048 /* Check the parameters */
4049 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4050 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
4051 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
4052 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
4053 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
4054
4055 /* Process Locked */
4056 __HAL_LOCK(htim);
4057
4058 if (Channel == TIM_CHANNEL_1)
4059 {
4060 /* TI1 Configuration */
4061 TIM_TI1_SetConfig(htim->Instance,
4062 sConfig->ICPolarity,
4063 sConfig->ICSelection,
4064 sConfig->ICFilter);
4065
4066 /* Reset the IC1PSC Bits */
4067 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4068
4069 /* Set the IC1PSC value */
4070 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
4071 }
4072 else if (Channel == TIM_CHANNEL_2)
4073 {
4074 /* TI2 Configuration */
4075 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4076
4077 TIM_TI2_SetConfig(htim->Instance,
4078 sConfig->ICPolarity,
4079 sConfig->ICSelection,
4080 sConfig->ICFilter);
4081
4082 /* Reset the IC2PSC Bits */
4083 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4084
4085 /* Set the IC2PSC value */
4086 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
4087 }
4088 else if (Channel == TIM_CHANNEL_3)
4089 {
4090 /* TI3 Configuration */
4091 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4092
4093 TIM_TI3_SetConfig(htim->Instance,
4094 sConfig->ICPolarity,
4095 sConfig->ICSelection,
4096 sConfig->ICFilter);
4097
4098 /* Reset the IC3PSC Bits */
4099 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
4100
4101 /* Set the IC3PSC value */
4102 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
4103 }
4104 else
4105 {
4106 /* TI4 Configuration */
4107 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4108
4109 TIM_TI4_SetConfig(htim->Instance,
4110 sConfig->ICPolarity,
4111 sConfig->ICSelection,
4112 sConfig->ICFilter);
4113
4114 /* Reset the IC4PSC Bits */
4115 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
4116
4117 /* Set the IC4PSC value */
4118 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
4119 }
4120
4121 __HAL_UNLOCK(htim);
4122
4123 return HAL_OK;
4124 }
4125
4126 /**
4127 * @brief Initializes the TIM PWM channels according to the specified
4128 * parameters in the TIM_OC_InitTypeDef.
4129 * @param htim TIM PWM handle
4130 * @param sConfig TIM PWM configuration structure
4131 * @param Channel TIM Channels to be configured
4132 * This parameter can be one of the following values:
4133 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4134 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4135 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4136 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4137 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
4138 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
4139 * @retval HAL status
4140 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4141 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
4142 TIM_OC_InitTypeDef *sConfig,
4143 uint32_t Channel)
4144 {
4145 /* Check the parameters */
4146 assert_param(IS_TIM_CHANNELS(Channel));
4147 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
4148 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4149 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
4150
4151 /* Process Locked */
4152 __HAL_LOCK(htim);
4153
4154 switch (Channel)
4155 {
4156 case TIM_CHANNEL_1:
4157 {
4158 /* Check the parameters */
4159 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4160
4161 /* Configure the Channel 1 in PWM mode */
4162 TIM_OC1_SetConfig(htim->Instance, sConfig);
4163
4164 /* Set the Preload enable bit for channel1 */
4165 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
4166
4167 /* Configure the Output Fast mode */
4168 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
4169 htim->Instance->CCMR1 |= sConfig->OCFastMode;
4170 break;
4171 }
4172
4173 case TIM_CHANNEL_2:
4174 {
4175 /* Check the parameters */
4176 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4177
4178 /* Configure the Channel 2 in PWM mode */
4179 TIM_OC2_SetConfig(htim->Instance, sConfig);
4180
4181 /* Set the Preload enable bit for channel2 */
4182 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
4183
4184 /* Configure the Output Fast mode */
4185 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
4186 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
4187 break;
4188 }
4189
4190 case TIM_CHANNEL_3:
4191 {
4192 /* Check the parameters */
4193 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4194
4195 /* Configure the Channel 3 in PWM mode */
4196 TIM_OC3_SetConfig(htim->Instance, sConfig);
4197
4198 /* Set the Preload enable bit for channel3 */
4199 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
4200
4201 /* Configure the Output Fast mode */
4202 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
4203 htim->Instance->CCMR2 |= sConfig->OCFastMode;
4204 break;
4205 }
4206
4207 case TIM_CHANNEL_4:
4208 {
4209 /* Check the parameters */
4210 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4211
4212 /* Configure the Channel 4 in PWM mode */
4213 TIM_OC4_SetConfig(htim->Instance, sConfig);
4214
4215 /* Set the Preload enable bit for channel4 */
4216 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
4217
4218 /* Configure the Output Fast mode */
4219 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
4220 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
4221 break;
4222 }
4223
4224 case TIM_CHANNEL_5:
4225 {
4226 /* Check the parameters */
4227 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4228
4229 /* Configure the Channel 5 in PWM mode */
4230 TIM_OC5_SetConfig(htim->Instance, sConfig);
4231
4232 /* Set the Preload enable bit for channel5*/
4233 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
4234
4235 /* Configure the Output Fast mode */
4236 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
4237 htim->Instance->CCMR3 |= sConfig->OCFastMode;
4238 break;
4239 }
4240
4241 case TIM_CHANNEL_6:
4242 {
4243 /* Check the parameters */
4244 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4245
4246 /* Configure the Channel 6 in PWM mode */
4247 TIM_OC6_SetConfig(htim->Instance, sConfig);
4248
4249 /* Set the Preload enable bit for channel6 */
4250 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
4251
4252 /* Configure the Output Fast mode */
4253 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
4254 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
4255 break;
4256 }
4257
4258 default:
4259 break;
4260 }
4261
4262 __HAL_UNLOCK(htim);
4263
4264 return HAL_OK;
4265 }
4266
4267 /**
4268 * @brief Initializes the TIM One Pulse Channels according to the specified
4269 * parameters in the TIM_OnePulse_InitTypeDef.
4270 * @param htim TIM One Pulse handle
4271 * @param sConfig TIM One Pulse configuration structure
4272 * @param OutputChannel TIM output channel to configure
4273 * This parameter can be one of the following values:
4274 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4275 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4276 * @param InputChannel TIM input Channel to configure
4277 * This parameter can be one of the following values:
4278 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4279 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4280 * @note To output a waveform with a minimum delay user can enable the fast
4281 * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
4282 * output is forced in response to the edge detection on TIx input,
4283 * without taking in account the comparison.
4284 * @retval HAL status
4285 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)4286 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
4287 uint32_t OutputChannel, uint32_t InputChannel)
4288 {
4289 TIM_OC_InitTypeDef temp1;
4290
4291 /* Check the parameters */
4292 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
4293 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
4294
4295 if (OutputChannel != InputChannel)
4296 {
4297 /* Process Locked */
4298 __HAL_LOCK(htim);
4299
4300 htim->State = HAL_TIM_STATE_BUSY;
4301
4302 /* Extract the Output compare configuration from sConfig structure */
4303 temp1.OCMode = sConfig->OCMode;
4304 temp1.Pulse = sConfig->Pulse;
4305 temp1.OCPolarity = sConfig->OCPolarity;
4306 temp1.OCNPolarity = sConfig->OCNPolarity;
4307 temp1.OCIdleState = sConfig->OCIdleState;
4308 temp1.OCNIdleState = sConfig->OCNIdleState;
4309
4310 switch (OutputChannel)
4311 {
4312 case TIM_CHANNEL_1:
4313 {
4314 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4315
4316 TIM_OC1_SetConfig(htim->Instance, &temp1);
4317 break;
4318 }
4319 case TIM_CHANNEL_2:
4320 {
4321 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4322
4323 TIM_OC2_SetConfig(htim->Instance, &temp1);
4324 break;
4325 }
4326 default:
4327 break;
4328 }
4329
4330 switch (InputChannel)
4331 {
4332 case TIM_CHANNEL_1:
4333 {
4334 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4335
4336 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
4337 sConfig->ICSelection, sConfig->ICFilter);
4338
4339 /* Reset the IC1PSC Bits */
4340 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4341
4342 /* Select the Trigger source */
4343 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4344 htim->Instance->SMCR |= TIM_TS_TI1FP1;
4345
4346 /* Select the Slave Mode */
4347 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4348 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4349 break;
4350 }
4351 case TIM_CHANNEL_2:
4352 {
4353 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4354
4355 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
4356 sConfig->ICSelection, sConfig->ICFilter);
4357
4358 /* Reset the IC2PSC Bits */
4359 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4360
4361 /* Select the Trigger source */
4362 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4363 htim->Instance->SMCR |= TIM_TS_TI2FP2;
4364
4365 /* Select the Slave Mode */
4366 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4367 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4368 break;
4369 }
4370
4371 default:
4372 break;
4373 }
4374
4375 htim->State = HAL_TIM_STATE_READY;
4376
4377 __HAL_UNLOCK(htim);
4378
4379 return HAL_OK;
4380 }
4381 else
4382 {
4383 return HAL_ERROR;
4384 }
4385 }
4386
4387 /**
4388 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
4389 * @param htim TIM handle
4390 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4391 * This parameter can be one of the following values:
4392 * @arg TIM_DMABASE_CR1
4393 * @arg TIM_DMABASE_CR2
4394 * @arg TIM_DMABASE_SMCR
4395 * @arg TIM_DMABASE_DIER
4396 * @arg TIM_DMABASE_SR
4397 * @arg TIM_DMABASE_EGR
4398 * @arg TIM_DMABASE_CCMR1
4399 * @arg TIM_DMABASE_CCMR2
4400 * @arg TIM_DMABASE_CCER
4401 * @arg TIM_DMABASE_CNT
4402 * @arg TIM_DMABASE_PSC
4403 * @arg TIM_DMABASE_ARR
4404 * @arg TIM_DMABASE_RCR
4405 * @arg TIM_DMABASE_CCR1
4406 * @arg TIM_DMABASE_CCR2
4407 * @arg TIM_DMABASE_CCR3
4408 * @arg TIM_DMABASE_CCR4
4409 * @arg TIM_DMABASE_BDTR
4410 * @arg TIM_DMABASE_OR1
4411 * @arg TIM_DMABASE_CCMR3
4412 * @arg TIM_DMABASE_CCR5
4413 * @arg TIM_DMABASE_CCR6
4414 * @arg TIM_DMABASE_OR2
4415 * @arg TIM_DMABASE_OR3
4416 * @param BurstRequestSrc TIM DMA Request sources
4417 * This parameter can be one of the following values:
4418 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4419 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4420 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4421 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4422 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4423 * @arg TIM_DMA_COM: TIM Commutation DMA source
4424 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4425 * @param BurstBuffer The Buffer address.
4426 * @param BurstLength DMA Burst length. This parameter can be one value
4427 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4428 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4429 * @retval HAL status
4430 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4431 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4432 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4433 {
4434 return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4435 ((BurstLength) >> 8U) + 1U);
4436 }
4437
4438 /**
4439 * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
4440 * @param htim TIM handle
4441 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4442 * This parameter can be one of the following values:
4443 * @arg TIM_DMABASE_CR1
4444 * @arg TIM_DMABASE_CR2
4445 * @arg TIM_DMABASE_SMCR
4446 * @arg TIM_DMABASE_DIER
4447 * @arg TIM_DMABASE_SR
4448 * @arg TIM_DMABASE_EGR
4449 * @arg TIM_DMABASE_CCMR1
4450 * @arg TIM_DMABASE_CCMR2
4451 * @arg TIM_DMABASE_CCER
4452 * @arg TIM_DMABASE_CNT
4453 * @arg TIM_DMABASE_PSC
4454 * @arg TIM_DMABASE_ARR
4455 * @arg TIM_DMABASE_RCR
4456 * @arg TIM_DMABASE_CCR1
4457 * @arg TIM_DMABASE_CCR2
4458 * @arg TIM_DMABASE_CCR3
4459 * @arg TIM_DMABASE_CCR4
4460 * @arg TIM_DMABASE_BDTR
4461 * @arg TIM_DMABASE_OR1
4462 * @arg TIM_DMABASE_CCMR3
4463 * @arg TIM_DMABASE_CCR5
4464 * @arg TIM_DMABASE_CCR6
4465 * @arg TIM_DMABASE_OR2
4466 * @arg TIM_DMABASE_OR3
4467 * @param BurstRequestSrc TIM DMA Request sources
4468 * This parameter can be one of the following values:
4469 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4470 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4471 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4472 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4473 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4474 * @arg TIM_DMA_COM: TIM Commutation DMA source
4475 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4476 * @param BurstBuffer The Buffer address.
4477 * @param BurstLength DMA Burst length. This parameter can be one value
4478 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4479 * @param DataLength Data length. This parameter can be one value
4480 * between 1 and 0xFFFF.
4481 * @retval HAL status
4482 */
HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4483 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4484 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
4485 uint32_t BurstLength, uint32_t DataLength)
4486 {
4487 /* Check the parameters */
4488 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4489 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4490 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4491 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4492 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4493
4494 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4495 {
4496 return HAL_BUSY;
4497 }
4498 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4499 {
4500 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4501 {
4502 return HAL_ERROR;
4503 }
4504 else
4505 {
4506 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4507 }
4508 }
4509 else
4510 {
4511 /* nothing to do */
4512 }
4513 switch (BurstRequestSrc)
4514 {
4515 case TIM_DMA_UPDATE:
4516 {
4517 /* Set the DMA Period elapsed callbacks */
4518 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4519 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4520
4521 /* Set the DMA error callback */
4522 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4523
4524 /* Enable the DMA channel */
4525 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
4526 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4527 {
4528 return HAL_ERROR;
4529 }
4530 break;
4531 }
4532 case TIM_DMA_CC1:
4533 {
4534 /* Set the DMA compare callbacks */
4535 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
4536 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4537
4538 /* Set the DMA error callback */
4539 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4540
4541 /* Enable the DMA channel */
4542 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
4543 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4544 {
4545 return HAL_ERROR;
4546 }
4547 break;
4548 }
4549 case TIM_DMA_CC2:
4550 {
4551 /* Set the DMA compare callbacks */
4552 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
4553 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4554
4555 /* Set the DMA error callback */
4556 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4557
4558 /* Enable the DMA channel */
4559 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
4560 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4561 {
4562 return HAL_ERROR;
4563 }
4564 break;
4565 }
4566 case TIM_DMA_CC3:
4567 {
4568 /* Set the DMA compare callbacks */
4569 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
4570 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4571
4572 /* Set the DMA error callback */
4573 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4574
4575 /* Enable the DMA channel */
4576 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4577 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4578 {
4579 return HAL_ERROR;
4580 }
4581 break;
4582 }
4583 case TIM_DMA_CC4:
4584 {
4585 /* Set the DMA compare callbacks */
4586 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4587 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4588
4589 /* Set the DMA error callback */
4590 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4591
4592 /* Enable the DMA channel */
4593 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4594 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4595 {
4596 return HAL_ERROR;
4597 }
4598 break;
4599 }
4600 case TIM_DMA_COM:
4601 {
4602 /* Set the DMA commutation callbacks */
4603 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4604 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4605
4606 /* Set the DMA error callback */
4607 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4608
4609 /* Enable the DMA channel */
4610 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
4611 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4612 {
4613 return HAL_ERROR;
4614 }
4615 break;
4616 }
4617 case TIM_DMA_TRIGGER:
4618 {
4619 /* Set the DMA trigger callbacks */
4620 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4621 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4622
4623 /* Set the DMA error callback */
4624 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4625
4626 /* Enable the DMA channel */
4627 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4628 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4629 {
4630 return HAL_ERROR;
4631 }
4632 break;
4633 }
4634 default:
4635 break;
4636 }
4637
4638 /* Configure the DMA Burst Mode */
4639 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4640 /* Enable the TIM DMA Request */
4641 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4642
4643 /* Return function status */
4644 return HAL_OK;
4645 }
4646
4647 /**
4648 * @brief Stops the TIM DMA Burst mode
4649 * @param htim TIM handle
4650 * @param BurstRequestSrc TIM DMA Request sources to disable
4651 * @retval HAL status
4652 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4653 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4654 {
4655 HAL_StatusTypeDef status = HAL_OK;
4656 /* Check the parameters */
4657 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4658
4659 /* Abort the DMA transfer (at least disable the DMA channel) */
4660 switch (BurstRequestSrc)
4661 {
4662 case TIM_DMA_UPDATE:
4663 {
4664 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4665 break;
4666 }
4667 case TIM_DMA_CC1:
4668 {
4669 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4670 break;
4671 }
4672 case TIM_DMA_CC2:
4673 {
4674 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4675 break;
4676 }
4677 case TIM_DMA_CC3:
4678 {
4679 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4680 break;
4681 }
4682 case TIM_DMA_CC4:
4683 {
4684 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4685 break;
4686 }
4687 case TIM_DMA_COM:
4688 {
4689 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4690 break;
4691 }
4692 case TIM_DMA_TRIGGER:
4693 {
4694 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4695 break;
4696 }
4697 default:
4698 break;
4699 }
4700
4701 if (HAL_OK == status)
4702 {
4703 /* Disable the TIM Update DMA request */
4704 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4705 }
4706
4707 /* Change the DMA burst operation state */
4708 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
4709
4710 /* Return function status */
4711 return status;
4712 }
4713
4714 /**
4715 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4716 * @param htim TIM handle
4717 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4718 * This parameter can be one of the following values:
4719 * @arg TIM_DMABASE_CR1
4720 * @arg TIM_DMABASE_CR2
4721 * @arg TIM_DMABASE_SMCR
4722 * @arg TIM_DMABASE_DIER
4723 * @arg TIM_DMABASE_SR
4724 * @arg TIM_DMABASE_EGR
4725 * @arg TIM_DMABASE_CCMR1
4726 * @arg TIM_DMABASE_CCMR2
4727 * @arg TIM_DMABASE_CCER
4728 * @arg TIM_DMABASE_CNT
4729 * @arg TIM_DMABASE_PSC
4730 * @arg TIM_DMABASE_ARR
4731 * @arg TIM_DMABASE_RCR
4732 * @arg TIM_DMABASE_CCR1
4733 * @arg TIM_DMABASE_CCR2
4734 * @arg TIM_DMABASE_CCR3
4735 * @arg TIM_DMABASE_CCR4
4736 * @arg TIM_DMABASE_BDTR
4737 * @arg TIM_DMABASE_OR1
4738 * @arg TIM_DMABASE_CCMR3
4739 * @arg TIM_DMABASE_CCR5
4740 * @arg TIM_DMABASE_CCR6
4741 * @arg TIM_DMABASE_OR2
4742 * @arg TIM_DMABASE_OR3
4743 * @param BurstRequestSrc TIM DMA Request sources
4744 * This parameter can be one of the following values:
4745 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4746 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4747 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4748 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4749 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4750 * @arg TIM_DMA_COM: TIM Commutation DMA source
4751 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4752 * @param BurstBuffer The Buffer address.
4753 * @param BurstLength DMA Burst length. This parameter can be one value
4754 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4755 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4756 * @retval HAL status
4757 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4758 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4759 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4760 {
4761 return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4762 ((BurstLength) >> 8U) + 1U);
4763 }
4764
4765 /**
4766 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4767 * @param htim TIM handle
4768 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4769 * This parameter can be one of the following values:
4770 * @arg TIM_DMABASE_CR1
4771 * @arg TIM_DMABASE_CR2
4772 * @arg TIM_DMABASE_SMCR
4773 * @arg TIM_DMABASE_DIER
4774 * @arg TIM_DMABASE_SR
4775 * @arg TIM_DMABASE_EGR
4776 * @arg TIM_DMABASE_CCMR1
4777 * @arg TIM_DMABASE_CCMR2
4778 * @arg TIM_DMABASE_CCER
4779 * @arg TIM_DMABASE_CNT
4780 * @arg TIM_DMABASE_PSC
4781 * @arg TIM_DMABASE_ARR
4782 * @arg TIM_DMABASE_RCR
4783 * @arg TIM_DMABASE_CCR1
4784 * @arg TIM_DMABASE_CCR2
4785 * @arg TIM_DMABASE_CCR3
4786 * @arg TIM_DMABASE_CCR4
4787 * @arg TIM_DMABASE_BDTR
4788 * @arg TIM_DMABASE_OR1
4789 * @arg TIM_DMABASE_CCMR3
4790 * @arg TIM_DMABASE_CCR5
4791 * @arg TIM_DMABASE_CCR6
4792 * @arg TIM_DMABASE_OR2
4793 * @arg TIM_DMABASE_OR3
4794 * @param BurstRequestSrc TIM DMA Request sources
4795 * This parameter can be one of the following values:
4796 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4797 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4798 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4799 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4800 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4801 * @arg TIM_DMA_COM: TIM Commutation DMA source
4802 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4803 * @param BurstBuffer The Buffer address.
4804 * @param BurstLength DMA Burst length. This parameter can be one value
4805 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4806 * @param DataLength Data length. This parameter can be one value
4807 * between 1 and 0xFFFF.
4808 * @retval HAL status
4809 */
HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4810 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4811 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
4812 uint32_t BurstLength, uint32_t DataLength)
4813 {
4814 /* Check the parameters */
4815 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4816 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4817 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4818 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4819 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4820
4821 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4822 {
4823 return HAL_BUSY;
4824 }
4825 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4826 {
4827 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4828 {
4829 return HAL_ERROR;
4830 }
4831 else
4832 {
4833 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4834 }
4835 }
4836 else
4837 {
4838 /* nothing to do */
4839 }
4840 switch (BurstRequestSrc)
4841 {
4842 case TIM_DMA_UPDATE:
4843 {
4844 /* Set the DMA Period elapsed callbacks */
4845 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4846 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4847
4848 /* Set the DMA error callback */
4849 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4850
4851 /* Enable the DMA channel */
4852 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4853 DataLength) != HAL_OK)
4854 {
4855 return HAL_ERROR;
4856 }
4857 break;
4858 }
4859 case TIM_DMA_CC1:
4860 {
4861 /* Set the DMA capture callbacks */
4862 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
4863 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4864
4865 /* Set the DMA error callback */
4866 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4867
4868 /* Enable the DMA channel */
4869 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4870 DataLength) != HAL_OK)
4871 {
4872 return HAL_ERROR;
4873 }
4874 break;
4875 }
4876 case TIM_DMA_CC2:
4877 {
4878 /* Set the DMA capture callbacks */
4879 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
4880 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4881
4882 /* Set the DMA error callback */
4883 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4884
4885 /* Enable the DMA channel */
4886 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4887 DataLength) != HAL_OK)
4888 {
4889 return HAL_ERROR;
4890 }
4891 break;
4892 }
4893 case TIM_DMA_CC3:
4894 {
4895 /* Set the DMA capture callbacks */
4896 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
4897 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4898
4899 /* Set the DMA error callback */
4900 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4901
4902 /* Enable the DMA channel */
4903 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4904 DataLength) != HAL_OK)
4905 {
4906 return HAL_ERROR;
4907 }
4908 break;
4909 }
4910 case TIM_DMA_CC4:
4911 {
4912 /* Set the DMA capture callbacks */
4913 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
4914 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4915
4916 /* Set the DMA error callback */
4917 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4918
4919 /* Enable the DMA channel */
4920 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4921 DataLength) != HAL_OK)
4922 {
4923 return HAL_ERROR;
4924 }
4925 break;
4926 }
4927 case TIM_DMA_COM:
4928 {
4929 /* Set the DMA commutation callbacks */
4930 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4931 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4932
4933 /* Set the DMA error callback */
4934 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4935
4936 /* Enable the DMA channel */
4937 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4938 DataLength) != HAL_OK)
4939 {
4940 return HAL_ERROR;
4941 }
4942 break;
4943 }
4944 case TIM_DMA_TRIGGER:
4945 {
4946 /* Set the DMA trigger callbacks */
4947 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4948 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4949
4950 /* Set the DMA error callback */
4951 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4952
4953 /* Enable the DMA channel */
4954 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4955 DataLength) != HAL_OK)
4956 {
4957 return HAL_ERROR;
4958 }
4959 break;
4960 }
4961 default:
4962 break;
4963 }
4964
4965 /* Configure the DMA Burst Mode */
4966 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4967
4968 /* Enable the TIM DMA Request */
4969 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4970
4971 /* Return function status */
4972 return HAL_OK;
4973 }
4974
4975 /**
4976 * @brief Stop the DMA burst reading
4977 * @param htim TIM handle
4978 * @param BurstRequestSrc TIM DMA Request sources to disable.
4979 * @retval HAL status
4980 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4981 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4982 {
4983 HAL_StatusTypeDef status = HAL_OK;
4984 /* Check the parameters */
4985 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4986
4987 /* Abort the DMA transfer (at least disable the DMA channel) */
4988 switch (BurstRequestSrc)
4989 {
4990 case TIM_DMA_UPDATE:
4991 {
4992 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4993 break;
4994 }
4995 case TIM_DMA_CC1:
4996 {
4997 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4998 break;
4999 }
5000 case TIM_DMA_CC2:
5001 {
5002 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
5003 break;
5004 }
5005 case TIM_DMA_CC3:
5006 {
5007 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
5008 break;
5009 }
5010 case TIM_DMA_CC4:
5011 {
5012 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
5013 break;
5014 }
5015 case TIM_DMA_COM:
5016 {
5017 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
5018 break;
5019 }
5020 case TIM_DMA_TRIGGER:
5021 {
5022 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
5023 break;
5024 }
5025 default:
5026 break;
5027 }
5028
5029 if (HAL_OK == status)
5030 {
5031 /* Disable the TIM Update DMA request */
5032 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
5033 }
5034
5035 /* Change the DMA burst operation state */
5036 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
5037
5038 /* Return function status */
5039 return status;
5040 }
5041
5042 /**
5043 * @brief Generate a software event
5044 * @param htim TIM handle
5045 * @param EventSource specifies the event source.
5046 * This parameter can be one of the following values:
5047 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
5048 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
5049 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
5050 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
5051 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
5052 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
5053 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
5054 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
5055 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
5056 * @note Basic timers can only generate an update event.
5057 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
5058 * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
5059 * only for timer instances supporting break input(s).
5060 * @retval HAL status
5061 */
5062
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)5063 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
5064 {
5065 /* Check the parameters */
5066 assert_param(IS_TIM_INSTANCE(htim->Instance));
5067 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
5068
5069 /* Process Locked */
5070 __HAL_LOCK(htim);
5071
5072 /* Change the TIM state */
5073 htim->State = HAL_TIM_STATE_BUSY;
5074
5075 /* Set the event sources */
5076 htim->Instance->EGR = EventSource;
5077
5078 /* Change the TIM state */
5079 htim->State = HAL_TIM_STATE_READY;
5080
5081 __HAL_UNLOCK(htim);
5082
5083 /* Return function status */
5084 return HAL_OK;
5085 }
5086
5087 /**
5088 * @brief Configures the OCRef clear feature
5089 * @param htim TIM handle
5090 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
5091 * contains the OCREF clear feature and parameters for the TIM peripheral.
5092 * @param Channel specifies the TIM Channel
5093 * This parameter can be one of the following values:
5094 * @arg TIM_CHANNEL_1: TIM Channel 1
5095 * @arg TIM_CHANNEL_2: TIM Channel 2
5096 * @arg TIM_CHANNEL_3: TIM Channel 3
5097 * @arg TIM_CHANNEL_4: TIM Channel 4
5098 * @arg TIM_CHANNEL_5: TIM Channel 5
5099 * @arg TIM_CHANNEL_6: TIM Channel 6
5100 * @retval HAL status
5101 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)5102 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
5103 TIM_ClearInputConfigTypeDef *sClearInputConfig,
5104 uint32_t Channel)
5105 {
5106 /* Check the parameters */
5107 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
5108 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
5109
5110 /* Process Locked */
5111 __HAL_LOCK(htim);
5112
5113 htim->State = HAL_TIM_STATE_BUSY;
5114
5115 switch (sClearInputConfig->ClearInputSource)
5116 {
5117 case TIM_CLEARINPUTSOURCE_NONE:
5118 {
5119 /* Clear the OCREF clear selection bit and the the ETR Bits */
5120 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5121 break;
5122 }
5123 case TIM_CLEARINPUTSOURCE_OCREFCLR:
5124 {
5125 /* Clear the OCREF clear selection bit */
5126 CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
5127 }
5128 break;
5129
5130 case TIM_CLEARINPUTSOURCE_ETR:
5131 {
5132 /* Check the parameters */
5133 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
5134 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
5135 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
5136
5137 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
5138 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
5139 {
5140 htim->State = HAL_TIM_STATE_READY;
5141 __HAL_UNLOCK(htim);
5142 return HAL_ERROR;
5143 }
5144
5145 TIM_ETR_SetConfig(htim->Instance,
5146 sClearInputConfig->ClearInputPrescaler,
5147 sClearInputConfig->ClearInputPolarity,
5148 sClearInputConfig->ClearInputFilter);
5149
5150 /* Set the OCREF clear selection bit */
5151 SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
5152 break;
5153 }
5154
5155 default:
5156 break;
5157 }
5158
5159 switch (Channel)
5160 {
5161 case TIM_CHANNEL_1:
5162 {
5163 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5164 {
5165 /* Enable the OCREF clear feature for Channel 1 */
5166 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5167 }
5168 else
5169 {
5170 /* Disable the OCREF clear feature for Channel 1 */
5171 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5172 }
5173 break;
5174 }
5175 case TIM_CHANNEL_2:
5176 {
5177 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5178 {
5179 /* Enable the OCREF clear feature for Channel 2 */
5180 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5181 }
5182 else
5183 {
5184 /* Disable the OCREF clear feature for Channel 2 */
5185 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5186 }
5187 break;
5188 }
5189 case TIM_CHANNEL_3:
5190 {
5191 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5192 {
5193 /* Enable the OCREF clear feature for Channel 3 */
5194 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5195 }
5196 else
5197 {
5198 /* Disable the OCREF clear feature for Channel 3 */
5199 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5200 }
5201 break;
5202 }
5203 case TIM_CHANNEL_4:
5204 {
5205 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5206 {
5207 /* Enable the OCREF clear feature for Channel 4 */
5208 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5209 }
5210 else
5211 {
5212 /* Disable the OCREF clear feature for Channel 4 */
5213 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5214 }
5215 break;
5216 }
5217 case TIM_CHANNEL_5:
5218 {
5219 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5220 {
5221 /* Enable the OCREF clear feature for Channel 5 */
5222 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5223 }
5224 else
5225 {
5226 /* Disable the OCREF clear feature for Channel 5 */
5227 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5228 }
5229 break;
5230 }
5231 case TIM_CHANNEL_6:
5232 {
5233 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5234 {
5235 /* Enable the OCREF clear feature for Channel 6 */
5236 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5237 }
5238 else
5239 {
5240 /* Disable the OCREF clear feature for Channel 6 */
5241 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5242 }
5243 break;
5244 }
5245 default:
5246 break;
5247 }
5248
5249 htim->State = HAL_TIM_STATE_READY;
5250
5251 __HAL_UNLOCK(htim);
5252
5253 return HAL_OK;
5254 }
5255
5256 /**
5257 * @brief Configures the clock source to be used
5258 * @param htim TIM handle
5259 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
5260 * contains the clock source information for the TIM peripheral.
5261 * @retval HAL status
5262 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,TIM_ClockConfigTypeDef * sClockSourceConfig)5263 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
5264 {
5265 uint32_t tmpsmcr;
5266
5267 /* Process Locked */
5268 __HAL_LOCK(htim);
5269
5270 htim->State = HAL_TIM_STATE_BUSY;
5271
5272 /* Check the parameters */
5273 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
5274
5275 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
5276 tmpsmcr = htim->Instance->SMCR;
5277 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
5278 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5279 htim->Instance->SMCR = tmpsmcr;
5280
5281 switch (sClockSourceConfig->ClockSource)
5282 {
5283 case TIM_CLOCKSOURCE_INTERNAL:
5284 {
5285 assert_param(IS_TIM_INSTANCE(htim->Instance));
5286 break;
5287 }
5288
5289 case TIM_CLOCKSOURCE_ETRMODE1:
5290 {
5291 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
5292 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
5293
5294 /* Check ETR input conditioning related parameters */
5295 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5296 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5297 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5298
5299 /* Configure the ETR Clock source */
5300 TIM_ETR_SetConfig(htim->Instance,
5301 sClockSourceConfig->ClockPrescaler,
5302 sClockSourceConfig->ClockPolarity,
5303 sClockSourceConfig->ClockFilter);
5304
5305 /* Select the External clock mode1 and the ETRF trigger */
5306 tmpsmcr = htim->Instance->SMCR;
5307 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
5308 /* Write to TIMx SMCR */
5309 htim->Instance->SMCR = tmpsmcr;
5310 break;
5311 }
5312
5313 case TIM_CLOCKSOURCE_ETRMODE2:
5314 {
5315 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
5316 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
5317
5318 /* Check ETR input conditioning related parameters */
5319 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5320 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5321 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5322
5323 /* Configure the ETR Clock source */
5324 TIM_ETR_SetConfig(htim->Instance,
5325 sClockSourceConfig->ClockPrescaler,
5326 sClockSourceConfig->ClockPolarity,
5327 sClockSourceConfig->ClockFilter);
5328 /* Enable the External clock mode2 */
5329 htim->Instance->SMCR |= TIM_SMCR_ECE;
5330 break;
5331 }
5332
5333 case TIM_CLOCKSOURCE_TI1:
5334 {
5335 /* Check whether or not the timer instance supports external clock mode 1 */
5336 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5337
5338 /* Check TI1 input conditioning related parameters */
5339 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5340 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5341
5342 TIM_TI1_ConfigInputStage(htim->Instance,
5343 sClockSourceConfig->ClockPolarity,
5344 sClockSourceConfig->ClockFilter);
5345 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
5346 break;
5347 }
5348
5349 case TIM_CLOCKSOURCE_TI2:
5350 {
5351 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
5352 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5353
5354 /* Check TI2 input conditioning related parameters */
5355 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5356 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5357
5358 TIM_TI2_ConfigInputStage(htim->Instance,
5359 sClockSourceConfig->ClockPolarity,
5360 sClockSourceConfig->ClockFilter);
5361 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
5362 break;
5363 }
5364
5365 case TIM_CLOCKSOURCE_TI1ED:
5366 {
5367 /* Check whether or not the timer instance supports external clock mode 1 */
5368 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5369
5370 /* Check TI1 input conditioning related parameters */
5371 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5372 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5373
5374 TIM_TI1_ConfigInputStage(htim->Instance,
5375 sClockSourceConfig->ClockPolarity,
5376 sClockSourceConfig->ClockFilter);
5377 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
5378 break;
5379 }
5380
5381 case TIM_CLOCKSOURCE_ITR0:
5382 case TIM_CLOCKSOURCE_ITR1:
5383 case TIM_CLOCKSOURCE_ITR2:
5384 case TIM_CLOCKSOURCE_ITR3:
5385 {
5386 /* Check whether or not the timer instance supports internal trigger input */
5387 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
5388
5389 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
5390 break;
5391 }
5392
5393 default:
5394 break;
5395 }
5396 htim->State = HAL_TIM_STATE_READY;
5397
5398 __HAL_UNLOCK(htim);
5399
5400 return HAL_OK;
5401 }
5402
5403 /**
5404 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
5405 * or a XOR combination between CH1_input, CH2_input & CH3_input
5406 * @param htim TIM handle.
5407 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
5408 * output of a XOR gate.
5409 * This parameter can be one of the following values:
5410 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
5411 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
5412 * pins are connected to the TI1 input (XOR combination)
5413 * @retval HAL status
5414 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)5415 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
5416 {
5417 uint32_t tmpcr2;
5418
5419 /* Check the parameters */
5420 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
5421 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
5422
5423 /* Get the TIMx CR2 register value */
5424 tmpcr2 = htim->Instance->CR2;
5425
5426 /* Reset the TI1 selection */
5427 tmpcr2 &= ~TIM_CR2_TI1S;
5428
5429 /* Set the TI1 selection */
5430 tmpcr2 |= TI1_Selection;
5431
5432 /* Write to TIMxCR2 */
5433 htim->Instance->CR2 = tmpcr2;
5434
5435 return HAL_OK;
5436 }
5437
5438 /**
5439 * @brief Configures the TIM in Slave mode
5440 * @param htim TIM handle.
5441 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5442 * contains the selected trigger (internal trigger input, filtered
5443 * timer input or external trigger input) and the Slave mode
5444 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5445 * @retval HAL status
5446 */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)5447 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
5448 {
5449 /* Check the parameters */
5450 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5451 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5452 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5453
5454 __HAL_LOCK(htim);
5455
5456 htim->State = HAL_TIM_STATE_BUSY;
5457
5458 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5459 {
5460 htim->State = HAL_TIM_STATE_READY;
5461 __HAL_UNLOCK(htim);
5462 return HAL_ERROR;
5463 }
5464
5465 /* Disable Trigger Interrupt */
5466 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
5467
5468 /* Disable Trigger DMA request */
5469 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5470
5471 htim->State = HAL_TIM_STATE_READY;
5472
5473 __HAL_UNLOCK(htim);
5474
5475 return HAL_OK;
5476 }
5477
5478 /**
5479 * @brief Configures the TIM in Slave mode in interrupt mode
5480 * @param htim TIM handle.
5481 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5482 * contains the selected trigger (internal trigger input, filtered
5483 * timer input or external trigger input) and the Slave mode
5484 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5485 * @retval HAL status
5486 */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)5487 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
5488 TIM_SlaveConfigTypeDef *sSlaveConfig)
5489 {
5490 /* Check the parameters */
5491 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5492 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5493 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5494
5495 __HAL_LOCK(htim);
5496
5497 htim->State = HAL_TIM_STATE_BUSY;
5498
5499 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5500 {
5501 htim->State = HAL_TIM_STATE_READY;
5502 __HAL_UNLOCK(htim);
5503 return HAL_ERROR;
5504 }
5505
5506 /* Enable Trigger Interrupt */
5507 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
5508
5509 /* Disable Trigger DMA request */
5510 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5511
5512 htim->State = HAL_TIM_STATE_READY;
5513
5514 __HAL_UNLOCK(htim);
5515
5516 return HAL_OK;
5517 }
5518
5519 /**
5520 * @brief Read the captured value from Capture Compare unit
5521 * @param htim TIM handle.
5522 * @param Channel TIM Channels to be enabled
5523 * This parameter can be one of the following values:
5524 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
5525 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
5526 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
5527 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
5528 * @retval Captured value
5529 */
HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef * htim,uint32_t Channel)5530 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
5531 {
5532 uint32_t tmpreg = 0U;
5533
5534 switch (Channel)
5535 {
5536 case TIM_CHANNEL_1:
5537 {
5538 /* Check the parameters */
5539 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5540
5541 /* Return the capture 1 value */
5542 tmpreg = htim->Instance->CCR1;
5543
5544 break;
5545 }
5546 case TIM_CHANNEL_2:
5547 {
5548 /* Check the parameters */
5549 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5550
5551 /* Return the capture 2 value */
5552 tmpreg = htim->Instance->CCR2;
5553
5554 break;
5555 }
5556
5557 case TIM_CHANNEL_3:
5558 {
5559 /* Check the parameters */
5560 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
5561
5562 /* Return the capture 3 value */
5563 tmpreg = htim->Instance->CCR3;
5564
5565 break;
5566 }
5567
5568 case TIM_CHANNEL_4:
5569 {
5570 /* Check the parameters */
5571 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
5572
5573 /* Return the capture 4 value */
5574 tmpreg = htim->Instance->CCR4;
5575
5576 break;
5577 }
5578
5579 default:
5580 break;
5581 }
5582
5583 return tmpreg;
5584 }
5585
5586 /**
5587 * @}
5588 */
5589
5590 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
5591 * @brief TIM Callbacks functions
5592 *
5593 @verbatim
5594 ==============================================================================
5595 ##### TIM Callbacks functions #####
5596 ==============================================================================
5597 [..]
5598 This section provides TIM callback functions:
5599 (+) TIM Period elapsed callback
5600 (+) TIM Output Compare callback
5601 (+) TIM Input capture callback
5602 (+) TIM Trigger callback
5603 (+) TIM Error callback
5604
5605 @endverbatim
5606 * @{
5607 */
5608
5609 /**
5610 * @brief Period elapsed callback in non-blocking mode
5611 * @param htim TIM handle
5612 * @retval None
5613 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)5614 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
5615 {
5616 /* Prevent unused argument(s) compilation warning */
5617 UNUSED(htim);
5618
5619 /* NOTE : This function should not be modified, when the callback is needed,
5620 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
5621 */
5622 }
5623
5624 /**
5625 * @brief Period elapsed half complete callback in non-blocking mode
5626 * @param htim TIM handle
5627 * @retval None
5628 */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)5629 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
5630 {
5631 /* Prevent unused argument(s) compilation warning */
5632 UNUSED(htim);
5633
5634 /* NOTE : This function should not be modified, when the callback is needed,
5635 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
5636 */
5637 }
5638
5639 /**
5640 * @brief Output Compare callback in non-blocking mode
5641 * @param htim TIM OC handle
5642 * @retval None
5643 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)5644 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
5645 {
5646 /* Prevent unused argument(s) compilation warning */
5647 UNUSED(htim);
5648
5649 /* NOTE : This function should not be modified, when the callback is needed,
5650 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
5651 */
5652 }
5653
5654 /**
5655 * @brief Input Capture callback in non-blocking mode
5656 * @param htim TIM IC handle
5657 * @retval None
5658 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)5659 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
5660 {
5661 /* Prevent unused argument(s) compilation warning */
5662 UNUSED(htim);
5663
5664 /* NOTE : This function should not be modified, when the callback is needed,
5665 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
5666 */
5667 }
5668
5669 /**
5670 * @brief Input Capture half complete callback in non-blocking mode
5671 * @param htim TIM IC handle
5672 * @retval None
5673 */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)5674 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
5675 {
5676 /* Prevent unused argument(s) compilation warning */
5677 UNUSED(htim);
5678
5679 /* NOTE : This function should not be modified, when the callback is needed,
5680 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
5681 */
5682 }
5683
5684 /**
5685 * @brief PWM Pulse finished callback in non-blocking mode
5686 * @param htim TIM handle
5687 * @retval None
5688 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)5689 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
5690 {
5691 /* Prevent unused argument(s) compilation warning */
5692 UNUSED(htim);
5693
5694 /* NOTE : This function should not be modified, when the callback is needed,
5695 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
5696 */
5697 }
5698
5699 /**
5700 * @brief PWM Pulse finished half complete callback in non-blocking mode
5701 * @param htim TIM handle
5702 * @retval None
5703 */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)5704 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
5705 {
5706 /* Prevent unused argument(s) compilation warning */
5707 UNUSED(htim);
5708
5709 /* NOTE : This function should not be modified, when the callback is needed,
5710 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
5711 */
5712 }
5713
5714 /**
5715 * @brief Hall Trigger detection callback in non-blocking mode
5716 * @param htim TIM handle
5717 * @retval None
5718 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)5719 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
5720 {
5721 /* Prevent unused argument(s) compilation warning */
5722 UNUSED(htim);
5723
5724 /* NOTE : This function should not be modified, when the callback is needed,
5725 the HAL_TIM_TriggerCallback could be implemented in the user file
5726 */
5727 }
5728
5729 /**
5730 * @brief Hall Trigger detection half complete callback in non-blocking mode
5731 * @param htim TIM handle
5732 * @retval None
5733 */
HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef * htim)5734 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
5735 {
5736 /* Prevent unused argument(s) compilation warning */
5737 UNUSED(htim);
5738
5739 /* NOTE : This function should not be modified, when the callback is needed,
5740 the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
5741 */
5742 }
5743
5744 /**
5745 * @brief Timer error callback in non-blocking mode
5746 * @param htim TIM handle
5747 * @retval None
5748 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)5749 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
5750 {
5751 /* Prevent unused argument(s) compilation warning */
5752 UNUSED(htim);
5753
5754 /* NOTE : This function should not be modified, when the callback is needed,
5755 the HAL_TIM_ErrorCallback could be implemented in the user file
5756 */
5757 }
5758
5759 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5760 /**
5761 * @brief Register a User TIM callback to be used instead of the weak predefined callback
5762 * @param htim tim handle
5763 * @param CallbackID ID of the callback to be registered
5764 * This parameter can be one of the following values:
5765 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5766 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5767 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5768 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5769 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5770 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5771 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5772 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5773 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5774 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5775 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5776 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5777 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5778 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5779 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5780 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5781 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5782 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5783 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5784 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5785 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5786 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5787 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5788 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5789 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
5790 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
5791 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
5792 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
5793 * @param pCallback pointer to the callback function
5794 * @retval status
5795 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)5796 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
5797 pTIM_CallbackTypeDef pCallback)
5798 {
5799 HAL_StatusTypeDef status = HAL_OK;
5800
5801 if (pCallback == NULL)
5802 {
5803 return HAL_ERROR;
5804 }
5805 /* Process locked */
5806 __HAL_LOCK(htim);
5807
5808 if (htim->State == HAL_TIM_STATE_READY)
5809 {
5810 switch (CallbackID)
5811 {
5812 case HAL_TIM_BASE_MSPINIT_CB_ID :
5813 htim->Base_MspInitCallback = pCallback;
5814 break;
5815
5816 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5817 htim->Base_MspDeInitCallback = pCallback;
5818 break;
5819
5820 case HAL_TIM_IC_MSPINIT_CB_ID :
5821 htim->IC_MspInitCallback = pCallback;
5822 break;
5823
5824 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5825 htim->IC_MspDeInitCallback = pCallback;
5826 break;
5827
5828 case HAL_TIM_OC_MSPINIT_CB_ID :
5829 htim->OC_MspInitCallback = pCallback;
5830 break;
5831
5832 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5833 htim->OC_MspDeInitCallback = pCallback;
5834 break;
5835
5836 case HAL_TIM_PWM_MSPINIT_CB_ID :
5837 htim->PWM_MspInitCallback = pCallback;
5838 break;
5839
5840 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5841 htim->PWM_MspDeInitCallback = pCallback;
5842 break;
5843
5844 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5845 htim->OnePulse_MspInitCallback = pCallback;
5846 break;
5847
5848 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5849 htim->OnePulse_MspDeInitCallback = pCallback;
5850 break;
5851
5852 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5853 htim->Encoder_MspInitCallback = pCallback;
5854 break;
5855
5856 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5857 htim->Encoder_MspDeInitCallback = pCallback;
5858 break;
5859
5860 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5861 htim->HallSensor_MspInitCallback = pCallback;
5862 break;
5863
5864 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5865 htim->HallSensor_MspDeInitCallback = pCallback;
5866 break;
5867
5868 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5869 htim->PeriodElapsedCallback = pCallback;
5870 break;
5871
5872 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
5873 htim->PeriodElapsedHalfCpltCallback = pCallback;
5874 break;
5875
5876 case HAL_TIM_TRIGGER_CB_ID :
5877 htim->TriggerCallback = pCallback;
5878 break;
5879
5880 case HAL_TIM_TRIGGER_HALF_CB_ID :
5881 htim->TriggerHalfCpltCallback = pCallback;
5882 break;
5883
5884 case HAL_TIM_IC_CAPTURE_CB_ID :
5885 htim->IC_CaptureCallback = pCallback;
5886 break;
5887
5888 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
5889 htim->IC_CaptureHalfCpltCallback = pCallback;
5890 break;
5891
5892 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5893 htim->OC_DelayElapsedCallback = pCallback;
5894 break;
5895
5896 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5897 htim->PWM_PulseFinishedCallback = pCallback;
5898 break;
5899
5900 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
5901 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
5902 break;
5903
5904 case HAL_TIM_ERROR_CB_ID :
5905 htim->ErrorCallback = pCallback;
5906 break;
5907
5908 case HAL_TIM_COMMUTATION_CB_ID :
5909 htim->CommutationCallback = pCallback;
5910 break;
5911
5912 case HAL_TIM_COMMUTATION_HALF_CB_ID :
5913 htim->CommutationHalfCpltCallback = pCallback;
5914 break;
5915
5916 case HAL_TIM_BREAK_CB_ID :
5917 htim->BreakCallback = pCallback;
5918 break;
5919
5920 case HAL_TIM_BREAK2_CB_ID :
5921 htim->Break2Callback = pCallback;
5922 break;
5923
5924 default :
5925 /* Return error status */
5926 status = HAL_ERROR;
5927 break;
5928 }
5929 }
5930 else if (htim->State == HAL_TIM_STATE_RESET)
5931 {
5932 switch (CallbackID)
5933 {
5934 case HAL_TIM_BASE_MSPINIT_CB_ID :
5935 htim->Base_MspInitCallback = pCallback;
5936 break;
5937
5938 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5939 htim->Base_MspDeInitCallback = pCallback;
5940 break;
5941
5942 case HAL_TIM_IC_MSPINIT_CB_ID :
5943 htim->IC_MspInitCallback = pCallback;
5944 break;
5945
5946 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5947 htim->IC_MspDeInitCallback = pCallback;
5948 break;
5949
5950 case HAL_TIM_OC_MSPINIT_CB_ID :
5951 htim->OC_MspInitCallback = pCallback;
5952 break;
5953
5954 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5955 htim->OC_MspDeInitCallback = pCallback;
5956 break;
5957
5958 case HAL_TIM_PWM_MSPINIT_CB_ID :
5959 htim->PWM_MspInitCallback = pCallback;
5960 break;
5961
5962 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5963 htim->PWM_MspDeInitCallback = pCallback;
5964 break;
5965
5966 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5967 htim->OnePulse_MspInitCallback = pCallback;
5968 break;
5969
5970 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5971 htim->OnePulse_MspDeInitCallback = pCallback;
5972 break;
5973
5974 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5975 htim->Encoder_MspInitCallback = pCallback;
5976 break;
5977
5978 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5979 htim->Encoder_MspDeInitCallback = pCallback;
5980 break;
5981
5982 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5983 htim->HallSensor_MspInitCallback = pCallback;
5984 break;
5985
5986 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5987 htim->HallSensor_MspDeInitCallback = pCallback;
5988 break;
5989
5990 default :
5991 /* Return error status */
5992 status = HAL_ERROR;
5993 break;
5994 }
5995 }
5996 else
5997 {
5998 /* Return error status */
5999 status = HAL_ERROR;
6000 }
6001
6002 /* Release Lock */
6003 __HAL_UNLOCK(htim);
6004
6005 return status;
6006 }
6007
6008 /**
6009 * @brief Unregister a TIM callback
6010 * TIM callback is redirected to the weak predefined callback
6011 * @param htim tim handle
6012 * @param CallbackID ID of the callback to be unregistered
6013 * This parameter can be one of the following values:
6014 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
6015 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
6016 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
6017 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
6018 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
6019 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
6020 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
6021 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
6022 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
6023 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
6024 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
6025 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
6026 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
6027 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
6028 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
6029 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
6030 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6031 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
6032 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6033 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6034 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6035 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6036 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6037 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6038 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6039 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6040 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6041 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
6042 * @retval status
6043 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)6044 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
6045 {
6046 HAL_StatusTypeDef status = HAL_OK;
6047
6048 /* Process locked */
6049 __HAL_LOCK(htim);
6050
6051 if (htim->State == HAL_TIM_STATE_READY)
6052 {
6053 switch (CallbackID)
6054 {
6055 case HAL_TIM_BASE_MSPINIT_CB_ID :
6056 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
6057 break;
6058
6059 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6060 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
6061 break;
6062
6063 case HAL_TIM_IC_MSPINIT_CB_ID :
6064 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
6065 break;
6066
6067 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6068 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
6069 break;
6070
6071 case HAL_TIM_OC_MSPINIT_CB_ID :
6072 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
6073 break;
6074
6075 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6076 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
6077 break;
6078
6079 case HAL_TIM_PWM_MSPINIT_CB_ID :
6080 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
6081 break;
6082
6083 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6084 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
6085 break;
6086
6087 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6088 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
6089 break;
6090
6091 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6092 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
6093 break;
6094
6095 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6096 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
6097 break;
6098
6099 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6100 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
6101 break;
6102
6103 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6104 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
6105 break;
6106
6107 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6108 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
6109 break;
6110
6111 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6112 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
6113 break;
6114
6115 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6116 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */
6117 break;
6118
6119 case HAL_TIM_TRIGGER_CB_ID :
6120 htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
6121 break;
6122
6123 case HAL_TIM_TRIGGER_HALF_CB_ID :
6124 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */
6125 break;
6126
6127 case HAL_TIM_IC_CAPTURE_CB_ID :
6128 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
6129 break;
6130
6131 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6132 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */
6133 break;
6134
6135 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6136 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
6137 break;
6138
6139 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6140 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
6141 break;
6142
6143 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6144 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
6145 break;
6146
6147 case HAL_TIM_ERROR_CB_ID :
6148 htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
6149 break;
6150
6151 case HAL_TIM_COMMUTATION_CB_ID :
6152 htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */
6153 break;
6154
6155 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6156 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */
6157 break;
6158
6159 case HAL_TIM_BREAK_CB_ID :
6160 htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
6161 break;
6162
6163 case HAL_TIM_BREAK2_CB_ID :
6164 htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */
6165 break;
6166
6167 default :
6168 /* Return error status */
6169 status = HAL_ERROR;
6170 break;
6171 }
6172 }
6173 else if (htim->State == HAL_TIM_STATE_RESET)
6174 {
6175 switch (CallbackID)
6176 {
6177 case HAL_TIM_BASE_MSPINIT_CB_ID :
6178 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
6179 break;
6180
6181 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6182 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
6183 break;
6184
6185 case HAL_TIM_IC_MSPINIT_CB_ID :
6186 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
6187 break;
6188
6189 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6190 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
6191 break;
6192
6193 case HAL_TIM_OC_MSPINIT_CB_ID :
6194 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
6195 break;
6196
6197 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6198 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
6199 break;
6200
6201 case HAL_TIM_PWM_MSPINIT_CB_ID :
6202 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
6203 break;
6204
6205 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6206 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
6207 break;
6208
6209 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6210 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
6211 break;
6212
6213 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6214 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
6215 break;
6216
6217 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6218 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
6219 break;
6220
6221 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6222 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
6223 break;
6224
6225 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6226 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
6227 break;
6228
6229 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6230 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
6231 break;
6232
6233 default :
6234 /* Return error status */
6235 status = HAL_ERROR;
6236 break;
6237 }
6238 }
6239 else
6240 {
6241 /* Return error status */
6242 status = HAL_ERROR;
6243 }
6244
6245 /* Release Lock */
6246 __HAL_UNLOCK(htim);
6247
6248 return status;
6249 }
6250 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6251
6252 /**
6253 * @}
6254 */
6255
6256 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
6257 * @brief TIM Peripheral State functions
6258 *
6259 @verbatim
6260 ==============================================================================
6261 ##### Peripheral State functions #####
6262 ==============================================================================
6263 [..]
6264 This subsection permits to get in run-time the status of the peripheral
6265 and the data flow.
6266
6267 @endverbatim
6268 * @{
6269 */
6270
6271 /**
6272 * @brief Return the TIM Base handle state.
6273 * @param htim TIM Base handle
6274 * @retval HAL state
6275 */
HAL_TIM_Base_GetState(TIM_HandleTypeDef * htim)6276 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
6277 {
6278 return htim->State;
6279 }
6280
6281 /**
6282 * @brief Return the TIM OC handle state.
6283 * @param htim TIM Output Compare handle
6284 * @retval HAL state
6285 */
HAL_TIM_OC_GetState(TIM_HandleTypeDef * htim)6286 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
6287 {
6288 return htim->State;
6289 }
6290
6291 /**
6292 * @brief Return the TIM PWM handle state.
6293 * @param htim TIM handle
6294 * @retval HAL state
6295 */
HAL_TIM_PWM_GetState(TIM_HandleTypeDef * htim)6296 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
6297 {
6298 return htim->State;
6299 }
6300
6301 /**
6302 * @brief Return the TIM Input Capture handle state.
6303 * @param htim TIM IC handle
6304 * @retval HAL state
6305 */
HAL_TIM_IC_GetState(TIM_HandleTypeDef * htim)6306 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
6307 {
6308 return htim->State;
6309 }
6310
6311 /**
6312 * @brief Return the TIM One Pulse Mode handle state.
6313 * @param htim TIM OPM handle
6314 * @retval HAL state
6315 */
HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef * htim)6316 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
6317 {
6318 return htim->State;
6319 }
6320
6321 /**
6322 * @brief Return the TIM Encoder Mode handle state.
6323 * @param htim TIM Encoder Interface handle
6324 * @retval HAL state
6325 */
HAL_TIM_Encoder_GetState(TIM_HandleTypeDef * htim)6326 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
6327 {
6328 return htim->State;
6329 }
6330
6331 /**
6332 * @brief Return the TIM Encoder Mode handle state.
6333 * @param htim TIM handle
6334 * @retval Active channel
6335 */
HAL_TIM_GetActiveChannel(TIM_HandleTypeDef * htim)6336 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
6337 {
6338 return htim->Channel;
6339 }
6340
6341 /**
6342 * @brief Return actual state of the TIM channel.
6343 * @param htim TIM handle
6344 * @param Channel TIM Channel
6345 * This parameter can be one of the following values:
6346 * @arg TIM_CHANNEL_1: TIM Channel 1
6347 * @arg TIM_CHANNEL_2: TIM Channel 2
6348 * @arg TIM_CHANNEL_3: TIM Channel 3
6349 * @arg TIM_CHANNEL_4: TIM Channel 4
6350 * @arg TIM_CHANNEL_5: TIM Channel 5
6351 * @arg TIM_CHANNEL_6: TIM Channel 6
6352 * @retval TIM Channel state
6353 */
HAL_TIM_GetChannelState(TIM_HandleTypeDef * htim,uint32_t Channel)6354 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel)
6355 {
6356 HAL_TIM_ChannelStateTypeDef channel_state;
6357
6358 /* Check the parameters */
6359 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
6360
6361 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
6362
6363 return channel_state;
6364 }
6365
6366 /**
6367 * @brief Return actual state of a DMA burst operation.
6368 * @param htim TIM handle
6369 * @retval DMA burst state
6370 */
HAL_TIM_DMABurstState(TIM_HandleTypeDef * htim)6371 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
6372 {
6373 /* Check the parameters */
6374 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
6375
6376 return htim->DMABurstState;
6377 }
6378
6379 /**
6380 * @}
6381 */
6382
6383 /**
6384 * @}
6385 */
6386
6387 /** @defgroup TIM_Private_Functions TIM Private Functions
6388 * @{
6389 */
6390
6391 /**
6392 * @brief TIM DMA error callback
6393 * @param hdma pointer to DMA handle.
6394 * @retval None
6395 */
TIM_DMAError(DMA_HandleTypeDef * hdma)6396 void TIM_DMAError(DMA_HandleTypeDef *hdma)
6397 {
6398 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6399
6400 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6401 {
6402 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6403 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6404 }
6405 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6406 {
6407 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6408 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6409 }
6410 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6411 {
6412 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6413 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6414 }
6415 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6416 {
6417 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6418 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6419 }
6420 else
6421 {
6422 htim->State = HAL_TIM_STATE_READY;
6423 }
6424
6425 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6426 htim->ErrorCallback(htim);
6427 #else
6428 HAL_TIM_ErrorCallback(htim);
6429 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6430
6431 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6432 }
6433
6434 /**
6435 * @brief TIM DMA Delay Pulse complete callback.
6436 * @param hdma pointer to DMA handle.
6437 * @retval None
6438 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)6439 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
6440 {
6441 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6442
6443 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6444 {
6445 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6446
6447 if (hdma->Init.Mode == DMA_NORMAL)
6448 {
6449 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6450 }
6451 }
6452 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6453 {
6454 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6455
6456 if (hdma->Init.Mode == DMA_NORMAL)
6457 {
6458 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6459 }
6460 }
6461 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6462 {
6463 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6464
6465 if (hdma->Init.Mode == DMA_NORMAL)
6466 {
6467 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6468 }
6469 }
6470 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6471 {
6472 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6473
6474 if (hdma->Init.Mode == DMA_NORMAL)
6475 {
6476 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6477 }
6478 }
6479 else
6480 {
6481 /* nothing to do */
6482 }
6483
6484 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6485 htim->PWM_PulseFinishedCallback(htim);
6486 #else
6487 HAL_TIM_PWM_PulseFinishedCallback(htim);
6488 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6489
6490 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6491 }
6492
6493 /**
6494 * @brief TIM DMA Delay Pulse half complete callback.
6495 * @param hdma pointer to DMA handle.
6496 * @retval None
6497 */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)6498 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
6499 {
6500 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6501
6502 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6503 {
6504 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6505 }
6506 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6507 {
6508 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6509 }
6510 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6511 {
6512 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6513 }
6514 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6515 {
6516 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6517 }
6518 else
6519 {
6520 /* nothing to do */
6521 }
6522
6523 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6524 htim->PWM_PulseFinishedHalfCpltCallback(htim);
6525 #else
6526 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
6527 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6528
6529 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6530 }
6531
6532 /**
6533 * @brief TIM DMA Capture complete callback.
6534 * @param hdma pointer to DMA handle.
6535 * @retval None
6536 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)6537 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
6538 {
6539 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6540
6541 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6542 {
6543 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6544
6545 if (hdma->Init.Mode == DMA_NORMAL)
6546 {
6547 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6548 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6549 }
6550 }
6551 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6552 {
6553 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6554
6555 if (hdma->Init.Mode == DMA_NORMAL)
6556 {
6557 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6558 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6559 }
6560 }
6561 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6562 {
6563 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6564
6565 if (hdma->Init.Mode == DMA_NORMAL)
6566 {
6567 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6568 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6569 }
6570 }
6571 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6572 {
6573 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6574
6575 if (hdma->Init.Mode == DMA_NORMAL)
6576 {
6577 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6578 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6579 }
6580 }
6581 else
6582 {
6583 /* nothing to do */
6584 }
6585
6586 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6587 htim->IC_CaptureCallback(htim);
6588 #else
6589 HAL_TIM_IC_CaptureCallback(htim);
6590 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6591
6592 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6593 }
6594
6595 /**
6596 * @brief TIM DMA Capture half complete callback.
6597 * @param hdma pointer to DMA handle.
6598 * @retval None
6599 */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)6600 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
6601 {
6602 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6603
6604 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6605 {
6606 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6607 }
6608 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6609 {
6610 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6611 }
6612 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6613 {
6614 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6615 }
6616 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6617 {
6618 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6619 }
6620 else
6621 {
6622 /* nothing to do */
6623 }
6624
6625 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6626 htim->IC_CaptureHalfCpltCallback(htim);
6627 #else
6628 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
6629 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6630
6631 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6632 }
6633
6634 /**
6635 * @brief TIM DMA Period Elapse complete callback.
6636 * @param hdma pointer to DMA handle.
6637 * @retval None
6638 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)6639 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
6640 {
6641 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6642
6643 if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
6644 {
6645 htim->State = HAL_TIM_STATE_READY;
6646 }
6647
6648 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6649 htim->PeriodElapsedCallback(htim);
6650 #else
6651 HAL_TIM_PeriodElapsedCallback(htim);
6652 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6653 }
6654
6655 /**
6656 * @brief TIM DMA Period Elapse half complete callback.
6657 * @param hdma pointer to DMA handle.
6658 * @retval None
6659 */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)6660 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
6661 {
6662 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6663
6664 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6665 htim->PeriodElapsedHalfCpltCallback(htim);
6666 #else
6667 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
6668 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6669 }
6670
6671 /**
6672 * @brief TIM DMA Trigger callback.
6673 * @param hdma pointer to DMA handle.
6674 * @retval None
6675 */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)6676 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
6677 {
6678 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6679
6680 if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
6681 {
6682 htim->State = HAL_TIM_STATE_READY;
6683 }
6684
6685 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6686 htim->TriggerCallback(htim);
6687 #else
6688 HAL_TIM_TriggerCallback(htim);
6689 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6690 }
6691
6692 /**
6693 * @brief TIM DMA Trigger half complete callback.
6694 * @param hdma pointer to DMA handle.
6695 * @retval None
6696 */
TIM_DMATriggerHalfCplt(DMA_HandleTypeDef * hdma)6697 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
6698 {
6699 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6700
6701 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6702 htim->TriggerHalfCpltCallback(htim);
6703 #else
6704 HAL_TIM_TriggerHalfCpltCallback(htim);
6705 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6706 }
6707
6708 /**
6709 * @brief Time Base configuration
6710 * @param TIMx TIM peripheral
6711 * @param Structure TIM Base configuration structure
6712 * @retval None
6713 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,TIM_Base_InitTypeDef * Structure)6714 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
6715 {
6716 uint32_t tmpcr1;
6717 tmpcr1 = TIMx->CR1;
6718
6719 /* Set TIM Time Base Unit parameters ---------------------------------------*/
6720 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
6721 {
6722 /* Select the Counter Mode */
6723 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
6724 tmpcr1 |= Structure->CounterMode;
6725 }
6726
6727 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
6728 {
6729 /* Set the clock division */
6730 tmpcr1 &= ~TIM_CR1_CKD;
6731 tmpcr1 |= (uint32_t)Structure->ClockDivision;
6732 }
6733
6734 /* Set the auto-reload preload */
6735 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
6736
6737 TIMx->CR1 = tmpcr1;
6738
6739 /* Set the Autoreload value */
6740 TIMx->ARR = (uint32_t)Structure->Period ;
6741
6742 /* Set the Prescaler value */
6743 TIMx->PSC = Structure->Prescaler;
6744
6745 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
6746 {
6747 /* Set the Repetition Counter value */
6748 TIMx->RCR = Structure->RepetitionCounter;
6749 }
6750
6751 /* Generate an update event to reload the Prescaler
6752 and the repetition counter (only for advanced timer) value immediately */
6753 TIMx->EGR = TIM_EGR_UG;
6754 }
6755
6756 /**
6757 * @brief Timer Output Compare 1 configuration
6758 * @param TIMx to select the TIM peripheral
6759 * @param OC_Config The output configuration structure
6760 * @retval None
6761 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6762 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6763 {
6764 uint32_t tmpccmrx;
6765 uint32_t tmpccer;
6766 uint32_t tmpcr2;
6767
6768 /* Disable the Channel 1: Reset the CC1E Bit */
6769 TIMx->CCER &= ~TIM_CCER_CC1E;
6770
6771 /* Get the TIMx CCER register value */
6772 tmpccer = TIMx->CCER;
6773 /* Get the TIMx CR2 register value */
6774 tmpcr2 = TIMx->CR2;
6775
6776 /* Get the TIMx CCMR1 register value */
6777 tmpccmrx = TIMx->CCMR1;
6778
6779 /* Reset the Output Compare Mode Bits */
6780 tmpccmrx &= ~TIM_CCMR1_OC1M;
6781 tmpccmrx &= ~TIM_CCMR1_CC1S;
6782 /* Select the Output Compare Mode */
6783 tmpccmrx |= OC_Config->OCMode;
6784
6785 /* Reset the Output Polarity level */
6786 tmpccer &= ~TIM_CCER_CC1P;
6787 /* Set the Output Compare Polarity */
6788 tmpccer |= OC_Config->OCPolarity;
6789
6790 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
6791 {
6792 /* Check parameters */
6793 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6794
6795 /* Reset the Output N Polarity level */
6796 tmpccer &= ~TIM_CCER_CC1NP;
6797 /* Set the Output N Polarity */
6798 tmpccer |= OC_Config->OCNPolarity;
6799 /* Reset the Output N State */
6800 tmpccer &= ~TIM_CCER_CC1NE;
6801 }
6802
6803 if (IS_TIM_BREAK_INSTANCE(TIMx))
6804 {
6805 /* Check parameters */
6806 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6807 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6808
6809 /* Reset the Output Compare and Output Compare N IDLE State */
6810 tmpcr2 &= ~TIM_CR2_OIS1;
6811 tmpcr2 &= ~TIM_CR2_OIS1N;
6812 /* Set the Output Idle state */
6813 tmpcr2 |= OC_Config->OCIdleState;
6814 /* Set the Output N Idle state */
6815 tmpcr2 |= OC_Config->OCNIdleState;
6816 }
6817
6818 /* Write to TIMx CR2 */
6819 TIMx->CR2 = tmpcr2;
6820
6821 /* Write to TIMx CCMR1 */
6822 TIMx->CCMR1 = tmpccmrx;
6823
6824 /* Set the Capture Compare Register value */
6825 TIMx->CCR1 = OC_Config->Pulse;
6826
6827 /* Write to TIMx CCER */
6828 TIMx->CCER = tmpccer;
6829 }
6830
6831 /**
6832 * @brief Timer Output Compare 2 configuration
6833 * @param TIMx to select the TIM peripheral
6834 * @param OC_Config The output configuration structure
6835 * @retval None
6836 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6837 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6838 {
6839 uint32_t tmpccmrx;
6840 uint32_t tmpccer;
6841 uint32_t tmpcr2;
6842
6843 /* Disable the Channel 2: Reset the CC2E Bit */
6844 TIMx->CCER &= ~TIM_CCER_CC2E;
6845
6846 /* Get the TIMx CCER register value */
6847 tmpccer = TIMx->CCER;
6848 /* Get the TIMx CR2 register value */
6849 tmpcr2 = TIMx->CR2;
6850
6851 /* Get the TIMx CCMR1 register value */
6852 tmpccmrx = TIMx->CCMR1;
6853
6854 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6855 tmpccmrx &= ~TIM_CCMR1_OC2M;
6856 tmpccmrx &= ~TIM_CCMR1_CC2S;
6857
6858 /* Select the Output Compare Mode */
6859 tmpccmrx |= (OC_Config->OCMode << 8U);
6860
6861 /* Reset the Output Polarity level */
6862 tmpccer &= ~TIM_CCER_CC2P;
6863 /* Set the Output Compare Polarity */
6864 tmpccer |= (OC_Config->OCPolarity << 4U);
6865
6866 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
6867 {
6868 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6869
6870 /* Reset the Output N Polarity level */
6871 tmpccer &= ~TIM_CCER_CC2NP;
6872 /* Set the Output N Polarity */
6873 tmpccer |= (OC_Config->OCNPolarity << 4U);
6874 /* Reset the Output N State */
6875 tmpccer &= ~TIM_CCER_CC2NE;
6876
6877 }
6878
6879 if (IS_TIM_BREAK_INSTANCE(TIMx))
6880 {
6881 /* Check parameters */
6882 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6883 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6884
6885 /* Reset the Output Compare and Output Compare N IDLE State */
6886 tmpcr2 &= ~TIM_CR2_OIS2;
6887 tmpcr2 &= ~TIM_CR2_OIS2N;
6888 /* Set the Output Idle state */
6889 tmpcr2 |= (OC_Config->OCIdleState << 2U);
6890 /* Set the Output N Idle state */
6891 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
6892 }
6893
6894 /* Write to TIMx CR2 */
6895 TIMx->CR2 = tmpcr2;
6896
6897 /* Write to TIMx CCMR1 */
6898 TIMx->CCMR1 = tmpccmrx;
6899
6900 /* Set the Capture Compare Register value */
6901 TIMx->CCR2 = OC_Config->Pulse;
6902
6903 /* Write to TIMx CCER */
6904 TIMx->CCER = tmpccer;
6905 }
6906
6907 /**
6908 * @brief Timer Output Compare 3 configuration
6909 * @param TIMx to select the TIM peripheral
6910 * @param OC_Config The output configuration structure
6911 * @retval None
6912 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6913 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6914 {
6915 uint32_t tmpccmrx;
6916 uint32_t tmpccer;
6917 uint32_t tmpcr2;
6918
6919 /* Disable the Channel 3: Reset the CC2E Bit */
6920 TIMx->CCER &= ~TIM_CCER_CC3E;
6921
6922 /* Get the TIMx CCER register value */
6923 tmpccer = TIMx->CCER;
6924 /* Get the TIMx CR2 register value */
6925 tmpcr2 = TIMx->CR2;
6926
6927 /* Get the TIMx CCMR2 register value */
6928 tmpccmrx = TIMx->CCMR2;
6929
6930 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6931 tmpccmrx &= ~TIM_CCMR2_OC3M;
6932 tmpccmrx &= ~TIM_CCMR2_CC3S;
6933 /* Select the Output Compare Mode */
6934 tmpccmrx |= OC_Config->OCMode;
6935
6936 /* Reset the Output Polarity level */
6937 tmpccer &= ~TIM_CCER_CC3P;
6938 /* Set the Output Compare Polarity */
6939 tmpccer |= (OC_Config->OCPolarity << 8U);
6940
6941 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
6942 {
6943 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6944
6945 /* Reset the Output N Polarity level */
6946 tmpccer &= ~TIM_CCER_CC3NP;
6947 /* Set the Output N Polarity */
6948 tmpccer |= (OC_Config->OCNPolarity << 8U);
6949 /* Reset the Output N State */
6950 tmpccer &= ~TIM_CCER_CC3NE;
6951 }
6952
6953 if (IS_TIM_BREAK_INSTANCE(TIMx))
6954 {
6955 /* Check parameters */
6956 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6957 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6958
6959 /* Reset the Output Compare and Output Compare N IDLE State */
6960 tmpcr2 &= ~TIM_CR2_OIS3;
6961 tmpcr2 &= ~TIM_CR2_OIS3N;
6962 /* Set the Output Idle state */
6963 tmpcr2 |= (OC_Config->OCIdleState << 4U);
6964 /* Set the Output N Idle state */
6965 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
6966 }
6967
6968 /* Write to TIMx CR2 */
6969 TIMx->CR2 = tmpcr2;
6970
6971 /* Write to TIMx CCMR2 */
6972 TIMx->CCMR2 = tmpccmrx;
6973
6974 /* Set the Capture Compare Register value */
6975 TIMx->CCR3 = OC_Config->Pulse;
6976
6977 /* Write to TIMx CCER */
6978 TIMx->CCER = tmpccer;
6979 }
6980
6981 /**
6982 * @brief Timer Output Compare 4 configuration
6983 * @param TIMx to select the TIM peripheral
6984 * @param OC_Config The output configuration structure
6985 * @retval None
6986 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6987 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6988 {
6989 uint32_t tmpccmrx;
6990 uint32_t tmpccer;
6991 uint32_t tmpcr2;
6992
6993 /* Disable the Channel 4: Reset the CC4E Bit */
6994 TIMx->CCER &= ~TIM_CCER_CC4E;
6995
6996 /* Get the TIMx CCER register value */
6997 tmpccer = TIMx->CCER;
6998 /* Get the TIMx CR2 register value */
6999 tmpcr2 = TIMx->CR2;
7000
7001 /* Get the TIMx CCMR2 register value */
7002 tmpccmrx = TIMx->CCMR2;
7003
7004 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7005 tmpccmrx &= ~TIM_CCMR2_OC4M;
7006 tmpccmrx &= ~TIM_CCMR2_CC4S;
7007
7008 /* Select the Output Compare Mode */
7009 tmpccmrx |= (OC_Config->OCMode << 8U);
7010
7011 /* Reset the Output Polarity level */
7012 tmpccer &= ~TIM_CCER_CC4P;
7013 /* Set the Output Compare Polarity */
7014 tmpccer |= (OC_Config->OCPolarity << 12U);
7015
7016 if (IS_TIM_BREAK_INSTANCE(TIMx))
7017 {
7018 /* Check parameters */
7019 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7020
7021 /* Reset the Output Compare IDLE State */
7022 tmpcr2 &= ~TIM_CR2_OIS4;
7023
7024 /* Set the Output Idle state */
7025 tmpcr2 |= (OC_Config->OCIdleState << 6U);
7026 }
7027
7028 /* Write to TIMx CR2 */
7029 TIMx->CR2 = tmpcr2;
7030
7031 /* Write to TIMx CCMR2 */
7032 TIMx->CCMR2 = tmpccmrx;
7033
7034 /* Set the Capture Compare Register value */
7035 TIMx->CCR4 = OC_Config->Pulse;
7036
7037 /* Write to TIMx CCER */
7038 TIMx->CCER = tmpccer;
7039 }
7040
7041 /**
7042 * @brief Timer Output Compare 5 configuration
7043 * @param TIMx to select the TIM peripheral
7044 * @param OC_Config The output configuration structure
7045 * @retval None
7046 */
TIM_OC5_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)7047 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
7048 TIM_OC_InitTypeDef *OC_Config)
7049 {
7050 uint32_t tmpccmrx;
7051 uint32_t tmpccer;
7052 uint32_t tmpcr2;
7053
7054 /* Disable the output: Reset the CCxE Bit */
7055 TIMx->CCER &= ~TIM_CCER_CC5E;
7056
7057 /* Get the TIMx CCER register value */
7058 tmpccer = TIMx->CCER;
7059 /* Get the TIMx CR2 register value */
7060 tmpcr2 = TIMx->CR2;
7061 /* Get the TIMx CCMR1 register value */
7062 tmpccmrx = TIMx->CCMR3;
7063
7064 /* Reset the Output Compare Mode Bits */
7065 tmpccmrx &= ~(TIM_CCMR3_OC5M);
7066 /* Select the Output Compare Mode */
7067 tmpccmrx |= OC_Config->OCMode;
7068
7069 /* Reset the Output Polarity level */
7070 tmpccer &= ~TIM_CCER_CC5P;
7071 /* Set the Output Compare Polarity */
7072 tmpccer |= (OC_Config->OCPolarity << 16U);
7073
7074 if (IS_TIM_BREAK_INSTANCE(TIMx))
7075 {
7076 /* Reset the Output Compare IDLE State */
7077 tmpcr2 &= ~TIM_CR2_OIS5;
7078 /* Set the Output Idle state */
7079 tmpcr2 |= (OC_Config->OCIdleState << 8U);
7080 }
7081 /* Write to TIMx CR2 */
7082 TIMx->CR2 = tmpcr2;
7083
7084 /* Write to TIMx CCMR3 */
7085 TIMx->CCMR3 = tmpccmrx;
7086
7087 /* Set the Capture Compare Register value */
7088 TIMx->CCR5 = OC_Config->Pulse;
7089
7090 /* Write to TIMx CCER */
7091 TIMx->CCER = tmpccer;
7092 }
7093
7094 /**
7095 * @brief Timer Output Compare 6 configuration
7096 * @param TIMx to select the TIM peripheral
7097 * @param OC_Config The output configuration structure
7098 * @retval None
7099 */
TIM_OC6_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)7100 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
7101 TIM_OC_InitTypeDef *OC_Config)
7102 {
7103 uint32_t tmpccmrx;
7104 uint32_t tmpccer;
7105 uint32_t tmpcr2;
7106
7107 /* Disable the output: Reset the CCxE Bit */
7108 TIMx->CCER &= ~TIM_CCER_CC6E;
7109
7110 /* Get the TIMx CCER register value */
7111 tmpccer = TIMx->CCER;
7112 /* Get the TIMx CR2 register value */
7113 tmpcr2 = TIMx->CR2;
7114 /* Get the TIMx CCMR1 register value */
7115 tmpccmrx = TIMx->CCMR3;
7116
7117 /* Reset the Output Compare Mode Bits */
7118 tmpccmrx &= ~(TIM_CCMR3_OC6M);
7119 /* Select the Output Compare Mode */
7120 tmpccmrx |= (OC_Config->OCMode << 8U);
7121
7122 /* Reset the Output Polarity level */
7123 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
7124 /* Set the Output Compare Polarity */
7125 tmpccer |= (OC_Config->OCPolarity << 20U);
7126
7127 if (IS_TIM_BREAK_INSTANCE(TIMx))
7128 {
7129 /* Reset the Output Compare IDLE State */
7130 tmpcr2 &= ~TIM_CR2_OIS6;
7131 /* Set the Output Idle state */
7132 tmpcr2 |= (OC_Config->OCIdleState << 10U);
7133 }
7134
7135 /* Write to TIMx CR2 */
7136 TIMx->CR2 = tmpcr2;
7137
7138 /* Write to TIMx CCMR3 */
7139 TIMx->CCMR3 = tmpccmrx;
7140
7141 /* Set the Capture Compare Register value */
7142 TIMx->CCR6 = OC_Config->Pulse;
7143
7144 /* Write to TIMx CCER */
7145 TIMx->CCER = tmpccer;
7146 }
7147
7148 /**
7149 * @brief Slave Timer configuration function
7150 * @param htim TIM handle
7151 * @param sSlaveConfig Slave timer configuration
7152 * @retval None
7153 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)7154 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
7155 TIM_SlaveConfigTypeDef *sSlaveConfig)
7156 {
7157 uint32_t tmpsmcr;
7158 uint32_t tmpccmr1;
7159 uint32_t tmpccer;
7160
7161 /* Get the TIMx SMCR register value */
7162 tmpsmcr = htim->Instance->SMCR;
7163
7164 /* Reset the Trigger Selection Bits */
7165 tmpsmcr &= ~TIM_SMCR_TS;
7166 /* Set the Input Trigger source */
7167 tmpsmcr |= sSlaveConfig->InputTrigger;
7168
7169 /* Reset the slave mode Bits */
7170 tmpsmcr &= ~TIM_SMCR_SMS;
7171 /* Set the slave mode */
7172 tmpsmcr |= sSlaveConfig->SlaveMode;
7173
7174 /* Write to TIMx SMCR */
7175 htim->Instance->SMCR = tmpsmcr;
7176
7177 /* Configure the trigger prescaler, filter, and polarity */
7178 switch (sSlaveConfig->InputTrigger)
7179 {
7180 case TIM_TS_ETRF:
7181 {
7182 /* Check the parameters */
7183 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
7184 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
7185 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7186 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7187 /* Configure the ETR Trigger source */
7188 TIM_ETR_SetConfig(htim->Instance,
7189 sSlaveConfig->TriggerPrescaler,
7190 sSlaveConfig->TriggerPolarity,
7191 sSlaveConfig->TriggerFilter);
7192 break;
7193 }
7194
7195 case TIM_TS_TI1F_ED:
7196 {
7197 /* Check the parameters */
7198 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7199 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7200
7201 if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
7202 {
7203 return HAL_ERROR;
7204 }
7205
7206 /* Disable the Channel 1: Reset the CC1E Bit */
7207 tmpccer = htim->Instance->CCER;
7208 htim->Instance->CCER &= ~TIM_CCER_CC1E;
7209 tmpccmr1 = htim->Instance->CCMR1;
7210
7211 /* Set the filter */
7212 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7213 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
7214
7215 /* Write to TIMx CCMR1 and CCER registers */
7216 htim->Instance->CCMR1 = tmpccmr1;
7217 htim->Instance->CCER = tmpccer;
7218 break;
7219 }
7220
7221 case TIM_TS_TI1FP1:
7222 {
7223 /* Check the parameters */
7224 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7225 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7226 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7227
7228 /* Configure TI1 Filter and Polarity */
7229 TIM_TI1_ConfigInputStage(htim->Instance,
7230 sSlaveConfig->TriggerPolarity,
7231 sSlaveConfig->TriggerFilter);
7232 break;
7233 }
7234
7235 case TIM_TS_TI2FP2:
7236 {
7237 /* Check the parameters */
7238 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7239 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7240 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7241
7242 /* Configure TI2 Filter and Polarity */
7243 TIM_TI2_ConfigInputStage(htim->Instance,
7244 sSlaveConfig->TriggerPolarity,
7245 sSlaveConfig->TriggerFilter);
7246 break;
7247 }
7248
7249 case TIM_TS_ITR0:
7250 case TIM_TS_ITR1:
7251 case TIM_TS_ITR2:
7252 case TIM_TS_ITR3:
7253 {
7254 /* Check the parameter */
7255 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7256 break;
7257 }
7258
7259 default:
7260 break;
7261 }
7262 return HAL_OK;
7263 }
7264
7265 /**
7266 * @brief Configure the TI1 as Input.
7267 * @param TIMx to select the TIM peripheral.
7268 * @param TIM_ICPolarity The Input Polarity.
7269 * This parameter can be one of the following values:
7270 * @arg TIM_ICPOLARITY_RISING
7271 * @arg TIM_ICPOLARITY_FALLING
7272 * @arg TIM_ICPOLARITY_BOTHEDGE
7273 * @param TIM_ICSelection specifies the input to be used.
7274 * This parameter can be one of the following values:
7275 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
7276 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
7277 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
7278 * @param TIM_ICFilter Specifies the Input Capture Filter.
7279 * This parameter must be a value between 0x00 and 0x0F.
7280 * @retval None
7281 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
7282 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
7283 * protected against un-initialized filter and polarity values.
7284 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7285 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7286 uint32_t TIM_ICFilter)
7287 {
7288 uint32_t tmpccmr1;
7289 uint32_t tmpccer;
7290
7291 /* Disable the Channel 1: Reset the CC1E Bit */
7292 TIMx->CCER &= ~TIM_CCER_CC1E;
7293 tmpccmr1 = TIMx->CCMR1;
7294 tmpccer = TIMx->CCER;
7295
7296 /* Select the Input */
7297 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
7298 {
7299 tmpccmr1 &= ~TIM_CCMR1_CC1S;
7300 tmpccmr1 |= TIM_ICSelection;
7301 }
7302 else
7303 {
7304 tmpccmr1 |= TIM_CCMR1_CC1S_0;
7305 }
7306
7307 /* Set the filter */
7308 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7309 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
7310
7311 /* Select the Polarity and set the CC1E Bit */
7312 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7313 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
7314
7315 /* Write to TIMx CCMR1 and CCER registers */
7316 TIMx->CCMR1 = tmpccmr1;
7317 TIMx->CCER = tmpccer;
7318 }
7319
7320 /**
7321 * @brief Configure the Polarity and Filter for TI1.
7322 * @param TIMx to select the TIM peripheral.
7323 * @param TIM_ICPolarity The Input Polarity.
7324 * This parameter can be one of the following values:
7325 * @arg TIM_ICPOLARITY_RISING
7326 * @arg TIM_ICPOLARITY_FALLING
7327 * @arg TIM_ICPOLARITY_BOTHEDGE
7328 * @param TIM_ICFilter Specifies the Input Capture Filter.
7329 * This parameter must be a value between 0x00 and 0x0F.
7330 * @retval None
7331 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7332 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7333 {
7334 uint32_t tmpccmr1;
7335 uint32_t tmpccer;
7336
7337 /* Disable the Channel 1: Reset the CC1E Bit */
7338 tmpccer = TIMx->CCER;
7339 TIMx->CCER &= ~TIM_CCER_CC1E;
7340 tmpccmr1 = TIMx->CCMR1;
7341
7342 /* Set the filter */
7343 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7344 tmpccmr1 |= (TIM_ICFilter << 4U);
7345
7346 /* Select the Polarity and set the CC1E Bit */
7347 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7348 tmpccer |= TIM_ICPolarity;
7349
7350 /* Write to TIMx CCMR1 and CCER registers */
7351 TIMx->CCMR1 = tmpccmr1;
7352 TIMx->CCER = tmpccer;
7353 }
7354
7355 /**
7356 * @brief Configure the TI2 as Input.
7357 * @param TIMx to select the TIM peripheral
7358 * @param TIM_ICPolarity The Input Polarity.
7359 * This parameter can be one of the following values:
7360 * @arg TIM_ICPOLARITY_RISING
7361 * @arg TIM_ICPOLARITY_FALLING
7362 * @arg TIM_ICPOLARITY_BOTHEDGE
7363 * @param TIM_ICSelection specifies the input to be used.
7364 * This parameter can be one of the following values:
7365 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
7366 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
7367 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
7368 * @param TIM_ICFilter Specifies the Input Capture Filter.
7369 * This parameter must be a value between 0x00 and 0x0F.
7370 * @retval None
7371 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
7372 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
7373 * protected against un-initialized filter and polarity values.
7374 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7375 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7376 uint32_t TIM_ICFilter)
7377 {
7378 uint32_t tmpccmr1;
7379 uint32_t tmpccer;
7380
7381 /* Disable the Channel 2: Reset the CC2E Bit */
7382 TIMx->CCER &= ~TIM_CCER_CC2E;
7383 tmpccmr1 = TIMx->CCMR1;
7384 tmpccer = TIMx->CCER;
7385
7386 /* Select the Input */
7387 tmpccmr1 &= ~TIM_CCMR1_CC2S;
7388 tmpccmr1 |= (TIM_ICSelection << 8U);
7389
7390 /* Set the filter */
7391 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7392 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
7393
7394 /* Select the Polarity and set the CC2E Bit */
7395 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7396 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
7397
7398 /* Write to TIMx CCMR1 and CCER registers */
7399 TIMx->CCMR1 = tmpccmr1 ;
7400 TIMx->CCER = tmpccer;
7401 }
7402
7403 /**
7404 * @brief Configure the Polarity and Filter for TI2.
7405 * @param TIMx to select the TIM peripheral.
7406 * @param TIM_ICPolarity The Input Polarity.
7407 * This parameter can be one of the following values:
7408 * @arg TIM_ICPOLARITY_RISING
7409 * @arg TIM_ICPOLARITY_FALLING
7410 * @arg TIM_ICPOLARITY_BOTHEDGE
7411 * @param TIM_ICFilter Specifies the Input Capture Filter.
7412 * This parameter must be a value between 0x00 and 0x0F.
7413 * @retval None
7414 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7415 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7416 {
7417 uint32_t tmpccmr1;
7418 uint32_t tmpccer;
7419
7420 /* Disable the Channel 2: Reset the CC2E Bit */
7421 TIMx->CCER &= ~TIM_CCER_CC2E;
7422 tmpccmr1 = TIMx->CCMR1;
7423 tmpccer = TIMx->CCER;
7424
7425 /* Set the filter */
7426 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7427 tmpccmr1 |= (TIM_ICFilter << 12U);
7428
7429 /* Select the Polarity and set the CC2E Bit */
7430 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7431 tmpccer |= (TIM_ICPolarity << 4U);
7432
7433 /* Write to TIMx CCMR1 and CCER registers */
7434 TIMx->CCMR1 = tmpccmr1 ;
7435 TIMx->CCER = tmpccer;
7436 }
7437
7438 /**
7439 * @brief Configure the TI3 as Input.
7440 * @param TIMx to select the TIM peripheral
7441 * @param TIM_ICPolarity The Input Polarity.
7442 * This parameter can be one of the following values:
7443 * @arg TIM_ICPOLARITY_RISING
7444 * @arg TIM_ICPOLARITY_FALLING
7445 * @arg TIM_ICPOLARITY_BOTHEDGE
7446 * @param TIM_ICSelection specifies the input to be used.
7447 * This parameter can be one of the following values:
7448 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
7449 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
7450 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
7451 * @param TIM_ICFilter Specifies the Input Capture Filter.
7452 * This parameter must be a value between 0x00 and 0x0F.
7453 * @retval None
7454 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
7455 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7456 * protected against un-initialized filter and polarity values.
7457 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7458 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7459 uint32_t TIM_ICFilter)
7460 {
7461 uint32_t tmpccmr2;
7462 uint32_t tmpccer;
7463
7464 /* Disable the Channel 3: Reset the CC3E Bit */
7465 TIMx->CCER &= ~TIM_CCER_CC3E;
7466 tmpccmr2 = TIMx->CCMR2;
7467 tmpccer = TIMx->CCER;
7468
7469 /* Select the Input */
7470 tmpccmr2 &= ~TIM_CCMR2_CC3S;
7471 tmpccmr2 |= TIM_ICSelection;
7472
7473 /* Set the filter */
7474 tmpccmr2 &= ~TIM_CCMR2_IC3F;
7475 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
7476
7477 /* Select the Polarity and set the CC3E Bit */
7478 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
7479 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
7480
7481 /* Write to TIMx CCMR2 and CCER registers */
7482 TIMx->CCMR2 = tmpccmr2;
7483 TIMx->CCER = tmpccer;
7484 }
7485
7486 /**
7487 * @brief Configure the TI4 as Input.
7488 * @param TIMx to select the TIM peripheral
7489 * @param TIM_ICPolarity The Input Polarity.
7490 * This parameter can be one of the following values:
7491 * @arg TIM_ICPOLARITY_RISING
7492 * @arg TIM_ICPOLARITY_FALLING
7493 * @arg TIM_ICPOLARITY_BOTHEDGE
7494 * @param TIM_ICSelection specifies the input to be used.
7495 * This parameter can be one of the following values:
7496 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
7497 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
7498 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
7499 * @param TIM_ICFilter Specifies the Input Capture Filter.
7500 * This parameter must be a value between 0x00 and 0x0F.
7501 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
7502 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7503 * protected against un-initialized filter and polarity values.
7504 * @retval None
7505 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7506 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7507 uint32_t TIM_ICFilter)
7508 {
7509 uint32_t tmpccmr2;
7510 uint32_t tmpccer;
7511
7512 /* Disable the Channel 4: Reset the CC4E Bit */
7513 TIMx->CCER &= ~TIM_CCER_CC4E;
7514 tmpccmr2 = TIMx->CCMR2;
7515 tmpccer = TIMx->CCER;
7516
7517 /* Select the Input */
7518 tmpccmr2 &= ~TIM_CCMR2_CC4S;
7519 tmpccmr2 |= (TIM_ICSelection << 8U);
7520
7521 /* Set the filter */
7522 tmpccmr2 &= ~TIM_CCMR2_IC4F;
7523 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
7524
7525 /* Select the Polarity and set the CC4E Bit */
7526 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
7527 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
7528
7529 /* Write to TIMx CCMR2 and CCER registers */
7530 TIMx->CCMR2 = tmpccmr2;
7531 TIMx->CCER = tmpccer ;
7532 }
7533
7534 /**
7535 * @brief Selects the Input Trigger source
7536 * @param TIMx to select the TIM peripheral
7537 * @param InputTriggerSource The Input Trigger source.
7538 * This parameter can be one of the following values:
7539 * @arg TIM_TS_ITR0: Internal Trigger 0
7540 * @arg TIM_TS_ITR1: Internal Trigger 1
7541 * @arg TIM_TS_ITR2: Internal Trigger 2
7542 * @arg TIM_TS_ITR3: Internal Trigger 3
7543 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
7544 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
7545 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
7546 * @arg TIM_TS_ETRF: External Trigger input
7547 * @retval None
7548 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)7549 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
7550 {
7551 uint32_t tmpsmcr;
7552
7553 /* Get the TIMx SMCR register value */
7554 tmpsmcr = TIMx->SMCR;
7555 /* Reset the TS Bits */
7556 tmpsmcr &= ~TIM_SMCR_TS;
7557 /* Set the Input Trigger source and the slave mode*/
7558 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
7559 /* Write to TIMx SMCR */
7560 TIMx->SMCR = tmpsmcr;
7561 }
7562 /**
7563 * @brief Configures the TIMx External Trigger (ETR).
7564 * @param TIMx to select the TIM peripheral
7565 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
7566 * This parameter can be one of the following values:
7567 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
7568 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
7569 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
7570 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
7571 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
7572 * This parameter can be one of the following values:
7573 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
7574 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
7575 * @param ExtTRGFilter External Trigger Filter.
7576 * This parameter must be a value between 0x00 and 0x0F
7577 * @retval None
7578 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)7579 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
7580 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
7581 {
7582 uint32_t tmpsmcr;
7583
7584 tmpsmcr = TIMx->SMCR;
7585
7586 /* Reset the ETR Bits */
7587 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
7588
7589 /* Set the Prescaler, the Filter value and the Polarity */
7590 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
7591
7592 /* Write to TIMx SMCR */
7593 TIMx->SMCR = tmpsmcr;
7594 }
7595
7596 /**
7597 * @brief Enables or disables the TIM Capture Compare Channel x.
7598 * @param TIMx to select the TIM peripheral
7599 * @param Channel specifies the TIM Channel
7600 * This parameter can be one of the following values:
7601 * @arg TIM_CHANNEL_1: TIM Channel 1
7602 * @arg TIM_CHANNEL_2: TIM Channel 2
7603 * @arg TIM_CHANNEL_3: TIM Channel 3
7604 * @arg TIM_CHANNEL_4: TIM Channel 4
7605 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
7606 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
7607 * @param ChannelState specifies the TIM Channel CCxE bit new state.
7608 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
7609 * @retval None
7610 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)7611 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
7612 {
7613 uint32_t tmp;
7614
7615 /* Check the parameters */
7616 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
7617 assert_param(IS_TIM_CHANNELS(Channel));
7618
7619 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
7620
7621 /* Reset the CCxE Bit */
7622 TIMx->CCER &= ~tmp;
7623
7624 /* Set or reset the CCxE Bit */
7625 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
7626 }
7627
7628 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7629 /**
7630 * @brief Reset interrupt callbacks to the legacy weak callbacks.
7631 * @param htim pointer to a TIM_HandleTypeDef structure that contains
7632 * the configuration information for TIM module.
7633 * @retval None
7634 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)7635 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
7636 {
7637 /* Reset the TIM callback to the legacy weak callbacks */
7638 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */
7639 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */
7640 htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */
7641 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */
7642 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */
7643 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */
7644 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */
7645 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */
7646 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
7647 htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */
7648 htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */
7649 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */
7650 htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */
7651 htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */
7652 }
7653 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7654
7655 /**
7656 * @}
7657 */
7658
7659 #endif /* HAL_TIM_MODULE_ENABLED */
7660 /**
7661 * @}
7662 */
7663
7664 /**
7665 * @}
7666 */
7667 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
7668