1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_spi.c
4 * @author MCD Application Team
5 * @brief SPI HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### How to use this driver #####
16 ==============================================================================
17 [..]
18 The SPI HAL driver can be used as follows:
19
20 (#) Declare a SPI_HandleTypeDef handle structure, for example:
21 SPI_HandleTypeDef hspi;
22
23 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
24 (##) Enable the SPIx interface clock
25 (##) SPI pins configuration
26 (+++) Enable the clock for the SPI GPIOs
27 (+++) Configure these SPI pins as alternate function push-pull
28 (##) NVIC configuration if you need to use interrupt process
29 (+++) Configure the SPIx interrupt priority
30 (+++) Enable the NVIC SPI IRQ handle
31 (##) DMA Configuration if you need to use DMA process
32 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
33 (+++) Enable the DMAx clock
34 (+++) Configure the DMA handle parameters
35 (+++) Configure the DMA Tx or Rx Stream/Channel
36 (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
38
39 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
40 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
41
42 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
43 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
44 by calling the customized HAL_SPI_MspInit() API.
45 [..]
46 Circular mode restriction:
47 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
48 (##) Master 2Lines RxOnly
49 (##) Master 1Line Rx
50 (#) The CRC feature is not managed when the DMA circular mode is enabled
51 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
52 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
53 [..]
54 Master Receive mode restriction:
55 (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
56 bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
57 does not initiate a new transfer the following procedure has to be respected:
58 (##) HAL_SPI_DeInit()
59 (##) HAL_SPI_Init()
60 [..]
61 Callback registration:
62
63 (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
64 allows the user to configure dynamically the driver callbacks.
65 Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
66
67 Function HAL_SPI_RegisterCallback() allows to register following callbacks:
68 (++) TxCpltCallback : SPI Tx Completed callback
69 (++) RxCpltCallback : SPI Rx Completed callback
70 (++) TxRxCpltCallback : SPI TxRx Completed callback
71 (++) TxHalfCpltCallback : SPI Tx Half Completed callback
72 (++) RxHalfCpltCallback : SPI Rx Half Completed callback
73 (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
74 (++) ErrorCallback : SPI Error callback
75 (++) AbortCpltCallback : SPI Abort callback
76 (++) MspInitCallback : SPI Msp Init callback
77 (++) MspDeInitCallback : SPI Msp DeInit callback
78 This function takes as parameters the HAL peripheral handle, the Callback ID
79 and a pointer to the user callback function.
80
81
82 (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
83 weak function.
84 HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
85 and the Callback ID.
86 This function allows to reset following callbacks:
87 (++) TxCpltCallback : SPI Tx Completed callback
88 (++) RxCpltCallback : SPI Rx Completed callback
89 (++) TxRxCpltCallback : SPI TxRx Completed callback
90 (++) TxHalfCpltCallback : SPI Tx Half Completed callback
91 (++) RxHalfCpltCallback : SPI Rx Half Completed callback
92 (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
93 (++) ErrorCallback : SPI Error callback
94 (++) AbortCpltCallback : SPI Abort callback
95 (++) MspInitCallback : SPI Msp Init callback
96 (++) MspDeInitCallback : SPI Msp DeInit callback
97
98 [..]
99 By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
100 all callbacks are set to the corresponding weak functions:
101 examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
102 Exception done for MspInit and MspDeInit functions that are
103 reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
104 these callbacks are null (not registered beforehand).
105 If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
106 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
107
108 [..]
109 Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
110 Exception done MspInit/MspDeInit functions that can be registered/unregistered
111 in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
112 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
113 Then, the user first registers the MspInit/MspDeInit user callbacks
114 using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
115 or HAL_SPI_Init() function.
116
117 [..]
118 When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
119 not defined, the callback registering feature is not available
120 and weak (surcharged) callbacks are used.
121
122 [..]
123 Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
124 the following table resume the max SPI frequency reached with data size 8bits/16bits,
125 according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
126
127 @endverbatim
128
129 Additional table :
130
131 DataSize = SPI_DATASIZE_8BIT:
132 +----------------------------------------------------------------------------------------------+
133 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
134 | Process | Transfer mode |---------------------|----------------------|----------------------|
135 | | | Master | Slave | Master | Slave | Master | Slave |
136 |==============================================================================================|
137 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
138 | X |----------------|----------|----------|-----------|----------|-----------|----------|
139 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
140 | R |----------------|----------|----------|-----------|----------|-----------|----------|
141 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
142 |=========|================|==========|==========|===========|==========|===========|==========|
143 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
144 | |----------------|----------|----------|-----------|----------|-----------|----------|
145 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
146 | X |----------------|----------|----------|-----------|----------|-----------|----------|
147 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
148 |=========|================|==========|==========|===========|==========|===========|==========|
149 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
150 | |----------------|----------|----------|-----------|----------|-----------|----------|
151 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
152 | X |----------------|----------|----------|-----------|----------|-----------|----------|
153 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
154 +----------------------------------------------------------------------------------------------+
155
156 DataSize = SPI_DATASIZE_16BIT:
157 +----------------------------------------------------------------------------------------------+
158 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
159 | Process | Transfer mode |---------------------|----------------------|----------------------|
160 | | | Master | Slave | Master | Slave | Master | Slave |
161 |==============================================================================================|
162 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
163 | X |----------------|----------|----------|-----------|----------|-----------|----------|
164 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
165 | R |----------------|----------|----------|-----------|----------|-----------|----------|
166 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
167 |=========|================|==========|==========|===========|==========|===========|==========|
168 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
169 | |----------------|----------|----------|-----------|----------|-----------|----------|
170 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
171 | X |----------------|----------|----------|-----------|----------|-----------|----------|
172 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
173 |=========|================|==========|==========|===========|==========|===========|==========|
174 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
175 | |----------------|----------|----------|-----------|----------|-----------|----------|
176 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
177 | X |----------------|----------|----------|-----------|----------|-----------|----------|
178 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
179 +----------------------------------------------------------------------------------------------+
180 @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
181 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
182 @note
183 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
184 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
185 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
186
187 ******************************************************************************
188 * @attention
189 *
190 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
191 * All rights reserved.</center></h2>
192 *
193 * This software component is licensed by ST under BSD 3-Clause license,
194 * the "License"; You may not use this file except in compliance with the
195 * License. You may obtain a copy of the License at:
196 * opensource.org/licenses/BSD-3-Clause
197 *
198 ******************************************************************************
199 */
200
201 /* Includes ------------------------------------------------------------------*/
202 #include "stm32l4xx_hal.h"
203
204 /** @addtogroup STM32L4xx_HAL_Driver
205 * @{
206 */
207
208 /** @defgroup SPI SPI
209 * @brief SPI HAL module driver
210 * @{
211 */
212 #ifdef HAL_SPI_MODULE_ENABLED
213
214 /* Private typedef -----------------------------------------------------------*/
215 /* Private defines -----------------------------------------------------------*/
216 /** @defgroup SPI_Private_Constants SPI Private Constants
217 * @{
218 */
219 #define SPI_DEFAULT_TIMEOUT 100U
220 /**
221 * @}
222 */
223
224 /* Private macros ------------------------------------------------------------*/
225 /* Private variables ---------------------------------------------------------*/
226 /* Private function prototypes -----------------------------------------------*/
227 /** @defgroup SPI_Private_Functions SPI Private Functions
228 * @{
229 */
230 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
231 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
232 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
233 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
234 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
235 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
236 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
237 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
238 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
239 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
240 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
241 uint32_t Timeout, uint32_t Tickstart);
242 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
243 uint32_t Timeout, uint32_t Tickstart);
244 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
245 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
246 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
247 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
248 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
249 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
250 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
251 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
252 #if (USE_SPI_CRC != 0U)
253 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
254 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
255 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
256 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
257 #endif /* USE_SPI_CRC */
258 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
259 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
260 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
261 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
262 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
263 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
264 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
265 /**
266 * @}
267 */
268
269 /* Exported functions --------------------------------------------------------*/
270 /** @defgroup SPI_Exported_Functions SPI Exported Functions
271 * @{
272 */
273
274 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
275 * @brief Initialization and Configuration functions
276 *
277 @verbatim
278 ===============================================================================
279 ##### Initialization and de-initialization functions #####
280 ===============================================================================
281 [..] This subsection provides a set of functions allowing to initialize and
282 de-initialize the SPIx peripheral:
283
284 (+) User must implement HAL_SPI_MspInit() function in which he configures
285 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
286
287 (+) Call the function HAL_SPI_Init() to configure the selected device with
288 the selected configuration:
289 (++) Mode
290 (++) Direction
291 (++) Data Size
292 (++) Clock Polarity and Phase
293 (++) NSS Management
294 (++) BaudRate Prescaler
295 (++) FirstBit
296 (++) TIMode
297 (++) CRC Calculation
298 (++) CRC Polynomial if CRC enabled
299 (++) CRC Length, used only with Data8 and Data16
300 (++) FIFO reception threshold
301
302 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
303 of the selected SPIx peripheral.
304
305 @endverbatim
306 * @{
307 */
308
309 /**
310 * @brief Initialize the SPI according to the specified parameters
311 * in the SPI_InitTypeDef and initialize the associated handle.
312 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
313 * the configuration information for SPI module.
314 * @retval HAL status
315 */
HAL_SPI_Init(SPI_HandleTypeDef * hspi)316 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
317 {
318 uint32_t frxth;
319
320 /* Check the SPI handle allocation */
321 if (hspi == NULL)
322 {
323 return HAL_ERROR;
324 }
325
326 /* Check the parameters */
327 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
328 assert_param(IS_SPI_MODE(hspi->Init.Mode));
329 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
330 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
331 assert_param(IS_SPI_NSS(hspi->Init.NSS));
332 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
333 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
334 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
335 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
336 if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
337 {
338 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
339 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
340
341 if (hspi->Init.Mode == SPI_MODE_MASTER)
342 {
343 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
344 }
345 else
346 {
347 /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
348 hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
349 }
350 }
351 else
352 {
353 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
354
355 /* Force polarity and phase to TI protocaol requirements */
356 hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
357 hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
358 }
359 #if (USE_SPI_CRC != 0U)
360 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
361 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
362 {
363 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
364 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
365 }
366 #else
367 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
368 #endif /* USE_SPI_CRC */
369
370 if (hspi->State == HAL_SPI_STATE_RESET)
371 {
372 /* Allocate lock resource and initialize it */
373 hspi->Lock = HAL_UNLOCKED;
374
375 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
376 /* Init the SPI Callback settings */
377 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
378 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
379 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
380 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
381 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
382 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
383 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
384 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
385
386 if (hspi->MspInitCallback == NULL)
387 {
388 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
389 }
390
391 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
392 hspi->MspInitCallback(hspi);
393 #else
394 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
395 HAL_SPI_MspInit(hspi);
396 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
397 }
398
399 hspi->State = HAL_SPI_STATE_BUSY;
400
401 /* Disable the selected SPI peripheral */
402 __HAL_SPI_DISABLE(hspi);
403
404 /* Align by default the rs fifo threshold on the data size */
405 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
406 {
407 frxth = SPI_RXFIFO_THRESHOLD_HF;
408 }
409 else
410 {
411 frxth = SPI_RXFIFO_THRESHOLD_QF;
412 }
413
414 /* CRC calculation is valid only for 16Bit and 8 Bit */
415 if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
416 {
417 /* CRC must be disabled */
418 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
419 }
420
421 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
422 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
423 Communication speed, First bit and CRC calculation state */
424 WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
425 (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
426 (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
427 (hspi->Init.CLKPhase & SPI_CR1_CPHA) |
428 (hspi->Init.NSS & SPI_CR1_SSM) |
429 (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
430 (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
431 (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
432 #if (USE_SPI_CRC != 0U)
433 /*---------------------------- SPIx CRCL Configuration -------------------*/
434 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
435 {
436 /* Align the CRC Length on the data size */
437 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
438 {
439 /* CRC Length aligned on the data size : value set by default */
440 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
441 {
442 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
443 }
444 else
445 {
446 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
447 }
448 }
449
450 /* Configure : CRC Length */
451 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
452 {
453 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL);
454 }
455 }
456 #endif /* USE_SPI_CRC */
457
458 /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
459 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
460 (hspi->Init.TIMode & SPI_CR2_FRF) |
461 (hspi->Init.NSSPMode & SPI_CR2_NSSP) |
462 (hspi->Init.DataSize & SPI_CR2_DS_Msk) |
463 (frxth & SPI_CR2_FRXTH)));
464
465 #if (USE_SPI_CRC != 0U)
466 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
467 /* Configure : CRC Polynomial */
468 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
469 {
470 WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
471 }
472 #endif /* USE_SPI_CRC */
473
474 #if defined(SPI_I2SCFGR_I2SMOD)
475 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
476 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
477 #endif /* SPI_I2SCFGR_I2SMOD */
478
479 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
480 hspi->State = HAL_SPI_STATE_READY;
481
482 return HAL_OK;
483 }
484
485 /**
486 * @brief De-Initialize the SPI peripheral.
487 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
488 * the configuration information for SPI module.
489 * @retval HAL status
490 */
HAL_SPI_DeInit(SPI_HandleTypeDef * hspi)491 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
492 {
493 /* Check the SPI handle allocation */
494 if (hspi == NULL)
495 {
496 return HAL_ERROR;
497 }
498
499 /* Check SPI Instance parameter */
500 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
501
502 hspi->State = HAL_SPI_STATE_BUSY;
503
504 /* Disable the SPI Peripheral Clock */
505 __HAL_SPI_DISABLE(hspi);
506
507 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
508 if (hspi->MspDeInitCallback == NULL)
509 {
510 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
511 }
512
513 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
514 hspi->MspDeInitCallback(hspi);
515 #else
516 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
517 HAL_SPI_MspDeInit(hspi);
518 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
519
520 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
521 hspi->State = HAL_SPI_STATE_RESET;
522
523 /* Release Lock */
524 __HAL_UNLOCK(hspi);
525
526 return HAL_OK;
527 }
528
529 /**
530 * @brief Initialize the SPI MSP.
531 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
532 * the configuration information for SPI module.
533 * @retval None
534 */
HAL_SPI_MspInit(SPI_HandleTypeDef * hspi)535 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
536 {
537 /* Prevent unused argument(s) compilation warning */
538 UNUSED(hspi);
539
540 /* NOTE : This function should not be modified, when the callback is needed,
541 the HAL_SPI_MspInit should be implemented in the user file
542 */
543 }
544
545 /**
546 * @brief De-Initialize the SPI MSP.
547 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
548 * the configuration information for SPI module.
549 * @retval None
550 */
HAL_SPI_MspDeInit(SPI_HandleTypeDef * hspi)551 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
552 {
553 /* Prevent unused argument(s) compilation warning */
554 UNUSED(hspi);
555
556 /* NOTE : This function should not be modified, when the callback is needed,
557 the HAL_SPI_MspDeInit should be implemented in the user file
558 */
559 }
560
561 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
562 /**
563 * @brief Register a User SPI Callback
564 * To be used instead of the weak predefined callback
565 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
566 * the configuration information for the specified SPI.
567 * @param CallbackID ID of the callback to be registered
568 * @param pCallback pointer to the Callback function
569 * @retval HAL status
570 */
HAL_SPI_RegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID,pSPI_CallbackTypeDef pCallback)571 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
572 pSPI_CallbackTypeDef pCallback)
573 {
574 HAL_StatusTypeDef status = HAL_OK;
575
576 if (pCallback == NULL)
577 {
578 /* Update the error code */
579 hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
580
581 return HAL_ERROR;
582 }
583 /* Process locked */
584 __HAL_LOCK(hspi);
585
586 if (HAL_SPI_STATE_READY == hspi->State)
587 {
588 switch (CallbackID)
589 {
590 case HAL_SPI_TX_COMPLETE_CB_ID :
591 hspi->TxCpltCallback = pCallback;
592 break;
593
594 case HAL_SPI_RX_COMPLETE_CB_ID :
595 hspi->RxCpltCallback = pCallback;
596 break;
597
598 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
599 hspi->TxRxCpltCallback = pCallback;
600 break;
601
602 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
603 hspi->TxHalfCpltCallback = pCallback;
604 break;
605
606 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
607 hspi->RxHalfCpltCallback = pCallback;
608 break;
609
610 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
611 hspi->TxRxHalfCpltCallback = pCallback;
612 break;
613
614 case HAL_SPI_ERROR_CB_ID :
615 hspi->ErrorCallback = pCallback;
616 break;
617
618 case HAL_SPI_ABORT_CB_ID :
619 hspi->AbortCpltCallback = pCallback;
620 break;
621
622 case HAL_SPI_MSPINIT_CB_ID :
623 hspi->MspInitCallback = pCallback;
624 break;
625
626 case HAL_SPI_MSPDEINIT_CB_ID :
627 hspi->MspDeInitCallback = pCallback;
628 break;
629
630 default :
631 /* Update the error code */
632 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
633
634 /* Return error status */
635 status = HAL_ERROR;
636 break;
637 }
638 }
639 else if (HAL_SPI_STATE_RESET == hspi->State)
640 {
641 switch (CallbackID)
642 {
643 case HAL_SPI_MSPINIT_CB_ID :
644 hspi->MspInitCallback = pCallback;
645 break;
646
647 case HAL_SPI_MSPDEINIT_CB_ID :
648 hspi->MspDeInitCallback = pCallback;
649 break;
650
651 default :
652 /* Update the error code */
653 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
654
655 /* Return error status */
656 status = HAL_ERROR;
657 break;
658 }
659 }
660 else
661 {
662 /* Update the error code */
663 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
664
665 /* Return error status */
666 status = HAL_ERROR;
667 }
668
669 /* Release Lock */
670 __HAL_UNLOCK(hspi);
671 return status;
672 }
673
674 /**
675 * @brief Unregister an SPI Callback
676 * SPI callback is redirected to the weak predefined callback
677 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
678 * the configuration information for the specified SPI.
679 * @param CallbackID ID of the callback to be unregistered
680 * @retval HAL status
681 */
HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID)682 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
683 {
684 HAL_StatusTypeDef status = HAL_OK;
685
686 /* Process locked */
687 __HAL_LOCK(hspi);
688
689 if (HAL_SPI_STATE_READY == hspi->State)
690 {
691 switch (CallbackID)
692 {
693 case HAL_SPI_TX_COMPLETE_CB_ID :
694 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
695 break;
696
697 case HAL_SPI_RX_COMPLETE_CB_ID :
698 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
699 break;
700
701 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
702 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
703 break;
704
705 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
706 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
707 break;
708
709 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
710 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
711 break;
712
713 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
714 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
715 break;
716
717 case HAL_SPI_ERROR_CB_ID :
718 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
719 break;
720
721 case HAL_SPI_ABORT_CB_ID :
722 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
723 break;
724
725 case HAL_SPI_MSPINIT_CB_ID :
726 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
727 break;
728
729 case HAL_SPI_MSPDEINIT_CB_ID :
730 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
731 break;
732
733 default :
734 /* Update the error code */
735 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
736
737 /* Return error status */
738 status = HAL_ERROR;
739 break;
740 }
741 }
742 else if (HAL_SPI_STATE_RESET == hspi->State)
743 {
744 switch (CallbackID)
745 {
746 case HAL_SPI_MSPINIT_CB_ID :
747 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
748 break;
749
750 case HAL_SPI_MSPDEINIT_CB_ID :
751 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
752 break;
753
754 default :
755 /* Update the error code */
756 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
757
758 /* Return error status */
759 status = HAL_ERROR;
760 break;
761 }
762 }
763 else
764 {
765 /* Update the error code */
766 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
767
768 /* Return error status */
769 status = HAL_ERROR;
770 }
771
772 /* Release Lock */
773 __HAL_UNLOCK(hspi);
774 return status;
775 }
776 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
777 /**
778 * @}
779 */
780
781 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
782 * @brief Data transfers functions
783 *
784 @verbatim
785 ==============================================================================
786 ##### IO operation functions #####
787 ===============================================================================
788 [..]
789 This subsection provides a set of functions allowing to manage the SPI
790 data transfers.
791
792 [..] The SPI supports master and slave mode :
793
794 (#) There are two modes of transfer:
795 (++) Blocking mode: The communication is performed in polling mode.
796 The HAL status of all data processing is returned by the same function
797 after finishing transfer.
798 (++) No-Blocking mode: The communication is performed using Interrupts
799 or DMA, These APIs return the HAL status.
800 The end of the data processing will be indicated through the
801 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
802 using DMA mode.
803 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
804 will be executed respectively at the end of the transmit or Receive process
805 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
806
807 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
808 exist for 1Line (simplex) and 2Lines (full duplex) modes.
809
810 @endverbatim
811 * @{
812 */
813
814 /**
815 * @brief Transmit an amount of data in blocking mode.
816 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
817 * the configuration information for SPI module.
818 * @param pData pointer to data buffer
819 * @param Size amount of data to be sent
820 * @param Timeout Timeout duration
821 * @retval HAL status
822 */
HAL_SPI_Transmit(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)823 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
824 {
825 uint32_t tickstart;
826 HAL_StatusTypeDef errorcode = HAL_OK;
827 uint16_t initial_TxXferCount;
828
829 /* Check Direction parameter */
830 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
831
832 /* Process Locked */
833 __HAL_LOCK(hspi);
834
835 /* Init tickstart for timeout management*/
836 tickstart = HAL_GetTick();
837 initial_TxXferCount = Size;
838
839 if (hspi->State != HAL_SPI_STATE_READY)
840 {
841 errorcode = HAL_BUSY;
842 goto error;
843 }
844
845 if ((pData == NULL) || (Size == 0U))
846 {
847 errorcode = HAL_ERROR;
848 goto error;
849 }
850
851 /* Set the transaction information */
852 hspi->State = HAL_SPI_STATE_BUSY_TX;
853 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
854 hspi->pTxBuffPtr = (uint8_t *)pData;
855 hspi->TxXferSize = Size;
856 hspi->TxXferCount = Size;
857
858 /*Init field not used in handle to zero */
859 hspi->pRxBuffPtr = (uint8_t *)NULL;
860 hspi->RxXferSize = 0U;
861 hspi->RxXferCount = 0U;
862 hspi->TxISR = NULL;
863 hspi->RxISR = NULL;
864
865 /* Configure communication direction : 1Line */
866 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
867 {
868 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
869 __HAL_SPI_DISABLE(hspi);
870 SPI_1LINE_TX(hspi);
871 }
872
873 #if (USE_SPI_CRC != 0U)
874 /* Reset CRC Calculation */
875 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
876 {
877 SPI_RESET_CRC(hspi);
878 }
879 #endif /* USE_SPI_CRC */
880
881 /* Check if the SPI is already enabled */
882 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
883 {
884 /* Enable SPI peripheral */
885 __HAL_SPI_ENABLE(hspi);
886 }
887
888 /* Transmit data in 16 Bit mode */
889 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
890 {
891 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
892 {
893 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
894 hspi->pTxBuffPtr += sizeof(uint16_t);
895 hspi->TxXferCount--;
896 }
897 /* Transmit data in 16 Bit mode */
898 while (hspi->TxXferCount > 0U)
899 {
900 /* Wait until TXE flag is set to send data */
901 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
902 {
903 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
904 hspi->pTxBuffPtr += sizeof(uint16_t);
905 hspi->TxXferCount--;
906 }
907 else
908 {
909 /* Timeout management */
910 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
911 {
912 errorcode = HAL_TIMEOUT;
913 goto error;
914 }
915 }
916 }
917 }
918 /* Transmit data in 8 Bit mode */
919 else
920 {
921 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
922 {
923 if (hspi->TxXferCount > 1U)
924 {
925 /* write on the data register in packing mode */
926 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
927 hspi->pTxBuffPtr += sizeof(uint16_t);
928 hspi->TxXferCount -= 2U;
929 }
930 else
931 {
932 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
933 hspi->pTxBuffPtr ++;
934 hspi->TxXferCount--;
935 }
936 }
937 while (hspi->TxXferCount > 0U)
938 {
939 /* Wait until TXE flag is set to send data */
940 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
941 {
942 if (hspi->TxXferCount > 1U)
943 {
944 /* write on the data register in packing mode */
945 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
946 hspi->pTxBuffPtr += sizeof(uint16_t);
947 hspi->TxXferCount -= 2U;
948 }
949 else
950 {
951 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
952 hspi->pTxBuffPtr++;
953 hspi->TxXferCount--;
954 }
955 }
956 else
957 {
958 /* Timeout management */
959 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
960 {
961 errorcode = HAL_TIMEOUT;
962 goto error;
963 }
964 }
965 }
966 }
967 #if (USE_SPI_CRC != 0U)
968 /* Enable CRC Transmission */
969 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
970 {
971 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
972 }
973 #endif /* USE_SPI_CRC */
974
975 /* Check the end of the transaction */
976 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
977 {
978 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
979 }
980
981 /* Clear overrun flag in 2 Lines communication mode because received is not read */
982 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
983 {
984 __HAL_SPI_CLEAR_OVRFLAG(hspi);
985 }
986
987 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
988 {
989 errorcode = HAL_ERROR;
990 }
991
992 error:
993 hspi->State = HAL_SPI_STATE_READY;
994 /* Process Unlocked */
995 __HAL_UNLOCK(hspi);
996 return errorcode;
997 }
998
999 /**
1000 * @brief Receive an amount of data in blocking mode.
1001 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1002 * the configuration information for SPI module.
1003 * @param pData pointer to data buffer
1004 * @param Size amount of data to be received
1005 * @param Timeout Timeout duration
1006 * @retval HAL status
1007 */
HAL_SPI_Receive(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)1008 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1009 {
1010 uint32_t tickstart;
1011 HAL_StatusTypeDef errorcode = HAL_OK;
1012
1013 if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
1014 {
1015 hspi->State = HAL_SPI_STATE_BUSY_RX;
1016 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1017 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
1018 }
1019
1020 /* Process Locked */
1021 __HAL_LOCK(hspi);
1022
1023 /* Init tickstart for timeout management*/
1024 tickstart = HAL_GetTick();
1025
1026 if (hspi->State != HAL_SPI_STATE_READY)
1027 {
1028 errorcode = HAL_BUSY;
1029 goto error;
1030 }
1031
1032 if ((pData == NULL) || (Size == 0U))
1033 {
1034 errorcode = HAL_ERROR;
1035 goto error;
1036 }
1037
1038 /* Set the transaction information */
1039 hspi->State = HAL_SPI_STATE_BUSY_RX;
1040 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1041 hspi->pRxBuffPtr = (uint8_t *)pData;
1042 hspi->RxXferSize = Size;
1043 hspi->RxXferCount = Size;
1044
1045 /*Init field not used in handle to zero */
1046 hspi->pTxBuffPtr = (uint8_t *)NULL;
1047 hspi->TxXferSize = 0U;
1048 hspi->TxXferCount = 0U;
1049 hspi->RxISR = NULL;
1050 hspi->TxISR = NULL;
1051
1052 #if (USE_SPI_CRC != 0U)
1053 /* Reset CRC Calculation */
1054 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1055 {
1056 SPI_RESET_CRC(hspi);
1057 /* this is done to handle the CRCNEXT before the latest data */
1058 hspi->RxXferCount--;
1059 }
1060 #endif /* USE_SPI_CRC */
1061
1062 /* Set the Rx Fifo threshold */
1063 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1064 {
1065 /* Set RX Fifo threshold according the reception data length: 16bit */
1066 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1067 }
1068 else
1069 {
1070 /* Set RX Fifo threshold according the reception data length: 8bit */
1071 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1072 }
1073
1074 /* Configure communication direction: 1Line */
1075 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1076 {
1077 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1078 __HAL_SPI_DISABLE(hspi);
1079 SPI_1LINE_RX(hspi);
1080 }
1081
1082 /* Check if the SPI is already enabled */
1083 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1084 {
1085 /* Enable SPI peripheral */
1086 __HAL_SPI_ENABLE(hspi);
1087 }
1088
1089 /* Receive data in 8 Bit mode */
1090 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
1091 {
1092 /* Transfer loop */
1093 while (hspi->RxXferCount > 0U)
1094 {
1095 /* Check the RXNE flag */
1096 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1097 {
1098 /* read the received data */
1099 (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1100 hspi->pRxBuffPtr += sizeof(uint8_t);
1101 hspi->RxXferCount--;
1102 }
1103 else
1104 {
1105 /* Timeout management */
1106 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1107 {
1108 errorcode = HAL_TIMEOUT;
1109 goto error;
1110 }
1111 }
1112 }
1113 }
1114 else
1115 {
1116 /* Transfer loop */
1117 while (hspi->RxXferCount > 0U)
1118 {
1119 /* Check the RXNE flag */
1120 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1121 {
1122 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1123 hspi->pRxBuffPtr += sizeof(uint16_t);
1124 hspi->RxXferCount--;
1125 }
1126 else
1127 {
1128 /* Timeout management */
1129 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1130 {
1131 errorcode = HAL_TIMEOUT;
1132 goto error;
1133 }
1134 }
1135 }
1136 }
1137
1138 #if (USE_SPI_CRC != 0U)
1139 /* Handle the CRC Transmission */
1140 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1141 {
1142 /* freeze the CRC before the latest data */
1143 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1144
1145 /* Read the latest data */
1146 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1147 {
1148 /* the latest data has not been received */
1149 errorcode = HAL_TIMEOUT;
1150 goto error;
1151 }
1152
1153 /* Receive last data in 16 Bit mode */
1154 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1155 {
1156 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1157 }
1158 /* Receive last data in 8 Bit mode */
1159 else
1160 {
1161 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1162 }
1163
1164 /* Wait the CRC data */
1165 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1166 {
1167 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1168 errorcode = HAL_TIMEOUT;
1169 goto error;
1170 }
1171
1172 /* Read CRC to Flush DR and RXNE flag */
1173 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1174 {
1175 /* Read 16bit CRC */
1176 READ_REG(hspi->Instance->DR);
1177 }
1178 else
1179 {
1180 /* Read 8bit CRC */
1181 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1182
1183 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1184 {
1185 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1186 {
1187 /* Error on the CRC reception */
1188 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1189 errorcode = HAL_TIMEOUT;
1190 goto error;
1191 }
1192 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1193 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1194 }
1195 }
1196 }
1197 #endif /* USE_SPI_CRC */
1198
1199 /* Check the end of the transaction */
1200 if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1201 {
1202 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1203 }
1204
1205 #if (USE_SPI_CRC != 0U)
1206 /* Check if CRC error occurred */
1207 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1208 {
1209 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1210 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1211 }
1212 #endif /* USE_SPI_CRC */
1213
1214 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1215 {
1216 errorcode = HAL_ERROR;
1217 }
1218
1219 error :
1220 hspi->State = HAL_SPI_STATE_READY;
1221 __HAL_UNLOCK(hspi);
1222 return errorcode;
1223 }
1224
1225 /**
1226 * @brief Transmit and Receive an amount of data in blocking mode.
1227 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1228 * the configuration information for SPI module.
1229 * @param pTxData pointer to transmission data buffer
1230 * @param pRxData pointer to reception data buffer
1231 * @param Size amount of data to be sent and received
1232 * @param Timeout Timeout duration
1233 * @retval HAL status
1234 */
HAL_SPI_TransmitReceive(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size,uint32_t Timeout)1235 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
1236 uint32_t Timeout)
1237 {
1238 uint16_t initial_TxXferCount;
1239 uint16_t initial_RxXferCount;
1240 uint32_t tmp_mode;
1241 HAL_SPI_StateTypeDef tmp_state;
1242 uint32_t tickstart;
1243 #if (USE_SPI_CRC != 0U)
1244 uint32_t spi_cr1;
1245 uint32_t spi_cr2;
1246 #endif /* USE_SPI_CRC */
1247
1248 /* Variable used to alternate Rx and Tx during transfer */
1249 uint32_t txallowed = 1U;
1250 HAL_StatusTypeDef errorcode = HAL_OK;
1251
1252 /* Check Direction parameter */
1253 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1254
1255 /* Process Locked */
1256 __HAL_LOCK(hspi);
1257
1258 /* Init tickstart for timeout management*/
1259 tickstart = HAL_GetTick();
1260
1261 /* Init temporary variables */
1262 tmp_state = hspi->State;
1263 tmp_mode = hspi->Init.Mode;
1264 initial_TxXferCount = Size;
1265 initial_RxXferCount = Size;
1266 #if (USE_SPI_CRC != 0U)
1267 spi_cr1 = READ_REG(hspi->Instance->CR1);
1268 spi_cr2 = READ_REG(hspi->Instance->CR2);
1269 #endif /* USE_SPI_CRC */
1270
1271 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1272 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1273 {
1274 errorcode = HAL_BUSY;
1275 goto error;
1276 }
1277
1278 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1279 {
1280 errorcode = HAL_ERROR;
1281 goto error;
1282 }
1283
1284 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1285 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1286 {
1287 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1288 }
1289
1290 /* Set the transaction information */
1291 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1292 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1293 hspi->RxXferCount = Size;
1294 hspi->RxXferSize = Size;
1295 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1296 hspi->TxXferCount = Size;
1297 hspi->TxXferSize = Size;
1298
1299 /*Init field not used in handle to zero */
1300 hspi->RxISR = NULL;
1301 hspi->TxISR = NULL;
1302
1303 #if (USE_SPI_CRC != 0U)
1304 /* Reset CRC Calculation */
1305 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1306 {
1307 SPI_RESET_CRC(hspi);
1308 }
1309 #endif /* USE_SPI_CRC */
1310
1311 /* Set the Rx Fifo threshold */
1312 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))
1313 {
1314 /* Set fiforxthreshold according the reception data length: 16bit */
1315 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1316 }
1317 else
1318 {
1319 /* Set fiforxthreshold according the reception data length: 8bit */
1320 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1321 }
1322
1323 /* Check if the SPI is already enabled */
1324 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1325 {
1326 /* Enable SPI peripheral */
1327 __HAL_SPI_ENABLE(hspi);
1328 }
1329
1330 /* Transmit and Receive data in 16 Bit mode */
1331 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1332 {
1333 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1334 {
1335 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1336 hspi->pTxBuffPtr += sizeof(uint16_t);
1337 hspi->TxXferCount--;
1338 }
1339 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1340 {
1341 /* Check TXE flag */
1342 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1343 {
1344 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1345 hspi->pTxBuffPtr += sizeof(uint16_t);
1346 hspi->TxXferCount--;
1347 /* Next Data is a reception (Rx). Tx not allowed */
1348 txallowed = 0U;
1349
1350 #if (USE_SPI_CRC != 0U)
1351 /* Enable CRC Transmission */
1352 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1353 {
1354 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1355 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1356 {
1357 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1358 }
1359 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1360 }
1361 #endif /* USE_SPI_CRC */
1362 }
1363
1364 /* Check RXNE flag */
1365 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1366 {
1367 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1368 hspi->pRxBuffPtr += sizeof(uint16_t);
1369 hspi->RxXferCount--;
1370 /* Next Data is a Transmission (Tx). Tx is allowed */
1371 txallowed = 1U;
1372 }
1373 if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
1374 {
1375 errorcode = HAL_TIMEOUT;
1376 goto error;
1377 }
1378 }
1379 }
1380 /* Transmit and Receive data in 8 Bit mode */
1381 else
1382 {
1383 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1384 {
1385 if (hspi->TxXferCount > 1U)
1386 {
1387 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1388 hspi->pTxBuffPtr += sizeof(uint16_t);
1389 hspi->TxXferCount -= 2U;
1390 }
1391 else
1392 {
1393 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1394 hspi->pTxBuffPtr++;
1395 hspi->TxXferCount--;
1396 }
1397 }
1398 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1399 {
1400 /* Check TXE flag */
1401 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1402 {
1403 if (hspi->TxXferCount > 1U)
1404 {
1405 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1406 hspi->pTxBuffPtr += sizeof(uint16_t);
1407 hspi->TxXferCount -= 2U;
1408 }
1409 else
1410 {
1411 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1412 hspi->pTxBuffPtr++;
1413 hspi->TxXferCount--;
1414 }
1415 /* Next Data is a reception (Rx). Tx not allowed */
1416 txallowed = 0U;
1417
1418 #if (USE_SPI_CRC != 0U)
1419 /* Enable CRC Transmission */
1420 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1421 {
1422 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1423 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1424 {
1425 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1426 }
1427 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1428 }
1429 #endif /* USE_SPI_CRC */
1430 }
1431
1432 /* Wait until RXNE flag is reset */
1433 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1434 {
1435 if (hspi->RxXferCount > 1U)
1436 {
1437 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1438 hspi->pRxBuffPtr += sizeof(uint16_t);
1439 hspi->RxXferCount -= 2U;
1440 if (hspi->RxXferCount <= 1U)
1441 {
1442 /* Set RX Fifo threshold before to switch on 8 bit data size */
1443 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1444 }
1445 }
1446 else
1447 {
1448 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1449 hspi->pRxBuffPtr++;
1450 hspi->RxXferCount--;
1451 }
1452 /* Next Data is a Transmission (Tx). Tx is allowed */
1453 txallowed = 1U;
1454 }
1455 if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
1456 {
1457 errorcode = HAL_TIMEOUT;
1458 goto error;
1459 }
1460 }
1461 }
1462
1463 #if (USE_SPI_CRC != 0U)
1464 /* Read CRC from DR to close CRC calculation process */
1465 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1466 {
1467 /* Wait until TXE flag */
1468 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1469 {
1470 /* Error on the CRC reception */
1471 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1472 errorcode = HAL_TIMEOUT;
1473 goto error;
1474 }
1475 /* Read CRC */
1476 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1477 {
1478 /* Read 16bit CRC */
1479 READ_REG(hspi->Instance->DR);
1480 }
1481 else
1482 {
1483 /* Read 8bit CRC */
1484 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1485
1486 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
1487 {
1488 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1489 {
1490 /* Error on the CRC reception */
1491 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1492 errorcode = HAL_TIMEOUT;
1493 goto error;
1494 }
1495 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1496 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1497 }
1498 }
1499 }
1500
1501 /* Check if CRC error occurred */
1502 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1503 {
1504 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1505 /* Clear CRC Flag */
1506 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1507
1508 errorcode = HAL_ERROR;
1509 }
1510 #endif /* USE_SPI_CRC */
1511
1512 /* Check the end of the transaction */
1513 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1514 {
1515 errorcode = HAL_ERROR;
1516 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1517 }
1518
1519 error :
1520 hspi->State = HAL_SPI_STATE_READY;
1521 __HAL_UNLOCK(hspi);
1522 return errorcode;
1523 }
1524
1525 /**
1526 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
1527 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1528 * the configuration information for SPI module.
1529 * @param pData pointer to data buffer
1530 * @param Size amount of data to be sent
1531 * @retval HAL status
1532 */
HAL_SPI_Transmit_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1533 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1534 {
1535 HAL_StatusTypeDef errorcode = HAL_OK;
1536
1537 /* Check Direction parameter */
1538 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1539
1540 /* Process Locked */
1541 __HAL_LOCK(hspi);
1542
1543 if ((pData == NULL) || (Size == 0U))
1544 {
1545 errorcode = HAL_ERROR;
1546 goto error;
1547 }
1548
1549 if (hspi->State != HAL_SPI_STATE_READY)
1550 {
1551 errorcode = HAL_BUSY;
1552 goto error;
1553 }
1554
1555 /* Set the transaction information */
1556 hspi->State = HAL_SPI_STATE_BUSY_TX;
1557 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1558 hspi->pTxBuffPtr = (uint8_t *)pData;
1559 hspi->TxXferSize = Size;
1560 hspi->TxXferCount = Size;
1561
1562 /* Init field not used in handle to zero */
1563 hspi->pRxBuffPtr = (uint8_t *)NULL;
1564 hspi->RxXferSize = 0U;
1565 hspi->RxXferCount = 0U;
1566 hspi->RxISR = NULL;
1567
1568 /* Set the function for IT treatment */
1569 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1570 {
1571 hspi->TxISR = SPI_TxISR_16BIT;
1572 }
1573 else
1574 {
1575 hspi->TxISR = SPI_TxISR_8BIT;
1576 }
1577
1578 /* Configure communication direction : 1Line */
1579 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1580 {
1581 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1582 __HAL_SPI_DISABLE(hspi);
1583 SPI_1LINE_TX(hspi);
1584 }
1585
1586 #if (USE_SPI_CRC != 0U)
1587 /* Reset CRC Calculation */
1588 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1589 {
1590 SPI_RESET_CRC(hspi);
1591 }
1592 #endif /* USE_SPI_CRC */
1593
1594 /* Enable TXE and ERR interrupt */
1595 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
1596
1597
1598 /* Check if the SPI is already enabled */
1599 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1600 {
1601 /* Enable SPI peripheral */
1602 __HAL_SPI_ENABLE(hspi);
1603 }
1604
1605 error :
1606 __HAL_UNLOCK(hspi);
1607 return errorcode;
1608 }
1609
1610 /**
1611 * @brief Receive an amount of data in non-blocking mode with Interrupt.
1612 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1613 * the configuration information for SPI module.
1614 * @param pData pointer to data buffer
1615 * @param Size amount of data to be sent
1616 * @retval HAL status
1617 */
HAL_SPI_Receive_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1618 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1619 {
1620 HAL_StatusTypeDef errorcode = HAL_OK;
1621
1622 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1623 {
1624 hspi->State = HAL_SPI_STATE_BUSY_RX;
1625 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1626 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
1627 }
1628
1629 /* Process Locked */
1630 __HAL_LOCK(hspi);
1631
1632 if (hspi->State != HAL_SPI_STATE_READY)
1633 {
1634 errorcode = HAL_BUSY;
1635 goto error;
1636 }
1637
1638 if ((pData == NULL) || (Size == 0U))
1639 {
1640 errorcode = HAL_ERROR;
1641 goto error;
1642 }
1643
1644 /* Set the transaction information */
1645 hspi->State = HAL_SPI_STATE_BUSY_RX;
1646 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1647 hspi->pRxBuffPtr = (uint8_t *)pData;
1648 hspi->RxXferSize = Size;
1649 hspi->RxXferCount = Size;
1650
1651 /* Init field not used in handle to zero */
1652 hspi->pTxBuffPtr = (uint8_t *)NULL;
1653 hspi->TxXferSize = 0U;
1654 hspi->TxXferCount = 0U;
1655 hspi->TxISR = NULL;
1656
1657 /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
1658 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1659 {
1660 /* Set RX Fifo threshold according the reception data length: 16 bit */
1661 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1662 hspi->RxISR = SPI_RxISR_16BIT;
1663 }
1664 else
1665 {
1666 /* Set RX Fifo threshold according the reception data length: 8 bit */
1667 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1668 hspi->RxISR = SPI_RxISR_8BIT;
1669 }
1670
1671 /* Configure communication direction : 1Line */
1672 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1673 {
1674 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1675 __HAL_SPI_DISABLE(hspi);
1676 SPI_1LINE_RX(hspi);
1677 }
1678
1679 #if (USE_SPI_CRC != 0U)
1680 /* Reset CRC Calculation */
1681 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1682 {
1683 hspi->CRCSize = 1U;
1684 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1685 {
1686 hspi->CRCSize = 2U;
1687 }
1688 SPI_RESET_CRC(hspi);
1689 }
1690 else
1691 {
1692 hspi->CRCSize = 0U;
1693 }
1694 #endif /* USE_SPI_CRC */
1695
1696 /* Enable TXE and ERR interrupt */
1697 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
1698
1699 /* Note : The SPI must be enabled after unlocking current process
1700 to avoid the risk of SPI interrupt handle execution before current
1701 process unlock */
1702
1703 /* Check if the SPI is already enabled */
1704 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1705 {
1706 /* Enable SPI peripheral */
1707 __HAL_SPI_ENABLE(hspi);
1708 }
1709
1710 error :
1711 /* Process Unlocked */
1712 __HAL_UNLOCK(hspi);
1713 return errorcode;
1714 }
1715
1716 /**
1717 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
1718 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1719 * the configuration information for SPI module.
1720 * @param pTxData pointer to transmission data buffer
1721 * @param pRxData pointer to reception data buffer
1722 * @param Size amount of data to be sent and received
1723 * @retval HAL status
1724 */
HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)1725 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1726 {
1727 uint32_t tmp_mode;
1728 HAL_SPI_StateTypeDef tmp_state;
1729 HAL_StatusTypeDef errorcode = HAL_OK;
1730
1731 /* Check Direction parameter */
1732 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1733
1734 /* Process locked */
1735 __HAL_LOCK(hspi);
1736
1737 /* Init temporary variables */
1738 tmp_state = hspi->State;
1739 tmp_mode = hspi->Init.Mode;
1740
1741 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1742 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1743 {
1744 errorcode = HAL_BUSY;
1745 goto error;
1746 }
1747
1748 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1749 {
1750 errorcode = HAL_ERROR;
1751 goto error;
1752 }
1753
1754 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1755 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1756 {
1757 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1758 }
1759
1760 /* Set the transaction information */
1761 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1762 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1763 hspi->TxXferSize = Size;
1764 hspi->TxXferCount = Size;
1765 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1766 hspi->RxXferSize = Size;
1767 hspi->RxXferCount = Size;
1768
1769 /* Set the function for IT treatment */
1770 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1771 {
1772 hspi->RxISR = SPI_2linesRxISR_16BIT;
1773 hspi->TxISR = SPI_2linesTxISR_16BIT;
1774 }
1775 else
1776 {
1777 hspi->RxISR = SPI_2linesRxISR_8BIT;
1778 hspi->TxISR = SPI_2linesTxISR_8BIT;
1779 }
1780
1781 #if (USE_SPI_CRC != 0U)
1782 /* Reset CRC Calculation */
1783 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1784 {
1785 hspi->CRCSize = 1U;
1786 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1787 {
1788 hspi->CRCSize = 2U;
1789 }
1790 SPI_RESET_CRC(hspi);
1791 }
1792 else
1793 {
1794 hspi->CRCSize = 0U;
1795 }
1796 #endif /* USE_SPI_CRC */
1797
1798 /* Check if packing mode is enabled and if there is more than 2 data to receive */
1799 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))
1800 {
1801 /* Set RX Fifo threshold according the reception data length: 16 bit */
1802 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1803 }
1804 else
1805 {
1806 /* Set RX Fifo threshold according the reception data length: 8 bit */
1807 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1808 }
1809
1810 /* Enable TXE, RXNE and ERR interrupt */
1811 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
1812
1813 /* Check if the SPI is already enabled */
1814 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1815 {
1816 /* Enable SPI peripheral */
1817 __HAL_SPI_ENABLE(hspi);
1818 }
1819
1820 error :
1821 /* Process Unlocked */
1822 __HAL_UNLOCK(hspi);
1823 return errorcode;
1824 }
1825
1826 /**
1827 * @brief Transmit an amount of data in non-blocking mode with DMA.
1828 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1829 * the configuration information for SPI module.
1830 * @param pData pointer to data buffer
1831 * @param Size amount of data to be sent
1832 * @retval HAL status
1833 */
HAL_SPI_Transmit_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1834 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1835 {
1836 HAL_StatusTypeDef errorcode = HAL_OK;
1837
1838 /* Check tx dma handle */
1839 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1840
1841 /* Check Direction parameter */
1842 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1843
1844 /* Process Locked */
1845 __HAL_LOCK(hspi);
1846
1847 if (hspi->State != HAL_SPI_STATE_READY)
1848 {
1849 errorcode = HAL_BUSY;
1850 goto error;
1851 }
1852
1853 if ((pData == NULL) || (Size == 0U))
1854 {
1855 errorcode = HAL_ERROR;
1856 goto error;
1857 }
1858
1859 /* Set the transaction information */
1860 hspi->State = HAL_SPI_STATE_BUSY_TX;
1861 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1862 hspi->pTxBuffPtr = (uint8_t *)pData;
1863 hspi->TxXferSize = Size;
1864 hspi->TxXferCount = Size;
1865
1866 /* Init field not used in handle to zero */
1867 hspi->pRxBuffPtr = (uint8_t *)NULL;
1868 hspi->TxISR = NULL;
1869 hspi->RxISR = NULL;
1870 hspi->RxXferSize = 0U;
1871 hspi->RxXferCount = 0U;
1872
1873 /* Configure communication direction : 1Line */
1874 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1875 {
1876 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1877 __HAL_SPI_DISABLE(hspi);
1878 SPI_1LINE_TX(hspi);
1879 }
1880
1881 #if (USE_SPI_CRC != 0U)
1882 /* Reset CRC Calculation */
1883 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1884 {
1885 SPI_RESET_CRC(hspi);
1886 }
1887 #endif /* USE_SPI_CRC */
1888
1889 /* Set the SPI TxDMA Half transfer complete callback */
1890 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
1891
1892 /* Set the SPI TxDMA transfer complete callback */
1893 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
1894
1895 /* Set the DMA error callback */
1896 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1897
1898 /* Set the DMA AbortCpltCallback */
1899 hspi->hdmatx->XferAbortCallback = NULL;
1900
1901 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1902 /* Packing mode is enabled only if the DMA setting is HALWORD */
1903 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
1904 {
1905 /* Check the even/odd of the data size + crc if enabled */
1906 if ((hspi->TxXferCount & 0x1U) == 0U)
1907 {
1908 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1909 hspi->TxXferCount = (hspi->TxXferCount >> 1U);
1910 }
1911 else
1912 {
1913 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1914 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
1915 }
1916 }
1917
1918 /* Enable the Tx DMA Stream/Channel */
1919 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
1920 hspi->TxXferCount))
1921 {
1922 /* Update SPI error code */
1923 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1924 errorcode = HAL_ERROR;
1925
1926 hspi->State = HAL_SPI_STATE_READY;
1927 goto error;
1928 }
1929
1930 /* Check if the SPI is already enabled */
1931 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1932 {
1933 /* Enable SPI peripheral */
1934 __HAL_SPI_ENABLE(hspi);
1935 }
1936
1937 /* Enable the SPI Error Interrupt Bit */
1938 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1939
1940 /* Enable Tx DMA Request */
1941 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1942
1943 error :
1944 /* Process Unlocked */
1945 __HAL_UNLOCK(hspi);
1946 return errorcode;
1947 }
1948
1949 /**
1950 * @brief Receive an amount of data in non-blocking mode with DMA.
1951 * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
1952 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1953 * the configuration information for SPI module.
1954 * @param pData pointer to data buffer
1955 * @note When the CRC feature is enabled the pData Length must be Size + 1.
1956 * @param Size amount of data to be sent
1957 * @retval HAL status
1958 */
HAL_SPI_Receive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1959 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1960 {
1961 HAL_StatusTypeDef errorcode = HAL_OK;
1962
1963 /* Check rx dma handle */
1964 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
1965
1966 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1967 {
1968 hspi->State = HAL_SPI_STATE_BUSY_RX;
1969
1970 /* Check tx dma handle */
1971 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1972
1973 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1974 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
1975 }
1976
1977 /* Process Locked */
1978 __HAL_LOCK(hspi);
1979
1980 if (hspi->State != HAL_SPI_STATE_READY)
1981 {
1982 errorcode = HAL_BUSY;
1983 goto error;
1984 }
1985
1986 if ((pData == NULL) || (Size == 0U))
1987 {
1988 errorcode = HAL_ERROR;
1989 goto error;
1990 }
1991
1992 /* Set the transaction information */
1993 hspi->State = HAL_SPI_STATE_BUSY_RX;
1994 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1995 hspi->pRxBuffPtr = (uint8_t *)pData;
1996 hspi->RxXferSize = Size;
1997 hspi->RxXferCount = Size;
1998
1999 /*Init field not used in handle to zero */
2000 hspi->RxISR = NULL;
2001 hspi->TxISR = NULL;
2002 hspi->TxXferSize = 0U;
2003 hspi->TxXferCount = 0U;
2004
2005 /* Configure communication direction : 1Line */
2006 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
2007 {
2008 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
2009 __HAL_SPI_DISABLE(hspi);
2010 SPI_1LINE_RX(hspi);
2011 }
2012
2013 #if (USE_SPI_CRC != 0U)
2014 /* Reset CRC Calculation */
2015 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2016 {
2017 SPI_RESET_CRC(hspi);
2018 }
2019 #endif /* USE_SPI_CRC */
2020
2021
2022 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2023 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
2024 {
2025 /* Set RX Fifo threshold according the reception data length: 16bit */
2026 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2027 }
2028 else
2029 {
2030 /* Set RX Fifo threshold according the reception data length: 8bit */
2031 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2032
2033 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2034 {
2035 /* Set RX Fifo threshold according the reception data length: 16bit */
2036 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2037
2038 if ((hspi->RxXferCount & 0x1U) == 0x0U)
2039 {
2040 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2041 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2042 }
2043 else
2044 {
2045 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2046 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2047 }
2048 }
2049 }
2050
2051 /* Set the SPI RxDMA Half transfer complete callback */
2052 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2053
2054 /* Set the SPI Rx DMA transfer complete callback */
2055 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2056
2057 /* Set the DMA error callback */
2058 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2059
2060 /* Set the DMA AbortCpltCallback */
2061 hspi->hdmarx->XferAbortCallback = NULL;
2062
2063 /* Enable the Rx DMA Stream/Channel */
2064 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
2065 hspi->RxXferCount))
2066 {
2067 /* Update SPI error code */
2068 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2069 errorcode = HAL_ERROR;
2070
2071 hspi->State = HAL_SPI_STATE_READY;
2072 goto error;
2073 }
2074
2075 /* Check if the SPI is already enabled */
2076 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2077 {
2078 /* Enable SPI peripheral */
2079 __HAL_SPI_ENABLE(hspi);
2080 }
2081
2082 /* Enable the SPI Error Interrupt Bit */
2083 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2084
2085 /* Enable Rx DMA Request */
2086 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2087
2088 error:
2089 /* Process Unlocked */
2090 __HAL_UNLOCK(hspi);
2091 return errorcode;
2092 }
2093
2094 /**
2095 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
2096 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2097 * the configuration information for SPI module.
2098 * @param pTxData pointer to transmission data buffer
2099 * @param pRxData pointer to reception data buffer
2100 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
2101 * @param Size amount of data to be sent
2102 * @retval HAL status
2103 */
HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)2104 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
2105 uint16_t Size)
2106 {
2107 uint32_t tmp_mode;
2108 HAL_SPI_StateTypeDef tmp_state;
2109 HAL_StatusTypeDef errorcode = HAL_OK;
2110
2111 /* Check rx & tx dma handles */
2112 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
2113 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
2114
2115 /* Check Direction parameter */
2116 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
2117
2118 /* Process locked */
2119 __HAL_LOCK(hspi);
2120
2121 /* Init temporary variables */
2122 tmp_state = hspi->State;
2123 tmp_mode = hspi->Init.Mode;
2124
2125 if (!((tmp_state == HAL_SPI_STATE_READY) ||
2126 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
2127 {
2128 errorcode = HAL_BUSY;
2129 goto error;
2130 }
2131
2132 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
2133 {
2134 errorcode = HAL_ERROR;
2135 goto error;
2136 }
2137
2138 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
2139 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
2140 {
2141 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
2142 }
2143
2144 /* Set the transaction information */
2145 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2146 hspi->pTxBuffPtr = (uint8_t *)pTxData;
2147 hspi->TxXferSize = Size;
2148 hspi->TxXferCount = Size;
2149 hspi->pRxBuffPtr = (uint8_t *)pRxData;
2150 hspi->RxXferSize = Size;
2151 hspi->RxXferCount = Size;
2152
2153 /* Init field not used in handle to zero */
2154 hspi->RxISR = NULL;
2155 hspi->TxISR = NULL;
2156
2157 #if (USE_SPI_CRC != 0U)
2158 /* Reset CRC Calculation */
2159 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2160 {
2161 SPI_RESET_CRC(hspi);
2162 }
2163 #endif /* USE_SPI_CRC */
2164
2165 /* Reset the threshold bit */
2166 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
2167
2168 /* The packing mode management is enabled by the DMA settings according the spi data size */
2169 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
2170 {
2171 /* Set fiforxthreshold according the reception data length: 16bit */
2172 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2173 }
2174 else
2175 {
2176 /* Set RX Fifo threshold according the reception data length: 8bit */
2177 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2178
2179 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2180 {
2181 if ((hspi->TxXferSize & 0x1U) == 0x0U)
2182 {
2183 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2184 hspi->TxXferCount = hspi->TxXferCount >> 1U;
2185 }
2186 else
2187 {
2188 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2189 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
2190 }
2191 }
2192
2193 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2194 {
2195 /* Set RX Fifo threshold according the reception data length: 16bit */
2196 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2197
2198 if ((hspi->RxXferCount & 0x1U) == 0x0U)
2199 {
2200 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2201 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2202 }
2203 else
2204 {
2205 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2206 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2207 }
2208 }
2209 }
2210
2211 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
2212 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
2213 {
2214 /* Set the SPI Rx DMA Half transfer complete callback */
2215 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2216 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2217 }
2218 else
2219 {
2220 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
2221 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
2222 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
2223 }
2224
2225 /* Set the DMA error callback */
2226 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2227
2228 /* Set the DMA AbortCpltCallback */
2229 hspi->hdmarx->XferAbortCallback = NULL;
2230
2231 /* Enable the Rx DMA Stream/Channel */
2232 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
2233 hspi->RxXferCount))
2234 {
2235 /* Update SPI error code */
2236 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2237 errorcode = HAL_ERROR;
2238
2239 hspi->State = HAL_SPI_STATE_READY;
2240 goto error;
2241 }
2242
2243 /* Enable Rx DMA Request */
2244 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2245
2246 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
2247 is performed in DMA reception complete callback */
2248 hspi->hdmatx->XferHalfCpltCallback = NULL;
2249 hspi->hdmatx->XferCpltCallback = NULL;
2250 hspi->hdmatx->XferErrorCallback = NULL;
2251 hspi->hdmatx->XferAbortCallback = NULL;
2252
2253 /* Enable the Tx DMA Stream/Channel */
2254 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
2255 hspi->TxXferCount))
2256 {
2257 /* Update SPI error code */
2258 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2259 errorcode = HAL_ERROR;
2260
2261 hspi->State = HAL_SPI_STATE_READY;
2262 goto error;
2263 }
2264
2265 /* Check if the SPI is already enabled */
2266 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2267 {
2268 /* Enable SPI peripheral */
2269 __HAL_SPI_ENABLE(hspi);
2270 }
2271 /* Enable the SPI Error Interrupt Bit */
2272 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2273
2274 /* Enable Tx DMA Request */
2275 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2276
2277 error :
2278 /* Process Unlocked */
2279 __HAL_UNLOCK(hspi);
2280 return errorcode;
2281 }
2282
2283 /**
2284 * @brief Abort ongoing transfer (blocking mode).
2285 * @param hspi SPI handle.
2286 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2287 * started in Interrupt or DMA mode.
2288 * This procedure performs following operations :
2289 * - Disable SPI Interrupts (depending of transfer direction)
2290 * - Disable the DMA transfer in the peripheral register (if enabled)
2291 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
2292 * - Set handle State to READY
2293 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
2294 * @retval HAL status
2295 */
HAL_SPI_Abort(SPI_HandleTypeDef * hspi)2296 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
2297 {
2298 HAL_StatusTypeDef errorcode;
2299 __IO uint32_t count;
2300 __IO uint32_t resetcount;
2301
2302 /* Initialized local variable */
2303 errorcode = HAL_OK;
2304 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2305 count = resetcount;
2306
2307 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2308 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2309
2310 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
2311 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2312 {
2313 hspi->TxISR = SPI_AbortTx_ISR;
2314 /* Wait HAL_SPI_STATE_ABORT state */
2315 do
2316 {
2317 if (count == 0U)
2318 {
2319 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2320 break;
2321 }
2322 count--;
2323 } while (hspi->State != HAL_SPI_STATE_ABORT);
2324 /* Reset Timeout Counter */
2325 count = resetcount;
2326 }
2327
2328 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2329 {
2330 hspi->RxISR = SPI_AbortRx_ISR;
2331 /* Wait HAL_SPI_STATE_ABORT state */
2332 do
2333 {
2334 if (count == 0U)
2335 {
2336 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2337 break;
2338 }
2339 count--;
2340 } while (hspi->State != HAL_SPI_STATE_ABORT);
2341 /* Reset Timeout Counter */
2342 count = resetcount;
2343 }
2344
2345 /* Disable the SPI DMA Tx request if enabled */
2346 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2347 {
2348 /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
2349 if (hspi->hdmatx != NULL)
2350 {
2351 /* Set the SPI DMA Abort callback :
2352 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2353 hspi->hdmatx->XferAbortCallback = NULL;
2354
2355 /* Abort DMA Tx Handle linked to SPI Peripheral */
2356 if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
2357 {
2358 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2359 }
2360
2361 /* Disable Tx DMA Request */
2362 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
2363
2364 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2365 {
2366 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2367 }
2368
2369 /* Disable SPI Peripheral */
2370 __HAL_SPI_DISABLE(hspi);
2371
2372 /* Empty the FRLVL fifo */
2373 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2374 {
2375 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2376 }
2377 }
2378 }
2379
2380 /* Disable the SPI DMA Rx request if enabled */
2381 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2382 {
2383 /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
2384 if (hspi->hdmarx != NULL)
2385 {
2386 /* Set the SPI DMA Abort callback :
2387 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2388 hspi->hdmarx->XferAbortCallback = NULL;
2389
2390 /* Abort DMA Rx Handle linked to SPI Peripheral */
2391 if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
2392 {
2393 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2394 }
2395
2396 /* Disable peripheral */
2397 __HAL_SPI_DISABLE(hspi);
2398
2399 /* Control the BSY flag */
2400 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2401 {
2402 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2403 }
2404
2405 /* Empty the FRLVL fifo */
2406 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2407 {
2408 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2409 }
2410
2411 /* Disable Rx DMA Request */
2412 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
2413 }
2414 }
2415 /* Reset Tx and Rx transfer counters */
2416 hspi->RxXferCount = 0U;
2417 hspi->TxXferCount = 0U;
2418
2419 /* Check error during Abort procedure */
2420 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2421 {
2422 /* return HAL_Error in case of error during Abort procedure */
2423 errorcode = HAL_ERROR;
2424 }
2425 else
2426 {
2427 /* Reset errorCode */
2428 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2429 }
2430
2431 /* Clear the Error flags in the SR register */
2432 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2433 __HAL_SPI_CLEAR_FREFLAG(hspi);
2434
2435 /* Restore hspi->state to ready */
2436 hspi->State = HAL_SPI_STATE_READY;
2437
2438 return errorcode;
2439 }
2440
2441 /**
2442 * @brief Abort ongoing transfer (Interrupt mode).
2443 * @param hspi SPI handle.
2444 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2445 * started in Interrupt or DMA mode.
2446 * This procedure performs following operations :
2447 * - Disable SPI Interrupts (depending of transfer direction)
2448 * - Disable the DMA transfer in the peripheral register (if enabled)
2449 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
2450 * - Set handle State to READY
2451 * - At abort completion, call user abort complete callback
2452 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
2453 * considered as completed only when user abort complete callback is executed (not when exiting function).
2454 * @retval HAL status
2455 */
HAL_SPI_Abort_IT(SPI_HandleTypeDef * hspi)2456 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
2457 {
2458 HAL_StatusTypeDef errorcode;
2459 uint32_t abortcplt ;
2460 __IO uint32_t count;
2461 __IO uint32_t resetcount;
2462
2463 /* Initialized local variable */
2464 errorcode = HAL_OK;
2465 abortcplt = 1U;
2466 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2467 count = resetcount;
2468
2469 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2470 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2471
2472 /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
2473 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2474 {
2475 hspi->TxISR = SPI_AbortTx_ISR;
2476 /* Wait HAL_SPI_STATE_ABORT state */
2477 do
2478 {
2479 if (count == 0U)
2480 {
2481 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2482 break;
2483 }
2484 count--;
2485 } while (hspi->State != HAL_SPI_STATE_ABORT);
2486 /* Reset Timeout Counter */
2487 count = resetcount;
2488 }
2489
2490 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2491 {
2492 hspi->RxISR = SPI_AbortRx_ISR;
2493 /* Wait HAL_SPI_STATE_ABORT state */
2494 do
2495 {
2496 if (count == 0U)
2497 {
2498 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2499 break;
2500 }
2501 count--;
2502 } while (hspi->State != HAL_SPI_STATE_ABORT);
2503 /* Reset Timeout Counter */
2504 count = resetcount;
2505 }
2506
2507 /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
2508 before any call to DMA Abort functions */
2509 /* DMA Tx Handle is valid */
2510 if (hspi->hdmatx != NULL)
2511 {
2512 /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
2513 Otherwise, set it to NULL */
2514 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2515 {
2516 hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
2517 }
2518 else
2519 {
2520 hspi->hdmatx->XferAbortCallback = NULL;
2521 }
2522 }
2523 /* DMA Rx Handle is valid */
2524 if (hspi->hdmarx != NULL)
2525 {
2526 /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
2527 Otherwise, set it to NULL */
2528 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2529 {
2530 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
2531 }
2532 else
2533 {
2534 hspi->hdmarx->XferAbortCallback = NULL;
2535 }
2536 }
2537
2538 /* Disable the SPI DMA Tx request if enabled */
2539 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2540 {
2541 /* Abort the SPI DMA Tx Stream/Channel */
2542 if (hspi->hdmatx != NULL)
2543 {
2544 /* Abort DMA Tx Handle linked to SPI Peripheral */
2545 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
2546 {
2547 hspi->hdmatx->XferAbortCallback = NULL;
2548 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2549 }
2550 else
2551 {
2552 abortcplt = 0U;
2553 }
2554 }
2555 }
2556 /* Disable the SPI DMA Rx request if enabled */
2557 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2558 {
2559 /* Abort the SPI DMA Rx Stream/Channel */
2560 if (hspi->hdmarx != NULL)
2561 {
2562 /* Abort DMA Rx Handle linked to SPI Peripheral */
2563 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
2564 {
2565 hspi->hdmarx->XferAbortCallback = NULL;
2566 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2567 }
2568 else
2569 {
2570 abortcplt = 0U;
2571 }
2572 }
2573 }
2574
2575 if (abortcplt == 1U)
2576 {
2577 /* Reset Tx and Rx transfer counters */
2578 hspi->RxXferCount = 0U;
2579 hspi->TxXferCount = 0U;
2580
2581 /* Check error during Abort procedure */
2582 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2583 {
2584 /* return HAL_Error in case of error during Abort procedure */
2585 errorcode = HAL_ERROR;
2586 }
2587 else
2588 {
2589 /* Reset errorCode */
2590 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2591 }
2592
2593 /* Clear the Error flags in the SR register */
2594 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2595 __HAL_SPI_CLEAR_FREFLAG(hspi);
2596
2597 /* Restore hspi->State to Ready */
2598 hspi->State = HAL_SPI_STATE_READY;
2599
2600 /* As no DMA to be aborted, call directly user Abort complete callback */
2601 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2602 hspi->AbortCpltCallback(hspi);
2603 #else
2604 HAL_SPI_AbortCpltCallback(hspi);
2605 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2606 }
2607
2608 return errorcode;
2609 }
2610
2611 /**
2612 * @brief Pause the DMA Transfer.
2613 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2614 * the configuration information for the specified SPI module.
2615 * @retval HAL status
2616 */
HAL_SPI_DMAPause(SPI_HandleTypeDef * hspi)2617 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
2618 {
2619 /* Process Locked */
2620 __HAL_LOCK(hspi);
2621
2622 /* Disable the SPI DMA Tx & Rx requests */
2623 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2624
2625 /* Process Unlocked */
2626 __HAL_UNLOCK(hspi);
2627
2628 return HAL_OK;
2629 }
2630
2631 /**
2632 * @brief Resume the DMA Transfer.
2633 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2634 * the configuration information for the specified SPI module.
2635 * @retval HAL status
2636 */
HAL_SPI_DMAResume(SPI_HandleTypeDef * hspi)2637 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
2638 {
2639 /* Process Locked */
2640 __HAL_LOCK(hspi);
2641
2642 /* Enable the SPI DMA Tx & Rx requests */
2643 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2644
2645 /* Process Unlocked */
2646 __HAL_UNLOCK(hspi);
2647
2648 return HAL_OK;
2649 }
2650
2651 /**
2652 * @brief Stop the DMA Transfer.
2653 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2654 * the configuration information for the specified SPI module.
2655 * @retval HAL status
2656 */
HAL_SPI_DMAStop(SPI_HandleTypeDef * hspi)2657 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
2658 {
2659 HAL_StatusTypeDef errorcode = HAL_OK;
2660 /* The Lock is not implemented on this API to allow the user application
2661 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
2662 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
2663 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
2664 */
2665
2666 /* Abort the SPI DMA tx Stream/Channel */
2667 if (hspi->hdmatx != NULL)
2668 {
2669 if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
2670 {
2671 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2672 errorcode = HAL_ERROR;
2673 }
2674 }
2675 /* Abort the SPI DMA rx Stream/Channel */
2676 if (hspi->hdmarx != NULL)
2677 {
2678 if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
2679 {
2680 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2681 errorcode = HAL_ERROR;
2682 }
2683 }
2684
2685 /* Disable the SPI DMA Tx & Rx requests */
2686 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2687 hspi->State = HAL_SPI_STATE_READY;
2688 return errorcode;
2689 }
2690
2691 /**
2692 * @brief Handle SPI interrupt request.
2693 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2694 * the configuration information for the specified SPI module.
2695 * @retval None
2696 */
HAL_SPI_IRQHandler(SPI_HandleTypeDef * hspi)2697 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
2698 {
2699 uint32_t itsource = hspi->Instance->CR2;
2700 uint32_t itflag = hspi->Instance->SR;
2701
2702 /* SPI in mode Receiver ----------------------------------------------------*/
2703 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
2704 (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
2705 {
2706 hspi->RxISR(hspi);
2707 return;
2708 }
2709
2710 /* SPI in mode Transmitter -------------------------------------------------*/
2711 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
2712 {
2713 hspi->TxISR(hspi);
2714 return;
2715 }
2716
2717 /* SPI in Error Treatment --------------------------------------------------*/
2718 if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2719 || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
2720 {
2721 /* SPI Overrun error interrupt occurred ----------------------------------*/
2722 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2723 {
2724 if (hspi->State != HAL_SPI_STATE_BUSY_TX)
2725 {
2726 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
2727 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2728 }
2729 else
2730 {
2731 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2732 return;
2733 }
2734 }
2735
2736 /* SPI Mode Fault error interrupt occurred -------------------------------*/
2737 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
2738 {
2739 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
2740 __HAL_SPI_CLEAR_MODFFLAG(hspi);
2741 }
2742
2743 /* SPI Frame error interrupt occurred ------------------------------------*/
2744 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
2745 {
2746 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
2747 __HAL_SPI_CLEAR_FREFLAG(hspi);
2748 }
2749
2750 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2751 {
2752 /* Disable all interrupts */
2753 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
2754
2755 hspi->State = HAL_SPI_STATE_READY;
2756 /* Disable the SPI DMA requests if enabled */
2757 if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
2758 {
2759 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
2760
2761 /* Abort the SPI DMA Rx channel */
2762 if (hspi->hdmarx != NULL)
2763 {
2764 /* Set the SPI DMA Abort callback :
2765 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2766 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
2767 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
2768 {
2769 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2770 }
2771 }
2772 /* Abort the SPI DMA Tx channel */
2773 if (hspi->hdmatx != NULL)
2774 {
2775 /* Set the SPI DMA Abort callback :
2776 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2777 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
2778 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
2779 {
2780 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2781 }
2782 }
2783 }
2784 else
2785 {
2786 /* Call user error callback */
2787 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2788 hspi->ErrorCallback(hspi);
2789 #else
2790 HAL_SPI_ErrorCallback(hspi);
2791 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2792 }
2793 }
2794 return;
2795 }
2796 }
2797
2798 /**
2799 * @brief Tx Transfer completed callback.
2800 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2801 * the configuration information for SPI module.
2802 * @retval None
2803 */
HAL_SPI_TxCpltCallback(SPI_HandleTypeDef * hspi)2804 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
2805 {
2806 /* Prevent unused argument(s) compilation warning */
2807 UNUSED(hspi);
2808
2809 /* NOTE : This function should not be modified, when the callback is needed,
2810 the HAL_SPI_TxCpltCallback should be implemented in the user file
2811 */
2812 }
2813
2814 /**
2815 * @brief Rx Transfer completed callback.
2816 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2817 * the configuration information for SPI module.
2818 * @retval None
2819 */
HAL_SPI_RxCpltCallback(SPI_HandleTypeDef * hspi)2820 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
2821 {
2822 /* Prevent unused argument(s) compilation warning */
2823 UNUSED(hspi);
2824
2825 /* NOTE : This function should not be modified, when the callback is needed,
2826 the HAL_SPI_RxCpltCallback should be implemented in the user file
2827 */
2828 }
2829
2830 /**
2831 * @brief Tx and Rx Transfer completed callback.
2832 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2833 * the configuration information for SPI module.
2834 * @retval None
2835 */
HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef * hspi)2836 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
2837 {
2838 /* Prevent unused argument(s) compilation warning */
2839 UNUSED(hspi);
2840
2841 /* NOTE : This function should not be modified, when the callback is needed,
2842 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
2843 */
2844 }
2845
2846 /**
2847 * @brief Tx Half Transfer completed callback.
2848 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2849 * the configuration information for SPI module.
2850 * @retval None
2851 */
HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef * hspi)2852 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2853 {
2854 /* Prevent unused argument(s) compilation warning */
2855 UNUSED(hspi);
2856
2857 /* NOTE : This function should not be modified, when the callback is needed,
2858 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
2859 */
2860 }
2861
2862 /**
2863 * @brief Rx Half Transfer completed callback.
2864 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2865 * the configuration information for SPI module.
2866 * @retval None
2867 */
HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef * hspi)2868 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2869 {
2870 /* Prevent unused argument(s) compilation warning */
2871 UNUSED(hspi);
2872
2873 /* NOTE : This function should not be modified, when the callback is needed,
2874 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
2875 */
2876 }
2877
2878 /**
2879 * @brief Tx and Rx Half Transfer callback.
2880 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2881 * the configuration information for SPI module.
2882 * @retval None
2883 */
HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef * hspi)2884 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2885 {
2886 /* Prevent unused argument(s) compilation warning */
2887 UNUSED(hspi);
2888
2889 /* NOTE : This function should not be modified, when the callback is needed,
2890 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
2891 */
2892 }
2893
2894 /**
2895 * @brief SPI error callback.
2896 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2897 * the configuration information for SPI module.
2898 * @retval None
2899 */
HAL_SPI_ErrorCallback(SPI_HandleTypeDef * hspi)2900 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
2901 {
2902 /* Prevent unused argument(s) compilation warning */
2903 UNUSED(hspi);
2904
2905 /* NOTE : This function should not be modified, when the callback is needed,
2906 the HAL_SPI_ErrorCallback should be implemented in the user file
2907 */
2908 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
2909 and user can use HAL_SPI_GetError() API to check the latest error occurred
2910 */
2911 }
2912
2913 /**
2914 * @brief SPI Abort Complete callback.
2915 * @param hspi SPI handle.
2916 * @retval None
2917 */
HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef * hspi)2918 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
2919 {
2920 /* Prevent unused argument(s) compilation warning */
2921 UNUSED(hspi);
2922
2923 /* NOTE : This function should not be modified, when the callback is needed,
2924 the HAL_SPI_AbortCpltCallback can be implemented in the user file.
2925 */
2926 }
2927
2928 /**
2929 * @}
2930 */
2931
2932 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
2933 * @brief SPI control functions
2934 *
2935 @verbatim
2936 ===============================================================================
2937 ##### Peripheral State and Errors functions #####
2938 ===============================================================================
2939 [..]
2940 This subsection provides a set of functions allowing to control the SPI.
2941 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
2942 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
2943 @endverbatim
2944 * @{
2945 */
2946
2947 /**
2948 * @brief Return the SPI handle state.
2949 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2950 * the configuration information for SPI module.
2951 * @retval SPI state
2952 */
HAL_SPI_GetState(SPI_HandleTypeDef * hspi)2953 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
2954 {
2955 /* Return SPI handle state */
2956 return hspi->State;
2957 }
2958
2959 /**
2960 * @brief Return the SPI error code.
2961 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2962 * the configuration information for SPI module.
2963 * @retval SPI error code in bitmap format
2964 */
HAL_SPI_GetError(SPI_HandleTypeDef * hspi)2965 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
2966 {
2967 /* Return SPI ErrorCode */
2968 return hspi->ErrorCode;
2969 }
2970
2971 /**
2972 * @}
2973 */
2974
2975 /**
2976 * @}
2977 */
2978
2979 /** @addtogroup SPI_Private_Functions
2980 * @brief Private functions
2981 * @{
2982 */
2983
2984 /**
2985 * @brief DMA SPI transmit process complete callback.
2986 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2987 * the configuration information for the specified DMA module.
2988 * @retval None
2989 */
SPI_DMATransmitCplt(DMA_HandleTypeDef * hdma)2990 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
2991 {
2992 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2993 uint32_t tickstart;
2994
2995 /* Init tickstart for timeout management*/
2996 tickstart = HAL_GetTick();
2997
2998 /* DMA Normal Mode */
2999 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3000 {
3001 /* Disable ERR interrupt */
3002 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3003
3004 /* Disable Tx DMA Request */
3005 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3006
3007 /* Check the end of the transaction */
3008 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3009 {
3010 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3011 }
3012
3013 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
3014 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
3015 {
3016 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3017 }
3018
3019 hspi->TxXferCount = 0U;
3020 hspi->State = HAL_SPI_STATE_READY;
3021
3022 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3023 {
3024 /* Call user error callback */
3025 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3026 hspi->ErrorCallback(hspi);
3027 #else
3028 HAL_SPI_ErrorCallback(hspi);
3029 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3030 return;
3031 }
3032 }
3033 /* Call user Tx complete callback */
3034 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3035 hspi->TxCpltCallback(hspi);
3036 #else
3037 HAL_SPI_TxCpltCallback(hspi);
3038 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3039 }
3040
3041 /**
3042 * @brief DMA SPI receive process complete callback.
3043 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3044 * the configuration information for the specified DMA module.
3045 * @retval None
3046 */
SPI_DMAReceiveCplt(DMA_HandleTypeDef * hdma)3047 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
3048 {
3049 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3050 uint32_t tickstart;
3051
3052 /* Init tickstart for timeout management*/
3053 tickstart = HAL_GetTick();
3054
3055 /* DMA Normal Mode */
3056 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3057 {
3058 /* Disable ERR interrupt */
3059 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3060
3061 #if (USE_SPI_CRC != 0U)
3062 /* CRC handling */
3063 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3064 {
3065 /* Wait until RXNE flag */
3066 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3067 {
3068 /* Error on the CRC reception */
3069 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3070 }
3071 /* Read CRC */
3072 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
3073 {
3074 /* Read 16bit CRC */
3075 READ_REG(hspi->Instance->DR);
3076 }
3077 else
3078 {
3079 /* Read 8bit CRC */
3080 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3081
3082 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
3083 {
3084 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3085 {
3086 /* Error on the CRC reception */
3087 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3088 }
3089 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
3090 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3091 }
3092 }
3093 }
3094 #endif /* USE_SPI_CRC */
3095
3096 /* Check if we are in Master RX 2 line mode */
3097 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
3098 {
3099 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
3100 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3101 }
3102 else
3103 {
3104 /* Normal case */
3105 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3106 }
3107
3108 /* Check the end of the transaction */
3109 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3110 {
3111 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
3112 }
3113
3114 hspi->RxXferCount = 0U;
3115 hspi->State = HAL_SPI_STATE_READY;
3116
3117 #if (USE_SPI_CRC != 0U)
3118 /* Check if CRC error occurred */
3119 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3120 {
3121 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3122 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3123 }
3124 #endif /* USE_SPI_CRC */
3125
3126 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3127 {
3128 /* Call user error callback */
3129 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3130 hspi->ErrorCallback(hspi);
3131 #else
3132 HAL_SPI_ErrorCallback(hspi);
3133 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3134 return;
3135 }
3136 }
3137 /* Call user Rx complete callback */
3138 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3139 hspi->RxCpltCallback(hspi);
3140 #else
3141 HAL_SPI_RxCpltCallback(hspi);
3142 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3143 }
3144
3145 /**
3146 * @brief DMA SPI transmit receive process complete callback.
3147 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3148 * the configuration information for the specified DMA module.
3149 * @retval None
3150 */
SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef * hdma)3151 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3152 {
3153 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3154 uint32_t tickstart;
3155
3156 /* Init tickstart for timeout management*/
3157 tickstart = HAL_GetTick();
3158
3159 /* DMA Normal Mode */
3160 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3161 {
3162 /* Disable ERR interrupt */
3163 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3164
3165 #if (USE_SPI_CRC != 0U)
3166 /* CRC handling */
3167 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3168 {
3169 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
3170 {
3171 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
3172 tickstart) != HAL_OK)
3173 {
3174 /* Error on the CRC reception */
3175 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3176 }
3177 /* Read CRC to Flush DR and RXNE flag */
3178 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3179 }
3180 else
3181 {
3182 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3183 {
3184 /* Error on the CRC reception */
3185 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3186 }
3187 /* Read CRC to Flush DR and RXNE flag */
3188 READ_REG(hspi->Instance->DR);
3189 }
3190 }
3191 #endif /* USE_SPI_CRC */
3192
3193 /* Check the end of the transaction */
3194 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3195 {
3196 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3197 }
3198
3199 /* Disable Rx/Tx DMA Request */
3200 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3201
3202 hspi->TxXferCount = 0U;
3203 hspi->RxXferCount = 0U;
3204 hspi->State = HAL_SPI_STATE_READY;
3205
3206 #if (USE_SPI_CRC != 0U)
3207 /* Check if CRC error occurred */
3208 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3209 {
3210 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3211 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3212 }
3213 #endif /* USE_SPI_CRC */
3214
3215 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3216 {
3217 /* Call user error callback */
3218 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3219 hspi->ErrorCallback(hspi);
3220 #else
3221 HAL_SPI_ErrorCallback(hspi);
3222 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3223 return;
3224 }
3225 }
3226 /* Call user TxRx complete callback */
3227 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3228 hspi->TxRxCpltCallback(hspi);
3229 #else
3230 HAL_SPI_TxRxCpltCallback(hspi);
3231 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3232 }
3233
3234 /**
3235 * @brief DMA SPI half transmit process complete callback.
3236 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3237 * the configuration information for the specified DMA module.
3238 * @retval None
3239 */
SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef * hdma)3240 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
3241 {
3242 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3243
3244 /* Call user Tx half complete callback */
3245 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3246 hspi->TxHalfCpltCallback(hspi);
3247 #else
3248 HAL_SPI_TxHalfCpltCallback(hspi);
3249 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3250 }
3251
3252 /**
3253 * @brief DMA SPI half receive process complete callback
3254 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3255 * the configuration information for the specified DMA module.
3256 * @retval None
3257 */
SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef * hdma)3258 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
3259 {
3260 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3261
3262 /* Call user Rx half complete callback */
3263 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3264 hspi->RxHalfCpltCallback(hspi);
3265 #else
3266 HAL_SPI_RxHalfCpltCallback(hspi);
3267 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3268 }
3269
3270 /**
3271 * @brief DMA SPI half transmit receive process complete callback.
3272 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3273 * the configuration information for the specified DMA module.
3274 * @retval None
3275 */
SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef * hdma)3276 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3277 {
3278 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3279
3280 /* Call user TxRx half complete callback */
3281 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3282 hspi->TxRxHalfCpltCallback(hspi);
3283 #else
3284 HAL_SPI_TxRxHalfCpltCallback(hspi);
3285 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3286 }
3287
3288 /**
3289 * @brief DMA SPI communication error callback.
3290 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3291 * the configuration information for the specified DMA module.
3292 * @retval None
3293 */
SPI_DMAError(DMA_HandleTypeDef * hdma)3294 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
3295 {
3296 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3297
3298 /* Stop the disable DMA transfer on SPI side */
3299 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3300
3301 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
3302 hspi->State = HAL_SPI_STATE_READY;
3303 /* Call user error callback */
3304 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3305 hspi->ErrorCallback(hspi);
3306 #else
3307 HAL_SPI_ErrorCallback(hspi);
3308 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3309 }
3310
3311 /**
3312 * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
3313 * (To be called at end of DMA Abort procedure following error occurrence).
3314 * @param hdma DMA handle.
3315 * @retval None
3316 */
SPI_DMAAbortOnError(DMA_HandleTypeDef * hdma)3317 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
3318 {
3319 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3320 hspi->RxXferCount = 0U;
3321 hspi->TxXferCount = 0U;
3322
3323 /* Call user error callback */
3324 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3325 hspi->ErrorCallback(hspi);
3326 #else
3327 HAL_SPI_ErrorCallback(hspi);
3328 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3329 }
3330
3331 /**
3332 * @brief DMA SPI Tx communication abort callback, when initiated by user
3333 * (To be called at end of DMA Tx Abort procedure following user abort request).
3334 * @note When this callback is executed, User Abort complete call back is called only if no
3335 * Abort still ongoing for Rx DMA Handle.
3336 * @param hdma DMA handle.
3337 * @retval None
3338 */
SPI_DMATxAbortCallback(DMA_HandleTypeDef * hdma)3339 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
3340 {
3341 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3342
3343 hspi->hdmatx->XferAbortCallback = NULL;
3344
3345 /* Disable Tx DMA Request */
3346 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3347
3348 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3349 {
3350 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3351 }
3352
3353 /* Disable SPI Peripheral */
3354 __HAL_SPI_DISABLE(hspi);
3355
3356 /* Empty the FRLVL fifo */
3357 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3358 {
3359 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3360 }
3361
3362 /* Check if an Abort process is still ongoing */
3363 if (hspi->hdmarx != NULL)
3364 {
3365 if (hspi->hdmarx->XferAbortCallback != NULL)
3366 {
3367 return;
3368 }
3369 }
3370
3371 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3372 hspi->RxXferCount = 0U;
3373 hspi->TxXferCount = 0U;
3374
3375 /* Check no error during Abort procedure */
3376 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3377 {
3378 /* Reset errorCode */
3379 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3380 }
3381
3382 /* Clear the Error flags in the SR register */
3383 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3384 __HAL_SPI_CLEAR_FREFLAG(hspi);
3385
3386 /* Restore hspi->State to Ready */
3387 hspi->State = HAL_SPI_STATE_READY;
3388
3389 /* Call user Abort complete callback */
3390 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3391 hspi->AbortCpltCallback(hspi);
3392 #else
3393 HAL_SPI_AbortCpltCallback(hspi);
3394 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3395 }
3396
3397 /**
3398 * @brief DMA SPI Rx communication abort callback, when initiated by user
3399 * (To be called at end of DMA Rx Abort procedure following user abort request).
3400 * @note When this callback is executed, User Abort complete call back is called only if no
3401 * Abort still ongoing for Tx DMA Handle.
3402 * @param hdma DMA handle.
3403 * @retval None
3404 */
SPI_DMARxAbortCallback(DMA_HandleTypeDef * hdma)3405 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
3406 {
3407 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3408
3409 /* Disable SPI Peripheral */
3410 __HAL_SPI_DISABLE(hspi);
3411
3412 hspi->hdmarx->XferAbortCallback = NULL;
3413
3414 /* Disable Rx DMA Request */
3415 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3416
3417 /* Control the BSY flag */
3418 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3419 {
3420 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3421 }
3422
3423 /* Empty the FRLVL fifo */
3424 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3425 {
3426 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3427 }
3428
3429 /* Check if an Abort process is still ongoing */
3430 if (hspi->hdmatx != NULL)
3431 {
3432 if (hspi->hdmatx->XferAbortCallback != NULL)
3433 {
3434 return;
3435 }
3436 }
3437
3438 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3439 hspi->RxXferCount = 0U;
3440 hspi->TxXferCount = 0U;
3441
3442 /* Check no error during Abort procedure */
3443 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3444 {
3445 /* Reset errorCode */
3446 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3447 }
3448
3449 /* Clear the Error flags in the SR register */
3450 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3451 __HAL_SPI_CLEAR_FREFLAG(hspi);
3452
3453 /* Restore hspi->State to Ready */
3454 hspi->State = HAL_SPI_STATE_READY;
3455
3456 /* Call user Abort complete callback */
3457 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3458 hspi->AbortCpltCallback(hspi);
3459 #else
3460 HAL_SPI_AbortCpltCallback(hspi);
3461 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3462 }
3463
3464 /**
3465 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3466 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3467 * the configuration information for SPI module.
3468 * @retval None
3469 */
SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3470 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3471 {
3472 /* Receive data in packing mode */
3473 if (hspi->RxXferCount > 1U)
3474 {
3475 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3476 hspi->pRxBuffPtr += sizeof(uint16_t);
3477 hspi->RxXferCount -= 2U;
3478 if (hspi->RxXferCount == 1U)
3479 {
3480 /* Set RX Fifo threshold according the reception data length: 8bit */
3481 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3482 }
3483 }
3484 /* Receive data in 8 Bit mode */
3485 else
3486 {
3487 *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
3488 hspi->pRxBuffPtr++;
3489 hspi->RxXferCount--;
3490 }
3491
3492 /* Check end of the reception */
3493 if (hspi->RxXferCount == 0U)
3494 {
3495 #if (USE_SPI_CRC != 0U)
3496 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3497 {
3498 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3499 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
3500 return;
3501 }
3502 #endif /* USE_SPI_CRC */
3503
3504 /* Disable RXNE and ERR interrupt */
3505 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3506
3507 if (hspi->TxXferCount == 0U)
3508 {
3509 SPI_CloseRxTx_ISR(hspi);
3510 }
3511 }
3512 }
3513
3514 #if (USE_SPI_CRC != 0U)
3515 /**
3516 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3517 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3518 * the configuration information for SPI module.
3519 * @retval None
3520 */
SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3521 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3522 {
3523 /* Read 8bit CRC to flush Data Register */
3524 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3525
3526 hspi->CRCSize--;
3527
3528 /* Check end of the reception */
3529 if (hspi->CRCSize == 0U)
3530 {
3531 /* Disable RXNE and ERR interrupt */
3532 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3533
3534 if (hspi->TxXferCount == 0U)
3535 {
3536 SPI_CloseRxTx_ISR(hspi);
3537 }
3538 }
3539 }
3540 #endif /* USE_SPI_CRC */
3541
3542 /**
3543 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
3544 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3545 * the configuration information for SPI module.
3546 * @retval None
3547 */
SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3548 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3549 {
3550 /* Transmit data in packing Bit mode */
3551 if (hspi->TxXferCount >= 2U)
3552 {
3553 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3554 hspi->pTxBuffPtr += sizeof(uint16_t);
3555 hspi->TxXferCount -= 2U;
3556 }
3557 /* Transmit data in 8 Bit mode */
3558 else
3559 {
3560 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3561 hspi->pTxBuffPtr++;
3562 hspi->TxXferCount--;
3563 }
3564
3565 /* Check the end of the transmission */
3566 if (hspi->TxXferCount == 0U)
3567 {
3568 #if (USE_SPI_CRC != 0U)
3569 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3570 {
3571 /* Set CRC Next Bit to send CRC */
3572 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3573 /* Disable TXE interrupt */
3574 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3575 return;
3576 }
3577 #endif /* USE_SPI_CRC */
3578
3579 /* Disable TXE interrupt */
3580 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3581
3582 if (hspi->RxXferCount == 0U)
3583 {
3584 SPI_CloseRxTx_ISR(hspi);
3585 }
3586 }
3587 }
3588
3589 /**
3590 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
3591 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3592 * the configuration information for SPI module.
3593 * @retval None
3594 */
SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3595 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3596 {
3597 /* Receive data in 16 Bit mode */
3598 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3599 hspi->pRxBuffPtr += sizeof(uint16_t);
3600 hspi->RxXferCount--;
3601
3602 if (hspi->RxXferCount == 0U)
3603 {
3604 #if (USE_SPI_CRC != 0U)
3605 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3606 {
3607 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
3608 return;
3609 }
3610 #endif /* USE_SPI_CRC */
3611
3612 /* Disable RXNE interrupt */
3613 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3614
3615 if (hspi->TxXferCount == 0U)
3616 {
3617 SPI_CloseRxTx_ISR(hspi);
3618 }
3619 }
3620 }
3621
3622 #if (USE_SPI_CRC != 0U)
3623 /**
3624 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
3625 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3626 * the configuration information for SPI module.
3627 * @retval None
3628 */
SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3629 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3630 {
3631 /* Read 16bit CRC to flush Data Register */
3632 READ_REG(hspi->Instance->DR);
3633
3634 /* Disable RXNE interrupt */
3635 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3636
3637 SPI_CloseRxTx_ISR(hspi);
3638 }
3639 #endif /* USE_SPI_CRC */
3640
3641 /**
3642 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
3643 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3644 * the configuration information for SPI module.
3645 * @retval None
3646 */
SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3647 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3648 {
3649 /* Transmit data in 16 Bit mode */
3650 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3651 hspi->pTxBuffPtr += sizeof(uint16_t);
3652 hspi->TxXferCount--;
3653
3654 /* Enable CRC Transmission */
3655 if (hspi->TxXferCount == 0U)
3656 {
3657 #if (USE_SPI_CRC != 0U)
3658 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3659 {
3660 /* Set CRC Next Bit to send CRC */
3661 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3662 /* Disable TXE interrupt */
3663 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3664 return;
3665 }
3666 #endif /* USE_SPI_CRC */
3667
3668 /* Disable TXE interrupt */
3669 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3670
3671 if (hspi->RxXferCount == 0U)
3672 {
3673 SPI_CloseRxTx_ISR(hspi);
3674 }
3675 }
3676 }
3677
3678 #if (USE_SPI_CRC != 0U)
3679 /**
3680 * @brief Manage the CRC 8-bit receive in Interrupt context.
3681 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3682 * the configuration information for SPI module.
3683 * @retval None
3684 */
SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3685 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3686 {
3687 /* Read 8bit CRC to flush Data Register */
3688 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3689
3690 hspi->CRCSize--;
3691
3692 if (hspi->CRCSize == 0U)
3693 {
3694 SPI_CloseRx_ISR(hspi);
3695 }
3696 }
3697 #endif /* USE_SPI_CRC */
3698
3699 /**
3700 * @brief Manage the receive 8-bit in Interrupt context.
3701 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3702 * the configuration information for SPI module.
3703 * @retval None
3704 */
SPI_RxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3705 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3706 {
3707 *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
3708 hspi->pRxBuffPtr++;
3709 hspi->RxXferCount--;
3710
3711 #if (USE_SPI_CRC != 0U)
3712 /* Enable CRC Transmission */
3713 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3714 {
3715 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3716 }
3717 #endif /* USE_SPI_CRC */
3718
3719 if (hspi->RxXferCount == 0U)
3720 {
3721 #if (USE_SPI_CRC != 0U)
3722 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3723 {
3724 hspi->RxISR = SPI_RxISR_8BITCRC;
3725 return;
3726 }
3727 #endif /* USE_SPI_CRC */
3728 SPI_CloseRx_ISR(hspi);
3729 }
3730 }
3731
3732 #if (USE_SPI_CRC != 0U)
3733 /**
3734 * @brief Manage the CRC 16-bit receive in Interrupt context.
3735 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3736 * the configuration information for SPI module.
3737 * @retval None
3738 */
SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3739 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3740 {
3741 /* Read 16bit CRC to flush Data Register */
3742 READ_REG(hspi->Instance->DR);
3743
3744 /* Disable RXNE and ERR interrupt */
3745 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3746
3747 SPI_CloseRx_ISR(hspi);
3748 }
3749 #endif /* USE_SPI_CRC */
3750
3751 /**
3752 * @brief Manage the 16-bit receive in Interrupt context.
3753 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3754 * the configuration information for SPI module.
3755 * @retval None
3756 */
SPI_RxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3757 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3758 {
3759 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3760 hspi->pRxBuffPtr += sizeof(uint16_t);
3761 hspi->RxXferCount--;
3762
3763 #if (USE_SPI_CRC != 0U)
3764 /* Enable CRC Transmission */
3765 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3766 {
3767 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3768 }
3769 #endif /* USE_SPI_CRC */
3770
3771 if (hspi->RxXferCount == 0U)
3772 {
3773 #if (USE_SPI_CRC != 0U)
3774 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3775 {
3776 hspi->RxISR = SPI_RxISR_16BITCRC;
3777 return;
3778 }
3779 #endif /* USE_SPI_CRC */
3780 SPI_CloseRx_ISR(hspi);
3781 }
3782 }
3783
3784 /**
3785 * @brief Handle the data 8-bit transmit in Interrupt mode.
3786 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3787 * the configuration information for SPI module.
3788 * @retval None
3789 */
SPI_TxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3790 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3791 {
3792 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3793 hspi->pTxBuffPtr++;
3794 hspi->TxXferCount--;
3795
3796 if (hspi->TxXferCount == 0U)
3797 {
3798 #if (USE_SPI_CRC != 0U)
3799 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3800 {
3801 /* Enable CRC Transmission */
3802 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3803 }
3804 #endif /* USE_SPI_CRC */
3805 SPI_CloseTx_ISR(hspi);
3806 }
3807 }
3808
3809 /**
3810 * @brief Handle the data 16-bit transmit in Interrupt mode.
3811 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3812 * the configuration information for SPI module.
3813 * @retval None
3814 */
SPI_TxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3815 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3816 {
3817 /* Transmit data in 16 Bit mode */
3818 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3819 hspi->pTxBuffPtr += sizeof(uint16_t);
3820 hspi->TxXferCount--;
3821
3822 if (hspi->TxXferCount == 0U)
3823 {
3824 #if (USE_SPI_CRC != 0U)
3825 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3826 {
3827 /* Enable CRC Transmission */
3828 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3829 }
3830 #endif /* USE_SPI_CRC */
3831 SPI_CloseTx_ISR(hspi);
3832 }
3833 }
3834
3835 /**
3836 * @brief Handle SPI Communication Timeout.
3837 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3838 * the configuration information for SPI module.
3839 * @param Flag SPI flag to check
3840 * @param State flag state to check
3841 * @param Timeout Timeout duration
3842 * @param Tickstart tick start value
3843 * @retval HAL status
3844 */
SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Flag,FlagStatus State,uint32_t Timeout,uint32_t Tickstart)3845 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
3846 uint32_t Timeout, uint32_t Tickstart)
3847 {
3848 __IO uint32_t count;
3849 uint32_t tmp_timeout;
3850 uint32_t tmp_tickstart;
3851
3852 /* Adjust Timeout value in case of end of transfer */
3853 tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
3854 tmp_tickstart = HAL_GetTick();
3855
3856 /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
3857 count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
3858
3859 while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
3860 {
3861 if (Timeout != HAL_MAX_DELAY)
3862 {
3863 if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
3864 {
3865 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3866 on both master and slave sides in order to resynchronize the master
3867 and slave for their respective CRC calculation */
3868
3869 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3870 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3871
3872 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3873 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3874 {
3875 /* Disable SPI peripheral */
3876 __HAL_SPI_DISABLE(hspi);
3877 }
3878
3879 /* Reset CRC Calculation */
3880 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3881 {
3882 SPI_RESET_CRC(hspi);
3883 }
3884
3885 hspi->State = HAL_SPI_STATE_READY;
3886
3887 /* Process Unlocked */
3888 __HAL_UNLOCK(hspi);
3889
3890 return HAL_TIMEOUT;
3891 }
3892 /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
3893 if(count == 0U)
3894 {
3895 tmp_timeout = 0U;
3896 }
3897 count--;
3898 }
3899 }
3900
3901 return HAL_OK;
3902 }
3903
3904 /**
3905 * @brief Handle SPI FIFO Communication Timeout.
3906 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3907 * the configuration information for SPI module.
3908 * @param Fifo Fifo to check
3909 * @param State Fifo state to check
3910 * @param Timeout Timeout duration
3911 * @param Tickstart tick start value
3912 * @retval HAL status
3913 */
SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Fifo,uint32_t State,uint32_t Timeout,uint32_t Tickstart)3914 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
3915 uint32_t Timeout, uint32_t Tickstart)
3916 {
3917 __IO uint32_t count;
3918 uint32_t tmp_timeout;
3919 uint32_t tmp_tickstart;
3920
3921 /* Adjust Timeout value in case of end of transfer */
3922 tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
3923 tmp_tickstart = HAL_GetTick();
3924
3925 /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
3926 count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
3927
3928 while ((hspi->Instance->SR & Fifo) != State)
3929 {
3930 if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
3931 {
3932 /* Read 8bit CRC to flush Data Register */
3933 READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));
3934 }
3935
3936 if (Timeout != HAL_MAX_DELAY)
3937 {
3938 if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
3939 {
3940 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3941 on both master and slave sides in order to resynchronize the master
3942 and slave for their respective CRC calculation */
3943
3944 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3945 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3946
3947 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3948 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3949 {
3950 /* Disable SPI peripheral */
3951 __HAL_SPI_DISABLE(hspi);
3952 }
3953
3954 /* Reset CRC Calculation */
3955 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3956 {
3957 SPI_RESET_CRC(hspi);
3958 }
3959
3960 hspi->State = HAL_SPI_STATE_READY;
3961
3962 /* Process Unlocked */
3963 __HAL_UNLOCK(hspi);
3964
3965 return HAL_TIMEOUT;
3966 }
3967 /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
3968 if(count == 0U)
3969 {
3970 tmp_timeout = 0U;
3971 }
3972 count--;
3973 }
3974 }
3975
3976 return HAL_OK;
3977 }
3978
3979 /**
3980 * @brief Handle the check of the RX transaction complete.
3981 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3982 * the configuration information for SPI module.
3983 * @param Timeout Timeout duration
3984 * @param Tickstart tick start value
3985 * @retval HAL status
3986 */
SPI_EndRxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)3987 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
3988 {
3989 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3990 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3991 {
3992 /* Disable SPI peripheral */
3993 __HAL_SPI_DISABLE(hspi);
3994 }
3995
3996 /* Control the BSY flag */
3997 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
3998 {
3999 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4000 return HAL_TIMEOUT;
4001 }
4002
4003 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
4004 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
4005 {
4006 /* Empty the FRLVL fifo */
4007 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4008 {
4009 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4010 return HAL_TIMEOUT;
4011 }
4012 }
4013 return HAL_OK;
4014 }
4015
4016 /**
4017 * @brief Handle the check of the RXTX or TX transaction complete.
4018 * @param hspi SPI handle
4019 * @param Timeout Timeout duration
4020 * @param Tickstart tick start value
4021 * @retval HAL status
4022 */
SPI_EndRxTxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)4023 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
4024 {
4025 /* Control if the TX fifo is empty */
4026 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4027 {
4028 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4029 return HAL_TIMEOUT;
4030 }
4031
4032 /* Control the BSY flag */
4033 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
4034 {
4035 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4036 return HAL_TIMEOUT;
4037 }
4038
4039 /* Control if the RX fifo is empty */
4040 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4041 {
4042 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4043 return HAL_TIMEOUT;
4044 }
4045
4046 return HAL_OK;
4047 }
4048
4049 /**
4050 * @brief Handle the end of the RXTX transaction.
4051 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4052 * the configuration information for SPI module.
4053 * @retval None
4054 */
SPI_CloseRxTx_ISR(SPI_HandleTypeDef * hspi)4055 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
4056 {
4057 uint32_t tickstart;
4058
4059 /* Init tickstart for timeout management */
4060 tickstart = HAL_GetTick();
4061
4062 /* Disable ERR interrupt */
4063 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
4064
4065 /* Check the end of the transaction */
4066 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4067 {
4068 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4069 }
4070
4071 #if (USE_SPI_CRC != 0U)
4072 /* Check if CRC error occurred */
4073 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4074 {
4075 hspi->State = HAL_SPI_STATE_READY;
4076 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4077 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4078 /* Call user error callback */
4079 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4080 hspi->ErrorCallback(hspi);
4081 #else
4082 HAL_SPI_ErrorCallback(hspi);
4083 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4084 }
4085 else
4086 {
4087 #endif /* USE_SPI_CRC */
4088 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4089 {
4090 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
4091 {
4092 hspi->State = HAL_SPI_STATE_READY;
4093 /* Call user Rx complete callback */
4094 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4095 hspi->RxCpltCallback(hspi);
4096 #else
4097 HAL_SPI_RxCpltCallback(hspi);
4098 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4099 }
4100 else
4101 {
4102 hspi->State = HAL_SPI_STATE_READY;
4103 /* Call user TxRx complete callback */
4104 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4105 hspi->TxRxCpltCallback(hspi);
4106 #else
4107 HAL_SPI_TxRxCpltCallback(hspi);
4108 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4109 }
4110 }
4111 else
4112 {
4113 hspi->State = HAL_SPI_STATE_READY;
4114 /* Call user error callback */
4115 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4116 hspi->ErrorCallback(hspi);
4117 #else
4118 HAL_SPI_ErrorCallback(hspi);
4119 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4120 }
4121 #if (USE_SPI_CRC != 0U)
4122 }
4123 #endif /* USE_SPI_CRC */
4124 }
4125
4126 /**
4127 * @brief Handle the end of the RX transaction.
4128 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4129 * the configuration information for SPI module.
4130 * @retval None
4131 */
SPI_CloseRx_ISR(SPI_HandleTypeDef * hspi)4132 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
4133 {
4134 /* Disable RXNE and ERR interrupt */
4135 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
4136
4137 /* Check the end of the transaction */
4138 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4139 {
4140 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4141 }
4142 hspi->State = HAL_SPI_STATE_READY;
4143
4144 #if (USE_SPI_CRC != 0U)
4145 /* Check if CRC error occurred */
4146 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4147 {
4148 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4149 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4150 /* Call user error callback */
4151 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4152 hspi->ErrorCallback(hspi);
4153 #else
4154 HAL_SPI_ErrorCallback(hspi);
4155 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4156 }
4157 else
4158 {
4159 #endif /* USE_SPI_CRC */
4160 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4161 {
4162 /* Call user Rx complete callback */
4163 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4164 hspi->RxCpltCallback(hspi);
4165 #else
4166 HAL_SPI_RxCpltCallback(hspi);
4167 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4168 }
4169 else
4170 {
4171 /* Call user error callback */
4172 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4173 hspi->ErrorCallback(hspi);
4174 #else
4175 HAL_SPI_ErrorCallback(hspi);
4176 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4177 }
4178 #if (USE_SPI_CRC != 0U)
4179 }
4180 #endif /* USE_SPI_CRC */
4181 }
4182
4183 /**
4184 * @brief Handle the end of the TX transaction.
4185 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4186 * the configuration information for SPI module.
4187 * @retval None
4188 */
SPI_CloseTx_ISR(SPI_HandleTypeDef * hspi)4189 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
4190 {
4191 uint32_t tickstart;
4192
4193 /* Init tickstart for timeout management*/
4194 tickstart = HAL_GetTick();
4195
4196 /* Disable TXE and ERR interrupt */
4197 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
4198
4199 /* Check the end of the transaction */
4200 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4201 {
4202 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4203 }
4204
4205 /* Clear overrun flag in 2 Lines communication mode because received is not read */
4206 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
4207 {
4208 __HAL_SPI_CLEAR_OVRFLAG(hspi);
4209 }
4210
4211 hspi->State = HAL_SPI_STATE_READY;
4212 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
4213 {
4214 /* Call user error callback */
4215 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4216 hspi->ErrorCallback(hspi);
4217 #else
4218 HAL_SPI_ErrorCallback(hspi);
4219 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4220 }
4221 else
4222 {
4223 /* Call user Rx complete callback */
4224 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4225 hspi->TxCpltCallback(hspi);
4226 #else
4227 HAL_SPI_TxCpltCallback(hspi);
4228 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4229 }
4230 }
4231
4232 /**
4233 * @brief Handle abort a Rx transaction.
4234 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4235 * the configuration information for SPI module.
4236 * @retval None
4237 */
SPI_AbortRx_ISR(SPI_HandleTypeDef * hspi)4238 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
4239 {
4240 __IO uint32_t count;
4241
4242 /* Disable SPI Peripheral */
4243 __HAL_SPI_DISABLE(hspi);
4244
4245 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4246
4247 /* Disable RXNEIE interrupt */
4248 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4249
4250 /* Check RXNEIE is disabled */
4251 do
4252 {
4253 if (count == 0U)
4254 {
4255 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4256 break;
4257 }
4258 count--;
4259 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4260
4261 /* Control the BSY flag */
4262 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4263 {
4264 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4265 }
4266
4267 /* Empty the FRLVL fifo */
4268 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4269 {
4270 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4271 }
4272
4273 hspi->State = HAL_SPI_STATE_ABORT;
4274 }
4275
4276 /**
4277 * @brief Handle abort a Tx or Rx/Tx transaction.
4278 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4279 * the configuration information for SPI module.
4280 * @retval None
4281 */
SPI_AbortTx_ISR(SPI_HandleTypeDef * hspi)4282 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
4283 {
4284 __IO uint32_t count;
4285
4286 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4287
4288 /* Disable TXEIE interrupt */
4289 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
4290
4291 /* Check TXEIE is disabled */
4292 do
4293 {
4294 if (count == 0U)
4295 {
4296 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4297 break;
4298 }
4299 count--;
4300 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
4301
4302 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4303 {
4304 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4305 }
4306
4307 /* Disable SPI Peripheral */
4308 __HAL_SPI_DISABLE(hspi);
4309
4310 /* Empty the FRLVL fifo */
4311 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4312 {
4313 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4314 }
4315
4316 /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
4317 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
4318 {
4319 /* Disable RXNEIE interrupt */
4320 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4321
4322 /* Check RXNEIE is disabled */
4323 do
4324 {
4325 if (count == 0U)
4326 {
4327 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4328 break;
4329 }
4330 count--;
4331 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4332
4333 /* Control the BSY flag */
4334 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4335 {
4336 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4337 }
4338
4339 /* Empty the FRLVL fifo */
4340 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4341 {
4342 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4343 }
4344 }
4345 hspi->State = HAL_SPI_STATE_ABORT;
4346 }
4347
4348 /**
4349 * @}
4350 */
4351
4352 #endif /* HAL_SPI_MODULE_ENABLED */
4353
4354 /**
4355 * @}
4356 */
4357
4358 /**
4359 * @}
4360 */
4361
4362 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
4363