1 /**************************************************************************//**
2 * @file core_armv8mml.h
3 * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
4 * @version V5.1.0
5 * @date 12. September 2018
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef __CORE_ARMV8MML_H_GENERIC
32 #define __CORE_ARMV8MML_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58 /**
59 \ingroup Cortex_ARMv8MML
60 @{
61 */
62
63 #include "cmsis_version.h"
64
65 /* CMSIS Armv8MML definitions */
66 #define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67 #define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68 #define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
69 __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70
71 #define __CORTEX_M (81U) /*!< Cortex-M Core */
72
73 /** __FPU_USED indicates whether an FPU is used or not.
74 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
75 */
76 #if defined ( __CC_ARM )
77 #if defined __TARGET_FPU_VFP
78 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
79 #define __FPU_USED 1U
80 #else
81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
82 #define __FPU_USED 0U
83 #endif
84 #else
85 #define __FPU_USED 0U
86 #endif
87
88 #if defined(__ARM_FEATURE_DSP)
89 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
90 #define __DSP_USED 1U
91 #else
92 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
93 #define __DSP_USED 0U
94 #endif
95 #else
96 #define __DSP_USED 0U
97 #endif
98
99 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
100 #if defined __ARM_FP
101 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
102 #define __FPU_USED 1U
103 #else
104 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
105 #define __FPU_USED 0U
106 #endif
107 #else
108 #define __FPU_USED 0U
109 #endif
110
111 #if defined(__ARM_FEATURE_DSP)
112 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
113 #define __DSP_USED 1U
114 #else
115 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
116 #define __DSP_USED 0U
117 #endif
118 #else
119 #define __DSP_USED 0U
120 #endif
121
122 #elif defined ( __GNUC__ )
123 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
124 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
125 #define __FPU_USED 1U
126 #else
127 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
128 #define __FPU_USED 0U
129 #endif
130 #else
131 #define __FPU_USED 0U
132 #endif
133
134 #if defined(__ARM_FEATURE_DSP)
135 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
136 #define __DSP_USED 1U
137 #else
138 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
139 #define __DSP_USED 0U
140 #endif
141 #else
142 #define __DSP_USED 0U
143 #endif
144
145 #elif defined ( __ICCARM__ )
146 #if defined __ARMVFP__
147 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
148 #define __FPU_USED 1U
149 #else
150 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
151 #define __FPU_USED 0U
152 #endif
153 #else
154 #define __FPU_USED 0U
155 #endif
156
157 #if defined(__ARM_FEATURE_DSP)
158 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
159 #define __DSP_USED 1U
160 #else
161 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
162 #define __DSP_USED 0U
163 #endif
164 #else
165 #define __DSP_USED 0U
166 #endif
167
168 #elif defined ( __TI_ARM__ )
169 #if defined __TI_VFP_SUPPORT__
170 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
171 #define __FPU_USED 1U
172 #else
173 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
174 #define __FPU_USED 0U
175 #endif
176 #else
177 #define __FPU_USED 0U
178 #endif
179
180 #elif defined ( __TASKING__ )
181 #if defined __FPU_VFP__
182 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
183 #define __FPU_USED 1U
184 #else
185 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
186 #define __FPU_USED 0U
187 #endif
188 #else
189 #define __FPU_USED 0U
190 #endif
191
192 #elif defined ( __CSMC__ )
193 #if ( __CSMC__ & 0x400U)
194 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
195 #define __FPU_USED 1U
196 #else
197 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
198 #define __FPU_USED 0U
199 #endif
200 #else
201 #define __FPU_USED 0U
202 #endif
203
204 #endif
205
206 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
207
208
209 #ifdef __cplusplus
210 }
211 #endif
212
213 #endif /* __CORE_ARMV8MML_H_GENERIC */
214
215 #ifndef __CMSIS_GENERIC
216
217 #ifndef __CORE_ARMV8MML_H_DEPENDANT
218 #define __CORE_ARMV8MML_H_DEPENDANT
219
220 #ifdef __cplusplus
221 extern "C" {
222 #endif
223
224 /* check device defines and use defaults */
225 #if defined __CHECK_DEVICE_DEFINES
226 #ifndef __ARMv8MML_REV
227 #define __ARMv8MML_REV 0x0000U
228 #warning "__ARMv8MML_REV not defined in device header file; using default!"
229 #endif
230
231 #ifndef __FPU_PRESENT
232 #define __FPU_PRESENT 0U
233 #warning "__FPU_PRESENT not defined in device header file; using default!"
234 #endif
235
236 #ifndef __MPU_PRESENT
237 #define __MPU_PRESENT 0U
238 #warning "__MPU_PRESENT not defined in device header file; using default!"
239 #endif
240
241 #ifndef __SAUREGION_PRESENT
242 #define __SAUREGION_PRESENT 0U
243 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
244 #endif
245
246 #ifndef __DSP_PRESENT
247 #define __DSP_PRESENT 0U
248 #warning "__DSP_PRESENT not defined in device header file; using default!"
249 #endif
250
251 #ifndef __NVIC_PRIO_BITS
252 #define __NVIC_PRIO_BITS 3U
253 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
254 #endif
255
256 #ifndef __Vendor_SysTickConfig
257 #define __Vendor_SysTickConfig 0U
258 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
259 #endif
260 #endif
261
262 /* IO definitions (access restrictions to peripheral registers) */
263 /**
264 \defgroup CMSIS_glob_defs CMSIS Global Defines
265
266 <strong>IO Type Qualifiers</strong> are used
267 \li to specify the access to peripheral variables.
268 \li for automatic generation of peripheral register debug information.
269 */
270 #ifdef __cplusplus
271 #define __I volatile /*!< Defines 'read only' permissions */
272 #else
273 #define __I volatile const /*!< Defines 'read only' permissions */
274 #endif
275 #define __O volatile /*!< Defines 'write only' permissions */
276 #define __IO volatile /*!< Defines 'read / write' permissions */
277
278 /* following defines should be used for structure members */
279 #define __IM volatile const /*! Defines 'read only' structure member permissions */
280 #define __OM volatile /*! Defines 'write only' structure member permissions */
281 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
282
283 /*@} end of group ARMv8MML */
284
285
286
287 /*******************************************************************************
288 * Register Abstraction
289 Core Register contain:
290 - Core Register
291 - Core NVIC Register
292 - Core SCB Register
293 - Core SysTick Register
294 - Core Debug Register
295 - Core MPU Register
296 - Core SAU Register
297 - Core FPU Register
298 ******************************************************************************/
299 /**
300 \defgroup CMSIS_core_register Defines and Type Definitions
301 \brief Type definitions and defines for Cortex-M processor based devices.
302 */
303
304 /**
305 \ingroup CMSIS_core_register
306 \defgroup CMSIS_CORE Status and Control Registers
307 \brief Core Register type definitions.
308 @{
309 */
310
311 /**
312 \brief Union type to access the Application Program Status Register (APSR).
313 */
314 typedef union
315 {
316 struct
317 {
318 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
319 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
320 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
321 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
322 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
323 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
324 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
325 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
326 } b; /*!< Structure used for bit access */
327 uint32_t w; /*!< Type used for word access */
328 } APSR_Type;
329
330 /* APSR Register Definitions */
331 #define APSR_N_Pos 31U /*!< APSR: N Position */
332 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
333
334 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
335 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
336
337 #define APSR_C_Pos 29U /*!< APSR: C Position */
338 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
339
340 #define APSR_V_Pos 28U /*!< APSR: V Position */
341 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
342
343 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
344 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
345
346 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
347 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
348
349
350 /**
351 \brief Union type to access the Interrupt Program Status Register (IPSR).
352 */
353 typedef union
354 {
355 struct
356 {
357 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
358 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
359 } b; /*!< Structure used for bit access */
360 uint32_t w; /*!< Type used for word access */
361 } IPSR_Type;
362
363 /* IPSR Register Definitions */
364 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
365 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
366
367
368 /**
369 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
370 */
371 typedef union
372 {
373 struct
374 {
375 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
376 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
377 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
378 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
379 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
380 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
381 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
382 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
383 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
384 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
385 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
386 } b; /*!< Structure used for bit access */
387 uint32_t w; /*!< Type used for word access */
388 } xPSR_Type;
389
390 /* xPSR Register Definitions */
391 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
392 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
393
394 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
395 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
396
397 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
398 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
399
400 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
401 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
402
403 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
404 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
405
406 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
407 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
408
409 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
410 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
411
412 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
413 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
414
415 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
416 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
417
418
419 /**
420 \brief Union type to access the Control Registers (CONTROL).
421 */
422 typedef union
423 {
424 struct
425 {
426 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
427 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
428 uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
429 uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
430 uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
431 } b; /*!< Structure used for bit access */
432 uint32_t w; /*!< Type used for word access */
433 } CONTROL_Type;
434
435 /* CONTROL Register Definitions */
436 #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
437 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
438
439 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
440 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
441
442 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
443 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
444
445 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
446 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
447
448 /*@} end of group CMSIS_CORE */
449
450
451 /**
452 \ingroup CMSIS_core_register
453 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
454 \brief Type definitions for the NVIC Registers
455 @{
456 */
457
458 /**
459 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
460 */
461 typedef struct
462 {
463 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
464 uint32_t RESERVED0[16U];
465 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
466 uint32_t RSERVED1[16U];
467 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
468 uint32_t RESERVED2[16U];
469 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
470 uint32_t RESERVED3[16U];
471 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
472 uint32_t RESERVED4[16U];
473 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
474 uint32_t RESERVED5[16U];
475 __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
476 uint32_t RESERVED6[580U];
477 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
478 } NVIC_Type;
479
480 /* Software Triggered Interrupt Register Definitions */
481 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
482 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
483
484 /*@} end of group CMSIS_NVIC */
485
486
487 /**
488 \ingroup CMSIS_core_register
489 \defgroup CMSIS_SCB System Control Block (SCB)
490 \brief Type definitions for the System Control Block Registers
491 @{
492 */
493
494 /**
495 \brief Structure type to access the System Control Block (SCB).
496 */
497 typedef struct
498 {
499 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
500 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
501 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
502 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
503 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
504 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
505 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
506 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
507 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
508 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
509 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
510 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
511 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
512 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
513 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
514 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
515 __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
516 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
517 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
518 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
519 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
520 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
521 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
522 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
523 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
524 uint32_t RESERVED3[92U];
525 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
526 uint32_t RESERVED4[15U];
527 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
528 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
529 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
530 uint32_t RESERVED5[1U];
531 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
532 uint32_t RESERVED6[1U];
533 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
534 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
535 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
536 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
537 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
538 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
539 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
540 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
541 } SCB_Type;
542
543 /* SCB CPUID Register Definitions */
544 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
545 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
546
547 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
548 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
549
550 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
551 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
552
553 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
554 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
555
556 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
557 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
558
559 /* SCB Interrupt Control State Register Definitions */
560 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
561 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
562
563 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
564 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
565
566 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
567 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
568
569 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
570 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
571
572 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
573 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
574
575 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
576 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
577
578 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
579 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
580
581 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
582 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
583
584 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
585 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
586
587 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
588 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
589
590 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
591 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
592
593 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
594 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
595
596 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
597 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
598
599 /* SCB Vector Table Offset Register Definitions */
600 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
601 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
602
603 /* SCB Application Interrupt and Reset Control Register Definitions */
604 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
605 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
606
607 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
608 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
609
610 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
611 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
612
613 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
614 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
615
616 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
617 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
618
619 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
620 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
621
622 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
623 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
624
625 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
626 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
627
628 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
629 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
630
631 /* SCB System Control Register Definitions */
632 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
633 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
634
635 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
636 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
637
638 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
639 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
640
641 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
642 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
643
644 /* SCB Configuration Control Register Definitions */
645 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
646 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
647
648 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
649 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
650
651 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
652 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
653
654 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
655 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
656
657 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
658 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
659
660 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
661 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
662
663 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
664 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
665
666 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
667 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
668
669 /* SCB System Handler Control and State Register Definitions */
670 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
671 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
672
673 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
674 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
675
676 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
677 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
678
679 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
680 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
681
682 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
683 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
684
685 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
686 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
687
688 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
689 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
690
691 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
692 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
693
694 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
695 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
696
697 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
698 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
699
700 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
701 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
702
703 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
704 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
705
706 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
707 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
708
709 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
710 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
711
712 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
713 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
714
715 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
716 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
717
718 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
719 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
720
721 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
722 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
723
724 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
725 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
726
727 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
728 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
729
730 /* SCB Configurable Fault Status Register Definitions */
731 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
732 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
733
734 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
735 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
736
737 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
738 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
739
740 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
741 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
742 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
743
744 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
745 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
746
747 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
748 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
749
750 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
751 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
752
753 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
754 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
755
756 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
757 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
758
759 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
760 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
761 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
762
763 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
764 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
765
766 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
767 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
768
769 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
770 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
771
772 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
773 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
774
775 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
776 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
777
778 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
779 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
780
781 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
782 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
783 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
784
785 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
786 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
787
788 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
789 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
790
791 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
792 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
793
794 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
795 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
796
797 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
798 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
799
800 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
801 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
802
803 /* SCB Hard Fault Status Register Definitions */
804 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
805 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
806
807 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
808 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
809
810 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
811 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
812
813 /* SCB Debug Fault Status Register Definitions */
814 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
815 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
816
817 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
818 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
819
820 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
821 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
822
823 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
824 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
825
826 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
827 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
828
829 /* SCB Non-Secure Access Control Register Definitions */
830 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
831 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
832
833 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
834 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
835
836 #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
837 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
838
839 /* SCB Cache Level ID Register Definitions */
840 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
841 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
842
843 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
844 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
845
846 /* SCB Cache Type Register Definitions */
847 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
848 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
849
850 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
851 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
852
853 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
854 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
855
856 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
857 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
858
859 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
860 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
861
862 /* SCB Cache Size ID Register Definitions */
863 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
864 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
865
866 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
867 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
868
869 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
870 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
871
872 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
873 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
874
875 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
876 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
877
878 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
879 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
880
881 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
882 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
883
884 /* SCB Cache Size Selection Register Definitions */
885 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
886 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
887
888 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
889 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
890
891 /* SCB Software Triggered Interrupt Register Definitions */
892 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
893 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
894
895 /* SCB D-Cache Invalidate by Set-way Register Definitions */
896 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
897 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
898
899 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
900 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
901
902 /* SCB D-Cache Clean by Set-way Register Definitions */
903 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
904 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
905
906 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
907 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
908
909 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
910 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
911 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
912
913 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
914 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
915
916 /*@} end of group CMSIS_SCB */
917
918
919 /**
920 \ingroup CMSIS_core_register
921 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
922 \brief Type definitions for the System Control and ID Register not in the SCB
923 @{
924 */
925
926 /**
927 \brief Structure type to access the System Control and ID Register not in the SCB.
928 */
929 typedef struct
930 {
931 uint32_t RESERVED0[1U];
932 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
933 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
934 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
935 } SCnSCB_Type;
936
937 /* Interrupt Controller Type Register Definitions */
938 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
939 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
940
941 /*@} end of group CMSIS_SCnotSCB */
942
943
944 /**
945 \ingroup CMSIS_core_register
946 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
947 \brief Type definitions for the System Timer Registers.
948 @{
949 */
950
951 /**
952 \brief Structure type to access the System Timer (SysTick).
953 */
954 typedef struct
955 {
956 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
957 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
958 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
959 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
960 } SysTick_Type;
961
962 /* SysTick Control / Status Register Definitions */
963 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
964 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
965
966 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
967 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
968
969 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
970 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
971
972 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
973 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
974
975 /* SysTick Reload Register Definitions */
976 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
977 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
978
979 /* SysTick Current Register Definitions */
980 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
981 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
982
983 /* SysTick Calibration Register Definitions */
984 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
985 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
986
987 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
988 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
989
990 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
991 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
992
993 /*@} end of group CMSIS_SysTick */
994
995
996 /**
997 \ingroup CMSIS_core_register
998 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
999 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
1000 @{
1001 */
1002
1003 /**
1004 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
1005 */
1006 typedef struct
1007 {
1008 __OM union
1009 {
1010 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1011 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1012 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
1013 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
1014 uint32_t RESERVED0[864U];
1015 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
1016 uint32_t RESERVED1[15U];
1017 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
1018 uint32_t RESERVED2[15U];
1019 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
1020 uint32_t RESERVED3[32U];
1021 uint32_t RESERVED4[43U];
1022 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
1023 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
1024 uint32_t RESERVED5[1U];
1025 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
1026 uint32_t RESERVED6[4U];
1027 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
1028 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
1029 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
1030 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
1031 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
1032 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
1033 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
1034 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
1035 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
1036 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
1037 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
1038 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
1039 } ITM_Type;
1040
1041 /* ITM Stimulus Port Register Definitions */
1042 #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
1043 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
1044
1045 #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
1046 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
1047
1048 /* ITM Trace Privilege Register Definitions */
1049 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
1050 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
1051
1052 /* ITM Trace Control Register Definitions */
1053 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
1054 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
1055
1056 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
1057 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
1058
1059 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
1060 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
1061
1062 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
1063 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
1064
1065 #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
1066 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
1067
1068 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
1069 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
1070
1071 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
1072 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
1073
1074 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
1075 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
1076
1077 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
1078 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
1079
1080 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
1081 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
1082
1083 /* ITM Lock Status Register Definitions */
1084 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
1085 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
1086
1087 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
1088 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
1089
1090 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
1091 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
1092
1093 /*@}*/ /* end of group CMSIS_ITM */
1094
1095
1096 /**
1097 \ingroup CMSIS_core_register
1098 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
1099 \brief Type definitions for the Data Watchpoint and Trace (DWT)
1100 @{
1101 */
1102
1103 /**
1104 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
1105 */
1106 typedef struct
1107 {
1108 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1109 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
1110 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1111 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
1112 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
1113 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1114 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
1115 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
1116 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
1117 uint32_t RESERVED1[1U];
1118 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1119 uint32_t RESERVED2[1U];
1120 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
1121 uint32_t RESERVED3[1U];
1122 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1123 uint32_t RESERVED4[1U];
1124 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
1125 uint32_t RESERVED5[1U];
1126 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
1127 uint32_t RESERVED6[1U];
1128 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
1129 uint32_t RESERVED7[1U];
1130 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
1131 uint32_t RESERVED8[1U];
1132 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
1133 uint32_t RESERVED9[1U];
1134 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
1135 uint32_t RESERVED10[1U];
1136 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
1137 uint32_t RESERVED11[1U];
1138 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
1139 uint32_t RESERVED12[1U];
1140 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
1141 uint32_t RESERVED13[1U];
1142 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
1143 uint32_t RESERVED14[1U];
1144 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
1145 uint32_t RESERVED15[1U];
1146 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
1147 uint32_t RESERVED16[1U];
1148 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
1149 uint32_t RESERVED17[1U];
1150 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
1151 uint32_t RESERVED18[1U];
1152 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
1153 uint32_t RESERVED19[1U];
1154 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
1155 uint32_t RESERVED20[1U];
1156 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
1157 uint32_t RESERVED21[1U];
1158 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
1159 uint32_t RESERVED22[1U];
1160 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
1161 uint32_t RESERVED23[1U];
1162 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
1163 uint32_t RESERVED24[1U];
1164 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
1165 uint32_t RESERVED25[1U];
1166 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
1167 uint32_t RESERVED26[1U];
1168 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
1169 uint32_t RESERVED27[1U];
1170 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
1171 uint32_t RESERVED28[1U];
1172 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
1173 uint32_t RESERVED29[1U];
1174 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
1175 uint32_t RESERVED30[1U];
1176 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
1177 uint32_t RESERVED31[1U];
1178 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
1179 uint32_t RESERVED32[934U];
1180 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1181 uint32_t RESERVED33[1U];
1182 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
1183 } DWT_Type;
1184
1185 /* DWT Control Register Definitions */
1186 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
1187 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
1188
1189 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
1190 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
1191
1192 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
1193 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
1194
1195 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
1196 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
1197
1198 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
1199 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
1200
1201 #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
1202 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
1203
1204 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
1205 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
1206
1207 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
1208 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
1209
1210 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
1211 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
1212
1213 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
1214 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
1215
1216 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
1217 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
1218
1219 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
1220 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
1221
1222 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
1223 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
1224
1225 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
1226 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
1227
1228 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
1229 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
1230
1231 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
1232 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
1233
1234 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
1235 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
1236
1237 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
1238 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
1239
1240 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
1241 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
1242
1243 /* DWT CPI Count Register Definitions */
1244 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
1245 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
1246
1247 /* DWT Exception Overhead Count Register Definitions */
1248 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
1249 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
1250
1251 /* DWT Sleep Count Register Definitions */
1252 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
1253 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1254
1255 /* DWT LSU Count Register Definitions */
1256 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
1257 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
1258
1259 /* DWT Folded-instruction Count Register Definitions */
1260 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
1261 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1262
1263 /* DWT Comparator Function Register Definitions */
1264 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
1265 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
1266
1267 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
1268 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1269
1270 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
1271 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1272
1273 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
1274 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
1275
1276 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
1277 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
1278
1279 /*@}*/ /* end of group CMSIS_DWT */
1280
1281
1282 /**
1283 \ingroup CMSIS_core_register
1284 \defgroup CMSIS_TPI Trace Port Interface (TPI)
1285 \brief Type definitions for the Trace Port Interface (TPI)
1286 @{
1287 */
1288
1289 /**
1290 \brief Structure type to access the Trace Port Interface Register (TPI).
1291 */
1292 typedef struct
1293 {
1294 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
1295 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
1296 uint32_t RESERVED0[2U];
1297 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1298 uint32_t RESERVED1[55U];
1299 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1300 uint32_t RESERVED2[131U];
1301 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1302 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1303 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
1304 uint32_t RESERVED3[809U];
1305 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
1306 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
1307 uint32_t RESERVED4[4U];
1308 __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
1309 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
1310 } TPI_Type;
1311
1312 /* TPI Asynchronous Clock Prescaler Register Definitions */
1313 #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
1314 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
1315
1316 /* TPI Selected Pin Protocol Register Definitions */
1317 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
1318 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1319
1320 /* TPI Formatter and Flush Status Register Definitions */
1321 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
1322 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1323
1324 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
1325 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1326
1327 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
1328 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1329
1330 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
1331 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1332
1333 /* TPI Formatter and Flush Control Register Definitions */
1334 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
1335 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1336
1337 #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
1338 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
1339
1340 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
1341 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1342
1343 /* TPI Periodic Synchronization Control Register Definitions */
1344 #define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
1345 #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
1346
1347 /* TPI Software Lock Status Register Definitions */
1348 #define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
1349 #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
1350
1351 #define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
1352 #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
1353
1354 #define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
1355 #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
1356
1357 /* TPI DEVID Register Definitions */
1358 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
1359 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1360
1361 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
1362 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1363
1364 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
1365 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1366
1367 #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
1368 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
1369
1370 /* TPI DEVTYPE Register Definitions */
1371 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
1372 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1373
1374 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
1375 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1376
1377 /*@}*/ /* end of group CMSIS_TPI */
1378
1379
1380 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1381 /**
1382 \ingroup CMSIS_core_register
1383 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1384 \brief Type definitions for the Memory Protection Unit (MPU)
1385 @{
1386 */
1387
1388 /**
1389 \brief Structure type to access the Memory Protection Unit (MPU).
1390 */
1391 typedef struct
1392 {
1393 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1394 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1395 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
1396 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1397 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
1398 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
1399 __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
1400 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
1401 __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
1402 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
1403 __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
1404 uint32_t RESERVED0[1];
1405 union {
1406 __IOM uint32_t MAIR[2];
1407 struct {
1408 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
1409 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
1410 };
1411 };
1412 } MPU_Type;
1413
1414 #define MPU_TYPE_RALIASES 4U
1415
1416 /* MPU Type Register Definitions */
1417 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1418 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1419
1420 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1421 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1422
1423 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1424 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1425
1426 /* MPU Control Register Definitions */
1427 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1428 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1429
1430 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1431 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1432
1433 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1434 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1435
1436 /* MPU Region Number Register Definitions */
1437 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1438 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1439
1440 /* MPU Region Base Address Register Definitions */
1441 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
1442 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
1443
1444 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
1445 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
1446
1447 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
1448 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
1449
1450 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
1451 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
1452
1453 /* MPU Region Limit Address Register Definitions */
1454 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
1455 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
1456
1457 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
1458 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
1459
1460 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
1461 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
1462
1463 /* MPU Memory Attribute Indirection Register 0 Definitions */
1464 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
1465 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
1466
1467 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
1468 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
1469
1470 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
1471 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
1472
1473 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
1474 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
1475
1476 /* MPU Memory Attribute Indirection Register 1 Definitions */
1477 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
1478 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
1479
1480 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
1481 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
1482
1483 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
1484 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
1485
1486 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
1487 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
1488
1489 /*@} end of group CMSIS_MPU */
1490 #endif
1491
1492
1493 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1494 /**
1495 \ingroup CMSIS_core_register
1496 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
1497 \brief Type definitions for the Security Attribution Unit (SAU)
1498 @{
1499 */
1500
1501 /**
1502 \brief Structure type to access the Security Attribution Unit (SAU).
1503 */
1504 typedef struct
1505 {
1506 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
1507 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
1508 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1509 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
1510 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
1511 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
1512 #else
1513 uint32_t RESERVED0[3];
1514 #endif
1515 __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
1516 __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
1517 } SAU_Type;
1518
1519 /* SAU Control Register Definitions */
1520 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
1521 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
1522
1523 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
1524 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
1525
1526 /* SAU Type Register Definitions */
1527 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
1528 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
1529
1530 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1531 /* SAU Region Number Register Definitions */
1532 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
1533 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
1534
1535 /* SAU Region Base Address Register Definitions */
1536 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
1537 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
1538
1539 /* SAU Region Limit Address Register Definitions */
1540 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
1541 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
1542
1543 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
1544 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
1545
1546 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
1547 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
1548
1549 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1550
1551 /* Secure Fault Status Register Definitions */
1552 #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
1553 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
1554
1555 #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
1556 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
1557
1558 #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
1559 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
1560
1561 #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
1562 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
1563
1564 #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
1565 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
1566
1567 #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
1568 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
1569
1570 #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
1571 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
1572
1573 #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
1574 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
1575
1576 /*@} end of group CMSIS_SAU */
1577 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1578
1579
1580 /**
1581 \ingroup CMSIS_core_register
1582 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1583 \brief Type definitions for the Floating Point Unit (FPU)
1584 @{
1585 */
1586
1587 /**
1588 \brief Structure type to access the Floating Point Unit (FPU).
1589 */
1590 typedef struct
1591 {
1592 uint32_t RESERVED0[1U];
1593 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1594 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1595 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1596 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
1597 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
1598 } FPU_Type;
1599
1600 /* Floating-Point Context Control Register Definitions */
1601 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
1602 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1603
1604 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
1605 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1606
1607 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
1608 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
1609
1610 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
1611 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
1612
1613 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
1614 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
1615
1616 #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
1617 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
1618
1619 #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
1620 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
1621
1622 #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
1623 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
1624
1625 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
1626 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1627
1628 #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
1629 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
1630
1631 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
1632 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1633
1634 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
1635 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1636
1637 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
1638 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1639
1640 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
1641 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1642
1643 #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
1644 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
1645
1646 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
1647 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1648
1649 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
1650 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1651
1652 /* Floating-Point Context Address Register Definitions */
1653 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
1654 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1655
1656 /* Floating-Point Default Status Control Register Definitions */
1657 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
1658 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1659
1660 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
1661 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1662
1663 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
1664 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1665
1666 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
1667 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1668
1669 /* Media and FP Feature Register 0 Definitions */
1670 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
1671 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1672
1673 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
1674 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1675
1676 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
1677 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1678
1679 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
1680 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1681
1682 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
1683 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1684
1685 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
1686 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1687
1688 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
1689 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1690
1691 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
1692 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
1693
1694 /* Media and FP Feature Register 1 Definitions */
1695 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
1696 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1697
1698 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
1699 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1700
1701 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
1702 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1703
1704 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
1705 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1706
1707 /*@} end of group CMSIS_FPU */
1708
1709
1710 /**
1711 \ingroup CMSIS_core_register
1712 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1713 \brief Type definitions for the Core Debug Registers
1714 @{
1715 */
1716
1717 /**
1718 \brief Structure type to access the Core Debug Register (CoreDebug).
1719 */
1720 typedef struct
1721 {
1722 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1723 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1724 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1725 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1726 uint32_t RESERVED4[1U];
1727 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
1728 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
1729 } CoreDebug_Type;
1730
1731 /* Debug Halting Control and Status Register Definitions */
1732 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
1733 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1734
1735 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
1736 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
1737
1738 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
1739 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1740
1741 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1742 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1743
1744 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
1745 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1746
1747 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
1748 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1749
1750 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
1751 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1752
1753 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
1754 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1755
1756 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1757 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1758
1759 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
1760 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1761
1762 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
1763 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1764
1765 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
1766 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1767
1768 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1769 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1770
1771 /* Debug Core Register Selector Register Definitions */
1772 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
1773 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1774
1775 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
1776 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1777
1778 /* Debug Exception and Monitor Control Register Definitions */
1779 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
1780 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1781
1782 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
1783 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1784
1785 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
1786 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1787
1788 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
1789 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1790
1791 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
1792 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1793
1794 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
1795 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1796
1797 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
1798 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1799
1800 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
1801 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1802
1803 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
1804 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1805
1806 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
1807 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1808
1809 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1810 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1811
1812 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
1813 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1814
1815 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
1816 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1817
1818 /* Debug Authentication Control Register Definitions */
1819 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
1820 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
1821
1822 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
1823 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
1824
1825 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
1826 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
1827
1828 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
1829 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
1830
1831 /* Debug Security Control and Status Register Definitions */
1832 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
1833 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
1834
1835 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
1836 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
1837
1838 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
1839 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
1840
1841 /*@} end of group CMSIS_CoreDebug */
1842
1843
1844 /**
1845 \ingroup CMSIS_core_register
1846 \defgroup CMSIS_core_bitfield Core register bit field macros
1847 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1848 @{
1849 */
1850
1851 /**
1852 \brief Mask and shift a bit field value for use in a register bit range.
1853 \param[in] field Name of the register bit field.
1854 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1855 \return Masked and shifted value.
1856 */
1857 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1858
1859 /**
1860 \brief Mask and shift a register value to extract a bit filed value.
1861 \param[in] field Name of the register bit field.
1862 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1863 \return Masked and shifted bit field value.
1864 */
1865 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1866
1867 /*@} end of group CMSIS_core_bitfield */
1868
1869
1870 /**
1871 \ingroup CMSIS_core_register
1872 \defgroup CMSIS_core_base Core Definitions
1873 \brief Definitions for base addresses, unions, and structures.
1874 @{
1875 */
1876
1877 /* Memory mapping of Core Hardware */
1878 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1879 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1880 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1881 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1882 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1883 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1884 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1885 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1886
1887 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1888 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1889 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1890 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1891 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1892 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1893 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1894 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
1895
1896 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1897 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1898 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1899 #endif
1900
1901 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1902 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
1903 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
1904 #endif
1905
1906 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
1907 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
1908
1909 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1910 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
1911 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
1912 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
1913 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
1914 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
1915
1916 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
1917 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
1918 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
1919 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
1920 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
1921
1922 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1923 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
1924 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
1925 #endif
1926
1927 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
1928 #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
1929
1930 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1931 /*@} */
1932
1933
1934
1935 /*******************************************************************************
1936 * Hardware Abstraction Layer
1937 Core Function Interface contains:
1938 - Core NVIC Functions
1939 - Core SysTick Functions
1940 - Core Debug Functions
1941 - Core Register Access Functions
1942 ******************************************************************************/
1943 /**
1944 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1945 */
1946
1947
1948
1949 /* ########################## NVIC functions #################################### */
1950 /**
1951 \ingroup CMSIS_Core_FunctionInterface
1952 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1953 \brief Functions that manage interrupts and exceptions via the NVIC.
1954 @{
1955 */
1956
1957 #ifdef CMSIS_NVIC_VIRTUAL
1958 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1959 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1960 #endif
1961 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1962 #else
1963 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1964 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1965 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1966 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1967 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1968 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1969 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1970 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1971 #define NVIC_GetActive __NVIC_GetActive
1972 #define NVIC_SetPriority __NVIC_SetPriority
1973 #define NVIC_GetPriority __NVIC_GetPriority
1974 #define NVIC_SystemReset __NVIC_SystemReset
1975 #endif /* CMSIS_NVIC_VIRTUAL */
1976
1977 #ifdef CMSIS_VECTAB_VIRTUAL
1978 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1979 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1980 #endif
1981 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1982 #else
1983 #define NVIC_SetVector __NVIC_SetVector
1984 #define NVIC_GetVector __NVIC_GetVector
1985 #endif /* (CMSIS_VECTAB_VIRTUAL) */
1986
1987 #define NVIC_USER_IRQ_OFFSET 16
1988
1989
1990 /* Special LR values for Secure/Non-Secure call handling and exception handling */
1991
1992 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
1993 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
1994
1995 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
1996 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
1997 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
1998 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
1999 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
2000 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
2001 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
2002 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
2003
2004 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
2005 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
2006 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
2007 #else
2008 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
2009 #endif
2010
2011
2012 /**
2013 \brief Set Priority Grouping
2014 \details Sets the priority grouping field using the required unlock sequence.
2015 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2016 Only values from 0..7 are used.
2017 In case of a conflict between priority grouping and available
2018 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2019 \param [in] PriorityGroup Priority grouping field.
2020 */
__NVIC_SetPriorityGrouping(uint32_t PriorityGroup)2021 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
2022 {
2023 uint32_t reg_value;
2024 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2025
2026 reg_value = SCB->AIRCR; /* read old register configuration */
2027 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2028 reg_value = (reg_value |
2029 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2030 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2031 SCB->AIRCR = reg_value;
2032 }
2033
2034
2035 /**
2036 \brief Get Priority Grouping
2037 \details Reads the priority grouping field from the NVIC Interrupt Controller.
2038 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2039 */
__NVIC_GetPriorityGrouping(void)2040 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2041 {
2042 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2043 }
2044
2045
2046 /**
2047 \brief Enable Interrupt
2048 \details Enables a device specific interrupt in the NVIC interrupt controller.
2049 \param [in] IRQn Device specific interrupt number.
2050 \note IRQn must not be negative.
2051 */
__NVIC_EnableIRQ(IRQn_Type IRQn)2052 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2053 {
2054 if ((int32_t)(IRQn) >= 0)
2055 {
2056 __COMPILER_BARRIER();
2057 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2058 __COMPILER_BARRIER();
2059 }
2060 }
2061
2062
2063 /**
2064 \brief Get Interrupt Enable status
2065 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
2066 \param [in] IRQn Device specific interrupt number.
2067 \return 0 Interrupt is not enabled.
2068 \return 1 Interrupt is enabled.
2069 \note IRQn must not be negative.
2070 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)2071 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2072 {
2073 if ((int32_t)(IRQn) >= 0)
2074 {
2075 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2076 }
2077 else
2078 {
2079 return(0U);
2080 }
2081 }
2082
2083
2084 /**
2085 \brief Disable Interrupt
2086 \details Disables a device specific interrupt in the NVIC interrupt controller.
2087 \param [in] IRQn Device specific interrupt number.
2088 \note IRQn must not be negative.
2089 */
__NVIC_DisableIRQ(IRQn_Type IRQn)2090 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2091 {
2092 if ((int32_t)(IRQn) >= 0)
2093 {
2094 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2095 __DSB();
2096 __ISB();
2097 }
2098 }
2099
2100
2101 /**
2102 \brief Get Pending Interrupt
2103 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
2104 \param [in] IRQn Device specific interrupt number.
2105 \return 0 Interrupt status is not pending.
2106 \return 1 Interrupt status is pending.
2107 \note IRQn must not be negative.
2108 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)2109 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2110 {
2111 if ((int32_t)(IRQn) >= 0)
2112 {
2113 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2114 }
2115 else
2116 {
2117 return(0U);
2118 }
2119 }
2120
2121
2122 /**
2123 \brief Set Pending Interrupt
2124 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
2125 \param [in] IRQn Device specific interrupt number.
2126 \note IRQn must not be negative.
2127 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)2128 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2129 {
2130 if ((int32_t)(IRQn) >= 0)
2131 {
2132 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2133 }
2134 }
2135
2136
2137 /**
2138 \brief Clear Pending Interrupt
2139 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
2140 \param [in] IRQn Device specific interrupt number.
2141 \note IRQn must not be negative.
2142 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)2143 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2144 {
2145 if ((int32_t)(IRQn) >= 0)
2146 {
2147 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2148 }
2149 }
2150
2151
2152 /**
2153 \brief Get Active Interrupt
2154 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
2155 \param [in] IRQn Device specific interrupt number.
2156 \return 0 Interrupt status is not active.
2157 \return 1 Interrupt status is active.
2158 \note IRQn must not be negative.
2159 */
__NVIC_GetActive(IRQn_Type IRQn)2160 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2161 {
2162 if ((int32_t)(IRQn) >= 0)
2163 {
2164 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2165 }
2166 else
2167 {
2168 return(0U);
2169 }
2170 }
2171
2172
2173 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2174 /**
2175 \brief Get Interrupt Target State
2176 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2177 \param [in] IRQn Device specific interrupt number.
2178 \return 0 if interrupt is assigned to Secure
2179 \return 1 if interrupt is assigned to Non Secure
2180 \note IRQn must not be negative.
2181 */
NVIC_GetTargetState(IRQn_Type IRQn)2182 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
2183 {
2184 if ((int32_t)(IRQn) >= 0)
2185 {
2186 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2187 }
2188 else
2189 {
2190 return(0U);
2191 }
2192 }
2193
2194
2195 /**
2196 \brief Set Interrupt Target State
2197 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2198 \param [in] IRQn Device specific interrupt number.
2199 \return 0 if interrupt is assigned to Secure
2200 1 if interrupt is assigned to Non Secure
2201 \note IRQn must not be negative.
2202 */
NVIC_SetTargetState(IRQn_Type IRQn)2203 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
2204 {
2205 if ((int32_t)(IRQn) >= 0)
2206 {
2207 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2208 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2209 }
2210 else
2211 {
2212 return(0U);
2213 }
2214 }
2215
2216
2217 /**
2218 \brief Clear Interrupt Target State
2219 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2220 \param [in] IRQn Device specific interrupt number.
2221 \return 0 if interrupt is assigned to Secure
2222 1 if interrupt is assigned to Non Secure
2223 \note IRQn must not be negative.
2224 */
NVIC_ClearTargetState(IRQn_Type IRQn)2225 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
2226 {
2227 if ((int32_t)(IRQn) >= 0)
2228 {
2229 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2230 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2231 }
2232 else
2233 {
2234 return(0U);
2235 }
2236 }
2237 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2238
2239
2240 /**
2241 \brief Set Interrupt Priority
2242 \details Sets the priority of a device specific interrupt or a processor exception.
2243 The interrupt number can be positive to specify a device specific interrupt,
2244 or negative to specify a processor exception.
2245 \param [in] IRQn Interrupt number.
2246 \param [in] priority Priority to set.
2247 \note The priority cannot be set for every processor exception.
2248 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)2249 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2250 {
2251 if ((int32_t)(IRQn) >= 0)
2252 {
2253 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2254 }
2255 else
2256 {
2257 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2258 }
2259 }
2260
2261
2262 /**
2263 \brief Get Interrupt Priority
2264 \details Reads the priority of a device specific interrupt or a processor exception.
2265 The interrupt number can be positive to specify a device specific interrupt,
2266 or negative to specify a processor exception.
2267 \param [in] IRQn Interrupt number.
2268 \return Interrupt Priority.
2269 Value is aligned automatically to the implemented priority bits of the microcontroller.
2270 */
__NVIC_GetPriority(IRQn_Type IRQn)2271 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2272 {
2273
2274 if ((int32_t)(IRQn) >= 0)
2275 {
2276 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2277 }
2278 else
2279 {
2280 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2281 }
2282 }
2283
2284
2285 /**
2286 \brief Encode Priority
2287 \details Encodes the priority for an interrupt with the given priority group,
2288 preemptive priority value, and subpriority value.
2289 In case of a conflict between priority grouping and available
2290 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2291 \param [in] PriorityGroup Used priority group.
2292 \param [in] PreemptPriority Preemptive priority value (starting from 0).
2293 \param [in] SubPriority Subpriority value (starting from 0).
2294 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
2295 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)2296 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2297 {
2298 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2299 uint32_t PreemptPriorityBits;
2300 uint32_t SubPriorityBits;
2301
2302 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2303 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2304
2305 return (
2306 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2307 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2308 );
2309 }
2310
2311
2312 /**
2313 \brief Decode Priority
2314 \details Decodes an interrupt priority value with a given priority group to
2315 preemptive priority value and subpriority value.
2316 In case of a conflict between priority grouping and available
2317 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
2318 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
2319 \param [in] PriorityGroup Used priority group.
2320 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
2321 \param [out] pSubPriority Subpriority value (starting from 0).
2322 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)2323 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2324 {
2325 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2326 uint32_t PreemptPriorityBits;
2327 uint32_t SubPriorityBits;
2328
2329 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2330 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2331
2332 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2333 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2334 }
2335
2336
2337 /**
2338 \brief Set Interrupt Vector
2339 \details Sets an interrupt vector in SRAM based interrupt vector table.
2340 The interrupt number can be positive to specify a device specific interrupt,
2341 or negative to specify a processor exception.
2342 VTOR must been relocated to SRAM before.
2343 \param [in] IRQn Interrupt number
2344 \param [in] vector Address of interrupt handler function
2345 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)2346 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2347 {
2348 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2349 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2350 __DSB();
2351 }
2352
2353
2354 /**
2355 \brief Get Interrupt Vector
2356 \details Reads an interrupt vector from interrupt vector table.
2357 The interrupt number can be positive to specify a device specific interrupt,
2358 or negative to specify a processor exception.
2359 \param [in] IRQn Interrupt number.
2360 \return Address of interrupt handler function
2361 */
__NVIC_GetVector(IRQn_Type IRQn)2362 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2363 {
2364 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2365 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2366 }
2367
2368
2369 /**
2370 \brief System Reset
2371 \details Initiates a system reset request to reset the MCU.
2372 */
__NVIC_SystemReset(void)2373 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2374 {
2375 __DSB(); /* Ensure all outstanding memory accesses included
2376 buffered write are completed before reset */
2377 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2378 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2379 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2380 __DSB(); /* Ensure completion of memory access */
2381
2382 for(;;) /* wait until reset */
2383 {
2384 __NOP();
2385 }
2386 }
2387
2388 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2389 /**
2390 \brief Set Priority Grouping (non-secure)
2391 \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
2392 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2393 Only values from 0..7 are used.
2394 In case of a conflict between priority grouping and available
2395 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2396 \param [in] PriorityGroup Priority grouping field.
2397 */
TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)2398 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
2399 {
2400 uint32_t reg_value;
2401 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2402
2403 reg_value = SCB_NS->AIRCR; /* read old register configuration */
2404 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2405 reg_value = (reg_value |
2406 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2407 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2408 SCB_NS->AIRCR = reg_value;
2409 }
2410
2411
2412 /**
2413 \brief Get Priority Grouping (non-secure)
2414 \details Reads the priority grouping field from the non-secure NVIC when in secure state.
2415 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2416 */
TZ_NVIC_GetPriorityGrouping_NS(void)2417 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
2418 {
2419 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2420 }
2421
2422
2423 /**
2424 \brief Enable Interrupt (non-secure)
2425 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2426 \param [in] IRQn Device specific interrupt number.
2427 \note IRQn must not be negative.
2428 */
TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)2429 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
2430 {
2431 if ((int32_t)(IRQn) >= 0)
2432 {
2433 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2434 }
2435 }
2436
2437
2438 /**
2439 \brief Get Interrupt Enable status (non-secure)
2440 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
2441 \param [in] IRQn Device specific interrupt number.
2442 \return 0 Interrupt is not enabled.
2443 \return 1 Interrupt is enabled.
2444 \note IRQn must not be negative.
2445 */
TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)2446 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
2447 {
2448 if ((int32_t)(IRQn) >= 0)
2449 {
2450 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2451 }
2452 else
2453 {
2454 return(0U);
2455 }
2456 }
2457
2458
2459 /**
2460 \brief Disable Interrupt (non-secure)
2461 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2462 \param [in] IRQn Device specific interrupt number.
2463 \note IRQn must not be negative.
2464 */
TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)2465 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
2466 {
2467 if ((int32_t)(IRQn) >= 0)
2468 {
2469 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2470 }
2471 }
2472
2473
2474 /**
2475 \brief Get Pending Interrupt (non-secure)
2476 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
2477 \param [in] IRQn Device specific interrupt number.
2478 \return 0 Interrupt status is not pending.
2479 \return 1 Interrupt status is pending.
2480 \note IRQn must not be negative.
2481 */
TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)2482 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
2483 {
2484 if ((int32_t)(IRQn) >= 0)
2485 {
2486 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2487 }
2488 else
2489 {
2490 return(0U);
2491 }
2492 }
2493
2494
2495 /**
2496 \brief Set Pending Interrupt (non-secure)
2497 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2498 \param [in] IRQn Device specific interrupt number.
2499 \note IRQn must not be negative.
2500 */
TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)2501 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
2502 {
2503 if ((int32_t)(IRQn) >= 0)
2504 {
2505 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2506 }
2507 }
2508
2509
2510 /**
2511 \brief Clear Pending Interrupt (non-secure)
2512 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2513 \param [in] IRQn Device specific interrupt number.
2514 \note IRQn must not be negative.
2515 */
TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)2516 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
2517 {
2518 if ((int32_t)(IRQn) >= 0)
2519 {
2520 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2521 }
2522 }
2523
2524
2525 /**
2526 \brief Get Active Interrupt (non-secure)
2527 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
2528 \param [in] IRQn Device specific interrupt number.
2529 \return 0 Interrupt status is not active.
2530 \return 1 Interrupt status is active.
2531 \note IRQn must not be negative.
2532 */
TZ_NVIC_GetActive_NS(IRQn_Type IRQn)2533 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
2534 {
2535 if ((int32_t)(IRQn) >= 0)
2536 {
2537 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2538 }
2539 else
2540 {
2541 return(0U);
2542 }
2543 }
2544
2545
2546 /**
2547 \brief Set Interrupt Priority (non-secure)
2548 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2549 The interrupt number can be positive to specify a device specific interrupt,
2550 or negative to specify a processor exception.
2551 \param [in] IRQn Interrupt number.
2552 \param [in] priority Priority to set.
2553 \note The priority cannot be set for every non-secure processor exception.
2554 */
TZ_NVIC_SetPriority_NS(IRQn_Type IRQn,uint32_t priority)2555 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2556 {
2557 if ((int32_t)(IRQn) >= 0)
2558 {
2559 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2560 }
2561 else
2562 {
2563 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2564 }
2565 }
2566
2567
2568 /**
2569 \brief Get Interrupt Priority (non-secure)
2570 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2571 The interrupt number can be positive to specify a device specific interrupt,
2572 or negative to specify a processor exception.
2573 \param [in] IRQn Interrupt number.
2574 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
2575 */
TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)2576 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2577 {
2578
2579 if ((int32_t)(IRQn) >= 0)
2580 {
2581 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2582 }
2583 else
2584 {
2585 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2586 }
2587 }
2588 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2589
2590 /*@} end of CMSIS_Core_NVICFunctions */
2591
2592 /* ########################## MPU functions #################################### */
2593
2594 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2595
2596 #include "mpu_armv8.h"
2597
2598 #endif
2599
2600 /* ########################## FPU functions #################################### */
2601 /**
2602 \ingroup CMSIS_Core_FunctionInterface
2603 \defgroup CMSIS_Core_FpuFunctions FPU Functions
2604 \brief Function that provides FPU type.
2605 @{
2606 */
2607
2608 /**
2609 \brief get FPU type
2610 \details returns the FPU type
2611 \returns
2612 - \b 0: No FPU
2613 - \b 1: Single precision FPU
2614 - \b 2: Double + Single precision FPU
2615 */
SCB_GetFPUType(void)2616 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2617 {
2618 uint32_t mvfr0;
2619
2620 mvfr0 = FPU->MVFR0;
2621 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2622 {
2623 return 2U; /* Double + Single precision FPU */
2624 }
2625 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2626 {
2627 return 1U; /* Single precision FPU */
2628 }
2629 else
2630 {
2631 return 0U; /* No FPU */
2632 }
2633 }
2634
2635
2636 /*@} end of CMSIS_Core_FpuFunctions */
2637
2638
2639
2640 /* ########################## SAU functions #################################### */
2641 /**
2642 \ingroup CMSIS_Core_FunctionInterface
2643 \defgroup CMSIS_Core_SAUFunctions SAU Functions
2644 \brief Functions that configure the SAU.
2645 @{
2646 */
2647
2648 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2649
2650 /**
2651 \brief Enable SAU
2652 \details Enables the Security Attribution Unit (SAU).
2653 */
TZ_SAU_Enable(void)2654 __STATIC_INLINE void TZ_SAU_Enable(void)
2655 {
2656 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2657 }
2658
2659
2660
2661 /**
2662 \brief Disable SAU
2663 \details Disables the Security Attribution Unit (SAU).
2664 */
TZ_SAU_Disable(void)2665 __STATIC_INLINE void TZ_SAU_Disable(void)
2666 {
2667 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2668 }
2669
2670 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2671
2672 /*@} end of CMSIS_Core_SAUFunctions */
2673
2674
2675
2676
2677 /* ################################## SysTick function ############################################ */
2678 /**
2679 \ingroup CMSIS_Core_FunctionInterface
2680 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2681 \brief Functions that configure the System.
2682 @{
2683 */
2684
2685 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2686
2687 /**
2688 \brief System Tick Configuration
2689 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
2690 Counter is in free running mode to generate periodic interrupts.
2691 \param [in] ticks Number of ticks between two interrupts.
2692 \return 0 Function succeeded.
2693 \return 1 Function failed.
2694 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2695 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
2696 must contain a vendor-specific implementation of this function.
2697 */
SysTick_Config(uint32_t ticks)2698 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2699 {
2700 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2701 {
2702 return (1UL); /* Reload value impossible */
2703 }
2704
2705 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2706 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2707 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2708 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2709 SysTick_CTRL_TICKINT_Msk |
2710 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2711 return (0UL); /* Function successful */
2712 }
2713
2714 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2715 /**
2716 \brief System Tick Configuration (non-secure)
2717 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
2718 Counter is in free running mode to generate periodic interrupts.
2719 \param [in] ticks Number of ticks between two interrupts.
2720 \return 0 Function succeeded.
2721 \return 1 Function failed.
2722 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2723 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
2724 must contain a vendor-specific implementation of this function.
2725
2726 */
TZ_SysTick_Config_NS(uint32_t ticks)2727 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
2728 {
2729 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2730 {
2731 return (1UL); /* Reload value impossible */
2732 }
2733
2734 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2735 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2736 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
2737 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2738 SysTick_CTRL_TICKINT_Msk |
2739 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2740 return (0UL); /* Function successful */
2741 }
2742 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2743
2744 #endif
2745
2746 /*@} end of CMSIS_Core_SysTickFunctions */
2747
2748
2749
2750 /* ##################################### Debug In/Output function ########################################### */
2751 /**
2752 \ingroup CMSIS_Core_FunctionInterface
2753 \defgroup CMSIS_core_DebugFunctions ITM Functions
2754 \brief Functions that access the ITM debug interface.
2755 @{
2756 */
2757
2758 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
2759 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
2760
2761
2762 /**
2763 \brief ITM Send Character
2764 \details Transmits a character via the ITM channel 0, and
2765 \li Just returns when no debugger is connected that has booked the output.
2766 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
2767 \param [in] ch Character to transmit.
2768 \returns Character to transmit.
2769 */
ITM_SendChar(uint32_t ch)2770 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2771 {
2772 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2773 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2774 {
2775 while (ITM->PORT[0U].u32 == 0UL)
2776 {
2777 __NOP();
2778 }
2779 ITM->PORT[0U].u8 = (uint8_t)ch;
2780 }
2781 return (ch);
2782 }
2783
2784
2785 /**
2786 \brief ITM Receive Character
2787 \details Inputs a character via the external variable \ref ITM_RxBuffer.
2788 \return Received character.
2789 \return -1 No character pending.
2790 */
ITM_ReceiveChar(void)2791 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
2792 {
2793 int32_t ch = -1; /* no character available */
2794
2795 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2796 {
2797 ch = ITM_RxBuffer;
2798 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2799 }
2800
2801 return (ch);
2802 }
2803
2804
2805 /**
2806 \brief ITM Check Character
2807 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
2808 \return 0 No character available.
2809 \return 1 Character available.
2810 */
ITM_CheckChar(void)2811 __STATIC_INLINE int32_t ITM_CheckChar (void)
2812 {
2813
2814 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2815 {
2816 return (0); /* no character available */
2817 }
2818 else
2819 {
2820 return (1); /* character available */
2821 }
2822 }
2823
2824 /*@} end of CMSIS_core_DebugFunctions */
2825
2826
2827
2828
2829 #ifdef __cplusplus
2830 }
2831 #endif
2832
2833 #endif /* __CORE_ARMV8MML_H_DEPENDANT */
2834
2835 #endif /* __CMSIS_GENERIC */
2836