1 /**
2 ******************************************************************************
3 * @file system_stm32l4xx.c
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
6 *
7 * This file provides two functions and one global variable to be called from
8 * user application:
9 * - SystemInit(): This function is called at startup just after reset and
10 * before branch to main program. This call is made inside
11 * the "startup_stm32l4xx.s" file.
12 *
13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14 * by the user application to setup the SysTick
15 * timer or configure other parameters.
16 *
17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18 * be called whenever the core clock is changed
19 * during program execution.
20 *
21 * After each device reset the MSI (4 MHz) is used as system clock source.
22 * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
23 * configure the system clock before to branch to main program.
24 *
25 * This file configures the system clock as follows:
26 *=============================================================================
27 *-----------------------------------------------------------------------------
28 * System Clock source | MSI
29 *-----------------------------------------------------------------------------
30 * SYSCLK(Hz) | 4000000
31 *-----------------------------------------------------------------------------
32 * HCLK(Hz) | 4000000
33 *-----------------------------------------------------------------------------
34 * AHB Prescaler | 1
35 *-----------------------------------------------------------------------------
36 * APB1 Prescaler | 1
37 *-----------------------------------------------------------------------------
38 * APB2 Prescaler | 1
39 *-----------------------------------------------------------------------------
40 * PLL_M | 1
41 *-----------------------------------------------------------------------------
42 * PLL_N | 8
43 *-----------------------------------------------------------------------------
44 * PLL_P | 7
45 *-----------------------------------------------------------------------------
46 * PLL_Q | 2
47 *-----------------------------------------------------------------------------
48 * PLL_R | 2
49 *-----------------------------------------------------------------------------
50 * PLLSAI1_P | NA
51 *-----------------------------------------------------------------------------
52 * PLLSAI1_Q | NA
53 *-----------------------------------------------------------------------------
54 * PLLSAI1_R | NA
55 *-----------------------------------------------------------------------------
56 * PLLSAI2_P | NA
57 *-----------------------------------------------------------------------------
58 * PLLSAI2_Q | NA
59 *-----------------------------------------------------------------------------
60 * PLLSAI2_R | NA
61 *-----------------------------------------------------------------------------
62 * Require 48MHz for USB OTG FS, | Disabled
63 * SDIO and RNG clock |
64 *-----------------------------------------------------------------------------
65 *=============================================================================
66 ******************************************************************************
67 * @attention
68 *
69 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
70 * All rights reserved.</center></h2>
71 *
72 * This software component is licensed by ST under BSD 3-Clause license,
73 * the "License"; You may not use this file except in compliance with the
74 * License. You may obtain a copy of the License at:
75 * opensource.org/licenses/BSD-3-Clause
76 *
77 ******************************************************************************
78 */
79
80 /** @addtogroup CMSIS
81 * @{
82 */
83
84 /** @addtogroup stm32l4xx_system
85 * @{
86 */
87
88 /** @addtogroup STM32L4xx_System_Private_Includes
89 * @{
90 */
91
92 #include "stm32l4xx.h"
93
94 #if !defined (HSE_VALUE)
95 #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
96 #endif /* HSE_VALUE */
97
98 #if !defined (MSI_VALUE)
99 #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
100 #endif /* MSI_VALUE */
101
102 #if !defined (HSI_VALUE)
103 #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
104 #endif /* HSI_VALUE */
105
106 /**
107 * @}
108 */
109
110 /** @addtogroup STM32L4xx_System_Private_TypesDefinitions
111 * @{
112 */
113
114 /**
115 * @}
116 */
117
118 /** @addtogroup STM32L4xx_System_Private_Defines
119 * @{
120 */
121
122 /************************* Miscellaneous Configuration ************************/
123 /*!< Uncomment the following line if you need to relocate your vector Table in
124 Internal SRAM. */
125 /* #define VECT_TAB_SRAM */
126 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
127 This value must be a multiple of 0x200. */
128 /******************************************************************************/
129 /**
130 * @}
131 */
132
133 /** @addtogroup STM32L4xx_System_Private_Macros
134 * @{
135 */
136
137 /**
138 * @}
139 */
140
141 /** @addtogroup STM32L4xx_System_Private_Variables
142 * @{
143 */
144 /* The SystemCoreClock variable is updated in three ways:
145 1) by calling CMSIS function SystemCoreClockUpdate()
146 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
147 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
148 Note: If you use this function to configure the system clock; then there
149 is no need to call the 2 first functions listed above, since SystemCoreClock
150 variable is updated automatically.
151 */
152 uint32_t SystemCoreClock = 4000000U;
153
154 const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
155 const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
156 const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \
157 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U};
158 /**
159 * @}
160 */
161
162 /** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
163 * @{
164 */
165
166 /**
167 * @}
168 */
169
170 /** @addtogroup STM32L4xx_System_Private_Functions
171 * @{
172 */
173
174 /**
175 * @brief Setup the microcontroller system.
176 * @param None
177 * @retval None
178 */
179
SystemInit(void)180 void SystemInit(void)
181 {
182 /* FPU settings ------------------------------------------------------------*/
183 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
184 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
185 #endif
186
187 /* Reset the RCC clock configuration to the default reset state ------------*/
188 /* Set MSION bit */
189 RCC->CR |= RCC_CR_MSION;
190
191 /* Reset CFGR register */
192 RCC->CFGR = 0x00000000U;
193
194 /* Reset HSEON, CSSON , HSION, and PLLON bits */
195 RCC->CR &= 0xEAF6FFFFU;
196
197 /* Reset PLLCFGR register */
198 RCC->PLLCFGR = 0x00001000U;
199
200 /* Reset HSEBYP bit */
201 RCC->CR &= 0xFFFBFFFFU;
202
203 /* Disable all interrupts */
204 RCC->CIER = 0x00000000U;
205
206 /* Configure the Vector Table location add offset address ------------------*/
207 #ifdef VECT_TAB_SRAM
208 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
209 #else
210 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
211 #endif
212 }
213
214 /**
215 * @brief Update SystemCoreClock variable according to Clock Register Values.
216 * The SystemCoreClock variable contains the core clock (HCLK), it can
217 * be used by the user application to setup the SysTick timer or configure
218 * other parameters.
219 *
220 * @note Each time the core clock (HCLK) changes, this function must be called
221 * to update SystemCoreClock variable value. Otherwise, any configuration
222 * based on this variable will be incorrect.
223 *
224 * @note - The system frequency computed by this function is not the real
225 * frequency in the chip. It is calculated based on the predefined
226 * constant and the selected clock source:
227 *
228 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
229 *
230 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
231 *
232 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
233 *
234 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
235 * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
236 *
237 * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
238 * 4 MHz) but the real value may vary depending on the variations
239 * in voltage and temperature.
240 *
241 * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
242 * 16 MHz) but the real value may vary depending on the variations
243 * in voltage and temperature.
244 *
245 * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
246 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
247 * frequency of the crystal used. Otherwise, this function may
248 * have wrong result.
249 *
250 * - The result of this function could be not correct when using fractional
251 * value for HSE crystal.
252 *
253 * @param None
254 * @retval None
255 */
SystemCoreClockUpdate(void)256 void SystemCoreClockUpdate(void)
257 {
258 uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U;
259
260 /* Get MSI Range frequency--------------------------------------------------*/
261 if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
262 { /* MSISRANGE from RCC_CSR applies */
263 msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
264 }
265 else
266 { /* MSIRANGE from RCC_CR applies */
267 msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
268 }
269 /*MSI frequency range in HZ*/
270 msirange = MSIRangeTable[msirange];
271
272 /* Get SYSCLK source -------------------------------------------------------*/
273 switch (RCC->CFGR & RCC_CFGR_SWS)
274 {
275 case 0x00: /* MSI used as system clock source */
276 SystemCoreClock = msirange;
277 break;
278
279 case 0x04: /* HSI used as system clock source */
280 SystemCoreClock = HSI_VALUE;
281 break;
282
283 case 0x08: /* HSE used as system clock source */
284 SystemCoreClock = HSE_VALUE;
285 break;
286
287 case 0x0C: /* PLL used as system clock source */
288 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
289 SYSCLK = PLL_VCO / PLLR
290 */
291 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
292 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
293
294 switch (pllsource)
295 {
296 case 0x02: /* HSI used as PLL clock source */
297 pllvco = (HSI_VALUE / pllm);
298 break;
299
300 case 0x03: /* HSE used as PLL clock source */
301 pllvco = (HSE_VALUE / pllm);
302 break;
303
304 default: /* MSI used as PLL clock source */
305 pllvco = (msirange / pllm);
306 break;
307 }
308 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
309 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
310 SystemCoreClock = pllvco/pllr;
311 break;
312
313 default:
314 SystemCoreClock = msirange;
315 break;
316 }
317 /* Compute HCLK clock frequency --------------------------------------------*/
318 /* Get HCLK prescaler */
319 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
320 /* HCLK clock frequency */
321 SystemCoreClock >>= tmp;
322 }
323
324
325 /**
326 * @}
327 */
328
329 /**
330 * @}
331 */
332
333 /**
334 * @}
335 */
336
337 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
338