1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32l4xx_ll_tim.h"
23 #include "stm32l4xx_ll_bus.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif /* USE_FULL_ASSERT */
30
31 /** @addtogroup STM32L4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
36
37 /** @addtogroup TIM_LL
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45 /** @addtogroup TIM_LL_Private_Macros
46 * @{
47 */
48 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
52 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
53
54 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
56 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
57
58 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
59 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
65 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
66 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
67 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
68 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
69 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
70 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
71 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
72
73 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
74 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
75
76 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
77 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
78
79 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
80 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
81
82 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
83 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
84 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
85
86 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
87 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
88 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
89 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
90
91 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
92 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
100 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
101 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
106 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
107
108 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
109 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
110 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
111
112 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
113 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
114 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
115
116 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
117 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
118
119 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
120 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
121
122 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
123 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
124
125 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
126 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
127 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
128 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
129
130 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
131 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
132
133 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
134 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
135
136 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
137 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
138 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
139 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
140 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
141 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
142 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
143 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
144 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
145 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
146 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
147 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
148 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
149 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
150 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
151 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
152
153 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
154 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
155
156 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
157 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
158
159 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
160 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
161 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
162 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
163 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
164 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
165 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
166 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
167 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
168 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
169 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
170 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
171 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
172 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
173 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
174 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
175
176 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
177 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
178 /**
179 * @}
180 */
181
182
183 /* Private function prototypes -----------------------------------------------*/
184 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
185 * @{
186 */
187 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
188 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
189 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
190 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
191 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
192 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
193 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
194 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
195 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
196 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
197 /**
198 * @}
199 */
200
201 /* Exported functions --------------------------------------------------------*/
202 /** @addtogroup TIM_LL_Exported_Functions
203 * @{
204 */
205
206 /** @addtogroup TIM_LL_EF_Init
207 * @{
208 */
209
210 /**
211 * @brief Set TIMx registers to their reset values.
212 * @param TIMx Timer instance
213 * @retval An ErrorStatus enumeration value:
214 * - SUCCESS: TIMx registers are de-initialized
215 * - ERROR: invalid TIMx instance
216 */
LL_TIM_DeInit(TIM_TypeDef * TIMx)217 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
218 {
219 ErrorStatus result = SUCCESS;
220
221 /* Check the parameters */
222 assert_param(IS_TIM_INSTANCE(TIMx));
223
224 if (TIMx == TIM1)
225 {
226 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
227 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
228 }
229 else if (TIMx == TIM2)
230 {
231 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
232 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
233 }
234 #if defined(TIM3)
235 else if (TIMx == TIM3)
236 {
237 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
238 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
239 }
240 #endif
241 #if defined(TIM4)
242 else if (TIMx == TIM4)
243 {
244 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
245 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
246 }
247 #endif
248 #if defined(TIM5)
249 else if (TIMx == TIM5)
250 {
251 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
252 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
253 }
254 #endif
255 else if (TIMx == TIM6)
256 {
257 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
258 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
259 }
260 #if defined (TIM7)
261 else if (TIMx == TIM7)
262 {
263 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
264 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
265 }
266 #endif
267 #if defined(TIM8)
268 else if (TIMx == TIM8)
269 {
270 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
271 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
272 }
273 #endif
274 else if (TIMx == TIM15)
275 {
276 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
277 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
278 }
279 else if (TIMx == TIM16)
280 {
281 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
282 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
283 }
284 #if defined(TIM17)
285 else if (TIMx == TIM17)
286 {
287 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
288 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
289 }
290 #endif
291 else
292 {
293 result = ERROR;
294 }
295
296 return result;
297 }
298
299 /**
300 * @brief Set the fields of the time base unit configuration data structure
301 * to their default values.
302 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
303 * @retval None
304 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)305 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
306 {
307 /* Set the default configuration */
308 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
309 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
310 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
311 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
312 TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
313 }
314
315 /**
316 * @brief Configure the TIMx time base unit.
317 * @param TIMx Timer Instance
318 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
319 * @retval An ErrorStatus enumeration value:
320 * - SUCCESS: TIMx registers are de-initialized
321 * - ERROR: not applicable
322 */
LL_TIM_Init(TIM_TypeDef * TIMx,LL_TIM_InitTypeDef * TIM_InitStruct)323 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
324 {
325 uint32_t tmpcr1;
326
327 /* Check the parameters */
328 assert_param(IS_TIM_INSTANCE(TIMx));
329 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
330 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
331
332 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
333
334 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
335 {
336 /* Select the Counter Mode */
337 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
338 }
339
340 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
341 {
342 /* Set the clock division */
343 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
344 }
345
346 /* Write to TIMx CR1 */
347 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
348
349 /* Set the Autoreload value */
350 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
351
352 /* Set the Prescaler value */
353 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
354
355 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
356 {
357 /* Set the Repetition Counter value */
358 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
359 }
360
361 /* Generate an update event to reload the Prescaler
362 and the repetition counter value (if applicable) immediately */
363 LL_TIM_GenerateEvent_UPDATE(TIMx);
364
365 return SUCCESS;
366 }
367
368 /**
369 * @brief Set the fields of the TIMx output channel configuration data
370 * structure to their default values.
371 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
372 * @retval None
373 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)374 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
375 {
376 /* Set the default configuration */
377 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
378 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
379 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
380 TIM_OC_InitStruct->CompareValue = 0x00000000U;
381 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
382 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
383 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
384 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
385 }
386
387 /**
388 * @brief Configure the TIMx output channel.
389 * @param TIMx Timer Instance
390 * @param Channel This parameter can be one of the following values:
391 * @arg @ref LL_TIM_CHANNEL_CH1
392 * @arg @ref LL_TIM_CHANNEL_CH2
393 * @arg @ref LL_TIM_CHANNEL_CH3
394 * @arg @ref LL_TIM_CHANNEL_CH4
395 * @arg @ref LL_TIM_CHANNEL_CH5
396 * @arg @ref LL_TIM_CHANNEL_CH6
397 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
398 * @retval An ErrorStatus enumeration value:
399 * - SUCCESS: TIMx output channel is initialized
400 * - ERROR: TIMx output channel is not initialized
401 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)402 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
403 {
404 ErrorStatus result = ERROR;
405
406 switch (Channel)
407 {
408 case LL_TIM_CHANNEL_CH1:
409 result = OC1Config(TIMx, TIM_OC_InitStruct);
410 break;
411 case LL_TIM_CHANNEL_CH2:
412 result = OC2Config(TIMx, TIM_OC_InitStruct);
413 break;
414 case LL_TIM_CHANNEL_CH3:
415 result = OC3Config(TIMx, TIM_OC_InitStruct);
416 break;
417 case LL_TIM_CHANNEL_CH4:
418 result = OC4Config(TIMx, TIM_OC_InitStruct);
419 break;
420 case LL_TIM_CHANNEL_CH5:
421 result = OC5Config(TIMx, TIM_OC_InitStruct);
422 break;
423 case LL_TIM_CHANNEL_CH6:
424 result = OC6Config(TIMx, TIM_OC_InitStruct);
425 break;
426 default:
427 break;
428 }
429
430 return result;
431 }
432
433 /**
434 * @brief Set the fields of the TIMx input channel configuration data
435 * structure to their default values.
436 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
437 * @retval None
438 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)439 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
440 {
441 /* Set the default configuration */
442 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
443 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
444 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
445 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
446 }
447
448 /**
449 * @brief Configure the TIMx input channel.
450 * @param TIMx Timer Instance
451 * @param Channel This parameter can be one of the following values:
452 * @arg @ref LL_TIM_CHANNEL_CH1
453 * @arg @ref LL_TIM_CHANNEL_CH2
454 * @arg @ref LL_TIM_CHANNEL_CH3
455 * @arg @ref LL_TIM_CHANNEL_CH4
456 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
457 * @retval An ErrorStatus enumeration value:
458 * - SUCCESS: TIMx output channel is initialized
459 * - ERROR: TIMx output channel is not initialized
460 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)461 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
462 {
463 ErrorStatus result = ERROR;
464
465 switch (Channel)
466 {
467 case LL_TIM_CHANNEL_CH1:
468 result = IC1Config(TIMx, TIM_IC_InitStruct);
469 break;
470 case LL_TIM_CHANNEL_CH2:
471 result = IC2Config(TIMx, TIM_IC_InitStruct);
472 break;
473 case LL_TIM_CHANNEL_CH3:
474 result = IC3Config(TIMx, TIM_IC_InitStruct);
475 break;
476 case LL_TIM_CHANNEL_CH4:
477 result = IC4Config(TIMx, TIM_IC_InitStruct);
478 break;
479 default:
480 break;
481 }
482
483 return result;
484 }
485
486 /**
487 * @brief Fills each TIM_EncoderInitStruct field with its default value
488 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
489 * @retval None
490 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)491 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
492 {
493 /* Set the default configuration */
494 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
495 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
496 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
497 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
498 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
499 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
500 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
501 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
502 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
503 }
504
505 /**
506 * @brief Configure the encoder interface of the timer instance.
507 * @param TIMx Timer Instance
508 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
509 * @retval An ErrorStatus enumeration value:
510 * - SUCCESS: TIMx registers are de-initialized
511 * - ERROR: not applicable
512 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)513 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
514 {
515 uint32_t tmpccmr1;
516 uint32_t tmpccer;
517
518 /* Check the parameters */
519 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
520 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
521 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
522 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
523 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
524 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
525 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
526 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
527 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
528 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
529
530 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
531 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
532
533 /* Get the TIMx CCMR1 register value */
534 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
535
536 /* Get the TIMx CCER register value */
537 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
538
539 /* Configure TI1 */
540 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
541 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
542 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
543 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
544
545 /* Configure TI2 */
546 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
547 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
548 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
549 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
550
551 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
552 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
553 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
554 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
555 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
556
557 /* Set encoder mode */
558 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
559
560 /* Write to TIMx CCMR1 */
561 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
562
563 /* Write to TIMx CCER */
564 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
565
566 return SUCCESS;
567 }
568
569 /**
570 * @brief Set the fields of the TIMx Hall sensor interface configuration data
571 * structure to their default values.
572 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
573 * @retval None
574 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)575 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
576 {
577 /* Set the default configuration */
578 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
579 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
580 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
581 TIM_HallSensorInitStruct->CommutationDelay = 0U;
582 }
583
584 /**
585 * @brief Configure the Hall sensor interface of the timer instance.
586 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
587 * to the TI1 input channel
588 * @note TIMx slave mode controller is configured in reset mode.
589 Selected internal trigger is TI1F_ED.
590 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
591 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
592 * between 2 changes on the inputs. It gives information about motor speed.
593 * @note Channel 2 is configured in output PWM 2 mode.
594 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
595 * @note OC2REF is selected as trigger output on TRGO.
596 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
597 * when TIMx operates in Hall sensor interface mode.
598 * @param TIMx Timer Instance
599 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
600 * @retval An ErrorStatus enumeration value:
601 * - SUCCESS: TIMx registers are de-initialized
602 * - ERROR: not applicable
603 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)604 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
605 {
606 uint32_t tmpcr2;
607 uint32_t tmpccmr1;
608 uint32_t tmpccer;
609 uint32_t tmpsmcr;
610
611 /* Check the parameters */
612 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
613 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
614 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
615 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
616
617 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
618 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
619
620 /* Get the TIMx CR2 register value */
621 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
622
623 /* Get the TIMx CCMR1 register value */
624 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
625
626 /* Get the TIMx CCER register value */
627 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
628
629 /* Get the TIMx SMCR register value */
630 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
631
632 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
633 tmpcr2 |= TIM_CR2_TI1S;
634
635 /* OC2REF signal is used as trigger output (TRGO) */
636 tmpcr2 |= LL_TIM_TRGO_OC2REF;
637
638 /* Configure the slave mode controller */
639 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
640 tmpsmcr |= LL_TIM_TS_TI1F_ED;
641 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
642
643 /* Configure input channel 1 */
644 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
645 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
646 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
647 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
648
649 /* Configure input channel 2 */
650 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
651 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
652
653 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
654 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
655 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
656 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
657
658 /* Write to TIMx CR2 */
659 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
660
661 /* Write to TIMx SMCR */
662 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
663
664 /* Write to TIMx CCMR1 */
665 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
666
667 /* Write to TIMx CCER */
668 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
669
670 /* Write to TIMx CCR2 */
671 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
672
673 return SUCCESS;
674 }
675
676 /**
677 * @brief Set the fields of the Break and Dead Time configuration data structure
678 * to their default values.
679 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
680 * @retval None
681 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)682 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
683 {
684 /* Set the default configuration */
685 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
686 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
687 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
688 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
689 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
690 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
691 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
692 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
693 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
694 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
695 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
696 }
697
698 /**
699 * @brief Configure the Break and Dead Time feature of the timer instance.
700 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
701 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
702 * can be necessary to configure all of them during the first write access to
703 * the TIMx_BDTR register.
704 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
705 * a timer instance provides a break input.
706 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
707 * a timer instance provides a second break input.
708 * @param TIMx Timer Instance
709 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
710 * @retval An ErrorStatus enumeration value:
711 * - SUCCESS: Break and Dead Time is initialized
712 * - ERROR: not applicable
713 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)714 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
715 {
716 uint32_t tmpbdtr = 0;
717
718 /* Check the parameters */
719 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
720 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
721 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
722 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
723 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
724 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
725 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
726
727 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
728 the OSSI State, the dead time value and the Automatic Output Enable Bit */
729
730 /* Set the BDTR bits */
731 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
732 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
733 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
734 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
735 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
736 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
737 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
738 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
739 if (IS_TIM_ADVANCED_INSTANCE(TIMx))
740 {
741 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
742 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
743 }
744
745 if (IS_TIM_BKIN2_INSTANCE(TIMx))
746 {
747 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
748 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
749 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
750
751 /* Set the BREAK2 input related BDTR bit-fields */
752 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
753 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
754 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
755 }
756
757 /* Set TIMx_BDTR */
758 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
759
760 return SUCCESS;
761 }
762 /**
763 * @}
764 */
765
766 /**
767 * @}
768 */
769
770 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
771 * @brief Private functions
772 * @{
773 */
774 /**
775 * @brief Configure the TIMx output channel 1.
776 * @param TIMx Timer Instance
777 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
778 * @retval An ErrorStatus enumeration value:
779 * - SUCCESS: TIMx registers are de-initialized
780 * - ERROR: not applicable
781 */
OC1Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)782 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
783 {
784 uint32_t tmpccmr1;
785 uint32_t tmpccer;
786 uint32_t tmpcr2;
787
788 /* Check the parameters */
789 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
790 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
791 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
792 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
793 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
794 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
795
796 /* Disable the Channel 1: Reset the CC1E Bit */
797 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
798
799 /* Get the TIMx CCER register value */
800 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
801
802 /* Get the TIMx CR2 register value */
803 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
804
805 /* Get the TIMx CCMR1 register value */
806 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
807
808 /* Reset Capture/Compare selection Bits */
809 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
810
811 /* Set the Output Compare Mode */
812 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
813
814 /* Set the Output Compare Polarity */
815 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
816
817 /* Set the Output State */
818 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
819
820 if (IS_TIM_BREAK_INSTANCE(TIMx))
821 {
822 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
823 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
824
825 /* Set the complementary output Polarity */
826 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
827
828 /* Set the complementary output State */
829 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
830
831 /* Set the Output Idle state */
832 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
833
834 /* Set the complementary output Idle state */
835 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
836 }
837
838 /* Write to TIMx CR2 */
839 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
840
841 /* Write to TIMx CCMR1 */
842 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
843
844 /* Set the Capture Compare Register value */
845 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
846
847 /* Write to TIMx CCER */
848 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
849
850 return SUCCESS;
851 }
852
853 /**
854 * @brief Configure the TIMx output channel 2.
855 * @param TIMx Timer Instance
856 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
857 * @retval An ErrorStatus enumeration value:
858 * - SUCCESS: TIMx registers are de-initialized
859 * - ERROR: not applicable
860 */
OC2Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)861 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
862 {
863 uint32_t tmpccmr1;
864 uint32_t tmpccer;
865 uint32_t tmpcr2;
866
867 /* Check the parameters */
868 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
869 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
870 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
871 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
872 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
873 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
874
875 /* Disable the Channel 2: Reset the CC2E Bit */
876 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
877
878 /* Get the TIMx CCER register value */
879 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
880
881 /* Get the TIMx CR2 register value */
882 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
883
884 /* Get the TIMx CCMR1 register value */
885 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
886
887 /* Reset Capture/Compare selection Bits */
888 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
889
890 /* Select the Output Compare Mode */
891 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
892
893 /* Set the Output Compare Polarity */
894 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
895
896 /* Set the Output State */
897 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
898
899 if (IS_TIM_BREAK_INSTANCE(TIMx))
900 {
901 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
902 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
903
904 /* Set the complementary output Polarity */
905 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
906
907 /* Set the complementary output State */
908 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
909
910 /* Set the Output Idle state */
911 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
912
913 /* Set the complementary output Idle state */
914 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
915 }
916
917 /* Write to TIMx CR2 */
918 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
919
920 /* Write to TIMx CCMR1 */
921 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
922
923 /* Set the Capture Compare Register value */
924 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
925
926 /* Write to TIMx CCER */
927 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
928
929 return SUCCESS;
930 }
931
932 /**
933 * @brief Configure the TIMx output channel 3.
934 * @param TIMx Timer Instance
935 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
936 * @retval An ErrorStatus enumeration value:
937 * - SUCCESS: TIMx registers are de-initialized
938 * - ERROR: not applicable
939 */
OC3Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)940 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
941 {
942 uint32_t tmpccmr2;
943 uint32_t tmpccer;
944 uint32_t tmpcr2;
945
946 /* Check the parameters */
947 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
948 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
949 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
950 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
951 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
952 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
953
954 /* Disable the Channel 3: Reset the CC3E Bit */
955 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
956
957 /* Get the TIMx CCER register value */
958 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
959
960 /* Get the TIMx CR2 register value */
961 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
962
963 /* Get the TIMx CCMR2 register value */
964 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
965
966 /* Reset Capture/Compare selection Bits */
967 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
968
969 /* Select the Output Compare Mode */
970 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
971
972 /* Set the Output Compare Polarity */
973 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
974
975 /* Set the Output State */
976 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
977
978 if (IS_TIM_BREAK_INSTANCE(TIMx))
979 {
980 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
981 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
982
983 /* Set the complementary output Polarity */
984 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
985
986 /* Set the complementary output State */
987 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
988
989 /* Set the Output Idle state */
990 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
991
992 /* Set the complementary output Idle state */
993 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
994 }
995
996 /* Write to TIMx CR2 */
997 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
998
999 /* Write to TIMx CCMR2 */
1000 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1001
1002 /* Set the Capture Compare Register value */
1003 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1004
1005 /* Write to TIMx CCER */
1006 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1007
1008 return SUCCESS;
1009 }
1010
1011 /**
1012 * @brief Configure the TIMx output channel 4.
1013 * @param TIMx Timer Instance
1014 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1015 * @retval An ErrorStatus enumeration value:
1016 * - SUCCESS: TIMx registers are de-initialized
1017 * - ERROR: not applicable
1018 */
OC4Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1019 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1020 {
1021 uint32_t tmpccmr2;
1022 uint32_t tmpccer;
1023 uint32_t tmpcr2;
1024
1025 /* Check the parameters */
1026 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1027 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1028 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1029 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1030 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1031 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1032
1033 /* Disable the Channel 4: Reset the CC4E Bit */
1034 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1035
1036 /* Get the TIMx CCER register value */
1037 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1038
1039 /* Get the TIMx CR2 register value */
1040 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1041
1042 /* Get the TIMx CCMR2 register value */
1043 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1044
1045 /* Reset Capture/Compare selection Bits */
1046 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1047
1048 /* Select the Output Compare Mode */
1049 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1050
1051 /* Set the Output Compare Polarity */
1052 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1053
1054 /* Set the Output State */
1055 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1056
1057 if (IS_TIM_BREAK_INSTANCE(TIMx))
1058 {
1059 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1060 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1061
1062 /* Set the Output Idle state */
1063 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1064 }
1065
1066 /* Write to TIMx CR2 */
1067 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1068
1069 /* Write to TIMx CCMR2 */
1070 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1071
1072 /* Set the Capture Compare Register value */
1073 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1074
1075 /* Write to TIMx CCER */
1076 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1077
1078 return SUCCESS;
1079 }
1080
1081 /**
1082 * @brief Configure the TIMx output channel 5.
1083 * @param TIMx Timer Instance
1084 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1085 * @retval An ErrorStatus enumeration value:
1086 * - SUCCESS: TIMx registers are de-initialized
1087 * - ERROR: not applicable
1088 */
OC5Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1089 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1090 {
1091 uint32_t tmpccmr3;
1092 uint32_t tmpccer;
1093
1094 /* Check the parameters */
1095 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1096 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1097 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1098 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1099 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1100 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1101
1102 /* Disable the Channel 5: Reset the CC5E Bit */
1103 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1104
1105 /* Get the TIMx CCER register value */
1106 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1107
1108 /* Get the TIMx CCMR3 register value */
1109 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1110
1111 /* Select the Output Compare Mode */
1112 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1113
1114 /* Set the Output Compare Polarity */
1115 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1116
1117 /* Set the Output State */
1118 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1119
1120 if (IS_TIM_BREAK_INSTANCE(TIMx))
1121 {
1122 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1123 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1124
1125 /* Set the Output Idle state */
1126 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1127
1128 }
1129
1130 /* Write to TIMx CCMR3 */
1131 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1132
1133 /* Set the Capture Compare Register value */
1134 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1135
1136 /* Write to TIMx CCER */
1137 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1138
1139 return SUCCESS;
1140 }
1141
1142 /**
1143 * @brief Configure the TIMx output channel 6.
1144 * @param TIMx Timer Instance
1145 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1146 * @retval An ErrorStatus enumeration value:
1147 * - SUCCESS: TIMx registers are de-initialized
1148 * - ERROR: not applicable
1149 */
OC6Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1150 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1151 {
1152 uint32_t tmpccmr3;
1153 uint32_t tmpccer;
1154
1155 /* Check the parameters */
1156 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1157 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1158 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1159 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1160 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1161 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1162
1163 /* Disable the Channel 5: Reset the CC6E Bit */
1164 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1165
1166 /* Get the TIMx CCER register value */
1167 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1168
1169 /* Get the TIMx CCMR3 register value */
1170 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1171
1172 /* Select the Output Compare Mode */
1173 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1174
1175 /* Set the Output Compare Polarity */
1176 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1177
1178 /* Set the Output State */
1179 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1180
1181 if (IS_TIM_BREAK_INSTANCE(TIMx))
1182 {
1183 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1184 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1185
1186 /* Set the Output Idle state */
1187 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1188 }
1189
1190 /* Write to TIMx CCMR3 */
1191 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1192
1193 /* Set the Capture Compare Register value */
1194 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1195
1196 /* Write to TIMx CCER */
1197 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1198
1199 return SUCCESS;
1200 }
1201
1202 /**
1203 * @brief Configure the TIMx input channel 1.
1204 * @param TIMx Timer Instance
1205 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1206 * @retval An ErrorStatus enumeration value:
1207 * - SUCCESS: TIMx registers are de-initialized
1208 * - ERROR: not applicable
1209 */
IC1Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1210 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1211 {
1212 /* Check the parameters */
1213 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1214 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1215 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1216 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1217 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1218
1219 /* Disable the Channel 1: Reset the CC1E Bit */
1220 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1221
1222 /* Select the Input and set the filter and the prescaler value */
1223 MODIFY_REG(TIMx->CCMR1,
1224 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1225 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1226
1227 /* Select the Polarity and set the CC1E Bit */
1228 MODIFY_REG(TIMx->CCER,
1229 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1230 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1231
1232 return SUCCESS;
1233 }
1234
1235 /**
1236 * @brief Configure the TIMx input channel 2.
1237 * @param TIMx Timer Instance
1238 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1239 * @retval An ErrorStatus enumeration value:
1240 * - SUCCESS: TIMx registers are de-initialized
1241 * - ERROR: not applicable
1242 */
IC2Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1243 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1244 {
1245 /* Check the parameters */
1246 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1247 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1248 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1249 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1250 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1251
1252 /* Disable the Channel 2: Reset the CC2E Bit */
1253 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1254
1255 /* Select the Input and set the filter and the prescaler value */
1256 MODIFY_REG(TIMx->CCMR1,
1257 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1258 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1259
1260 /* Select the Polarity and set the CC2E Bit */
1261 MODIFY_REG(TIMx->CCER,
1262 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1263 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1264
1265 return SUCCESS;
1266 }
1267
1268 /**
1269 * @brief Configure the TIMx input channel 3.
1270 * @param TIMx Timer Instance
1271 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1272 * @retval An ErrorStatus enumeration value:
1273 * - SUCCESS: TIMx registers are de-initialized
1274 * - ERROR: not applicable
1275 */
IC3Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1276 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1277 {
1278 /* Check the parameters */
1279 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1280 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1281 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1282 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1283 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1284
1285 /* Disable the Channel 3: Reset the CC3E Bit */
1286 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1287
1288 /* Select the Input and set the filter and the prescaler value */
1289 MODIFY_REG(TIMx->CCMR2,
1290 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1291 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1292
1293 /* Select the Polarity and set the CC3E Bit */
1294 MODIFY_REG(TIMx->CCER,
1295 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1296 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1297
1298 return SUCCESS;
1299 }
1300
1301 /**
1302 * @brief Configure the TIMx input channel 4.
1303 * @param TIMx Timer Instance
1304 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1305 * @retval An ErrorStatus enumeration value:
1306 * - SUCCESS: TIMx registers are de-initialized
1307 * - ERROR: not applicable
1308 */
IC4Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1309 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1310 {
1311 /* Check the parameters */
1312 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1313 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1314 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1315 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1316 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1317
1318 /* Disable the Channel 4: Reset the CC4E Bit */
1319 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1320
1321 /* Select the Input and set the filter and the prescaler value */
1322 MODIFY_REG(TIMx->CCMR2,
1323 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1324 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1325
1326 /* Select the Polarity and set the CC2E Bit */
1327 MODIFY_REG(TIMx->CCER,
1328 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1329 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1330
1331 return SUCCESS;
1332 }
1333
1334
1335 /**
1336 * @}
1337 */
1338
1339 /**
1340 * @}
1341 */
1342
1343 #endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
1344
1345 /**
1346 * @}
1347 */
1348
1349 #endif /* USE_FULL_LL_DRIVER */
1350
1351 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1352