1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_fmc.c
4 * @author MCD Application Team
5 * @brief FMC Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
9 * + Initialization/de-initialization functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### FMC peripheral features #####
16 ==============================================================================
17 [..] The Flexible memory controller (FMC) includes following memory controllers:
18 (+) The NOR/PSRAM memory controller
19 (+) The NAND memory controller
20
21 [..] The FMC functional block makes the interface with synchronous and asynchronous static
22 memories. Its main purposes are:
23 (+) to translate AHB transactions into the appropriate external device protocol
24 (+) to meet the access time requirements of the external memory devices
25
26 [..] All external memories share the addresses, data and control signals with the controller.
27 Each external device is accessed by means of a unique Chip Select. The FMC performs
28 only one access at a time to an external device.
29 The main features of the FMC controller are the following:
30 (+) Interface with static-memory mapped devices including:
31 (++) Static random access memory (SRAM)
32 (++) Read-only memory (ROM)
33 (++) NOR Flash memory/OneNAND Flash memory
34 (++) PSRAM (4 memory banks)
35 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
36 data
37 (+) Independent Chip Select control for each memory bank
38 (+) Independent configuration for each memory bank
39
40 @endverbatim
41 ******************************************************************************
42 * @attention
43 *
44 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
45 * All rights reserved.</center></h2>
46 *
47 * This software component is licensed by ST under BSD 3-Clause license,
48 * the "License"; You may not use this file except in compliance with the
49 * License. You may obtain a copy of the License at:
50 * opensource.org/licenses/BSD-3-Clause
51 *
52 ******************************************************************************
53 */
54
55 /* Includes ------------------------------------------------------------------*/
56 #include "stm32l4xx_hal.h"
57
58 /** @addtogroup STM32L4xx_HAL_Driver
59 * @{
60 */
61 #if ((defined HAL_NOR_MODULE_ENABLED || defined HAL_SRAM_MODULE_ENABLED) || defined HAL_NAND_MODULE_ENABLED )
62
63 /** @defgroup FMC_LL FMC Low Layer
64 * @brief FMC driver modules
65 * @{
66 */
67
68 /* Private typedef -----------------------------------------------------------*/
69 /* Private define ------------------------------------------------------------*/
70
71 /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
72 * @{
73 */
74
75 /* ----------------------- FMC registers bit mask --------------------------- */
76
77 #if defined FMC_BANK1
78 /* --- BCR Register ---*/
79 /* BCR register clear mask */
80
81 /* --- BTR Register ---*/
82 /* BTR register clear mask */
83 #if defined(FMC_BTRx_DATAHLD)
84 #define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\
85 FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
86 FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\
87 FMC_BTRx_ACCMOD | FMC_BTRx_DATAHLD))
88 #else
89 #define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\
90 FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
91 FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\
92 FMC_BTRx_ACCMOD))
93 #endif /* FMC_BTRx_DATAHLD */
94
95 /* --- BWTR Register ---*/
96 /* BWTR register clear mask */
97 #if defined(FMC_BWTRx_DATAHLD)
98 #if defined(FMC_BWTRx_BUSTURN)
99 #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
100 FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\
101 FMC_BWTRx_ACCMOD | FMC_BWTRx_DATAHLD))
102 #else
103 #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
104 FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD |\
105 FMC_BWTRx_DATAHLD))
106 #endif /* FMC_BWTRx_BUSTURN */
107 #else
108 #if defined(FMC_BWTRx_BUSTURN)
109 #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
110 FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\
111 FMC_BWTRx_ACCMOD))
112 #else
113 #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
114 FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD))
115 #endif /* FMC_BWTRx_BUSTURN */
116 #endif /* FMC_BWTRx_DATAHLD */
117 #endif /* FMC_BANK1 */
118 #if defined(FMC_BANK3)
119
120 /* --- PCR Register ---*/
121 /* PCR register clear mask */
122 #define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \
123 FMC_PCR_PTYP | FMC_PCR_PWID | \
124 FMC_PCR_ECCEN | FMC_PCR_TCLR | \
125 FMC_PCR_TAR | FMC_PCR_ECCPS))
126 /* --- PMEM Register ---*/
127 /* PMEM register clear mask */
128 #define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET | FMC_PMEM_MEMWAIT |\
129 FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ))
130
131 /* --- PATT Register ---*/
132 /* PATT register clear mask */
133 #define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET | FMC_PATT_ATTWAIT |\
134 FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ))
135
136 #endif /* FMC_BANK3 */
137
138 /**
139 * @}
140 */
141
142 /* Private macro -------------------------------------------------------------*/
143 /* Private variables ---------------------------------------------------------*/
144 /* Private function prototypes -----------------------------------------------*/
145 /* Exported functions --------------------------------------------------------*/
146
147 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
148 * @{
149 */
150
151 #if defined FMC_BANK1
152
153 /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
154 * @brief NORSRAM Controller functions
155 *
156 @verbatim
157 ==============================================================================
158 ##### How to use NORSRAM device driver #####
159 ==============================================================================
160
161 [..]
162 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
163 to run the NORSRAM external devices.
164
165 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
166 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
167 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
168 (+) FMC NORSRAM bank extended timing configuration using the function
169 FMC_NORSRAM_Extended_Timing_Init()
170 (+) FMC NORSRAM bank enable/disable write operation using the functions
171 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
172
173 @endverbatim
174 * @{
175 */
176
177 /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
178 * @brief Initialization and Configuration functions
179 *
180 @verbatim
181 ==============================================================================
182 ##### Initialization and de_initialization functions #####
183 ==============================================================================
184 [..]
185 This section provides functions allowing to:
186 (+) Initialize and configure the FMC NORSRAM interface
187 (+) De-initialize the FMC NORSRAM interface
188 (+) Configure the FMC clock and associated GPIOs
189
190 @endverbatim
191 * @{
192 */
193
194 /**
195 * @brief Initialize the FMC_NORSRAM device according to the specified
196 * control parameters in the FMC_NORSRAM_InitTypeDef
197 * @param Device Pointer to NORSRAM device instance
198 * @param Init Pointer to NORSRAM Initialization structure
199 * @retval HAL status
200 */
FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_InitTypeDef * Init)201 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init)
202 {
203 uint32_t flashaccess;
204 uint32_t btcr_reg;
205 uint32_t mask;
206
207 /* Check the parameters */
208 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
209 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
210 assert_param(IS_FMC_MUX(Init->DataAddressMux));
211 assert_param(IS_FMC_MEMORY(Init->MemoryType));
212 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
213 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
214 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
215 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
216 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
217 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
218 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
219 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
220 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
221 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
222 #if defined(FMC_BCR1_WFDIS)
223 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
224 #endif /* FMC_BCR1_WFDIS */
225 assert_param(IS_FMC_PAGESIZE(Init->PageSize));
226 #if defined(FMC_BCRx_NBLSET)
227 assert_param(IS_FMC_NBL_SETUPTIME(Init->NBLSetupTime));
228 #endif /* FMC_BCRx_NBLSET */
229 #if defined(FMC_PCSCNTR_CSCOUNT)
230 assert_param(IS_FUNCTIONAL_STATE(Init->MaxChipSelectPulse));
231 #endif /* FMC_PCSCNTR_CSCOUNT */
232
233 /* Disable NORSRAM Device */
234 __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
235
236 /* Set NORSRAM device control parameters */
237 if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
238 {
239 flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
240 }
241 else
242 {
243 flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
244 }
245
246 btcr_reg = (flashaccess | \
247 Init->DataAddressMux | \
248 Init->MemoryType | \
249 Init->MemoryDataWidth | \
250 Init->BurstAccessMode | \
251 Init->WaitSignalPolarity | \
252 Init->WaitSignalActive | \
253 Init->WriteOperation | \
254 Init->WaitSignal | \
255 Init->ExtendedMode | \
256 Init->AsynchronousWait | \
257 Init->WriteBurst);
258
259 btcr_reg |= Init->ContinuousClock;
260 #if defined(FMC_BCR1_WFDIS)
261 btcr_reg |= Init->WriteFifo;
262 #endif /* FMC_BCR1_WFDIS */
263 #if defined(FMC_BCRx_NBLSET)
264 btcr_reg |= Init->NBLSetupTime;
265 #endif /* FMC_BCRx_NBLSET */
266 btcr_reg |= Init->PageSize;
267
268 mask = (FMC_BCRx_MBKEN |
269 FMC_BCRx_MUXEN |
270 FMC_BCRx_MTYP |
271 FMC_BCRx_MWID |
272 FMC_BCRx_FACCEN |
273 FMC_BCRx_BURSTEN |
274 FMC_BCRx_WAITPOL |
275 FMC_BCRx_WAITCFG |
276 FMC_BCRx_WREN |
277 FMC_BCRx_WAITEN |
278 FMC_BCRx_EXTMOD |
279 FMC_BCRx_ASYNCWAIT |
280 FMC_BCRx_CBURSTRW);
281
282 mask |= FMC_BCR1_CCLKEN;
283 #if defined(FMC_BCR1_WFDIS)
284 mask |= FMC_BCR1_WFDIS;
285 #endif /* FMC_BCR1_WFDIS */
286 #if defined(FMC_BCRx_NBLSET)
287 mask |= FMC_BCRx_NBLSET;
288 #endif /* FMC_BCRx_NBLSET */
289 mask |= FMC_BCRx_CPSIZE;
290
291 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
292
293 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
294 if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
295 {
296 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
297 }
298 #if defined(FMC_BCR1_WFDIS)
299
300 if (Init->NSBank != FMC_NORSRAM_BANK1)
301 {
302 /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
303 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
304 }
305 #endif /* FMC_BCR1_WFDIS */
306 #if defined(FMC_PCSCNTR_CSCOUNT)
307
308 /* Check PSRAM chip select counter state */
309 if(Init->MaxChipSelectPulse == ENABLE)
310 {
311 /* Check the parameters */
312 assert_param(IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(Init->MaxChipSelectPulseTime));
313
314 /* Configure PSRAM chip select counter value */
315 MODIFY_REG(Device->PCSCNTR, FMC_PCSCNTR_CSCOUNT, (uint32_t)(Init->MaxChipSelectPulseTime));
316
317 /* Enable PSRAM chip select counter for the bank */
318 switch (Init->NSBank)
319 {
320 case FMC_NORSRAM_BANK1 :
321 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN);
322 break;
323
324 case FMC_NORSRAM_BANK2 :
325 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN);
326 break;
327
328 case FMC_NORSRAM_BANK3 :
329 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);
330 break;
331
332 case FMC_NORSRAM_BANK4 :
333 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);
334 break;
335
336 default :
337 break;
338 }
339 }
340 #endif /* FMC_PCSCNTR_CSCOUNT */
341
342 return HAL_OK;
343 }
344
345 /**
346 * @brief DeInitialize the FMC_NORSRAM peripheral
347 * @param Device Pointer to NORSRAM device instance
348 * @param ExDevice Pointer to NORSRAM extended mode device instance
349 * @param Bank NORSRAM bank number
350 * @retval HAL status
351 */
FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_EXTENDED_TypeDef * ExDevice,uint32_t Bank)352 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
353 {
354 /* Check the parameters */
355 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
356 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
357 assert_param(IS_FMC_NORSRAM_BANK(Bank));
358
359 /* Disable the FMC_NORSRAM device */
360 __FMC_NORSRAM_DISABLE(Device, Bank);
361
362 /* De-initialize the FMC_NORSRAM device */
363 /* FMC_NORSRAM_BANK1 */
364 if (Bank == FMC_NORSRAM_BANK1)
365 {
366 Device->BTCR[Bank] = 0x000030DBU;
367 }
368 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
369 else
370 {
371 Device->BTCR[Bank] = 0x000030D2U;
372 }
373
374 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
375 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
376 #if defined(FMC_PCSCNTR_CSCOUNT)
377
378 /* De-initialize PSRAM chip select counter */
379 switch (Bank)
380 {
381 case FMC_NORSRAM_BANK1 :
382 CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN);
383 break;
384
385 case FMC_NORSRAM_BANK2 :
386 CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN);
387 break;
388
389 case FMC_NORSRAM_BANK3 :
390 CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);
391 break;
392
393 case FMC_NORSRAM_BANK4 :
394 CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);
395 break;
396
397 default :
398 break;
399 }
400 #endif /* FMC_PCSCNTR_CSCOUNT */
401
402 return HAL_OK;
403 }
404
405 /**
406 * @brief Initialize the FMC_NORSRAM Timing according to the specified
407 * parameters in the FMC_NORSRAM_TimingTypeDef
408 * @param Device Pointer to NORSRAM device instance
409 * @param Timing Pointer to NORSRAM Timing structure
410 * @param Bank NORSRAM bank number
411 * @retval HAL status
412 */
FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank)413 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
414 {
415 uint32_t tmpr;
416
417 /* Check the parameters */
418 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
419 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
420 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
421 #if defined(FMC_BTRx_DATAHLD)
422 assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));
423 #endif /* FMC_BTRx_DATAHLD */
424 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
425 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
426 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
427 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
428 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
429 assert_param(IS_FMC_NORSRAM_BANK(Bank));
430
431 /* Set FMC_NORSRAM device timing parameters */
432 MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
433 ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) |
434 ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) |
435 #if defined(FMC_BTRx_DATAHLD)
436 ((Timing->DataHoldTime) << FMC_BTRx_DATAHLD_Pos) |
437 #endif /* FMC_BTRx_DATAHLD */
438 ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) |
439 (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) |
440 (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) |
441 (Timing->AccessMode)));
442
443 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
444 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
445 {
446 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(((uint32_t)0x0F) << FMC_BTRx_CLKDIV_Pos));
447 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos);
448 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr);
449 }
450
451 return HAL_OK;
452 }
453
454 /**
455 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
456 * parameters in the FMC_NORSRAM_TimingTypeDef
457 * @param Device Pointer to NORSRAM device instance
458 * @param Timing Pointer to NORSRAM Timing structure
459 * @param Bank NORSRAM bank number
460 * @param ExtendedMode FMC Extended Mode
461 * This parameter can be one of the following values:
462 * @arg FMC_EXTENDED_MODE_DISABLE
463 * @arg FMC_EXTENDED_MODE_ENABLE
464 * @retval HAL status
465 */
FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef * Device,FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank,uint32_t ExtendedMode)466 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
467 {
468 /* Check the parameters */
469 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
470
471 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
472 if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
473 {
474 /* Check the parameters */
475 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
476 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
477 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
478 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
479 #if defined(FMC_BTRx_DATAHLD)
480 assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));
481 #endif /* FMC_BTRx_DATAHLD */
482 #if defined(FMC_BWTRx_BUSTURN)
483 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
484 #endif /* FMC_BWTRx_BUSTURN */
485 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
486 assert_param(IS_FMC_NORSRAM_BANK(Bank));
487
488 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
489 MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
490 ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) |
491 ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) |
492 #if defined(FMC_BTRx_DATAHLD)
493 ((Timing->DataHoldTime) << FMC_BWTRx_DATAHLD_Pos) |
494 #endif /* FMC_BTRx_DATAHLD */
495 #if defined(FMC_BWTRx_BUSTURN)
496 Timing->AccessMode |
497 ((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos)));
498 #else
499 Timing->AccessMode));
500 #endif /* FMC_BWTRx_BUSTURN */
501 }
502 else
503 {
504 Device->BWTR[Bank] = 0x0FFFFFFFU;
505 }
506
507 return HAL_OK;
508 }
509 /**
510 * @}
511 */
512
513 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
514 * @brief management functions
515 *
516 @verbatim
517 ==============================================================================
518 ##### FMC_NORSRAM Control functions #####
519 ==============================================================================
520 [..]
521 This subsection provides a set of functions allowing to control dynamically
522 the FMC NORSRAM interface.
523
524 @endverbatim
525 * @{
526 */
527
528 /**
529 * @brief Enables dynamically FMC_NORSRAM write operation.
530 * @param Device Pointer to NORSRAM device instance
531 * @param Bank NORSRAM bank number
532 * @retval HAL status
533 */
FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)534 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
535 {
536 /* Check the parameters */
537 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
538 assert_param(IS_FMC_NORSRAM_BANK(Bank));
539
540 /* Enable write operation */
541 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
542
543 return HAL_OK;
544 }
545
546 /**
547 * @brief Disables dynamically FMC_NORSRAM write operation.
548 * @param Device Pointer to NORSRAM device instance
549 * @param Bank NORSRAM bank number
550 * @retval HAL status
551 */
FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)552 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
553 {
554 /* Check the parameters */
555 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
556 assert_param(IS_FMC_NORSRAM_BANK(Bank));
557
558 /* Disable write operation */
559 CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
560
561 return HAL_OK;
562 }
563
564 /**
565 * @}
566 */
567
568 /**
569 * @}
570 */
571 #endif /* FMC_BANK1 */
572
573 #if defined(FMC_BANK3)
574
575 /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
576 * @brief NAND Controller functions
577 *
578 @verbatim
579 ==============================================================================
580 ##### How to use NAND device driver #####
581 ==============================================================================
582 [..]
583 This driver contains a set of APIs to interface with the FMC NAND banks in order
584 to run the NAND external devices.
585
586 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
587 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
588 (+) FMC NAND bank common space timing configuration using the function
589 FMC_NAND_CommonSpace_Timing_Init()
590 (+) FMC NAND bank attribute space timing configuration using the function
591 FMC_NAND_AttributeSpace_Timing_Init()
592 (+) FMC NAND bank enable/disable ECC correction feature using the functions
593 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
594 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
595
596 @endverbatim
597 * @{
598 */
599
600 /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
601 * @brief Initialization and Configuration functions
602 *
603 @verbatim
604 ==============================================================================
605 ##### Initialization and de_initialization functions #####
606 ==============================================================================
607 [..]
608 This section provides functions allowing to:
609 (+) Initialize and configure the FMC NAND interface
610 (+) De-initialize the FMC NAND interface
611 (+) Configure the FMC clock and associated GPIOs
612
613 @endverbatim
614 * @{
615 */
616
617 /**
618 * @brief Initializes the FMC_NAND device according to the specified
619 * control parameters in the FMC_NAND_HandleTypeDef
620 * @param Device Pointer to NAND device instance
621 * @param Init Pointer to NAND Initialization structure
622 * @retval HAL status
623 */
FMC_NAND_Init(FMC_NAND_TypeDef * Device,FMC_NAND_InitTypeDef * Init)624 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
625 {
626 /* Check the parameters */
627 assert_param(IS_FMC_NAND_DEVICE(Device));
628 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
629 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
630 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
631 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
632 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
633 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
634 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
635
636 /* NAND bank 3 registers configuration */
637 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature |
638 FMC_PCR_MEMORY_TYPE_NAND |
639 Init->MemoryDataWidth |
640 Init->EccComputation |
641 Init->ECCPageSize |
642 ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) |
643 ((Init->TARSetupTime) << FMC_PCR_TAR_Pos)));
644
645 return HAL_OK;
646 }
647
648 /**
649 * @brief Initializes the FMC_NAND Common space Timing according to the specified
650 * parameters in the FMC_NAND_PCC_TimingTypeDef
651 * @param Device Pointer to NAND device instance
652 * @param Timing Pointer to NAND timing structure
653 * @param Bank NAND bank number
654 * @retval HAL status
655 */
FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)656 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
657 {
658 /* Check the parameters */
659 assert_param(IS_FMC_NAND_DEVICE(Device));
660 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
661 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
662 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
663 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
664 assert_param(IS_FMC_NAND_BANK(Bank));
665
666 /* Prevent unused argument(s) compilation warning if no assert_param check */
667 UNUSED(Bank);
668
669 /* NAND bank 3 registers configuration */
670 MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime |
671 ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) |
672 ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) |
673 ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)));
674
675 return HAL_OK;
676 }
677
678 /**
679 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
680 * parameters in the FMC_NAND_PCC_TimingTypeDef
681 * @param Device Pointer to NAND device instance
682 * @param Timing Pointer to NAND timing structure
683 * @param Bank NAND bank number
684 * @retval HAL status
685 */
FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)686 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
687 {
688 /* Check the parameters */
689 assert_param(IS_FMC_NAND_DEVICE(Device));
690 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
691 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
692 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
693 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
694 assert_param(IS_FMC_NAND_BANK(Bank));
695
696 /* Prevent unused argument(s) compilation warning if no assert_param check */
697 UNUSED(Bank);
698
699 /* NAND bank 3 registers configuration */
700 MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime |
701 ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) |
702 ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) |
703 ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)));
704
705 return HAL_OK;
706 }
707
708 /**
709 * @brief DeInitializes the FMC_NAND device
710 * @param Device Pointer to NAND device instance
711 * @param Bank NAND bank number
712 * @retval HAL status
713 */
FMC_NAND_DeInit(FMC_NAND_TypeDef * Device,uint32_t Bank)714 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
715 {
716 /* Check the parameters */
717 assert_param(IS_FMC_NAND_DEVICE(Device));
718 assert_param(IS_FMC_NAND_BANK(Bank));
719
720 /* Disable the NAND Bank */
721 __FMC_NAND_DISABLE(Device, Bank);
722
723 /* De-initialize the NAND Bank */
724 /* Prevent unused argument(s) compilation warning if no assert_param check */
725 UNUSED(Bank);
726
727 /* Set the FMC_NAND_BANK3 registers to their reset values */
728 WRITE_REG(Device->PCR, 0x00000018U);
729 WRITE_REG(Device->SR, 0x00000040U);
730 WRITE_REG(Device->PMEM, 0xFCFCFCFCU);
731 WRITE_REG(Device->PATT, 0xFCFCFCFCU);
732
733 return HAL_OK;
734 }
735
736 /**
737 * @}
738 */
739
740 /** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions
741 * @brief management functions
742 *
743 @verbatim
744 ==============================================================================
745 ##### FMC_NAND Control functions #####
746 ==============================================================================
747 [..]
748 This subsection provides a set of functions allowing to control dynamically
749 the FMC NAND interface.
750
751 @endverbatim
752 * @{
753 */
754
755
756 /**
757 * @brief Enables dynamically FMC_NAND ECC feature.
758 * @param Device Pointer to NAND device instance
759 * @param Bank NAND bank number
760 * @retval HAL status
761 */
FMC_NAND_ECC_Enable(FMC_NAND_TypeDef * Device,uint32_t Bank)762 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
763 {
764 /* Check the parameters */
765 assert_param(IS_FMC_NAND_DEVICE(Device));
766 assert_param(IS_FMC_NAND_BANK(Bank));
767
768 /* Enable ECC feature */
769 /* Prevent unused argument(s) compilation warning if no assert_param check */
770 UNUSED(Bank);
771
772 SET_BIT(Device->PCR, FMC_PCR_ECCEN);
773
774 return HAL_OK;
775 }
776
777
778 /**
779 * @brief Disables dynamically FMC_NAND ECC feature.
780 * @param Device Pointer to NAND device instance
781 * @param Bank NAND bank number
782 * @retval HAL status
783 */
FMC_NAND_ECC_Disable(FMC_NAND_TypeDef * Device,uint32_t Bank)784 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
785 {
786 /* Check the parameters */
787 assert_param(IS_FMC_NAND_DEVICE(Device));
788 assert_param(IS_FMC_NAND_BANK(Bank));
789
790 /* Disable ECC feature */
791 /* Prevent unused argument(s) compilation warning if no assert_param check */
792 UNUSED(Bank);
793
794 CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
795
796 return HAL_OK;
797 }
798
799 /**
800 * @brief Disables dynamically FMC_NAND ECC feature.
801 * @param Device Pointer to NAND device instance
802 * @param ECCval Pointer to ECC value
803 * @param Bank NAND bank number
804 * @param Timeout Timeout wait value
805 * @retval HAL status
806 */
FMC_NAND_GetECC(FMC_NAND_TypeDef * Device,uint32_t * ECCval,uint32_t Bank,uint32_t Timeout)807 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
808 {
809 uint32_t tickstart;
810
811 /* Check the parameters */
812 assert_param(IS_FMC_NAND_DEVICE(Device));
813 assert_param(IS_FMC_NAND_BANK(Bank));
814
815 /* Get tick */
816 tickstart = HAL_GetTick();
817
818 /* Wait until FIFO is empty */
819 while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
820 {
821 /* Check for the Timeout */
822 if (Timeout != HAL_MAX_DELAY)
823 {
824 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
825 {
826 return HAL_TIMEOUT;
827 }
828 }
829 }
830
831 /* Prevent unused argument(s) compilation warning if no assert_param check */
832 UNUSED(Bank);
833
834 /* Get the ECCR register value */
835 *ECCval = (uint32_t)Device->ECCR;
836
837 return HAL_OK;
838 }
839
840 /**
841 * @}
842 */
843 #endif /* FMC_BANK3 */
844
845
846
847 /**
848 * @}
849 */
850
851 /**
852 * @}
853 */
854
855 #endif /* HAL_NOR_MODULE_ENABLED */
856 /**
857 * @}
858 */
859
860 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
861