1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32l4xx_ll_adc.h"
23 #include "stm32l4xx_ll_bus.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif
30
31 /** @addtogroup STM32L4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
36
37 /** @addtogroup ADC_LL ADC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /** @addtogroup ADC_LL_Private_Constants
45 * @{
46 */
47
48 /* Definitions of ADC hardware constraints delays */
49 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
50 /* not timeout values: */
51 /* Timeout values for ADC operations are dependent to device clock */
52 /* configuration (system clock versus ADC clock), */
53 /* and therefore must be defined in user application. */
54 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
55 /* values definition. */
56 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
57 /* of device clock setting. */
58 /* In user application, ADC timeout values should be defined with */
59 /* temporal values, in function of device clock settings. */
60 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
61 /* - ADC clock from synchronous clock with AHB prescaler 512, */
62 /* APB prescaler 16, ADC prescaler 4. */
63 /* - ADC clock from asynchronous clock (PLLSAI) with prescaler 1, */
64 /* with highest ratio CPU clock frequency vs HSI clock frequency: */
65 /* CPU clock frequency max 72MHz, PLLSAI freq min 26MHz: ratio 4. */
66 /* Unit: CPU cycles. */
67 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
68 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
69 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
70
71 /**
72 * @}
73 */
74
75 /* Private macros ------------------------------------------------------------*/
76
77 /** @addtogroup ADC_LL_Private_Macros
78 * @{
79 */
80
81 /* Check of parameters for configuration of ADC hierarchical scope: */
82 /* common to several ADC instances. */
83 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
84 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
85 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
86 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
87 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
88 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
89 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
90 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
91 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
92 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
93 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
94 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
95 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
96 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
97 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
98 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
99 )
100
101 /* Check of parameters for configuration of ADC hierarchical scope: */
102 /* ADC instance. */
103 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
104 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
105 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
106 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
107 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
108 )
109
110 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
111 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
112 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
113 )
114
115 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
116 ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
117 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
118 )
119
120 /* Check of parameters for configuration of ADC hierarchical scope: */
121 /* ADC group regular */
122 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
123 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
124 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
125 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
126 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
127 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
128 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
129 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
130 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
131 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
132 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
133 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
134 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
135 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
136 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
137 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
138 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
139 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
140 )
141
142 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
143 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
144 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
145 )
146
147 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
148 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
149 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
150 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
151 )
152
153 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
154 ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
155 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
156 )
157
158 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
159 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
160 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
161 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
162 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
163 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
164 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
165 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
166 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
167 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
168 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
169 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
170 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
171 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
172 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
173 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
174 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
175 )
176
177 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
178 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
179 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
180 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
181 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
182 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
183 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
184 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
185 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
186 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
187 )
188
189 /* Check of parameters for configuration of ADC hierarchical scope: */
190 /* ADC group injected */
191 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
192 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
193 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
194 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
195 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
196 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
197 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
198 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
199 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
200 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
201 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
202 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
203 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
204 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
205 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
206 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
207 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
208 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
209 )
210
211 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
212 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
213 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
214 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
215 )
216
217 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
218 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
219 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
220 )
221
222 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
223 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
224 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
225 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
226 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
227 )
228
229 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
230 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
231 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
232 )
233
234 #if defined(ADC_MULTIMODE_SUPPORT)
235 /* Check of parameters for configuration of ADC hierarchical scope: */
236 /* multimode. */
237 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
238 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
239 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
240 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
241 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
242 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
243 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
244 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
245 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
246 )
247
248 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
249 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
250 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \
251 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \
252 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \
253 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B) \
254 )
255
256 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
257 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \
258 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \
259 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \
260 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \
261 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
262 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
263 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
264 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
265 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
266 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
267 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
268 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
269 )
270
271 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
272 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
273 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
274 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
275 )
276
277 #endif /* ADC_MULTIMODE_SUPPORT */
278 /**
279 * @}
280 */
281
282
283 /* Private function prototypes -----------------------------------------------*/
284
285 /* Exported functions --------------------------------------------------------*/
286 /** @addtogroup ADC_LL_Exported_Functions
287 * @{
288 */
289
290 /** @addtogroup ADC_LL_EF_Init
291 * @{
292 */
293
294 /**
295 * @brief De-initialize registers of all ADC instances belonging to
296 * the same ADC common instance to their default reset values.
297 * @note This function is performing a hard reset, using high level
298 * clock source RCC ADC reset.
299 * Caution: On this STM32 serie, if several ADC instances are available
300 * on the selected device, RCC ADC reset will reset
301 * all ADC instances belonging to the common ADC instance.
302 * To de-initialize only 1 ADC instance, use
303 * function @ref LL_ADC_DeInit().
304 * @param ADCxy_COMMON ADC common instance
305 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
306 * @retval An ErrorStatus enumeration value:
307 * - SUCCESS: ADC common registers are de-initialized
308 * - ERROR: not applicable
309 */
LL_ADC_CommonDeInit(ADC_Common_TypeDef * ADCxy_COMMON)310 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
311 {
312 /* Check the parameters */
313 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
314
315 /* Force reset of ADC clock (core clock) */
316 LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC);
317
318 /* Release reset of ADC clock (core clock) */
319 LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC);
320
321 return SUCCESS;
322 }
323
324 /**
325 * @brief Initialize some features of ADC common parameters
326 * (all ADC instances belonging to the same ADC common instance)
327 * and multimode (for devices with several ADC instances available).
328 * @note The setting of ADC common parameters is conditioned to
329 * ADC instances state:
330 * All ADC instances belonging to the same ADC common instance
331 * must be disabled.
332 * @param ADCxy_COMMON ADC common instance
333 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
334 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
335 * @retval An ErrorStatus enumeration value:
336 * - SUCCESS: ADC common registers are initialized
337 * - ERROR: ADC common registers are not initialized
338 */
LL_ADC_CommonInit(ADC_Common_TypeDef * ADCxy_COMMON,LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)339 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
340 {
341 ErrorStatus status = SUCCESS;
342
343 /* Check the parameters */
344 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
345 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
346
347 #if defined(ADC_MULTIMODE_SUPPORT)
348 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
349 if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
350 {
351 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
352 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
353 }
354 #endif /* ADC_MULTIMODE_SUPPORT */
355
356 /* Note: Hardware constraint (refer to description of functions */
357 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
358 /* On this STM32 serie, setting of these features is conditioned to */
359 /* ADC state: */
360 /* All ADC instances of the ADC common group must be disabled. */
361 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
362 {
363 /* Configuration of ADC hierarchical scope: */
364 /* - common to several ADC */
365 /* (all ADC instances belonging to the same ADC common instance) */
366 /* - Set ADC clock (conversion clock) */
367 /* - multimode (if several ADC instances available on the */
368 /* selected device) */
369 /* - Set ADC multimode configuration */
370 /* - Set ADC multimode DMA transfer */
371 /* - Set ADC multimode: delay between 2 sampling phases */
372 #if defined(ADC_MULTIMODE_SUPPORT)
373 if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
374 {
375 MODIFY_REG(ADCxy_COMMON->CCR,
376 ADC_CCR_CKMODE
377 | ADC_CCR_PRESC
378 | ADC_CCR_DUAL
379 | ADC_CCR_MDMA
380 | ADC_CCR_DELAY
381 ,
382 ADC_CommonInitStruct->CommonClock
383 | ADC_CommonInitStruct->Multimode
384 | ADC_CommonInitStruct->MultiDMATransfer
385 | ADC_CommonInitStruct->MultiTwoSamplingDelay
386 );
387 }
388 else
389 {
390 MODIFY_REG(ADCxy_COMMON->CCR,
391 ADC_CCR_CKMODE
392 | ADC_CCR_PRESC
393 | ADC_CCR_DUAL
394 | ADC_CCR_MDMA
395 | ADC_CCR_DELAY
396 ,
397 ADC_CommonInitStruct->CommonClock
398 | LL_ADC_MULTI_INDEPENDENT
399 );
400 }
401 #else
402 LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
403 #endif
404 }
405 else
406 {
407 /* Initialization error: One or several ADC instances belonging to */
408 /* the same ADC common instance are not disabled. */
409 status = ERROR;
410 }
411
412 return status;
413 }
414
415 /**
416 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
417 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
418 * whose fields will be set to default values.
419 * @retval None
420 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)421 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
422 {
423 /* Set ADC_CommonInitStruct fields to default values */
424 /* Set fields of ADC common */
425 /* (all ADC instances belonging to the same ADC common instance) */
426 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
427
428 #if defined(ADC_MULTIMODE_SUPPORT)
429 /* Set fields of ADC multimode */
430 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
431 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
432 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
433 #endif /* ADC_MULTIMODE_SUPPORT */
434 }
435
436 /**
437 * @brief De-initialize registers of the selected ADC instance
438 * to their default reset values.
439 * @note To reset all ADC instances quickly (perform a hard reset),
440 * use function @ref LL_ADC_CommonDeInit().
441 * @note If this functions returns error status, it means that ADC instance
442 * is in an unknown state.
443 * In this case, perform a hard reset using high level
444 * clock source RCC ADC reset.
445 * Caution: On this STM32 serie, if several ADC instances are available
446 * on the selected device, RCC ADC reset will reset
447 * all ADC instances belonging to the common ADC instance.
448 * Refer to function @ref LL_ADC_CommonDeInit().
449 * @param ADCx ADC instance
450 * @retval An ErrorStatus enumeration value:
451 * - SUCCESS: ADC registers are de-initialized
452 * - ERROR: ADC registers are not de-initialized
453 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)454 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
455 {
456 ErrorStatus status = SUCCESS;
457
458 __IO uint32_t timeout_cpu_cycles = 0UL;
459
460 /* Check the parameters */
461 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
462
463 /* Disable ADC instance if not already disabled. */
464 if (LL_ADC_IsEnabled(ADCx) == 1UL)
465 {
466 /* Set ADC group regular trigger source to SW start to ensure to not */
467 /* have an external trigger event occurring during the conversion stop */
468 /* ADC disable process. */
469 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
470
471 /* Stop potential ADC conversion on going on ADC group regular. */
472 if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
473 {
474 if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
475 {
476 LL_ADC_REG_StopConversion(ADCx);
477 }
478 }
479
480 /* Set ADC group injected trigger source to SW start to ensure to not */
481 /* have an external trigger event occurring during the conversion stop */
482 /* ADC disable process. */
483 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
484
485 /* Stop potential ADC conversion on going on ADC group injected. */
486 if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
487 {
488 if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
489 {
490 LL_ADC_INJ_StopConversion(ADCx);
491 }
492 }
493
494 /* Wait for ADC conversions are effectively stopped */
495 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
496 while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
497 | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
498 {
499 timeout_cpu_cycles--;
500 if (timeout_cpu_cycles == 0UL)
501 {
502 /* Time-out error */
503 status = ERROR;
504 break;
505 }
506 }
507
508 /* Flush group injected contexts queue (register JSQR): */
509 /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
510 /* contexts queue is maintained with the last active context). */
511 LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
512
513 /* Disable the ADC instance */
514 LL_ADC_Disable(ADCx);
515
516 /* Wait for ADC instance is effectively disabled */
517 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
518 while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
519 {
520 timeout_cpu_cycles--;
521 if (timeout_cpu_cycles == 0UL)
522 {
523 /* Time-out error */
524 status = ERROR;
525 break;
526 }
527 }
528 }
529
530 /* Check whether ADC state is compliant with expected state */
531 if (READ_BIT(ADCx->CR,
532 (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
533 | ADC_CR_ADDIS | ADC_CR_ADEN)
534 )
535 == 0UL)
536 {
537 /* ========== Reset ADC registers ========== */
538 /* Reset register IER */
539 CLEAR_BIT(ADCx->IER,
540 (LL_ADC_IT_ADRDY
541 | LL_ADC_IT_EOC
542 | LL_ADC_IT_EOS
543 | LL_ADC_IT_OVR
544 | LL_ADC_IT_EOSMP
545 | LL_ADC_IT_JEOC
546 | LL_ADC_IT_JEOS
547 | LL_ADC_IT_JQOVF
548 | LL_ADC_IT_AWD1
549 | LL_ADC_IT_AWD2
550 | LL_ADC_IT_AWD3
551 )
552 );
553
554 /* Reset register ISR */
555 SET_BIT(ADCx->ISR,
556 (LL_ADC_FLAG_ADRDY
557 | LL_ADC_FLAG_EOC
558 | LL_ADC_FLAG_EOS
559 | LL_ADC_FLAG_OVR
560 | LL_ADC_FLAG_EOSMP
561 | LL_ADC_FLAG_JEOC
562 | LL_ADC_FLAG_JEOS
563 | LL_ADC_FLAG_JQOVF
564 | LL_ADC_FLAG_AWD1
565 | LL_ADC_FLAG_AWD2
566 | LL_ADC_FLAG_AWD3
567 )
568 );
569
570 /* Reset register CR */
571 /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
572 /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
573 /* access mode "read-set": no direct reset applicable. */
574 /* - Reset Calibration mode to default setting (single ended). */
575 /* - Disable ADC internal voltage regulator. */
576 /* - Enable ADC deep power down. */
577 /* Note: ADC internal voltage regulator disable and ADC deep power */
578 /* down enable are conditioned to ADC state disabled: */
579 /* already done above. */
580 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
581 SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
582
583 /* Reset register CFGR */
584 MODIFY_REG(ADCx->CFGR,
585 (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
586 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
587 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
588 | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
589 | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN
590 | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN),
591 ADC_CFGR_JQDIS
592 );
593
594 /* Reset register CFGR2 */
595 CLEAR_BIT(ADCx->CFGR2,
596 (ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS
597 | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
598 );
599
600 /* Reset register SMPR1 */
601 CLEAR_BIT(ADCx->SMPR1,
602 (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
603 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
604 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
605 );
606
607 /* Reset register SMPR2 */
608 CLEAR_BIT(ADCx->SMPR2,
609 (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
610 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
611 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
612 );
613
614 /* Reset register TR1 */
615 MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
616
617 /* Reset register TR2 */
618 MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
619
620 /* Reset register TR3 */
621 MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
622
623 /* Reset register SQR1 */
624 CLEAR_BIT(ADCx->SQR1,
625 (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
626 | ADC_SQR1_SQ1 | ADC_SQR1_L)
627 );
628
629 /* Reset register SQR2 */
630 CLEAR_BIT(ADCx->SQR2,
631 (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
632 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
633 );
634
635 /* Reset register SQR3 */
636 CLEAR_BIT(ADCx->SQR3,
637 (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
638 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
639 );
640
641 /* Reset register SQR4 */
642 CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
643
644 /* Reset register JSQR */
645 CLEAR_BIT(ADCx->JSQR,
646 (ADC_JSQR_JL
647 | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
648 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
649 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1)
650 );
651
652 /* Reset register DR */
653 /* Note: bits in access mode read only, no direct reset applicable */
654
655 /* Reset register OFR1 */
656 CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
657 /* Reset register OFR2 */
658 CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
659 /* Reset register OFR3 */
660 CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
661 /* Reset register OFR4 */
662 CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
663
664 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
665 /* Note: bits in access mode read only, no direct reset applicable */
666
667 /* Reset register AWD2CR */
668 CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
669
670 /* Reset register AWD3CR */
671 CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
672
673 /* Reset register DIFSEL */
674 CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
675
676 /* Reset register CALFACT */
677 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
678 }
679 else
680 {
681 /* ADC instance is in an unknown state */
682 /* Need to performing a hard reset of ADC instance, using high level */
683 /* clock source RCC ADC reset. */
684 /* Caution: On this STM32 serie, if several ADC instances are available */
685 /* on the selected device, RCC ADC reset will reset */
686 /* all ADC instances belonging to the common ADC instance. */
687 /* Caution: On this STM32 serie, if several ADC instances are available */
688 /* on the selected device, RCC ADC reset will reset */
689 /* all ADC instances belonging to the common ADC instance. */
690 status = ERROR;
691 }
692
693 return status;
694 }
695
696 /**
697 * @brief Initialize some features of ADC instance.
698 * @note These parameters have an impact on ADC scope: ADC instance.
699 * Affects both group regular and group injected (availability
700 * of ADC group injected depends on STM32 families).
701 * Refer to corresponding unitary functions into
702 * @ref ADC_LL_EF_Configuration_ADC_Instance .
703 * @note The setting of these parameters by function @ref LL_ADC_Init()
704 * is conditioned to ADC state:
705 * ADC instance must be disabled.
706 * This condition is applied to all ADC features, for efficiency
707 * and compatibility over all STM32 families. However, the different
708 * features can be set under different ADC state conditions
709 * (setting possible with ADC enabled without conversion on going,
710 * ADC enabled with conversion on going, ...)
711 * Each feature can be updated afterwards with a unitary function
712 * and potentially with ADC in a different state than disabled,
713 * refer to description of each function for setting
714 * conditioned to ADC state.
715 * @note After using this function, some other features must be configured
716 * using LL unitary functions.
717 * The minimum configuration remaining to be done is:
718 * - Set ADC group regular or group injected sequencer:
719 * map channel on the selected sequencer rank.
720 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
721 * - Set ADC channel sampling time
722 * Refer to function LL_ADC_SetChannelSamplingTime();
723 * @param ADCx ADC instance
724 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
725 * @retval An ErrorStatus enumeration value:
726 * - SUCCESS: ADC registers are initialized
727 * - ERROR: ADC registers are not initialized
728 */
LL_ADC_Init(ADC_TypeDef * ADCx,LL_ADC_InitTypeDef * ADC_InitStruct)729 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
730 {
731 ErrorStatus status = SUCCESS;
732
733 /* Check the parameters */
734 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
735
736 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
737 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
738 assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
739
740 /* Note: Hardware constraint (refer to description of this function): */
741 /* ADC instance must be disabled. */
742 if (LL_ADC_IsEnabled(ADCx) == 0UL)
743 {
744 /* Configuration of ADC hierarchical scope: */
745 /* - ADC instance */
746 /* - Set ADC data resolution */
747 /* - Set ADC conversion data alignment */
748 /* - Set ADC low power mode */
749 MODIFY_REG(ADCx->CFGR,
750 ADC_CFGR_RES
751 | ADC_CFGR_ALIGN
752 | ADC_CFGR_AUTDLY
753 ,
754 ADC_InitStruct->Resolution
755 | ADC_InitStruct->DataAlignment
756 | ADC_InitStruct->LowPowerMode
757 );
758
759 }
760 else
761 {
762 /* Initialization error: ADC instance is not disabled. */
763 status = ERROR;
764 }
765 return status;
766 }
767
768 /**
769 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
770 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
771 * whose fields will be set to default values.
772 * @retval None
773 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * ADC_InitStruct)774 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
775 {
776 /* Set ADC_InitStruct fields to default values */
777 /* Set fields of ADC instance */
778 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
779 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
780 ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
781
782 }
783
784 /**
785 * @brief Initialize some features of ADC group regular.
786 * @note These parameters have an impact on ADC scope: ADC group regular.
787 * Refer to corresponding unitary functions into
788 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
789 * (functions with prefix "REG").
790 * @note The setting of these parameters by function @ref LL_ADC_Init()
791 * is conditioned to ADC state:
792 * ADC instance must be disabled.
793 * This condition is applied to all ADC features, for efficiency
794 * and compatibility over all STM32 families. However, the different
795 * features can be set under different ADC state conditions
796 * (setting possible with ADC enabled without conversion on going,
797 * ADC enabled with conversion on going, ...)
798 * Each feature can be updated afterwards with a unitary function
799 * and potentially with ADC in a different state than disabled,
800 * refer to description of each function for setting
801 * conditioned to ADC state.
802 * @note After using this function, other features must be configured
803 * using LL unitary functions.
804 * The minimum configuration remaining to be done is:
805 * - Set ADC group regular or group injected sequencer:
806 * map channel on the selected sequencer rank.
807 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
808 * - Set ADC channel sampling time
809 * Refer to function LL_ADC_SetChannelSamplingTime();
810 * @param ADCx ADC instance
811 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
812 * @retval An ErrorStatus enumeration value:
813 * - SUCCESS: ADC registers are initialized
814 * - ERROR: ADC registers are not initialized
815 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)816 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
817 {
818 ErrorStatus status = SUCCESS;
819
820 /* Check the parameters */
821 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
822 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
823 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
824 if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
825 {
826 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
827 }
828 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
829 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
830 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
831
832 /* Note: Hardware constraint (refer to description of this function): */
833 /* ADC instance must be disabled. */
834 if (LL_ADC_IsEnabled(ADCx) == 0UL)
835 {
836 /* Configuration of ADC hierarchical scope: */
837 /* - ADC group regular */
838 /* - Set ADC group regular trigger source */
839 /* - Set ADC group regular sequencer length */
840 /* - Set ADC group regular sequencer discontinuous mode */
841 /* - Set ADC group regular continuous mode */
842 /* - Set ADC group regular conversion data transfer: no transfer or */
843 /* transfer by DMA, and DMA requests mode */
844 /* - Set ADC group regular overrun behavior */
845 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
846 /* setting of trigger source to SW start. */
847 if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
848 {
849 MODIFY_REG(ADCx->CFGR,
850 ADC_CFGR_EXTSEL
851 | ADC_CFGR_EXTEN
852 | ADC_CFGR_DISCEN
853 | ADC_CFGR_DISCNUM
854 | ADC_CFGR_CONT
855 | ADC_CFGR_DMAEN
856 | ADC_CFGR_DMACFG
857 | ADC_CFGR_OVRMOD
858 ,
859 ADC_REG_InitStruct->TriggerSource
860 | ADC_REG_InitStruct->SequencerDiscont
861 | ADC_REG_InitStruct->ContinuousMode
862 | ADC_REG_InitStruct->DMATransfer
863 | ADC_REG_InitStruct->Overrun
864 );
865 }
866 else
867 {
868 MODIFY_REG(ADCx->CFGR,
869 ADC_CFGR_EXTSEL
870 | ADC_CFGR_EXTEN
871 | ADC_CFGR_DISCEN
872 | ADC_CFGR_DISCNUM
873 | ADC_CFGR_CONT
874 | ADC_CFGR_DMAEN
875 | ADC_CFGR_DMACFG
876 | ADC_CFGR_OVRMOD
877 ,
878 ADC_REG_InitStruct->TriggerSource
879 | LL_ADC_REG_SEQ_DISCONT_DISABLE
880 | ADC_REG_InitStruct->ContinuousMode
881 | ADC_REG_InitStruct->DMATransfer
882 | ADC_REG_InitStruct->Overrun
883 );
884 }
885
886 /* Set ADC group regular sequencer length and scan direction */
887 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
888 }
889 else
890 {
891 /* Initialization error: ADC instance is not disabled. */
892 status = ERROR;
893 }
894 return status;
895 }
896
897 /**
898 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
899 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
900 * whose fields will be set to default values.
901 * @retval None
902 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)903 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
904 {
905 /* Set ADC_REG_InitStruct fields to default values */
906 /* Set fields of ADC group regular */
907 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
908 /* setting of trigger source to SW start. */
909 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
910 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
911 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
912 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
913 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
914 ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
915 }
916
917 /**
918 * @brief Initialize some features of ADC group injected.
919 * @note These parameters have an impact on ADC scope: ADC group injected.
920 * Refer to corresponding unitary functions into
921 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
922 * (functions with prefix "INJ").
923 * @note The setting of these parameters by function @ref LL_ADC_Init()
924 * is conditioned to ADC state:
925 * ADC instance must be disabled.
926 * This condition is applied to all ADC features, for efficiency
927 * and compatibility over all STM32 families. However, the different
928 * features can be set under different ADC state conditions
929 * (setting possible with ADC enabled without conversion on going,
930 * ADC enabled with conversion on going, ...)
931 * Each feature can be updated afterwards with a unitary function
932 * and potentially with ADC in a different state than disabled,
933 * refer to description of each function for setting
934 * conditioned to ADC state.
935 * @note After using this function, other features must be configured
936 * using LL unitary functions.
937 * The minimum configuration remaining to be done is:
938 * - Set ADC group injected sequencer:
939 * map channel on the selected sequencer rank.
940 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
941 * - Set ADC channel sampling time
942 * Refer to function LL_ADC_SetChannelSamplingTime();
943 * @param ADCx ADC instance
944 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
945 * @retval An ErrorStatus enumeration value:
946 * - SUCCESS: ADC registers are initialized
947 * - ERROR: ADC registers are not initialized
948 */
LL_ADC_INJ_Init(ADC_TypeDef * ADCx,LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct)949 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
950 {
951 ErrorStatus status = SUCCESS;
952
953 /* Check the parameters */
954 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
955 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
956 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
957 if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
958 {
959 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
960 }
961 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
962
963 /* Note: Hardware constraint (refer to description of this function): */
964 /* ADC instance must be disabled. */
965 if (LL_ADC_IsEnabled(ADCx) == 0UL)
966 {
967 /* Configuration of ADC hierarchical scope: */
968 /* - ADC group injected */
969 /* - Set ADC group injected trigger source */
970 /* - Set ADC group injected sequencer length */
971 /* - Set ADC group injected sequencer discontinuous mode */
972 /* - Set ADC group injected conversion trigger: independent or */
973 /* from ADC group regular */
974 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
975 /* setting of trigger source to SW start. */
976 if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
977 {
978 MODIFY_REG(ADCx->CFGR,
979 ADC_CFGR_JDISCEN
980 | ADC_CFGR_JAUTO
981 ,
982 ADC_INJ_InitStruct->SequencerDiscont
983 | ADC_INJ_InitStruct->TrigAuto
984 );
985 }
986 else
987 {
988 MODIFY_REG(ADCx->CFGR,
989 ADC_CFGR_JDISCEN
990 | ADC_CFGR_JAUTO
991 ,
992 LL_ADC_REG_SEQ_DISCONT_DISABLE
993 | ADC_INJ_InitStruct->TrigAuto
994 );
995 }
996
997 MODIFY_REG(ADCx->JSQR,
998 ADC_JSQR_JEXTSEL
999 | ADC_JSQR_JEXTEN
1000 | ADC_JSQR_JL
1001 ,
1002 ADC_INJ_InitStruct->TriggerSource
1003 | ADC_INJ_InitStruct->SequencerLength
1004 );
1005 }
1006 else
1007 {
1008 /* Initialization error: ADC instance is not disabled. */
1009 status = ERROR;
1010 }
1011 return status;
1012 }
1013
1014 /**
1015 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
1016 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1017 * whose fields will be set to default values.
1018 * @retval None
1019 */
LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct)1020 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1021 {
1022 /* Set ADC_INJ_InitStruct fields to default values */
1023 /* Set fields of ADC group injected */
1024 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
1025 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
1026 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
1027 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
1028 }
1029
1030 /**
1031 * @}
1032 */
1033
1034 /**
1035 * @}
1036 */
1037
1038 /**
1039 * @}
1040 */
1041
1042 #endif /* ADC1 || ADC2 || ADC3 */
1043
1044 /**
1045 * @}
1046 */
1047
1048 #endif /* USE_FULL_LL_DRIVER */
1049
1050 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1051