1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_dma2d.c
4 * @author MCD Application Team
5 * @brief DMA2D HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the DMA2D peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State and Errors functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### How to use this driver #####
16 ==============================================================================
17 [..]
18 (#) Program the required configuration through the following parameters:
19 the transfer mode, the output color mode and the output offset using
20 HAL_DMA2D_Init() function.
21
22 (#) Program the required configuration through the following parameters:
23 the input color mode, the input color, the input alpha value, the alpha mode,
24 the red/blue swap mode, the inverted alpha mode and the input offset using
25 HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.
26
27 *** Polling mode IO operation ***
28 =================================
29 [..]
30 (#) Configure pdata parameter (explained hereafter), destination and data length
31 and enable the transfer using HAL_DMA2D_Start().
32 (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
33 user can specify the value of timeout according to his end application.
34
35 *** Interrupt mode IO operation ***
36 ===================================
37 [..]
38 (#) Configure pdata parameter, destination and data length and enable
39 the transfer using HAL_DMA2D_Start_IT().
40 (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
41 (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
42 add his own function by customization of function pointer XferCpltCallback (member
43 of DMA2D handle structure).
44 (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback
45 XferErrorCallback.
46
47 -@- In Register-to-Memory transfer mode, pdata parameter is the register
48 color, in Memory-to-memory or Memory-to-Memory with pixel format
49 conversion pdata is the source address.
50
51 -@- Configure the foreground source address, the background source address,
52 the destination and data length then Enable the transfer using
53 HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
54 in interrupt mode.
55
56 -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
57 are used if the memory to memory with blending transfer mode is selected.
58
59 (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
60 mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
61
62 (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent().
63
64 (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
65 consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
66 and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or
67 HAL_DMA2D_DisableDeadTime().
68
69 (#) The transfer can be suspended, resumed and aborted using the following
70 functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
71
72 (#) The CLUT loading can be suspended, resumed and aborted using the following
73 functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
74 HAL_DMA2D_CLUTLoading_Abort().
75
76 (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
77
78 (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
79
80 *** DMA2D HAL driver macros list ***
81 =============================================
82 [..]
83 Below the list of most used macros in DMA2D HAL driver :
84
85 (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
86 (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
87 (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
88 (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
89 (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
90 (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.
91
92 *** Callback registration ***
93 ===================================
94 [..]
95 (#) The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1
96 allows the user to configure dynamically the driver callbacks.
97 Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback.
98
99 (#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks:
100 (+) XferCpltCallback : callback for transfer complete.
101 (+) XferErrorCallback : callback for transfer error.
102 (+) LineEventCallback : callback for line event.
103 (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
104 (+) MspInitCallback : DMA2D MspInit.
105 (+) MspDeInitCallback : DMA2D MspDeInit.
106 This function takes as parameters the HAL peripheral handle, the Callback ID
107 and a pointer to the user callback function.
108
109 (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default
110 weak (surcharged) function.
111 @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
112 and the Callback ID.
113 This function allows to reset following callbacks:
114 (+) XferCpltCallback : callback for transfer complete.
115 (+) XferErrorCallback : callback for transfer error.
116 (+) LineEventCallback : callback for line event.
117 (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
118 (+) MspInitCallback : DMA2D MspInit.
119 (+) MspDeInitCallback : DMA2D MspDeInit.
120
121 (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET
122 all callbacks are reset to the corresponding legacy weak (surcharged) functions:
123 examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback()
124 Exception done for MspInit and MspDeInit callbacks that are respectively
125 reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init
126 and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand)
127 If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit
128 keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
129
130 Exception as well for Transfer Completion and Transfer Error callbacks that are not defined
131 as weak (surcharged) functions. They must be defined by the user to be resorted to.
132
133 Callbacks can be registered/unregistered in READY state only.
134 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
135 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
136 during the Init/DeInit.
137 In that case first register the MspInit/MspDeInit user callbacks
138 using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit
139 or @ref HAL_DMA2D_Init function.
140
141 When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or
142 not defined, the callback registering feature is not available
143 and weak (surcharged) callbacks are used.
144
145 [..]
146 (@) You can refer to the DMA2D HAL driver header file for more useful macros
147
148 @endverbatim
149 ******************************************************************************
150 * @attention
151 *
152 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
153 * All rights reserved.</center></h2>
154 *
155 * This software component is licensed by ST under BSD 3-Clause license,
156 * the "License"; You may not use this file except in compliance with the
157 * License. You may obtain a copy of the License at:
158 * opensource.org/licenses/BSD-3-Clause
159 *
160 ******************************************************************************
161 */
162
163 /* Includes ------------------------------------------------------------------*/
164 #include "stm32l4xx_hal.h"
165
166 #ifdef HAL_DMA2D_MODULE_ENABLED
167 #if defined (DMA2D)
168
169 /** @addtogroup STM32L4xx_HAL_Driver
170 * @{
171 */
172
173 /** @defgroup DMA2D DMA2D
174 * @brief DMA2D HAL module driver
175 * @{
176 */
177
178 /* Private types -------------------------------------------------------------*/
179 /* Private define ------------------------------------------------------------*/
180 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
181 * @{
182 */
183
184 /** @defgroup DMA2D_TimeOut DMA2D Time Out
185 * @{
186 */
187 #define DMA2D_TIMEOUT_ABORT (1000U) /*!< 1s */
188 #define DMA2D_TIMEOUT_SUSPEND (1000U) /*!< 1s */
189 /**
190 * @}
191 */
192
193 /**
194 * @}
195 */
196
197 /* Private variables ---------------------------------------------------------*/
198 /* Private constants ---------------------------------------------------------*/
199 /* Private macro -------------------------------------------------------------*/
200 /* Private function prototypes -----------------------------------------------*/
201 /** @addtogroup DMA2D_Private_Functions DMA2D Private Functions
202 * @{
203 */
204 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
205 /**
206 * @}
207 */
208
209 /* Private functions ---------------------------------------------------------*/
210 /* Exported functions --------------------------------------------------------*/
211 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
212 * @{
213 */
214
215 /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
216 * @brief Initialization and Configuration functions
217 *
218 @verbatim
219 ===============================================================================
220 ##### Initialization and Configuration functions #####
221 ===============================================================================
222 [..] This section provides functions allowing to:
223 (+) Initialize and configure the DMA2D
224 (+) De-initialize the DMA2D
225
226 @endverbatim
227 * @{
228 */
229
230 /**
231 * @brief Initialize the DMA2D according to the specified
232 * parameters in the DMA2D_InitTypeDef and create the associated handle.
233 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
234 * the configuration information for the DMA2D.
235 * @retval HAL status
236 */
HAL_DMA2D_Init(DMA2D_HandleTypeDef * hdma2d)237 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
238 {
239 /* Check the DMA2D peripheral state */
240 if(hdma2d == NULL)
241 {
242 return HAL_ERROR;
243 }
244
245 /* Check the parameters */
246 assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
247 assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
248 assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
249 assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
250 assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->Init.AlphaInverted));
251 assert_param(IS_DMA2D_RB_SWAP(hdma2d->Init.RedBlueSwap));
252 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
253 assert_param(IS_DMA2D_LOM_MODE(hdma2d->Init.LineOffsetMode));
254 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
255 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
256 assert_param(IS_DMA2D_BYTES_SWAP(hdma2d->Init.BytesSwap));
257 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
258
259 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
260 if (hdma2d->State == HAL_DMA2D_STATE_RESET)
261 {
262 /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */
263 hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
264 hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
265 if(hdma2d->MspInitCallback == NULL)
266 {
267 hdma2d->MspInitCallback = HAL_DMA2D_MspInit;
268 }
269
270 /* Init the low level hardware */
271 hdma2d->MspInitCallback(hdma2d);
272 }
273 #else
274 if(hdma2d->State == HAL_DMA2D_STATE_RESET)
275 {
276 /* Allocate lock resource and initialize it */
277 hdma2d->Lock = HAL_UNLOCKED;
278 /* Init the low level hardware */
279 HAL_DMA2D_MspInit(hdma2d);
280 }
281 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
282
283 /* Change DMA2D peripheral state */
284 hdma2d->State = HAL_DMA2D_STATE_BUSY;
285
286 /* DMA2D CR register configuration -------------------------------------------*/
287 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
288 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE | DMA2D_CR_LOM, hdma2d->Init.Mode | hdma2d->Init.LineOffsetMode);
289 #else
290 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
291 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
292
293 /* DMA2D OPFCCR register configuration ---------------------------------------*/
294 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
295 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB, hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap);
296 #else
297 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
298 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
299
300 /* DMA2D OOR register configuration ------------------------------------------*/
301 MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
302 /* DMA2D OPFCCR AI and RBS fields setting (Output Alpha Inversion)*/
303 MODIFY_REG(hdma2d->Instance->OPFCCR,(DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos)));
304
305
306 /* Update error code */
307 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
308
309 /* Initialize the DMA2D state*/
310 hdma2d->State = HAL_DMA2D_STATE_READY;
311
312 return HAL_OK;
313 }
314
315 /**
316 * @brief Deinitializes the DMA2D peripheral registers to their default reset
317 * values.
318 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
319 * the configuration information for the DMA2D.
320 * @retval None
321 */
322
HAL_DMA2D_DeInit(DMA2D_HandleTypeDef * hdma2d)323 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
324 {
325
326 /* Check the DMA2D peripheral state */
327 if(hdma2d == NULL)
328 {
329 return HAL_ERROR;
330 }
331
332 /* Before aborting any DMA2D transfer or CLUT loading, check
333 first whether or not DMA2D clock is enabled */
334 if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
335 {
336 /* Abort DMA2D transfer if any */
337 if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
338 {
339 if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
340 {
341 /* Issue when aborting DMA2D transfer */
342 return HAL_ERROR;
343 }
344 }
345 else
346 {
347 /* Abort background CLUT loading if any */
348 if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
349 {
350 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
351 {
352 /* Issue when aborting background CLUT loading */
353 return HAL_ERROR;
354 }
355 }
356 else
357 {
358 /* Abort foreground CLUT loading if any */
359 if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
360 {
361 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
362 {
363 /* Issue when aborting foreground CLUT loading */
364 return HAL_ERROR;
365 }
366 }
367 }
368 }
369 }
370
371 /* Reset DMA2D control registers*/
372 hdma2d->Instance->CR = 0U;
373 hdma2d->Instance->IFCR = 0x3FU;
374 hdma2d->Instance->FGOR = 0U;
375 hdma2d->Instance->BGOR = 0U;
376 hdma2d->Instance->FGPFCCR = 0U;
377 hdma2d->Instance->BGPFCCR = 0U;
378 hdma2d->Instance->OPFCCR = 0U;
379
380 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
381
382 if(hdma2d->MspDeInitCallback == NULL)
383 {
384 hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;
385 }
386
387 /* DeInit the low level hardware */
388 hdma2d->MspDeInitCallback(hdma2d);
389
390 #else
391 /* Carry on with de-initialization of low level hardware */
392 HAL_DMA2D_MspDeInit(hdma2d);
393 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
394
395 /* Update error code */
396 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
397
398 /* Initialize the DMA2D state*/
399 hdma2d->State = HAL_DMA2D_STATE_RESET;
400
401 /* Release Lock */
402 __HAL_UNLOCK(hdma2d);
403
404 return HAL_OK;
405 }
406
407 /**
408 * @brief Initializes the DMA2D MSP.
409 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
410 * the configuration information for the DMA2D.
411 * @retval None
412 */
HAL_DMA2D_MspInit(DMA2D_HandleTypeDef * hdma2d)413 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
414 {
415 /* Prevent unused argument(s) compilation warning */
416 UNUSED(hdma2d);
417
418 /* NOTE : This function should not be modified; when the callback is needed,
419 the HAL_DMA2D_MspInit can be implemented in the user file.
420 */
421 }
422
423 /**
424 * @brief DeInitializes the DMA2D MSP.
425 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
426 * the configuration information for the DMA2D.
427 * @retval None
428 */
HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef * hdma2d)429 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
430 {
431 /* Prevent unused argument(s) compilation warning */
432 UNUSED(hdma2d);
433
434 /* NOTE : This function should not be modified; when the callback is needed,
435 the HAL_DMA2D_MspDeInit can be implemented in the user file.
436 */
437 }
438
439 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
440 /**
441 * @brief Register a User DMA2D Callback
442 * To be used instead of the weak (surcharged) predefined callback
443 * @param hdma2d DMA2D handle
444 * @param CallbackID ID of the callback to be registered
445 * This parameter can be one of the following values:
446 * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
447 * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
448 * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
449 * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
450 * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
451 * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
452 * @param pCallback pointer to the Callback function
453 * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
454 * @retval status
455 */
HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef * hdma2d,HAL_DMA2D_CallbackIDTypeDef CallbackID,pDMA2D_CallbackTypeDef pCallback)456 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback)
457 {
458 HAL_StatusTypeDef status = HAL_OK;
459
460 if(pCallback == NULL)
461 {
462 /* Update the error code */
463 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
464 return HAL_ERROR;
465 }
466 /* Process locked */
467 __HAL_LOCK(hdma2d);
468
469 if(HAL_DMA2D_STATE_READY == hdma2d->State)
470 {
471 switch (CallbackID)
472 {
473 case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
474 hdma2d->XferCpltCallback = pCallback;
475 break;
476
477 case HAL_DMA2D_TRANSFERERROR_CB_ID :
478 hdma2d->XferErrorCallback = pCallback;
479 break;
480
481 case HAL_DMA2D_LINEEVENT_CB_ID :
482 hdma2d->LineEventCallback = pCallback;
483 break;
484
485 case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
486 hdma2d->CLUTLoadingCpltCallback = pCallback;
487 break;
488
489 case HAL_DMA2D_MSPINIT_CB_ID :
490 hdma2d->MspInitCallback = pCallback;
491 break;
492
493 case HAL_DMA2D_MSPDEINIT_CB_ID :
494 hdma2d->MspDeInitCallback = pCallback;
495 break;
496
497 default :
498 /* Update the error code */
499 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
500 /* update return status */
501 status = HAL_ERROR;
502 break;
503 }
504 }
505 else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
506 {
507 switch (CallbackID)
508 {
509 case HAL_DMA2D_MSPINIT_CB_ID :
510 hdma2d->MspInitCallback = pCallback;
511 break;
512
513 case HAL_DMA2D_MSPDEINIT_CB_ID :
514 hdma2d->MspDeInitCallback = pCallback;
515 break;
516
517 default :
518 /* Update the error code */
519 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
520 /* update return status */
521 status = HAL_ERROR;
522 break;
523 }
524 }
525 else
526 {
527 /* Update the error code */
528 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
529 /* update return status */
530 status = HAL_ERROR;
531 }
532
533 /* Release Lock */
534 __HAL_UNLOCK(hdma2d);
535 return status;
536 }
537
538 /**
539 * @brief Unregister a DMA2D Callback
540 * DMA2D Callback is redirected to the weak (surcharged) predefined callback
541 * @param hdma2d DMA2D handle
542 * @param CallbackID ID of the callback to be unregistered
543 * This parameter can be one of the following values:
544 * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
545 * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
546 * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
547 * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
548 * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
549 * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
550 * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
551 * @retval status
552 */
HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef * hdma2d,HAL_DMA2D_CallbackIDTypeDef CallbackID)553 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID)
554 {
555 HAL_StatusTypeDef status = HAL_OK;
556
557 /* Process locked */
558 __HAL_LOCK(hdma2d);
559
560 if(HAL_DMA2D_STATE_READY == hdma2d->State)
561 {
562 switch (CallbackID)
563 {
564 case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
565 hdma2d->XferCpltCallback = NULL;
566 break;
567
568 case HAL_DMA2D_TRANSFERERROR_CB_ID :
569 hdma2d->XferErrorCallback = NULL;
570 break;
571
572 case HAL_DMA2D_LINEEVENT_CB_ID :
573 hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
574 break;
575
576 case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
577 hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
578 break;
579
580 case HAL_DMA2D_MSPINIT_CB_ID :
581 hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
582 break;
583
584 case HAL_DMA2D_MSPDEINIT_CB_ID :
585 hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
586 break;
587
588 default :
589 /* Update the error code */
590 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
591 /* update return status */
592 status = HAL_ERROR;
593 break;
594 }
595 }
596 else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
597 {
598 switch (CallbackID)
599 {
600 case HAL_DMA2D_MSPINIT_CB_ID :
601 hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
602 break;
603
604 case HAL_DMA2D_MSPDEINIT_CB_ID :
605 hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
606 break;
607
608 default :
609 /* Update the error code */
610 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
611 /* update return status */
612 status = HAL_ERROR;
613 break;
614 }
615 }
616 else
617 {
618 /* Update the error code */
619 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
620 /* update return status */
621 status = HAL_ERROR;
622 }
623
624 /* Release Lock */
625 __HAL_UNLOCK(hdma2d);
626 return status;
627 }
628 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
629
630 /**
631 * @}
632 */
633
634
635 /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
636 * @brief IO operation functions
637 *
638 @verbatim
639 ===============================================================================
640 ##### IO operation functions #####
641 ===============================================================================
642 [..] This section provides functions allowing to:
643 (+) Configure the pdata, destination address and data size then
644 start the DMA2D transfer.
645 (+) Configure the source for foreground and background, destination address
646 and data size then start a MultiBuffer DMA2D transfer.
647 (+) Configure the pdata, destination address and data size then
648 start the DMA2D transfer with interrupt.
649 (+) Configure the source for foreground and background, destination address
650 and data size then start a MultiBuffer DMA2D transfer with interrupt.
651 (+) Abort DMA2D transfer.
652 (+) Suspend DMA2D transfer.
653 (+) Resume DMA2D transfer.
654 (+) Enable CLUT transfer.
655 (+) Configure CLUT loading then start transfer in polling mode.
656 (+) Configure CLUT loading then start transfer in interrupt mode.
657 (+) Abort DMA2D CLUT loading.
658 (+) Suspend DMA2D CLUT loading.
659 (+) Resume DMA2D CLUT loading.
660 (+) Poll for transfer complete.
661 (+) handle DMA2D interrupt request.
662 (+) Transfer watermark callback.
663 (+) CLUT Transfer Complete callback.
664
665
666 @endverbatim
667 * @{
668 */
669
670 /**
671 * @brief Start the DMA2D Transfer.
672 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
673 * the configuration information for the DMA2D.
674 * @param pdata Configure the source memory Buffer address if
675 * Memory-to-Memory or Memory-to-Memory with pixel format
676 * conversion mode is selected, or configure
677 * the color value if Register-to-Memory mode is selected.
678 * @param DstAddress The destination memory Buffer address.
679 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
680 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
681 * @retval HAL status
682 */
HAL_DMA2D_Start(DMA2D_HandleTypeDef * hdma2d,uint32_t pdata,uint32_t DstAddress,uint32_t Width,uint32_t Height)683 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
684 {
685 /* Check the parameters */
686 assert_param(IS_DMA2D_LINE(Height));
687 assert_param(IS_DMA2D_PIXEL(Width));
688
689 /* Process locked */
690 __HAL_LOCK(hdma2d);
691
692 /* Change DMA2D peripheral state */
693 hdma2d->State = HAL_DMA2D_STATE_BUSY;
694
695 /* Configure the source, destination address and the data size */
696 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
697
698 /* Enable the Peripheral */
699 __HAL_DMA2D_ENABLE(hdma2d);
700
701 return HAL_OK;
702 }
703
704 /**
705 * @brief Start the DMA2D Transfer with interrupt enabled.
706 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
707 * the configuration information for the DMA2D.
708 * @param pdata Configure the source memory Buffer address if
709 * the Memory-to-Memory or Memory-to-Memory with pixel format
710 * conversion mode is selected, or configure
711 * the color value if Register-to-Memory mode is selected.
712 * @param DstAddress The destination memory Buffer address.
713 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
714 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
715 * @retval HAL status
716 */
HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef * hdma2d,uint32_t pdata,uint32_t DstAddress,uint32_t Width,uint32_t Height)717 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
718 {
719 /* Check the parameters */
720 assert_param(IS_DMA2D_LINE(Height));
721 assert_param(IS_DMA2D_PIXEL(Width));
722
723 /* Process locked */
724 __HAL_LOCK(hdma2d);
725
726 /* Change DMA2D peripheral state */
727 hdma2d->State = HAL_DMA2D_STATE_BUSY;
728
729 /* Configure the source, destination address and the data size */
730 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
731
732 /* Enable the transfer complete, transfer error and configuration error interrupts */
733 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
734
735 /* Enable the Peripheral */
736 __HAL_DMA2D_ENABLE(hdma2d);
737
738 return HAL_OK;
739 }
740
741 /**
742 * @brief Start the multi-source DMA2D Transfer.
743 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
744 * the configuration information for the DMA2D.
745 * @param SrcAddress1 The source memory Buffer address for the foreground layer.
746 * @param SrcAddress2 The source memory Buffer address for the background layer.
747 * @param DstAddress The destination memory Buffer address.
748 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
749 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
750 * @retval HAL status
751 */
HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef * hdma2d,uint32_t SrcAddress1,uint32_t SrcAddress2,uint32_t DstAddress,uint32_t Width,uint32_t Height)752 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
753 {
754 /* Check the parameters */
755 assert_param(IS_DMA2D_LINE(Height));
756 assert_param(IS_DMA2D_PIXEL(Width));
757
758 /* Process locked */
759 __HAL_LOCK(hdma2d);
760
761 /* Change DMA2D peripheral state */
762 hdma2d->State = HAL_DMA2D_STATE_BUSY;
763
764 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT)
765 if(hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
766 {
767 /*blending & fixed FG*/
768 WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
769 /* Configure the source, destination address and the data size */
770 DMA2D_SetConfig(hdma2d, SrcAddress2, DstAddress, Width, Height);
771 }
772 else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_BG)
773 {
774 /*blending & fixed BG*/
775 WRITE_REG(hdma2d->Instance->BGCOLR, SrcAddress2);
776 /* Configure the source, destination address and the data size */
777 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
778 }
779 else
780 {
781 /* Configure DMA2D Stream source2 address */
782 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
783
784 /* Configure the source, destination address and the data size */
785 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
786 }
787
788 #else
789 /* Configure DMA2D Stream source2 address */
790 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
791
792 /* Configure the source, destination address and the data size */
793 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
794
795 #endif /*DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT*/
796 /* Enable the Peripheral */
797 __HAL_DMA2D_ENABLE(hdma2d);
798
799 return HAL_OK;
800 }
801
802 /**
803 * @brief Start the multi-source DMA2D Transfer with interrupt enabled.
804 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
805 * the configuration information for the DMA2D.
806 * @param SrcAddress1 The source memory Buffer address for the foreground layer.
807 * @param SrcAddress2 The source memory Buffer address for the background layer.
808 * @param DstAddress The destination memory Buffer address.
809 * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
810 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
811 * @retval HAL status
812 */
HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef * hdma2d,uint32_t SrcAddress1,uint32_t SrcAddress2,uint32_t DstAddress,uint32_t Width,uint32_t Height)813 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
814 {
815 /* Check the parameters */
816 assert_param(IS_DMA2D_LINE(Height));
817 assert_param(IS_DMA2D_PIXEL(Width));
818
819 /* Process locked */
820 __HAL_LOCK(hdma2d);
821
822 /* Change DMA2D peripheral state */
823 hdma2d->State = HAL_DMA2D_STATE_BUSY;
824
825 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT)
826 if(hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
827 {
828 /*blending & fixed FG*/
829 WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
830 /* Configure the source, destination address and the data size */
831 DMA2D_SetConfig(hdma2d, SrcAddress2, DstAddress, Width, Height);
832 }
833 else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_BG)
834 {
835 /*blending & fixed BG*/
836 WRITE_REG(hdma2d->Instance->BGCOLR, SrcAddress2);
837 /* Configure the source, destination address and the data size */
838 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
839 }
840 else
841 {
842 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
843
844 /* Configure the source, destination address and the data size */
845 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
846 }
847
848 #else
849 /* Configure DMA2D Stream source2 address */
850 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
851
852 /* Configure the source, destination address and the data size */
853 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
854
855 #endif /*DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT*/
856 /* Enable the transfer complete, transfer error and configuration error interrupts */
857 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
858
859 /* Enable the Peripheral */
860 __HAL_DMA2D_ENABLE(hdma2d);
861
862 return HAL_OK;
863 }
864
865 /**
866 * @brief Abort the DMA2D Transfer.
867 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
868 * the configuration information for the DMA2D.
869 * @retval HAL status
870 */
HAL_DMA2D_Abort(DMA2D_HandleTypeDef * hdma2d)871 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
872 {
873 uint32_t tickstart;
874
875 /* Abort the DMA2D transfer */
876 /* START bit is reset to make sure not to set it again, in the event the HW clears it
877 between the register read and the register write by the CPU (writing 0 has no
878 effect on START bitvalue) */
879 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
880
881 /* Get tick */
882 tickstart = HAL_GetTick();
883
884 /* Check if the DMA2D is effectively disabled */
885 while((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
886 {
887 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
888 {
889 /* Update error code */
890 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
891
892 /* Change the DMA2D state */
893 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
894
895 /* Process Unlocked */
896 __HAL_UNLOCK(hdma2d);
897
898 return HAL_TIMEOUT;
899 }
900 }
901
902 /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
903 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
904
905 /* Change the DMA2D state*/
906 hdma2d->State = HAL_DMA2D_STATE_READY;
907
908 /* Process Unlocked */
909 __HAL_UNLOCK(hdma2d);
910
911 return HAL_OK;
912 }
913
914 /**
915 * @brief Suspend the DMA2D Transfer.
916 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
917 * the configuration information for the DMA2D.
918 * @retval HAL status
919 */
HAL_DMA2D_Suspend(DMA2D_HandleTypeDef * hdma2d)920 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
921 {
922 uint32_t tickstart;
923
924 /* Suspend the DMA2D transfer */
925 /* START bit is reset to make sure not to set it again, in the event the HW clears it
926 between the register read and the register write by the CPU (writing 0 has no
927 effect on START bitvalue). */
928 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
929
930 /* Get tick */
931 tickstart = HAL_GetTick();
932
933 /* Check if the DMA2D is effectively suspended */
934 while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START)
935 {
936 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
937 {
938 /* Update error code */
939 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
940
941 /* Change the DMA2D state */
942 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
943
944 return HAL_TIMEOUT;
945 }
946 }
947
948 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
949 if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
950 {
951 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
952 }
953 else
954 {
955 /* Make sure SUSP bit is cleared since it is meaningless
956 when no tranfer is on-going */
957 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
958 }
959
960 return HAL_OK;
961 }
962
963 /**
964 * @brief Resume the DMA2D Transfer.
965 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
966 * the configuration information for the DMA2D.
967 * @retval HAL status
968 */
HAL_DMA2D_Resume(DMA2D_HandleTypeDef * hdma2d)969 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
970 {
971 /* Check the SUSP and START bits */
972 if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
973 {
974 /* Ongoing transfer is suspended: change the DMA2D state before resuming */
975 hdma2d->State = HAL_DMA2D_STATE_BUSY;
976 }
977
978 /* Resume the DMA2D transfer */
979 /* START bit is reset to make sure not to set it again, in the event the HW clears it
980 between the register read and the register write by the CPU (writing 0 has no
981 effect on START bitvalue). */
982 CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
983
984 return HAL_OK;
985 }
986
987
988 /**
989 * @brief Enable the DMA2D CLUT Transfer.
990 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
991 * the configuration information for the DMA2D.
992 * @param LayerIdx DMA2D Layer index.
993 * This parameter can be one of the following values:
994 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
995 * @retval HAL status
996 */
HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef * hdma2d,uint32_t LayerIdx)997 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
998 {
999 /* Check the parameters */
1000 assert_param(IS_DMA2D_LAYER(LayerIdx));
1001
1002 /* Process locked */
1003 __HAL_LOCK(hdma2d);
1004
1005 /* Change DMA2D peripheral state */
1006 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1007
1008 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1009 {
1010 /* Enable the background CLUT loading */
1011 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1012 }
1013 else
1014 {
1015 /* Enable the foreground CLUT loading */
1016 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1017 }
1018
1019 return HAL_OK;
1020 }
1021
1022 /**
1023 * @brief Start DMA2D CLUT Loading.
1024 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1025 * the configuration information for the DMA2D.
1026 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1027 * the configuration information for the color look up table.
1028 * @param LayerIdx DMA2D Layer index.
1029 * This parameter can be one of the following values:
1030 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1031 * @retval HAL status
1032 */
HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef * hdma2d,DMA2D_CLUTCfgTypeDef * CLUTCfg,uint32_t LayerIdx)1033 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx)
1034 {
1035 /* Check the parameters */
1036 assert_param(IS_DMA2D_LAYER(LayerIdx));
1037 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
1038 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
1039
1040 /* Process locked */
1041 __HAL_LOCK(hdma2d);
1042
1043 /* Change DMA2D peripheral state */
1044 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1045
1046 /* Configure the CLUT of the background DMA2D layer */
1047 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1048 {
1049 /* Write background CLUT memory address */
1050 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
1051
1052 /* Write background CLUT size and CLUT color mode */
1053 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1054 ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1055
1056 /* Enable the CLUT loading for the background */
1057 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1058 }
1059 /* Configure the CLUT of the foreground DMA2D layer */
1060 else
1061 {
1062 /* Write foreground CLUT memory address */
1063 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
1064
1065 /* Write foreground CLUT size and CLUT color mode */
1066 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1067 ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1068
1069 /* Enable the CLUT loading for the foreground */
1070 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1071 }
1072
1073 return HAL_OK;
1074 }
1075
1076 /**
1077 * @brief Start DMA2D CLUT Loading with interrupt enabled.
1078 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1079 * the configuration information for the DMA2D.
1080 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1081 * the configuration information for the color look up table.
1082 * @param LayerIdx DMA2D Layer index.
1083 * This parameter can be one of the following values:
1084 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1085 * @retval HAL status
1086 */
HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef * hdma2d,DMA2D_CLUTCfgTypeDef * CLUTCfg,uint32_t LayerIdx)1087 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx)
1088 {
1089 /* Check the parameters */
1090 assert_param(IS_DMA2D_LAYER(LayerIdx));
1091 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
1092 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
1093
1094 /* Process locked */
1095 __HAL_LOCK(hdma2d);
1096
1097 /* Change DMA2D peripheral state */
1098 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1099
1100 /* Configure the CLUT of the background DMA2D layer */
1101 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1102 {
1103 /* Write background CLUT memory address */
1104 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
1105
1106 /* Write background CLUT size and CLUT color mode */
1107 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1108 ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1109
1110 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1111 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
1112
1113 /* Enable the CLUT loading for the background */
1114 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1115 }
1116 /* Configure the CLUT of the foreground DMA2D layer */
1117 else
1118 {
1119 /* Write foreground CLUT memory address */
1120 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
1121
1122 /* Write foreground CLUT size and CLUT color mode */
1123 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1124 ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1125
1126 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1127 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
1128
1129 /* Enable the CLUT loading for the foreground */
1130 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1131 }
1132
1133 return HAL_OK;
1134 }
1135
1136 /**
1137 * @brief Start DMA2D CLUT Loading.
1138 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1139 * the configuration information for the DMA2D.
1140 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1141 * the configuration information for the color look up table.
1142 * @param LayerIdx DMA2D Layer index.
1143 * This parameter can be one of the following values:
1144 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1145 * @note API obsolete and maintained for compatibility with legacy. User is
1146 * invited to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from
1147 * code compactness, code size and improved heap usage.
1148 * @retval HAL status
1149 */
HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef * hdma2d,DMA2D_CLUTCfgTypeDef CLUTCfg,uint32_t LayerIdx)1150 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1151 {
1152 /* Check the parameters */
1153 assert_param(IS_DMA2D_LAYER(LayerIdx));
1154 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1155 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1156
1157 /* Process locked */
1158 __HAL_LOCK(hdma2d);
1159
1160 /* Change DMA2D peripheral state */
1161 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1162
1163 /* Configure the CLUT of the background DMA2D layer */
1164 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1165 {
1166 /* Write background CLUT memory address */
1167 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1168
1169 /* Write background CLUT size and CLUT color mode */
1170 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1171 ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1172
1173 /* Enable the CLUT loading for the background */
1174 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1175 }
1176 /* Configure the CLUT of the foreground DMA2D layer */
1177 else
1178 {
1179 /* Write foreground CLUT memory address */
1180 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1181
1182 /* Write foreground CLUT size and CLUT color mode */
1183 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1184 ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1185
1186 /* Enable the CLUT loading for the foreground */
1187 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1188 }
1189
1190 return HAL_OK;
1191 }
1192
1193 /**
1194 * @brief Start DMA2D CLUT Loading with interrupt enabled.
1195 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1196 * the configuration information for the DMA2D.
1197 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1198 * the configuration information for the color look up table.
1199 * @param LayerIdx DMA2D Layer index.
1200 * This parameter can be one of the following values:
1201 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1202 * @note API obsolete and maintained for compatibility with legacy. User is
1203 * invited to resort to HAL_DMA2D_CLUTStartLoad_IT() instead to benefit
1204 * from code compactness, code size and improved heap usage.
1205 * @retval HAL status
1206 */
HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef * hdma2d,DMA2D_CLUTCfgTypeDef CLUTCfg,uint32_t LayerIdx)1207 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1208 {
1209 /* Check the parameters */
1210 assert_param(IS_DMA2D_LAYER(LayerIdx));
1211 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1212 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1213
1214 /* Process locked */
1215 __HAL_LOCK(hdma2d);
1216
1217 /* Change DMA2D peripheral state */
1218 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1219
1220 /* Configure the CLUT of the background DMA2D layer */
1221 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1222 {
1223 /* Write background CLUT memory address */
1224 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1225
1226 /* Write background CLUT size and CLUT color mode */
1227 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1228 ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1229
1230 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1231 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
1232
1233 /* Enable the CLUT loading for the background */
1234 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1235 }
1236 /* Configure the CLUT of the foreground DMA2D layer */
1237 else
1238 {
1239 /* Write foreground CLUT memory address */
1240 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1241
1242 /* Write foreground CLUT size and CLUT color mode */
1243 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1244 ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1245
1246 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1247 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
1248
1249 /* Enable the CLUT loading for the foreground */
1250 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1251 }
1252
1253 return HAL_OK;
1254 }
1255
1256 /**
1257 * @brief Abort the DMA2D CLUT loading.
1258 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1259 * the configuration information for the DMA2D.
1260 * @param LayerIdx DMA2D Layer index.
1261 * This parameter can be one of the following values:
1262 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1263 * @retval HAL status
1264 */
HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef * hdma2d,uint32_t LayerIdx)1265 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1266 {
1267 uint32_t tickstart;
1268 const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
1269
1270 /* Abort the CLUT loading */
1271 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
1272
1273 /* If foreground CLUT loading is considered, update local variables */
1274 if(LayerIdx == DMA2D_FOREGROUND_LAYER)
1275 {
1276 reg = &(hdma2d->Instance->FGPFCCR);
1277 }
1278
1279
1280 /* Get tick */
1281 tickstart = HAL_GetTick();
1282
1283 /* Check if the CLUT loading is aborted */
1284 while((*reg & DMA2D_BGPFCCR_START) != 0U)
1285 {
1286 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
1287 {
1288 /* Update error code */
1289 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1290
1291 /* Change the DMA2D state */
1292 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1293
1294 /* Process Unlocked */
1295 __HAL_UNLOCK(hdma2d);
1296
1297 return HAL_TIMEOUT;
1298 }
1299 }
1300
1301 /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
1302 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
1303
1304 /* Change the DMA2D state*/
1305 hdma2d->State = HAL_DMA2D_STATE_READY;
1306
1307 /* Process Unlocked */
1308 __HAL_UNLOCK(hdma2d);
1309
1310 return HAL_OK;
1311 }
1312
1313 /**
1314 * @brief Suspend the DMA2D CLUT loading.
1315 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1316 * the configuration information for the DMA2D.
1317 * @param LayerIdx DMA2D Layer index.
1318 * This parameter can be one of the following values:
1319 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1320 * @retval HAL status
1321 */
HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef * hdma2d,uint32_t LayerIdx)1322 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1323 {
1324 uint32_t tickstart;
1325 uint32_t loadsuspended;
1326 const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
1327
1328 /* Suspend the CLUT loading */
1329 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1330
1331 /* If foreground CLUT loading is considered, update local variables */
1332 if(LayerIdx == DMA2D_FOREGROUND_LAYER)
1333 {
1334 reg = &(hdma2d->Instance->FGPFCCR);
1335 }
1336
1337 /* Get tick */
1338 tickstart = HAL_GetTick();
1339
1340 /* Check if the CLUT loading is suspended */
1341 loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
1342 loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
1343 while (loadsuspended == 0UL)
1344 {
1345 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
1346 {
1347 /* Update error code */
1348 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1349
1350 /* Change the DMA2D state */
1351 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1352
1353 return HAL_TIMEOUT;
1354 }
1355 loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
1356 loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
1357 }
1358
1359 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
1360 if ((*reg & DMA2D_BGPFCCR_START) != 0U)
1361 {
1362 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
1363 }
1364 else
1365 {
1366 /* Make sure SUSP bit is cleared since it is meaningless
1367 when no tranfer is on-going */
1368 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1369 }
1370
1371 return HAL_OK;
1372 }
1373
1374 /**
1375 * @brief Resume the DMA2D CLUT loading.
1376 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
1377 * the configuration information for the DMA2D.
1378 * @param LayerIdx DMA2D Layer index.
1379 * This parameter can be one of the following values:
1380 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1381 * @retval HAL status
1382 */
HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef * hdma2d,uint32_t LayerIdx)1383 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1384 {
1385 /* Check the SUSP and START bits for background or foreground CLUT loading */
1386 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1387 {
1388 /* Background CLUT loading suspension check */
1389 if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
1390 {
1391 if((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
1392 {
1393 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
1394 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1395 }
1396 }
1397 }
1398 else
1399 {
1400 /* Foreground CLUT loading suspension check */
1401 if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
1402 {
1403 if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
1404 {
1405 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
1406 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1407 }
1408 }
1409 }
1410
1411 /* Resume the CLUT loading */
1412 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1413
1414 return HAL_OK;
1415 }
1416
1417
1418 /**
1419
1420 * @brief Polling for transfer complete or CLUT loading.
1421 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1422 * the configuration information for the DMA2D.
1423 * @param Timeout Timeout duration
1424 * @retval HAL status
1425 */
HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef * hdma2d,uint32_t Timeout)1426 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
1427 {
1428 uint32_t tickstart;
1429 uint32_t layer_start;
1430 __IO uint32_t isrflags = 0x0U;
1431
1432 /* Polling for DMA2D transfer */
1433 if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
1434 {
1435 /* Get tick */
1436 tickstart = HAL_GetTick();
1437
1438 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
1439 {
1440 isrflags = READ_REG(hdma2d->Instance->ISR);
1441 if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
1442 {
1443 if ((isrflags & DMA2D_FLAG_CE) != 0U)
1444 {
1445 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1446 }
1447 if ((isrflags & DMA2D_FLAG_TE) != 0U)
1448 {
1449 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1450 }
1451 /* Clear the transfer and configuration error flags */
1452 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1453
1454 /* Change DMA2D state */
1455 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1456
1457 /* Process unlocked */
1458 __HAL_UNLOCK(hdma2d);
1459
1460 return HAL_ERROR;
1461 }
1462 /* Check for the Timeout */
1463 if(Timeout != HAL_MAX_DELAY)
1464 {
1465 if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
1466 {
1467 /* Update error code */
1468 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1469
1470 /* Change the DMA2D state */
1471 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1472
1473 /* Process unlocked */
1474 __HAL_UNLOCK(hdma2d);
1475
1476 return HAL_TIMEOUT;
1477 }
1478 }
1479 }
1480 }
1481 /* Polling for CLUT loading (foreground or background) */
1482 layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;
1483 layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;
1484 if (layer_start != 0U)
1485 {
1486 /* Get tick */
1487 tickstart = HAL_GetTick();
1488
1489 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
1490 {
1491 isrflags = READ_REG(hdma2d->Instance->ISR);
1492 if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
1493 {
1494 if ((isrflags & DMA2D_FLAG_CAE) != 0U)
1495 {
1496 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1497 }
1498 if ((isrflags & DMA2D_FLAG_CE) != 0U)
1499 {
1500 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1501 }
1502 if ((isrflags & DMA2D_FLAG_TE) != 0U)
1503 {
1504 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1505 }
1506 /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
1507 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1508
1509 /* Change DMA2D state */
1510 hdma2d->State= HAL_DMA2D_STATE_ERROR;
1511
1512 /* Process unlocked */
1513 __HAL_UNLOCK(hdma2d);
1514
1515 return HAL_ERROR;
1516 }
1517 /* Check for the Timeout */
1518 if(Timeout != HAL_MAX_DELAY)
1519 {
1520 if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
1521 {
1522 /* Update error code */
1523 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1524
1525 /* Change the DMA2D state */
1526 hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
1527
1528 /* Process unlocked */
1529 __HAL_UNLOCK(hdma2d);
1530
1531 return HAL_TIMEOUT;
1532 }
1533 }
1534 }
1535 }
1536
1537 /* Clear the transfer complete and CLUT loading flags */
1538 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
1539
1540 /* Change DMA2D state */
1541 hdma2d->State = HAL_DMA2D_STATE_READY;
1542
1543 /* Process unlocked */
1544 __HAL_UNLOCK(hdma2d);
1545
1546 return HAL_OK;
1547 }
1548 /**
1549 * @brief Handle DMA2D interrupt request.
1550 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1551 * the configuration information for the DMA2D.
1552 * @retval HAL status
1553 */
HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef * hdma2d)1554 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
1555 {
1556 uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
1557 uint32_t crflags = READ_REG(hdma2d->Instance->CR);
1558
1559 /* Transfer Error Interrupt management ***************************************/
1560 if ((isrflags & DMA2D_FLAG_TE) != 0U)
1561 {
1562 if ((crflags & DMA2D_IT_TE) != 0U)
1563 {
1564 /* Disable the transfer Error interrupt */
1565 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
1566
1567 /* Update error code */
1568 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1569
1570 /* Clear the transfer error flag */
1571 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
1572
1573 /* Change DMA2D state */
1574 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1575
1576 /* Process Unlocked */
1577 __HAL_UNLOCK(hdma2d);
1578
1579 if(hdma2d->XferErrorCallback != NULL)
1580 {
1581 /* Transfer error Callback */
1582 hdma2d->XferErrorCallback(hdma2d);
1583 }
1584 }
1585 }
1586 /* Configuration Error Interrupt management **********************************/
1587 if ((isrflags & DMA2D_FLAG_CE) != 0U)
1588 {
1589 if ((crflags & DMA2D_IT_CE) != 0U)
1590 {
1591 /* Disable the Configuration Error interrupt */
1592 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
1593
1594 /* Clear the Configuration error flag */
1595 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
1596
1597 /* Update error code */
1598 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1599
1600 /* Change DMA2D state */
1601 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1602
1603 /* Process Unlocked */
1604 __HAL_UNLOCK(hdma2d);
1605
1606 if(hdma2d->XferErrorCallback != NULL)
1607 {
1608 /* Transfer error Callback */
1609 hdma2d->XferErrorCallback(hdma2d);
1610 }
1611 }
1612 }
1613 /* CLUT access Error Interrupt management ***********************************/
1614 if ((isrflags & DMA2D_FLAG_CAE) != 0U)
1615 {
1616 if ((crflags & DMA2D_IT_CAE) != 0U)
1617 {
1618 /* Disable the CLUT access error interrupt */
1619 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
1620
1621 /* Clear the CLUT access error flag */
1622 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
1623
1624 /* Update error code */
1625 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1626
1627 /* Change DMA2D state */
1628 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1629
1630 /* Process Unlocked */
1631 __HAL_UNLOCK(hdma2d);
1632
1633 if(hdma2d->XferErrorCallback != NULL)
1634 {
1635 /* Transfer error Callback */
1636 hdma2d->XferErrorCallback(hdma2d);
1637 }
1638 }
1639 }
1640 /* Transfer watermark Interrupt management **********************************/
1641 if ((isrflags & DMA2D_FLAG_TW) != 0U)
1642 {
1643 if ((crflags & DMA2D_IT_TW) != 0U)
1644 {
1645 /* Disable the transfer watermark interrupt */
1646 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
1647
1648 /* Clear the transfer watermark flag */
1649 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
1650
1651 /* Transfer watermark Callback */
1652 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
1653 hdma2d->LineEventCallback(hdma2d);
1654 #else
1655 HAL_DMA2D_LineEventCallback(hdma2d);
1656 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
1657
1658 }
1659 }
1660 /* Transfer Complete Interrupt management ************************************/
1661 if ((isrflags & DMA2D_FLAG_TC) != 0U)
1662 {
1663 if ((crflags & DMA2D_IT_TC) != 0U)
1664 {
1665 /* Disable the transfer complete interrupt */
1666 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
1667
1668 /* Clear the transfer complete flag */
1669 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
1670
1671 /* Update error code */
1672 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1673
1674 /* Change DMA2D state */
1675 hdma2d->State = HAL_DMA2D_STATE_READY;
1676
1677 /* Process Unlocked */
1678 __HAL_UNLOCK(hdma2d);
1679
1680 if(hdma2d->XferCpltCallback != NULL)
1681 {
1682 /* Transfer complete Callback */
1683 hdma2d->XferCpltCallback(hdma2d);
1684 }
1685 }
1686 }
1687 /* CLUT Transfer Complete Interrupt management ******************************/
1688 if ((isrflags & DMA2D_FLAG_CTC) != 0U)
1689 {
1690 if ((crflags & DMA2D_IT_CTC) != 0U)
1691 {
1692 /* Disable the CLUT transfer complete interrupt */
1693 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
1694
1695 /* Clear the CLUT transfer complete flag */
1696 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
1697
1698 /* Update error code */
1699 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1700
1701 /* Change DMA2D state */
1702 hdma2d->State = HAL_DMA2D_STATE_READY;
1703
1704 /* Process Unlocked */
1705 __HAL_UNLOCK(hdma2d);
1706
1707 /* CLUT Transfer complete Callback */
1708 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
1709 hdma2d->CLUTLoadingCpltCallback(hdma2d);
1710 #else
1711 HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
1712 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
1713 }
1714 }
1715
1716 }
1717
1718 /**
1719 * @brief Transfer watermark callback.
1720 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
1721 * the configuration information for the DMA2D.
1722 * @retval None
1723 */
HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef * hdma2d)1724 __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
1725 {
1726 /* Prevent unused argument(s) compilation warning */
1727 UNUSED(hdma2d);
1728
1729 /* NOTE : This function should not be modified; when the callback is needed,
1730 the HAL_DMA2D_LineEventCallback can be implemented in the user file.
1731 */
1732 }
1733
1734 /**
1735 * @brief CLUT Transfer Complete callback.
1736 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
1737 * the configuration information for the DMA2D.
1738 * @retval None
1739 */
HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef * hdma2d)1740 __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
1741 {
1742 /* Prevent unused argument(s) compilation warning */
1743 UNUSED(hdma2d);
1744
1745 /* NOTE : This function should not be modified; when the callback is needed,
1746 the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
1747 */
1748 }
1749
1750 /**
1751 * @}
1752 */
1753
1754 /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
1755 * @brief Peripheral Control functions
1756 *
1757 @verbatim
1758 ===============================================================================
1759 ##### Peripheral Control functions #####
1760 ===============================================================================
1761 [..] This section provides functions allowing to:
1762 (+) Configure the DMA2D foreground or background layer parameters.
1763 (+) Configure the DMA2D CLUT transfer.
1764 (+) Configure the line watermark
1765 (+) Configure the dead time value.
1766 (+) Enable or disable the dead time value functionality.
1767
1768
1769 @endverbatim
1770 * @{
1771 */
1772
1773 /**
1774 * @brief Configure the DMA2D Layer according to the specified
1775 * parameters in the DMA2D_HandleTypeDef.
1776 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1777 * the configuration information for the DMA2D.
1778 * @param LayerIdx DMA2D Layer index.
1779 * This parameter can be one of the following values:
1780 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1781 * @retval HAL status
1782 */
HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef * hdma2d,uint32_t LayerIdx)1783 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1784 {
1785 DMA2D_LayerCfgTypeDef *pLayerCfg;
1786 uint32_t regMask, regValue;
1787
1788 /* Check the parameters */
1789 assert_param(IS_DMA2D_LAYER(LayerIdx));
1790 assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
1791 if(hdma2d->Init.Mode != DMA2D_R2M)
1792 {
1793 assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode));
1794 if(hdma2d->Init.Mode != DMA2D_M2M)
1795 {
1796 assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
1797 }
1798 }
1799 assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted));
1800 assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap));
1801
1802 /* Process locked */
1803 __HAL_LOCK(hdma2d);
1804
1805 /* Change DMA2D peripheral state */
1806 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1807
1808 pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
1809
1810 /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
1811 regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) |\
1812 (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);
1813 regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS);
1814
1815
1816 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1817 {
1818 regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
1819 }
1820 else
1821 {
1822 regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
1823 }
1824
1825 /* Configure the background DMA2D layer */
1826 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1827 {
1828 /* Write DMA2D BGPFCCR register */
1829 MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
1830
1831 /* DMA2D BGOR register configuration -------------------------------------*/
1832 WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
1833
1834 /* DMA2D BGCOLR register configuration -------------------------------------*/
1835 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1836 {
1837 WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
1838 }
1839 }
1840 /* Configure the foreground DMA2D layer */
1841 else
1842 {
1843
1844
1845 /* Write DMA2D FGPFCCR register */
1846 MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
1847
1848 /* DMA2D FGOR register configuration -------------------------------------*/
1849 WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
1850
1851 /* DMA2D FGCOLR register configuration -------------------------------------*/
1852 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1853 {
1854 WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
1855 }
1856 }
1857 /* Initialize the DMA2D state*/
1858 hdma2d->State = HAL_DMA2D_STATE_READY;
1859
1860 /* Process unlocked */
1861 __HAL_UNLOCK(hdma2d);
1862
1863 return HAL_OK;
1864 }
1865
1866 /**
1867 * @brief Configure the DMA2D CLUT Transfer.
1868 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1869 * the configuration information for the DMA2D.
1870 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1871 * the configuration information for the color look up table.
1872 * @param LayerIdx DMA2D Layer index.
1873 * This parameter can be one of the following values:
1874 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1875 * @note API obsolete and maintained for compatibility with legacy. User is invited
1876 * to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from code compactness,
1877 * code size and improved heap usage.
1878 * @retval HAL status
1879 */
HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef * hdma2d,DMA2D_CLUTCfgTypeDef CLUTCfg,uint32_t LayerIdx)1880 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1881 {
1882 /* Check the parameters */
1883 assert_param(IS_DMA2D_LAYER(LayerIdx));
1884 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1885 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1886
1887 /* Process locked */
1888 __HAL_LOCK(hdma2d);
1889
1890 /* Change DMA2D peripheral state */
1891 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1892
1893 /* Configure the CLUT of the background DMA2D layer */
1894 if(LayerIdx == DMA2D_BACKGROUND_LAYER)
1895 {
1896 /* Write background CLUT memory address */
1897 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1898
1899 /* Write background CLUT size and CLUT color mode */
1900 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1901 ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1902 }
1903 /* Configure the CLUT of the foreground DMA2D layer */
1904 else
1905 {
1906 /* Write foreground CLUT memory address */
1907 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1908
1909 /* Write foreground CLUT size and CLUT color mode */
1910 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1911 ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1912 }
1913
1914 /* Set the DMA2D state to Ready*/
1915 hdma2d->State = HAL_DMA2D_STATE_READY;
1916
1917 /* Process unlocked */
1918 __HAL_UNLOCK(hdma2d);
1919
1920 return HAL_OK;
1921 }
1922
1923
1924 /**
1925 * @brief Configure the line watermark.
1926 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1927 * the configuration information for the DMA2D.
1928 * @param Line Line Watermark configuration (maximum 16-bit long value expected).
1929 * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
1930 * @note The transfer watermark interrupt is disabled once it has occurred.
1931 * @retval HAL status
1932 */
1933
HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef * hdma2d,uint32_t Line)1934 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
1935 {
1936 /* Check the parameters */
1937 assert_param(IS_DMA2D_LINEWATERMARK(Line));
1938
1939 if (Line > DMA2D_LWR_LW)
1940 {
1941 return HAL_ERROR;
1942 }
1943 else
1944 {
1945 /* Process locked */
1946 __HAL_LOCK(hdma2d);
1947
1948 /* Change DMA2D peripheral state */
1949 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1950
1951 /* Sets the Line watermark configuration */
1952 WRITE_REG(hdma2d->Instance->LWR, Line);
1953
1954 /* Enable the Line interrupt */
1955 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
1956
1957 /* Initialize the DMA2D state*/
1958 hdma2d->State = HAL_DMA2D_STATE_READY;
1959
1960 /* Process unlocked */
1961 __HAL_UNLOCK(hdma2d);
1962
1963 return HAL_OK;
1964 }
1965 }
1966
1967 /**
1968 * @brief Enable DMA2D dead time feature.
1969 * @param hdma2d DMA2D handle.
1970 * @retval HAL status
1971 */
HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef * hdma2d)1972 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
1973 {
1974 /* Process Locked */
1975 __HAL_LOCK(hdma2d);
1976
1977 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1978
1979 /* Set DMA2D_AMTCR EN bit */
1980 SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
1981
1982 hdma2d->State = HAL_DMA2D_STATE_READY;
1983
1984 /* Process Unlocked */
1985 __HAL_UNLOCK(hdma2d);
1986
1987 return HAL_OK;
1988 }
1989
1990 /**
1991 * @brief Disable DMA2D dead time feature.
1992 * @param hdma2d DMA2D handle.
1993 * @retval HAL status
1994 */
HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef * hdma2d)1995 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
1996 {
1997 /* Process Locked */
1998 __HAL_LOCK(hdma2d);
1999
2000 hdma2d->State = HAL_DMA2D_STATE_BUSY;
2001
2002 /* Clear DMA2D_AMTCR EN bit */
2003 CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
2004
2005 hdma2d->State = HAL_DMA2D_STATE_READY;
2006
2007 /* Process Unlocked */
2008 __HAL_UNLOCK(hdma2d);
2009
2010 return HAL_OK;
2011 }
2012
2013 /**
2014 * @brief Configure dead time.
2015 * @note The dead time value represents the guaranteed minimum number of cycles between
2016 * two consecutive transactions on the AHB bus.
2017 * @param hdma2d DMA2D handle.
2018 * @param DeadTime dead time value.
2019 * @retval HAL status
2020 */
HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef * hdma2d,uint8_t DeadTime)2021 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
2022 {
2023 /* Process Locked */
2024 __HAL_LOCK(hdma2d);
2025
2026 hdma2d->State = HAL_DMA2D_STATE_BUSY;
2027
2028 /* Set DMA2D_AMTCR DT field */
2029 MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos));
2030
2031 hdma2d->State = HAL_DMA2D_STATE_READY;
2032
2033 /* Process Unlocked */
2034 __HAL_UNLOCK(hdma2d);
2035
2036 return HAL_OK;
2037 }
2038
2039 /**
2040 * @}
2041 */
2042
2043
2044 /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
2045 * @brief Peripheral State functions
2046 *
2047 @verbatim
2048 ===============================================================================
2049 ##### Peripheral State and Errors functions #####
2050 ===============================================================================
2051 [..]
2052 This subsection provides functions allowing to:
2053 (+) Get the DMA2D state
2054 (+) Get the DMA2D error code
2055
2056 @endverbatim
2057 * @{
2058 */
2059
2060 /**
2061 * @brief Return the DMA2D state
2062 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
2063 * the configuration information for the DMA2D.
2064 * @retval HAL state
2065 */
HAL_DMA2D_GetState(DMA2D_HandleTypeDef * hdma2d)2066 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
2067 {
2068 return hdma2d->State;
2069 }
2070
2071 /**
2072 * @brief Return the DMA2D error code
2073 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
2074 * the configuration information for DMA2D.
2075 * @retval DMA2D Error Code
2076 */
HAL_DMA2D_GetError(DMA2D_HandleTypeDef * hdma2d)2077 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
2078 {
2079 return hdma2d->ErrorCode;
2080 }
2081
2082 /**
2083 * @}
2084 */
2085
2086 /**
2087 * @}
2088 */
2089
2090
2091 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
2092 * @{
2093 */
2094
2095 /**
2096 * @brief Set the DMA2D transfer parameters.
2097 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
2098 * the configuration information for the specified DMA2D.
2099 * @param pdata The source memory Buffer address
2100 * @param DstAddress The destination memory Buffer address
2101 * @param Width The width of data to be transferred from source to destination.
2102 * @param Height The height of data to be transferred from source to destination.
2103 * @retval HAL status
2104 */
DMA2D_SetConfig(DMA2D_HandleTypeDef * hdma2d,uint32_t pdata,uint32_t DstAddress,uint32_t Width,uint32_t Height)2105 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
2106 {
2107 uint32_t tmp;
2108 uint32_t tmp1;
2109 uint32_t tmp2;
2110 uint32_t tmp3;
2111 uint32_t tmp4;
2112
2113 /* Configure DMA2D data size */
2114 MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos)));
2115
2116 /* Configure DMA2D destination address */
2117 WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
2118
2119 /* Register to memory DMA2D mode selected */
2120 if (hdma2d->Init.Mode == DMA2D_R2M)
2121 {
2122 tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
2123 tmp2 = pdata & DMA2D_OCOLR_RED_1;
2124 tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
2125 tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
2126
2127 /* Prepare the value to be written to the OCOLR register according to the color mode */
2128 if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
2129 {
2130 tmp = (tmp3 | tmp2 | tmp1| tmp4);
2131 }
2132 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
2133 {
2134 tmp = (tmp3 | tmp2 | tmp4);
2135 }
2136 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
2137 {
2138 tmp2 = (tmp2 >> 19U);
2139 tmp3 = (tmp3 >> 10U);
2140 tmp4 = (tmp4 >> 3U );
2141 tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
2142 }
2143 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
2144 {
2145 tmp1 = (tmp1 >> 31U);
2146 tmp2 = (tmp2 >> 19U);
2147 tmp3 = (tmp3 >> 11U);
2148 tmp4 = (tmp4 >> 3U );
2149 tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
2150 }
2151 else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
2152 {
2153 tmp1 = (tmp1 >> 28U);
2154 tmp2 = (tmp2 >> 20U);
2155 tmp3 = (tmp3 >> 12U);
2156 tmp4 = (tmp4 >> 4U );
2157 tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
2158 }
2159 /* Write to DMA2D OCOLR register */
2160 WRITE_REG(hdma2d->Instance->OCOLR, tmp);
2161 }
2162 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT)
2163 else if(hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) /*M2M_blending with fixed color FG DMA2D Mode selected*/
2164 {
2165 WRITE_REG(hdma2d->Instance->BGMAR , pdata);
2166 }
2167 else /* M2M, M2M_PFC,M2M_Blending or M2M_blending with fixed color BG DMA2D Mode */
2168 #else
2169 else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
2170 #endif /*DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT*/
2171 {
2172 /* Configure DMA2D source address */
2173 WRITE_REG(hdma2d->Instance->FGMAR, pdata);
2174 }
2175 }
2176
2177 /**
2178 * @}
2179 */
2180
2181 /**
2182 * @}
2183 */
2184
2185 /**
2186 * @}
2187 */
2188 #endif /* DMA2D */
2189 #endif /* HAL_DMA2D_MODULE_ENABLED */
2190
2191 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2192