1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_adc.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Analog to Digital Convertor (ADC)
7 * peripheral:
8 * + Initialization and de-initialization functions
9 * ++ Initialization and Configuration of ADC
10 * + Operation functions
11 * ++ Start, stop, get result of conversions of regular
12 * group, using 3 possible modes: polling, interruption or DMA.
13 * + Control functions
14 * ++ Channels configuration on regular group
15 * ++ Analog Watchdog configuration
16 * + State functions
17 * ++ ADC state machine management
18 * ++ Interrupts and flags management
19 * Other functions (extended functions) are available in file
20 * "stm32l4xx_hal_adc_ex.c".
21 *
22 @verbatim
23 ==============================================================================
24 ##### ADC peripheral features #####
25 ==============================================================================
26 [..]
27 (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
28
29 (+) Interrupt generation at the end of regular conversion and in case of
30 analog watchdog or overrun events.
31
32 (+) Single and continuous conversion modes.
33
34 (+) Scan mode for conversion of several channels sequentially.
35
36 (+) Data alignment with in-built data coherency.
37
38 (+) Programmable sampling time (channel wise)
39
40 (+) External trigger (timer or EXTI) with configurable polarity
41
42 (+) DMA request generation for transfer of conversions data of regular group.
43
44 (+) Configurable delay between conversions in Dual interleaved mode.
45
46 (+) ADC channels selectable single/differential input.
47
48 (+) ADC offset shared on 4 offset instances.
49 (+) ADC calibration
50
51 (+) ADC conversion of regular group.
52
53 (+) ADC supply requirements: 1.62 V to 3.6 V.
54
55 (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
56 Vdda or to an external voltage reference).
57
58
59 ##### How to use this driver #####
60 ==============================================================================
61 [..]
62
63 *** Configuration of top level parameters related to ADC ***
64 ============================================================
65 [..]
66
67 (#) Enable the ADC interface
68 (++) As prerequisite, ADC clock must be configured at RCC top level.
69
70 (++) Two clock settings are mandatory:
71 (+++) ADC clock (core clock, also possibly conversion clock).
72
73 (+++) ADC clock (conversions clock).
74 Two possible clock sources: synchronous clock derived from APB clock
75 or asynchronous clock derived from system clock, PLLSAI1 or the PLLSAI2
76 running up to 80MHz.
77
78 (+++) Example:
79 Into HAL_ADC_MspInit() (recommended code location) or with
80 other device clock parameters configuration:
81 (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory)
82
83 RCC_ADCCLKSOURCE_PLL enable: (optional: if asynchronous clock selected)
84 (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit;
85 (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
86 (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLL;
87 (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
88
89 (++) ADC clock source and clock prescaler are configured at ADC level with
90 parameter "ClockPrescaler" using function HAL_ADC_Init().
91
92 (#) ADC pins configuration
93 (++) Enable the clock for the ADC GPIOs
94 using macro __HAL_RCC_GPIOx_CLK_ENABLE()
95 (++) Configure these ADC pins in analog mode
96 using function HAL_GPIO_Init()
97
98 (#) Optionally, in case of usage of ADC with interruptions:
99 (++) Configure the NVIC for ADC
100 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
101 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
102 into the function of corresponding ADC interruption vector
103 ADCx_IRQHandler().
104
105 (#) Optionally, in case of usage of DMA:
106 (++) Configure the DMA (DMA channel, mode normal or circular, ...)
107 using function HAL_DMA_Init().
108 (++) Configure the NVIC for DMA
109 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
110 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
111 into the function of corresponding DMA interruption vector
112 DMAx_Channelx_IRQHandler().
113
114 *** Configuration of ADC, group regular, channels parameters ***
115 ================================================================
116 [..]
117
118 (#) Configure the ADC parameters (resolution, data alignment, ...)
119 and regular group parameters (conversion trigger, sequencer, ...)
120 using function HAL_ADC_Init().
121
122 (#) Configure the channels for regular group parameters (channel number,
123 channel rank into sequencer, ..., into regular group)
124 using function HAL_ADC_ConfigChannel().
125
126 (#) Optionally, configure the analog watchdog parameters (channels
127 monitored, thresholds, ...)
128 using function HAL_ADC_AnalogWDGConfig().
129
130 *** Execution of ADC conversions ***
131 ====================================
132 [..]
133
134 (#) Optionally, perform an automatic ADC calibration to improve the
135 conversion accuracy
136 using function HAL_ADCEx_Calibration_Start().
137
138 (#) ADC driver can be used among three modes: polling, interruption,
139 transfer by DMA.
140
141 (++) ADC conversion by polling:
142 (+++) Activate the ADC peripheral and start conversions
143 using function HAL_ADC_Start()
144 (+++) Wait for ADC conversion completion
145 using function HAL_ADC_PollForConversion()
146 (+++) Retrieve conversion results
147 using function HAL_ADC_GetValue()
148 (+++) Stop conversion and disable the ADC peripheral
149 using function HAL_ADC_Stop()
150
151 (++) ADC conversion by interruption:
152 (+++) Activate the ADC peripheral and start conversions
153 using function HAL_ADC_Start_IT()
154 (+++) Wait for ADC conversion completion by call of function
155 HAL_ADC_ConvCpltCallback()
156 (this function must be implemented in user program)
157 (+++) Retrieve conversion results
158 using function HAL_ADC_GetValue()
159 (+++) Stop conversion and disable the ADC peripheral
160 using function HAL_ADC_Stop_IT()
161
162 (++) ADC conversion with transfer by DMA:
163 (+++) Activate the ADC peripheral and start conversions
164 using function HAL_ADC_Start_DMA()
165 (+++) Wait for ADC conversion completion by call of function
166 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
167 (these functions must be implemented in user program)
168 (+++) Conversion results are automatically transferred by DMA into
169 destination variable address.
170 (+++) Stop conversion and disable the ADC peripheral
171 using function HAL_ADC_Stop_DMA()
172
173 [..]
174
175 (@) Callback functions must be implemented in user program:
176 (+@) HAL_ADC_ErrorCallback()
177 (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
178 (+@) HAL_ADC_ConvCpltCallback()
179 (+@) HAL_ADC_ConvHalfCpltCallback
180
181 *** Deinitialization of ADC ***
182 ============================================================
183 [..]
184
185 (#) Disable the ADC interface
186 (++) ADC clock can be hard reset and disabled at RCC top level.
187 (++) Hard reset of ADC peripherals
188 using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
189 (++) ADC clock disable
190 using the equivalent macro/functions as configuration step.
191 (+++) Example:
192 Into HAL_ADC_MspDeInit() (recommended code location) or with
193 other device clock parameters configuration:
194 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
195 (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
196 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
197
198 (#) ADC pins configuration
199 (++) Disable the clock for the ADC GPIOs
200 using macro __HAL_RCC_GPIOx_CLK_DISABLE()
201
202 (#) Optionally, in case of usage of ADC with interruptions:
203 (++) Disable the NVIC for ADC
204 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
205
206 (#) Optionally, in case of usage of DMA:
207 (++) Deinitialize the DMA
208 using function HAL_DMA_Init().
209 (++) Disable the NVIC for DMA
210 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
211
212 [..]
213
214 *** Callback registration ***
215 =============================================
216 [..]
217
218 The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
219 allows the user to configure dynamically the driver callbacks.
220 Use Functions @ref HAL_ADC_RegisterCallback()
221 to register an interrupt callback.
222 [..]
223
224 Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
225 (+) ConvCpltCallback : ADC conversion complete callback
226 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
227 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
228 (+) ErrorCallback : ADC error callback
229 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
230 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
231 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
232 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
233 (+) EndOfSamplingCallback : ADC end of sampling callback
234 (+) MspInitCallback : ADC Msp Init callback
235 (+) MspDeInitCallback : ADC Msp DeInit callback
236 This function takes as parameters the HAL peripheral handle, the Callback ID
237 and a pointer to the user callback function.
238 [..]
239
240 Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
241 weak function.
242 [..]
243
244 @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
245 and the Callback ID.
246 This function allows to reset following callbacks:
247 (+) ConvCpltCallback : ADC conversion complete callback
248 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
249 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
250 (+) ErrorCallback : ADC error callback
251 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
252 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
253 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
254 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
255 (+) EndOfSamplingCallback : ADC end of sampling callback
256 (+) MspInitCallback : ADC Msp Init callback
257 (+) MspDeInitCallback : ADC Msp DeInit callback
258 [..]
259
260 By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
261 all callbacks are set to the corresponding weak functions:
262 examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
263 Exception done for MspInit and MspDeInit functions that are
264 reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
265 these callbacks are null (not registered beforehand).
266 [..]
267
268 If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
269 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
270 [..]
271
272 Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
273 Exception done MspInit/MspDeInit functions that can be registered/unregistered
274 in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
275 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
276 [..]
277
278 Then, the user first registers the MspInit/MspDeInit user callbacks
279 using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
280 or @ref HAL_ADC_Init() function.
281 [..]
282
283 When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
284 not defined, the callback registration feature is not available and all callbacks
285 are set to the corresponding weak functions.
286
287 @endverbatim
288 ******************************************************************************
289 * @attention
290 *
291 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
292 * All rights reserved.</center></h2>
293 *
294 * This software component is licensed by ST under BSD 3-Clause license,
295 * the "License"; You may not use this file except in compliance with the
296 * License. You may obtain a copy of the License at:
297 * opensource.org/licenses/BSD-3-Clause
298 *
299 ******************************************************************************
300 */
301
302 /* Includes ------------------------------------------------------------------*/
303 #include "stm32l4xx_hal.h"
304
305 /** @addtogroup STM32L4xx_HAL_Driver
306 * @{
307 */
308
309 /** @defgroup ADC ADC
310 * @brief ADC HAL module driver
311 * @{
312 */
313
314 #ifdef HAL_ADC_MODULE_ENABLED
315
316 /* Private typedef -----------------------------------------------------------*/
317 /* Private define ------------------------------------------------------------*/
318
319 /** @defgroup ADC_Private_Constants ADC Private Constants
320 * @{
321 */
322
323 #define ADC_CFGR_FIELDS_1 ((ADC_CFGR_RES | ADC_CFGR_ALIGN |\
324 ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
325 ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
326 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
327 when no regular conversion is on-going */
328
329 /* Timeout values for ADC operations (enable settling time, */
330 /* disable settling time, ...). */
331 /* Values defined to be higher than worst cases: low clock frequency, */
332 /* maximum prescalers. */
333 #define ADC_ENABLE_TIMEOUT (2UL) /*!< ADC enable time-out value */
334 #define ADC_DISABLE_TIMEOUT (2UL) /*!< ADC disable time-out value */
335
336 /* Timeout to wait for current conversion on going to be completed. */
337 /* Timeout fixed to longest ADC conversion possible, for 1 channel: */
338 /* - maximum sampling time (640.5 adc_clk) */
339 /* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */
340 /* - System clock / ADC clock <= 4096 (hypothesis of maximum clock ratio) */
341 /* - ADC oversampling ratio 256 */
342 /* Calculation: 653 * 4096 * 256 CPU clock cycles max */
343 /* Unit: cycles of CPU clock. */
344 #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL) /*!< ADC conversion completion time-out value */
345
346
347 /**
348 * @}
349 */
350
351 /* Private macro -------------------------------------------------------------*/
352 /* Private variables ---------------------------------------------------------*/
353 /* Private function prototypes -----------------------------------------------*/
354 /* Exported functions --------------------------------------------------------*/
355
356 /** @defgroup ADC_Exported_Functions ADC Exported Functions
357 * @{
358 */
359
360 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
361 * @brief ADC Initialization and Configuration functions
362 *
363 @verbatim
364 ===============================================================================
365 ##### Initialization and de-initialization functions #####
366 ===============================================================================
367 [..] This section provides functions allowing to:
368 (+) Initialize and configure the ADC.
369 (+) De-initialize the ADC.
370 @endverbatim
371 * @{
372 */
373
374 /**
375 * @brief Initialize the ADC peripheral and regular group according to
376 * parameters specified in structure "ADC_InitTypeDef".
377 * @note As prerequisite, ADC clock must be configured at RCC top level
378 * (refer to description of RCC configuration for ADC
379 * in header of this file).
380 * @note Possibility to update parameters on the fly:
381 * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
382 * coming from ADC state reset. Following calls to this function can
383 * be used to reconfigure some parameters of ADC_InitTypeDef
384 * structure on the fly, without modifying MSP configuration. If ADC
385 * MSP has to be modified again, HAL_ADC_DeInit() must be called
386 * before HAL_ADC_Init().
387 * The setting of these parameters is conditioned to ADC state.
388 * For parameters constraints, see comments of structure
389 * "ADC_InitTypeDef".
390 * @note This function configures the ADC within 2 scopes: scope of entire
391 * ADC and scope of regular group. For parameters details, see comments
392 * of structure "ADC_InitTypeDef".
393 * @note Parameters related to common ADC registers (ADC clock mode) are set
394 * only if all ADCs are disabled.
395 * If this is not the case, these common parameters setting are
396 * bypassed without error reporting: it can be the intended behaviour in
397 * case of update of a parameter of ADC_InitTypeDef on the fly,
398 * without disabling the other ADCs.
399 * @param hadc ADC handle
400 * @retval HAL status
401 */
HAL_ADC_Init(ADC_HandleTypeDef * hadc)402 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
403 {
404 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
405 uint32_t tmpCFGR;
406 uint32_t tmp_adc_reg_is_conversion_on_going;
407 __IO uint32_t wait_loop_index = 0UL;
408 uint32_t tmp_adc_is_conversion_on_going_regular;
409 uint32_t tmp_adc_is_conversion_on_going_injected;
410
411 /* Check ADC handle */
412 if (hadc == NULL)
413 {
414 return HAL_ERROR;
415 }
416
417 /* Check the parameters */
418 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
419 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
420 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
421 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
422 assert_param(IS_ADC_DFSDMCFG_MODE(hadc));
423 #endif
424 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
425 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
426 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
427 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
428 assert_param(IS_ADC_EXTTRIG(hadc, hadc->Init.ExternalTrigConv));
429 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
430 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
431 assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
432 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
433 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
434
435 if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
436 {
437 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
438 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
439
440 if (hadc->Init.DiscontinuousConvMode == ENABLE)
441 {
442 assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
443 }
444 }
445
446 /* DISCEN and CONT bits cannot be set at the same time */
447 assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
448
449 /* Actions performed only if ADC is coming from state reset: */
450 /* - Initialization of ADC MSP */
451 if (hadc->State == HAL_ADC_STATE_RESET)
452 {
453 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
454 /* Init the ADC Callback settings */
455 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
456 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
457 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
458 hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
459 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
460 hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */
461 hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */
462 hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */
463 hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */
464
465 if (hadc->MspInitCallback == NULL)
466 {
467 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
468 }
469
470 /* Init the low level hardware */
471 hadc->MspInitCallback(hadc);
472 #else
473 /* Init the low level hardware */
474 HAL_ADC_MspInit(hadc);
475 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
476
477 /* Set ADC error code to none */
478 ADC_CLEAR_ERRORCODE(hadc);
479
480 /* Initialize Lock */
481 hadc->Lock = HAL_UNLOCKED;
482 }
483
484 /* - Exit from deep-power-down mode and ADC voltage regulator enable */
485 if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
486 {
487 /* Disable ADC deep power down mode */
488 LL_ADC_DisableDeepPowerDown(hadc->Instance);
489
490 /* System was in deep power down mode, calibration must
491 be relaunched or a previously saved calibration factor
492 re-applied once the ADC voltage regulator is enabled */
493 }
494
495 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
496 {
497 /* Enable ADC internal voltage regulator */
498 LL_ADC_EnableInternalRegulator(hadc->Instance);
499
500 /* Note: Variable divided by 2 to compensate partially */
501 /* CPU processing cycles, scaling in us split to not */
502 /* exceed 32 bits register capacity and handle low frequency. */
503 wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
504 while (wait_loop_index != 0UL)
505 {
506 wait_loop_index--;
507 }
508 }
509
510 /* Verification that ADC voltage regulator is correctly enabled, whether */
511 /* or not ADC is coming from state reset (if any potential problem of */
512 /* clocking, voltage regulator would not be enabled). */
513 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
514 {
515 /* Update ADC state machine to error */
516 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
517
518 /* Set ADC error code to ADC peripheral internal error */
519 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
520
521 tmp_hal_status = HAL_ERROR;
522 }
523
524 /* Configuration of ADC parameters if previous preliminary actions are */
525 /* correctly completed and if there is no conversion on going on regular */
526 /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
527 /* called to update a parameter on the fly). */
528 tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
529
530 if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
531 && (tmp_adc_reg_is_conversion_on_going == 0UL)
532 )
533 {
534 /* Set ADC state */
535 ADC_STATE_CLR_SET(hadc->State,
536 HAL_ADC_STATE_REG_BUSY,
537 HAL_ADC_STATE_BUSY_INTERNAL);
538
539 /* Configuration of common ADC parameters */
540
541 /* Parameters update conditioned to ADC state: */
542 /* Parameters that can be updated only when ADC is disabled: */
543 /* - clock configuration */
544 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
545 {
546 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
547 {
548 /* Reset configuration of ADC common register CCR: */
549 /* */
550 /* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */
551 /* according to adc->Init.ClockPrescaler. It selects the clock */
552 /* source and sets the clock division factor. */
553 /* */
554 /* Some parameters of this register are not reset, since they are set */
555 /* by other functions and must be kept in case of usage of this */
556 /* function on the fly (update of a parameter of ADC_InitTypeDef */
557 /* without needing to reconfigure all other ADC groups/channels */
558 /* parameters): */
559 /* - when multimode feature is available, multimode-related */
560 /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
561 /* HAL_ADCEx_MultiModeConfigChannel() ) */
562 /* - internal measurement paths: Vbat, temperature sensor, Vref */
563 /* (set into HAL_ADC_ConfigChannel() or */
564 /* HAL_ADCEx_InjectedConfigChannel() ) */
565 LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
566 }
567 }
568
569 /* Configuration of ADC: */
570 /* - resolution Init.Resolution */
571 /* - data alignment Init.DataAlign */
572 /* - external trigger to start conversion Init.ExternalTrigConv */
573 /* - external trigger polarity Init.ExternalTrigConvEdge */
574 /* - continuous conversion mode Init.ContinuousConvMode */
575 /* - overrun Init.Overrun */
576 /* - discontinuous mode Init.DiscontinuousConvMode */
577 /* - discontinuous mode channel count Init.NbrOfDiscConversion */
578 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
579 hadc->Init.Overrun |
580 hadc->Init.DataAlign |
581 hadc->Init.Resolution |
582 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
583
584 if (hadc->Init.DiscontinuousConvMode == ENABLE)
585 {
586 tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
587 }
588
589 /* Enable external trigger if trigger selection is different of software */
590 /* start. */
591 /* Note: This configuration keeps the hardware feature of parameter */
592 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
593 /* software start. */
594 if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
595 {
596 tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
597 | hadc->Init.ExternalTrigConvEdge
598 );
599 }
600
601 /* Update Configuration Register CFGR */
602 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
603
604 /* Parameters update conditioned to ADC state: */
605 /* Parameters that can be updated when ADC is disabled or enabled without */
606 /* conversion on going on regular and injected groups: */
607 /* - DMA continuous request Init.DMAContinuousRequests */
608 /* - LowPowerAutoWait feature Init.LowPowerAutoWait */
609 /* - Oversampling parameters Init.Oversampling */
610 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
611 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
612 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
613 && (tmp_adc_is_conversion_on_going_injected == 0UL)
614 )
615 {
616 tmpCFGR = (ADC_CFGR_DFSDM(hadc) |
617 ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
618 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
619
620 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
621
622 if (hadc->Init.OversamplingMode == ENABLE)
623 {
624 assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
625 assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
626 assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
627 assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
628
629 /* Configuration of Oversampler: */
630 /* - Oversampling Ratio */
631 /* - Right bit shift */
632 /* - Triggered mode */
633 /* - Oversampling mode (continued/resumed) */
634 MODIFY_REG(hadc->Instance->CFGR2,
635 ADC_CFGR2_OVSR |
636 ADC_CFGR2_OVSS |
637 ADC_CFGR2_TROVS |
638 ADC_CFGR2_ROVSM,
639 ADC_CFGR2_ROVSE |
640 hadc->Init.Oversampling.Ratio |
641 hadc->Init.Oversampling.RightBitShift |
642 hadc->Init.Oversampling.TriggeredMode |
643 hadc->Init.Oversampling.OversamplingStopReset
644 );
645 }
646 else
647 {
648 /* Disable ADC oversampling scope on ADC group regular */
649 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
650 }
651
652 }
653
654 /* Configuration of regular group sequencer: */
655 /* - if scan mode is disabled, regular channels sequence length is set to */
656 /* 0x00: 1 channel converted (channel on regular rank 1) */
657 /* Parameter "NbrOfConversion" is discarded. */
658 /* Note: Scan mode is not present by hardware on this device, but */
659 /* emulated by software for alignment over all STM32 devices. */
660 /* - if scan mode is enabled, regular channels sequence length is set to */
661 /* parameter "NbrOfConversion". */
662
663 if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
664 {
665 /* Set number of ranks in regular group sequencer */
666 MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
667 }
668 else
669 {
670 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
671 }
672
673 /* Initialize the ADC state */
674 /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
675 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
676 }
677 else
678 {
679 /* Update ADC state machine to error */
680 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
681
682 tmp_hal_status = HAL_ERROR;
683 }
684
685 /* Return function status */
686 return tmp_hal_status;
687 }
688
689 /**
690 * @brief Deinitialize the ADC peripheral registers to their default reset
691 * values, with deinitialization of the ADC MSP.
692 * @note For devices with several ADCs: reset of ADC common registers is done
693 * only if all ADCs sharing the same common group are disabled.
694 * (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
695 * all ADC instances use the same core clock at RCC level, disabling
696 * the core clock reset all ADC instances).
697 * If this is not the case, reset of these common parameters reset is
698 * bypassed without error reporting: it can be the intended behavior in
699 * case of reset of a single ADC while the other ADCs sharing the same
700 * common group is still running.
701 * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
702 * this saves more power by reducing leakage currents
703 * and is particularly interesting before entering MCU low-power modes.
704 * @param hadc ADC handle
705 * @retval HAL status
706 */
HAL_ADC_DeInit(ADC_HandleTypeDef * hadc)707 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
708 {
709 HAL_StatusTypeDef tmp_hal_status;
710
711 /* Check ADC handle */
712 if (hadc == NULL)
713 {
714 return HAL_ERROR;
715 }
716
717 /* Check the parameters */
718 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
719
720 /* Set ADC state */
721 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
722
723 /* Stop potential conversion on going */
724 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
725
726 /* Disable ADC peripheral if conversions are effectively stopped */
727 /* Flush register JSQR: reset the queue sequencer when injected */
728 /* queue sequencer is enabled and ADC disabled. */
729 /* The software and hardware triggers of the injected sequence are both */
730 /* internally disabled just after the completion of the last valid */
731 /* injected sequence. */
732 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
733
734 /* Disable ADC peripheral if conversions are effectively stopped */
735 if (tmp_hal_status == HAL_OK)
736 {
737 /* Disable the ADC peripheral */
738 tmp_hal_status = ADC_Disable(hadc);
739
740 /* Check if ADC is effectively disabled */
741 if (tmp_hal_status == HAL_OK)
742 {
743 /* Change ADC state */
744 hadc->State = HAL_ADC_STATE_READY;
745 }
746 }
747
748 /* Note: HAL ADC deInit is done independently of ADC conversion stop */
749 /* and disable return status. In case of status fail, attempt to */
750 /* perform deinitialization anyway and it is up user code in */
751 /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */
752 /* system RCC hard reset. */
753
754 /* ========== Reset ADC registers ========== */
755 /* Reset register IER */
756 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
757 ADC_IT_JQOVF | ADC_IT_OVR |
758 ADC_IT_JEOS | ADC_IT_JEOC |
759 ADC_IT_EOS | ADC_IT_EOC |
760 ADC_IT_EOSMP | ADC_IT_RDY));
761
762 /* Reset register ISR */
763 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
764 ADC_FLAG_JQOVF | ADC_FLAG_OVR |
765 ADC_FLAG_JEOS | ADC_FLAG_JEOC |
766 ADC_FLAG_EOS | ADC_FLAG_EOC |
767 ADC_FLAG_EOSMP | ADC_FLAG_RDY));
768
769 /* Reset register CR */
770 /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
771 ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
772 no direct reset applicable.
773 Update CR register to reset value where doable by software */
774 CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
775 SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
776
777 /* Reset register CFGR */
778 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS);
779 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
780
781 /* Reset register CFGR2 */
782 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS |
783 ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
784
785 /* Reset register SMPR1 */
786 CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
787
788 /* Reset register SMPR2 */
789 CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
790 ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
791 ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
792
793 /* Reset register TR1 */
794 CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1);
795
796 /* Reset register TR2 */
797 CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
798
799 /* Reset register TR3 */
800 CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
801
802 /* Reset register SQR1 */
803 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
804 ADC_SQR1_SQ1 | ADC_SQR1_L);
805
806 /* Reset register SQR2 */
807 CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
808 ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
809
810 /* Reset register SQR3 */
811 CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
812 ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
813
814 /* Reset register SQR4 */
815 CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
816
817 /* Register JSQR was reset when the ADC was disabled */
818
819 /* Reset register DR */
820 /* bits in access mode read only, no direct reset applicable*/
821
822 /* Reset register OFR1 */
823 CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
824 /* Reset register OFR2 */
825 CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
826 /* Reset register OFR3 */
827 CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
828 /* Reset register OFR4 */
829 CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
830
831 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
832 /* bits in access mode read only, no direct reset applicable*/
833
834 /* Reset register AWD2CR */
835 CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
836
837 /* Reset register AWD3CR */
838 CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
839
840 /* Reset register DIFSEL */
841 CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
842
843 /* Reset register CALFACT */
844 CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
845
846
847 /* ========== Reset common ADC registers ========== */
848
849 /* Software is allowed to change common parameters only when all the other
850 ADCs are disabled. */
851 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
852 {
853 /* Reset configuration of ADC common register CCR:
854 - clock mode: CKMODE, PRESCEN
855 - multimode related parameters (when this feature is available): MDMA,
856 DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API)
857 - internal measurement paths: Vbat, temperature sensor, Vref (set into
858 HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
859 */
860 ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
861 }
862
863 /* DeInit the low level hardware.
864
865 For example:
866 __HAL_RCC_ADC_FORCE_RESET();
867 __HAL_RCC_ADC_RELEASE_RESET();
868 __HAL_RCC_ADC_CLK_DISABLE();
869
870 Keep in mind that all ADCs use the same clock: disabling
871 the clock will reset all ADCs.
872
873 */
874 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
875 if (hadc->MspDeInitCallback == NULL)
876 {
877 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
878 }
879
880 /* DeInit the low level hardware: RCC clock, NVIC */
881 hadc->MspDeInitCallback(hadc);
882 #else
883 /* DeInit the low level hardware: RCC clock, NVIC */
884 HAL_ADC_MspDeInit(hadc);
885 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
886
887 /* Set ADC error code to none */
888 ADC_CLEAR_ERRORCODE(hadc);
889
890 /* Reset injected channel configuration parameters */
891 hadc->InjectionConfig.ContextQueue = 0;
892 hadc->InjectionConfig.ChannelCount = 0;
893
894 /* Set ADC state */
895 hadc->State = HAL_ADC_STATE_RESET;
896
897 /* Process unlocked */
898 __HAL_UNLOCK(hadc);
899
900 /* Return function status */
901 return tmp_hal_status;
902 }
903
904 /**
905 * @brief Initialize the ADC MSP.
906 * @param hadc ADC handle
907 * @retval None
908 */
HAL_ADC_MspInit(ADC_HandleTypeDef * hadc)909 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
910 {
911 /* Prevent unused argument(s) compilation warning */
912 UNUSED(hadc);
913
914 /* NOTE : This function should not be modified. When the callback is needed,
915 function HAL_ADC_MspInit must be implemented in the user file.
916 */
917 }
918
919 /**
920 * @brief DeInitialize the ADC MSP.
921 * @param hadc ADC handle
922 * @note All ADC instances use the same core clock at RCC level, disabling
923 * the core clock reset all ADC instances).
924 * @retval None
925 */
HAL_ADC_MspDeInit(ADC_HandleTypeDef * hadc)926 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
927 {
928 /* Prevent unused argument(s) compilation warning */
929 UNUSED(hadc);
930
931 /* NOTE : This function should not be modified. When the callback is needed,
932 function HAL_ADC_MspDeInit must be implemented in the user file.
933 */
934 }
935
936 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
937 /**
938 * @brief Register a User ADC Callback
939 * To be used instead of the weak predefined callback
940 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
941 * the configuration information for the specified ADC.
942 * @param CallbackID ID of the callback to be registered
943 * This parameter can be one of the following values:
944 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
945 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
946 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
947 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
948 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
949 * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
950 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
951 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
952 * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
953 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
954 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
955 * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
956 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
957 * @param pCallback pointer to the Callback function
958 * @retval HAL status
959 */
HAL_ADC_RegisterCallback(ADC_HandleTypeDef * hadc,HAL_ADC_CallbackIDTypeDef CallbackID,pADC_CallbackTypeDef pCallback)960 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
961 {
962 HAL_StatusTypeDef status = HAL_OK;
963
964 if (pCallback == NULL)
965 {
966 /* Update the error code */
967 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
968
969 return HAL_ERROR;
970 }
971
972 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
973 {
974 switch (CallbackID)
975 {
976 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
977 hadc->ConvCpltCallback = pCallback;
978 break;
979
980 case HAL_ADC_CONVERSION_HALF_CB_ID :
981 hadc->ConvHalfCpltCallback = pCallback;
982 break;
983
984 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
985 hadc->LevelOutOfWindowCallback = pCallback;
986 break;
987
988 case HAL_ADC_ERROR_CB_ID :
989 hadc->ErrorCallback = pCallback;
990 break;
991
992 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
993 hadc->InjectedConvCpltCallback = pCallback;
994 break;
995
996 case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
997 hadc->InjectedQueueOverflowCallback = pCallback;
998 break;
999
1000 case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
1001 hadc->LevelOutOfWindow2Callback = pCallback;
1002 break;
1003
1004 case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
1005 hadc->LevelOutOfWindow3Callback = pCallback;
1006 break;
1007
1008 case HAL_ADC_END_OF_SAMPLING_CB_ID :
1009 hadc->EndOfSamplingCallback = pCallback;
1010 break;
1011
1012 case HAL_ADC_MSPINIT_CB_ID :
1013 hadc->MspInitCallback = pCallback;
1014 break;
1015
1016 case HAL_ADC_MSPDEINIT_CB_ID :
1017 hadc->MspDeInitCallback = pCallback;
1018 break;
1019
1020 default :
1021 /* Update the error code */
1022 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1023
1024 /* Return error status */
1025 status = HAL_ERROR;
1026 break;
1027 }
1028 }
1029 else if (HAL_ADC_STATE_RESET == hadc->State)
1030 {
1031 switch (CallbackID)
1032 {
1033 case HAL_ADC_MSPINIT_CB_ID :
1034 hadc->MspInitCallback = pCallback;
1035 break;
1036
1037 case HAL_ADC_MSPDEINIT_CB_ID :
1038 hadc->MspDeInitCallback = pCallback;
1039 break;
1040
1041 default :
1042 /* Update the error code */
1043 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1044
1045 /* Return error status */
1046 status = HAL_ERROR;
1047 break;
1048 }
1049 }
1050 else
1051 {
1052 /* Update the error code */
1053 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1054
1055 /* Return error status */
1056 status = HAL_ERROR;
1057 }
1058
1059 return status;
1060 }
1061
1062 /**
1063 * @brief Unregister a ADC Callback
1064 * ADC callback is redirected to the weak predefined callback
1065 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
1066 * the configuration information for the specified ADC.
1067 * @param CallbackID ID of the callback to be unregistered
1068 * This parameter can be one of the following values:
1069 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
1070 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
1071 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
1072 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
1073 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
1074 * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
1075 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
1076 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
1077 * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
1078 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
1079 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
1080 * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
1081 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
1082 * @retval HAL status
1083 */
HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef * hadc,HAL_ADC_CallbackIDTypeDef CallbackID)1084 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
1085 {
1086 HAL_StatusTypeDef status = HAL_OK;
1087
1088 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
1089 {
1090 switch (CallbackID)
1091 {
1092 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
1093 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
1094 break;
1095
1096 case HAL_ADC_CONVERSION_HALF_CB_ID :
1097 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
1098 break;
1099
1100 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
1101 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
1102 break;
1103
1104 case HAL_ADC_ERROR_CB_ID :
1105 hadc->ErrorCallback = HAL_ADC_ErrorCallback;
1106 break;
1107
1108 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
1109 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
1110 break;
1111
1112 case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
1113 hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;
1114 break;
1115
1116 case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
1117 hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
1118 break;
1119
1120 case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
1121 hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
1122 break;
1123
1124 case HAL_ADC_END_OF_SAMPLING_CB_ID :
1125 hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
1126 break;
1127
1128 case HAL_ADC_MSPINIT_CB_ID :
1129 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
1130 break;
1131
1132 case HAL_ADC_MSPDEINIT_CB_ID :
1133 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
1134 break;
1135
1136 default :
1137 /* Update the error code */
1138 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1139
1140 /* Return error status */
1141 status = HAL_ERROR;
1142 break;
1143 }
1144 }
1145 else if (HAL_ADC_STATE_RESET == hadc->State)
1146 {
1147 switch (CallbackID)
1148 {
1149 case HAL_ADC_MSPINIT_CB_ID :
1150 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
1151 break;
1152
1153 case HAL_ADC_MSPDEINIT_CB_ID :
1154 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
1155 break;
1156
1157 default :
1158 /* Update the error code */
1159 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1160
1161 /* Return error status */
1162 status = HAL_ERROR;
1163 break;
1164 }
1165 }
1166 else
1167 {
1168 /* Update the error code */
1169 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1170
1171 /* Return error status */
1172 status = HAL_ERROR;
1173 }
1174
1175 return status;
1176 }
1177
1178 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1179
1180 /**
1181 * @}
1182 */
1183
1184 /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
1185 * @brief ADC IO operation functions
1186 *
1187 @verbatim
1188 ===============================================================================
1189 ##### IO operation functions #####
1190 ===============================================================================
1191 [..] This section provides functions allowing to:
1192 (+) Start conversion of regular group.
1193 (+) Stop conversion of regular group.
1194 (+) Poll for conversion complete on regular group.
1195 (+) Poll for conversion event.
1196 (+) Get result of regular channel conversion.
1197 (+) Start conversion of regular group and enable interruptions.
1198 (+) Stop conversion of regular group and disable interruptions.
1199 (+) Handle ADC interrupt request
1200 (+) Start conversion of regular group and enable DMA transfer.
1201 (+) Stop conversion of regular group and disable ADC DMA transfer.
1202 @endverbatim
1203 * @{
1204 */
1205
1206 /**
1207 * @brief Enable ADC, start conversion of regular group.
1208 * @note Interruptions enabled in this function: None.
1209 * @note Case of multimode enabled (when multimode feature is available):
1210 * if ADC is Slave, ADC is enabled but conversion is not started,
1211 * if ADC is master, ADC is enabled and multimode conversion is started.
1212 * @param hadc ADC handle
1213 * @retval HAL status
1214 */
HAL_ADC_Start(ADC_HandleTypeDef * hadc)1215 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
1216 {
1217 HAL_StatusTypeDef tmp_hal_status;
1218 #if defined(ADC_MULTIMODE_SUPPORT)
1219 const ADC_TypeDef *tmpADC_Master;
1220 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
1221 #endif
1222
1223 /* Check the parameters */
1224 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1225
1226 /* Perform ADC enable and conversion start if no conversion is on going */
1227 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
1228 {
1229 /* Process locked */
1230 __HAL_LOCK(hadc);
1231
1232 /* Enable the ADC peripheral */
1233 tmp_hal_status = ADC_Enable(hadc);
1234
1235 /* Start conversion if ADC is effectively enabled */
1236 if (tmp_hal_status == HAL_OK)
1237 {
1238 /* Set ADC state */
1239 /* - Clear state bitfield related to regular group conversion results */
1240 /* - Set state bitfield related to regular operation */
1241 ADC_STATE_CLR_SET(hadc->State,
1242 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
1243 HAL_ADC_STATE_REG_BUSY);
1244
1245 #if defined(ADC_MULTIMODE_SUPPORT)
1246 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
1247 - if ADC instance is master or if multimode feature is not available
1248 - if multimode setting is disabled (ADC instance slave in independent mode) */
1249 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1250 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1251 )
1252 {
1253 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1254 }
1255 #endif
1256
1257 /* Set ADC error code */
1258 /* Check if a conversion is on going on ADC group injected */
1259 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1260 {
1261 /* Reset ADC error code fields related to regular conversions only */
1262 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1263 }
1264 else
1265 {
1266 /* Reset all ADC error code fields */
1267 ADC_CLEAR_ERRORCODE(hadc);
1268 }
1269
1270 /* Clear ADC group regular conversion flag and overrun flag */
1271 /* (To ensure of no unknown state from potential previous ADC operations) */
1272 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1273
1274 /* Process unlocked */
1275 /* Unlock before starting ADC conversions: in case of potential */
1276 /* interruption, to let the process to ADC IRQ Handler. */
1277 __HAL_UNLOCK(hadc);
1278
1279 /* Enable conversion of regular group. */
1280 /* If software start has been selected, conversion starts immediately. */
1281 /* If external trigger has been selected, conversion will start at next */
1282 /* trigger event. */
1283 /* Case of multimode enabled (when multimode feature is available): */
1284 /* - if ADC is slave and dual regular conversions are enabled, ADC is */
1285 /* enabled only (conversion is not started), */
1286 /* - if ADC is master, ADC is enabled and conversion is started. */
1287 #if defined(ADC_MULTIMODE_SUPPORT)
1288 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1289 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1290 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
1291 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
1292 )
1293 {
1294 /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
1295 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
1296 {
1297 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1298 }
1299
1300 /* Start ADC group regular conversion */
1301 LL_ADC_REG_StartConversion(hadc->Instance);
1302 }
1303 else
1304 {
1305 /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
1306 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1307 /* if Master ADC JAUTO bit is set, update Slave State in setting
1308 HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
1309 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
1310 if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
1311 {
1312 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1313 }
1314
1315 }
1316 #else
1317 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
1318 {
1319 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1320 }
1321
1322 /* Start ADC group regular conversion */
1323 LL_ADC_REG_StartConversion(hadc->Instance);
1324 #endif
1325 }
1326 else
1327 {
1328 /* Process unlocked */
1329 __HAL_UNLOCK(hadc);
1330 }
1331 }
1332 else
1333 {
1334 tmp_hal_status = HAL_BUSY;
1335 }
1336
1337 /* Return function status */
1338 return tmp_hal_status;
1339 }
1340
1341 /**
1342 * @brief Stop ADC conversion of regular group (and injected channels in
1343 * case of auto_injection mode), disable ADC peripheral.
1344 * @note: ADC peripheral disable is forcing stop of potential
1345 * conversion on injected group. If injected group is under use, it
1346 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
1347 * @param hadc ADC handle
1348 * @retval HAL status.
1349 */
HAL_ADC_Stop(ADC_HandleTypeDef * hadc)1350 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
1351 {
1352 HAL_StatusTypeDef tmp_hal_status;
1353
1354 /* Check the parameters */
1355 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1356
1357 /* Process locked */
1358 __HAL_LOCK(hadc);
1359
1360 /* 1. Stop potential conversion on going, on ADC groups regular and injected */
1361 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
1362
1363 /* Disable ADC peripheral if conversions are effectively stopped */
1364 if (tmp_hal_status == HAL_OK)
1365 {
1366 /* 2. Disable the ADC peripheral */
1367 tmp_hal_status = ADC_Disable(hadc);
1368
1369 /* Check if ADC is effectively disabled */
1370 if (tmp_hal_status == HAL_OK)
1371 {
1372 /* Set ADC state */
1373 ADC_STATE_CLR_SET(hadc->State,
1374 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1375 HAL_ADC_STATE_READY);
1376 }
1377 }
1378
1379 /* Process unlocked */
1380 __HAL_UNLOCK(hadc);
1381
1382 /* Return function status */
1383 return tmp_hal_status;
1384 }
1385
1386 /**
1387 * @brief Wait for regular group conversion to be completed.
1388 * @note ADC conversion flags EOS (end of sequence) and EOC (end of
1389 * conversion) are cleared by this function, with an exception:
1390 * if low power feature "LowPowerAutoWait" is enabled, flags are
1391 * not cleared to not interfere with this feature until data register
1392 * is read using function HAL_ADC_GetValue().
1393 * @note This function cannot be used in a particular setup: ADC configured
1394 * in DMA mode and polling for end of each conversion (ADC init
1395 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
1396 * In this case, DMA resets the flag EOC and polling cannot be
1397 * performed on each conversion. Nevertheless, polling can still
1398 * be performed on the complete sequence (ADC init
1399 * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
1400 * @param hadc ADC handle
1401 * @param Timeout Timeout value in millisecond.
1402 * @retval HAL status
1403 */
HAL_ADC_PollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)1404 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
1405 {
1406 uint32_t tickstart;
1407 uint32_t tmp_Flag_End;
1408 uint32_t tmp_cfgr;
1409 #if defined(ADC_MULTIMODE_SUPPORT)
1410 const ADC_TypeDef *tmpADC_Master;
1411 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
1412 #endif
1413
1414 /* Check the parameters */
1415 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1416
1417 /* If end of conversion selected to end of sequence conversions */
1418 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
1419 {
1420 tmp_Flag_End = ADC_FLAG_EOS;
1421 }
1422 /* If end of conversion selected to end of unitary conversion */
1423 else /* ADC_EOC_SINGLE_CONV */
1424 {
1425 /* Verification that ADC configuration is compliant with polling for */
1426 /* each conversion: */
1427 /* Particular case is ADC configured in DMA mode and ADC sequencer with */
1428 /* several ranks and polling for end of each conversion. */
1429 /* For code simplicity sake, this particular case is generalized to */
1430 /* ADC configured in DMA mode and and polling for end of each conversion. */
1431 #if defined(ADC_MULTIMODE_SUPPORT)
1432 if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1433 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
1434 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
1435 )
1436 {
1437 /* Check ADC DMA mode in independent mode on ADC group regular */
1438 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
1439 {
1440 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1441 return HAL_ERROR;
1442 }
1443 else
1444 {
1445 tmp_Flag_End = (ADC_FLAG_EOC);
1446 }
1447 }
1448 else
1449 {
1450 /* Check ADC DMA mode in multimode on ADC group regular */
1451 if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
1452 {
1453 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1454 return HAL_ERROR;
1455 }
1456 else
1457 {
1458 tmp_Flag_End = (ADC_FLAG_EOC);
1459 }
1460 }
1461 #else
1462 /* Check ADC DMA mode */
1463 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
1464 {
1465 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1466 return HAL_ERROR;
1467 }
1468 else
1469 {
1470 tmp_Flag_End = (ADC_FLAG_EOC);
1471 }
1472 #endif
1473 }
1474
1475 /* Get tick count */
1476 tickstart = HAL_GetTick();
1477
1478 /* Wait until End of unitary conversion or sequence conversions flag is raised */
1479 while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
1480 {
1481 /* Check if timeout is disabled (set to infinite wait) */
1482 if (Timeout != HAL_MAX_DELAY)
1483 {
1484 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
1485 {
1486 /* Update ADC state machine to timeout */
1487 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1488
1489 /* Process unlocked */
1490 __HAL_UNLOCK(hadc);
1491
1492 return HAL_TIMEOUT;
1493 }
1494 }
1495 }
1496
1497 /* Update ADC state machine */
1498 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1499
1500 /* Determine whether any further conversion upcoming on group regular */
1501 /* by external trigger, continuous mode or scan sequence on going. */
1502 if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
1503 && (hadc->Init.ContinuousConvMode == DISABLE)
1504 )
1505 {
1506 /* Check whether end of sequence is reached */
1507 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
1508 {
1509 /* Set ADC state */
1510 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1511
1512 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
1513 {
1514 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1515 }
1516 }
1517 }
1518
1519 /* Get relevant register CFGR in ADC instance of ADC master or slave */
1520 /* in function of multimode state (for devices with multimode */
1521 /* available). */
1522 #if defined(ADC_MULTIMODE_SUPPORT)
1523 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1524 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1525 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
1526 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
1527 )
1528 {
1529 /* Retrieve handle ADC CFGR register */
1530 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
1531 }
1532 else
1533 {
1534 /* Retrieve Master ADC CFGR register */
1535 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
1536 tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
1537 }
1538 #else
1539 /* Retrieve handle ADC CFGR register */
1540 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
1541 #endif
1542
1543 /* Clear polled flag */
1544 if (tmp_Flag_End == ADC_FLAG_EOS)
1545 {
1546 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
1547 }
1548 else
1549 {
1550 /* Clear end of conversion EOC flag of regular group if low power feature */
1551 /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
1552 /* until data register is read using function HAL_ADC_GetValue(). */
1553 if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
1554 {
1555 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
1556 }
1557 }
1558
1559 /* Return function status */
1560 return HAL_OK;
1561 }
1562
1563 /**
1564 * @brief Poll for ADC event.
1565 * @param hadc ADC handle
1566 * @param EventType the ADC event type.
1567 * This parameter can be one of the following values:
1568 * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
1569 * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
1570 * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
1571 * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
1572 * @arg @ref ADC_OVR_EVENT ADC Overrun event
1573 * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event
1574 * @param Timeout Timeout value in millisecond.
1575 * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
1576 * Indeed, the latter is reset only if hadc->Init.Overrun field is set
1577 * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
1578 * by a new converted data as soon as OVR is cleared.
1579 * To reset OVR flag once the preserved data is retrieved, the user can resort
1580 * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1581 * @retval HAL status
1582 */
HAL_ADC_PollForEvent(ADC_HandleTypeDef * hadc,uint32_t EventType,uint32_t Timeout)1583 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
1584 {
1585 uint32_t tickstart;
1586
1587 /* Check the parameters */
1588 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1589 assert_param(IS_ADC_EVENT_TYPE(EventType));
1590
1591 /* Get tick count */
1592 tickstart = HAL_GetTick();
1593
1594 /* Check selected event flag */
1595 while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
1596 {
1597 /* Check if timeout is disabled (set to infinite wait) */
1598 if (Timeout != HAL_MAX_DELAY)
1599 {
1600 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
1601 {
1602 /* Update ADC state machine to timeout */
1603 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1604
1605 /* Process unlocked */
1606 __HAL_UNLOCK(hadc);
1607
1608 return HAL_TIMEOUT;
1609 }
1610 }
1611 }
1612
1613 switch (EventType)
1614 {
1615 /* End Of Sampling event */
1616 case ADC_EOSMP_EVENT:
1617 /* Set ADC state */
1618 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
1619
1620 /* Clear the End Of Sampling flag */
1621 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
1622
1623 break;
1624
1625 /* Analog watchdog (level out of window) event */
1626 /* Note: In case of several analog watchdog enabled, if needed to know */
1627 /* which one triggered and on which ADCx, test ADC state of analog watchdog */
1628 /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */
1629 /* For example: */
1630 /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */
1631 /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */
1632 /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */
1633
1634 /* Check analog watchdog 1 flag */
1635 case ADC_AWD_EVENT:
1636 /* Set ADC state */
1637 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1638
1639 /* Clear ADC analog watchdog flag */
1640 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
1641
1642 break;
1643
1644 /* Check analog watchdog 2 flag */
1645 case ADC_AWD2_EVENT:
1646 /* Set ADC state */
1647 SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
1648
1649 /* Clear ADC analog watchdog flag */
1650 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
1651
1652 break;
1653
1654 /* Check analog watchdog 3 flag */
1655 case ADC_AWD3_EVENT:
1656 /* Set ADC state */
1657 SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
1658
1659 /* Clear ADC analog watchdog flag */
1660 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
1661
1662 break;
1663
1664 /* Injected context queue overflow event */
1665 case ADC_JQOVF_EVENT:
1666 /* Set ADC state */
1667 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
1668
1669 /* Set ADC error code to Injected context queue overflow */
1670 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
1671
1672 /* Clear ADC Injected context queue overflow flag */
1673 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
1674
1675 break;
1676
1677 /* Overrun event */
1678 default: /* Case ADC_OVR_EVENT */
1679 /* If overrun is set to overwrite previous data, overrun event is not */
1680 /* considered as an error. */
1681 /* (cf ref manual "Managing conversions without using the DMA and without */
1682 /* overrun ") */
1683 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
1684 {
1685 /* Set ADC state */
1686 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
1687
1688 /* Set ADC error code to overrun */
1689 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
1690 }
1691 else
1692 {
1693 /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
1694 otherwise, data register is potentially overwritten by new converted data as soon
1695 as OVR is cleared. */
1696 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1697 }
1698 break;
1699 }
1700
1701 /* Return function status */
1702 return HAL_OK;
1703 }
1704
1705 /**
1706 * @brief Enable ADC, start conversion of regular group with interruption.
1707 * @note Interruptions enabled in this function according to initialization
1708 * setting : EOC (end of conversion), EOS (end of sequence),
1709 * OVR overrun.
1710 * Each of these interruptions has its dedicated callback function.
1711 * @note Case of multimode enabled (when multimode feature is available):
1712 * HAL_ADC_Start_IT() must be called for ADC Slave first, then for
1713 * ADC Master.
1714 * For ADC Slave, ADC is enabled only (conversion is not started).
1715 * For ADC Master, ADC is enabled and multimode conversion is started.
1716 * @note To guarantee a proper reset of all interruptions once all the needed
1717 * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
1718 * a correct stop of the IT-based conversions.
1719 * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
1720 * interruption. If required (e.g. in case of oversampling with trigger
1721 * mode), the user must:
1722 * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
1723 * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
1724 * before calling HAL_ADC_Start_IT().
1725 * @param hadc ADC handle
1726 * @retval HAL status
1727 */
HAL_ADC_Start_IT(ADC_HandleTypeDef * hadc)1728 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
1729 {
1730 HAL_StatusTypeDef tmp_hal_status;
1731 #if defined(ADC_MULTIMODE_SUPPORT)
1732 const ADC_TypeDef *tmpADC_Master;
1733 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
1734 #endif
1735
1736 /* Check the parameters */
1737 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1738
1739 /* Perform ADC enable and conversion start if no conversion is on going */
1740 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
1741 {
1742 /* Process locked */
1743 __HAL_LOCK(hadc);
1744
1745 /* Enable the ADC peripheral */
1746 tmp_hal_status = ADC_Enable(hadc);
1747
1748 /* Start conversion if ADC is effectively enabled */
1749 if (tmp_hal_status == HAL_OK)
1750 {
1751 /* Set ADC state */
1752 /* - Clear state bitfield related to regular group conversion results */
1753 /* - Set state bitfield related to regular operation */
1754 ADC_STATE_CLR_SET(hadc->State,
1755 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
1756 HAL_ADC_STATE_REG_BUSY);
1757
1758 #if defined(ADC_MULTIMODE_SUPPORT)
1759 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
1760 - if ADC instance is master or if multimode feature is not available
1761 - if multimode setting is disabled (ADC instance slave in independent mode) */
1762 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1763 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1764 )
1765 {
1766 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1767 }
1768 #endif
1769
1770 /* Set ADC error code */
1771 /* Check if a conversion is on going on ADC group injected */
1772 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
1773 {
1774 /* Reset ADC error code fields related to regular conversions only */
1775 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1776 }
1777 else
1778 {
1779 /* Reset all ADC error code fields */
1780 ADC_CLEAR_ERRORCODE(hadc);
1781 }
1782
1783 /* Clear ADC group regular conversion flag and overrun flag */
1784 /* (To ensure of no unknown state from potential previous ADC operations) */
1785 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1786
1787 /* Process unlocked */
1788 /* Unlock before starting ADC conversions: in case of potential */
1789 /* interruption, to let the process to ADC IRQ Handler. */
1790 __HAL_UNLOCK(hadc);
1791
1792 /* Disable all interruptions before enabling the desired ones */
1793 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
1794
1795 /* Enable ADC end of conversion interrupt */
1796 switch (hadc->Init.EOCSelection)
1797 {
1798 case ADC_EOC_SEQ_CONV:
1799 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
1800 break;
1801 /* case ADC_EOC_SINGLE_CONV */
1802 default:
1803 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
1804 break;
1805 }
1806
1807 /* Enable ADC overrun interrupt */
1808 /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
1809 ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
1810 behavior and no CPU time is lost for a non-processed interruption */
1811 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
1812 {
1813 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
1814 }
1815
1816 /* Enable conversion of regular group. */
1817 /* If software start has been selected, conversion starts immediately. */
1818 /* If external trigger has been selected, conversion will start at next */
1819 /* trigger event. */
1820 /* Case of multimode enabled (when multimode feature is available): */
1821 /* - if ADC is slave and dual regular conversions are enabled, ADC is */
1822 /* enabled only (conversion is not started), */
1823 /* - if ADC is master, ADC is enabled and conversion is started. */
1824 #if defined(ADC_MULTIMODE_SUPPORT)
1825 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1826 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1827 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
1828 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
1829 )
1830 {
1831 /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
1832 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
1833 {
1834 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1835
1836 /* Enable as well injected interruptions in case
1837 HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
1838 allows to start regular and injected conversions when JAUTO is
1839 set with a single call to HAL_ADC_Start_IT() */
1840 switch (hadc->Init.EOCSelection)
1841 {
1842 case ADC_EOC_SEQ_CONV:
1843 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1844 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
1845 break;
1846 /* case ADC_EOC_SINGLE_CONV */
1847 default:
1848 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
1849 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
1850 break;
1851 }
1852 }
1853
1854 /* Start ADC group regular conversion */
1855 LL_ADC_REG_StartConversion(hadc->Instance);
1856 }
1857 else
1858 {
1859 /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
1860 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1861 /* if Master ADC JAUTO bit is set, Slave injected interruptions
1862 are enabled nevertheless (for same reason as above) */
1863 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
1864 if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
1865 {
1866 /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
1867 and in resetting HAL_ADC_STATE_INJ_EOC bit */
1868 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1869 /* Next, set Slave injected interruptions */
1870 switch (hadc->Init.EOCSelection)
1871 {
1872 case ADC_EOC_SEQ_CONV:
1873 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1874 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
1875 break;
1876 /* case ADC_EOC_SINGLE_CONV */
1877 default:
1878 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
1879 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
1880 break;
1881 }
1882 }
1883 }
1884 #else
1885 /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
1886 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
1887 {
1888 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1889
1890 /* Enable as well injected interruptions in case
1891 HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
1892 allows to start regular and injected conversions when JAUTO is
1893 set with a single call to HAL_ADC_Start_IT() */
1894 switch (hadc->Init.EOCSelection)
1895 {
1896 case ADC_EOC_SEQ_CONV:
1897 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1898 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
1899 break;
1900 /* case ADC_EOC_SINGLE_CONV */
1901 default:
1902 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
1903 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
1904 break;
1905 }
1906 }
1907
1908 /* Start ADC group regular conversion */
1909 LL_ADC_REG_StartConversion(hadc->Instance);
1910 #endif
1911 }
1912 else
1913 {
1914 /* Process unlocked */
1915 __HAL_UNLOCK(hadc);
1916 }
1917
1918 }
1919 else
1920 {
1921 tmp_hal_status = HAL_BUSY;
1922 }
1923
1924 /* Return function status */
1925 return tmp_hal_status;
1926 }
1927
1928 /**
1929 * @brief Stop ADC conversion of regular group (and injected group in
1930 * case of auto_injection mode), disable interrution of
1931 * end-of-conversion, disable ADC peripheral.
1932 * @param hadc ADC handle
1933 * @retval HAL status.
1934 */
HAL_ADC_Stop_IT(ADC_HandleTypeDef * hadc)1935 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
1936 {
1937 HAL_StatusTypeDef tmp_hal_status;
1938
1939 /* Check the parameters */
1940 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1941
1942 /* Process locked */
1943 __HAL_LOCK(hadc);
1944
1945 /* 1. Stop potential conversion on going, on ADC groups regular and injected */
1946 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
1947
1948 /* Disable ADC peripheral if conversions are effectively stopped */
1949 if (tmp_hal_status == HAL_OK)
1950 {
1951 /* Disable ADC end of conversion interrupt for regular group */
1952 /* Disable ADC overrun interrupt */
1953 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
1954
1955 /* 2. Disable the ADC peripheral */
1956 tmp_hal_status = ADC_Disable(hadc);
1957
1958 /* Check if ADC is effectively disabled */
1959 if (tmp_hal_status == HAL_OK)
1960 {
1961 /* Set ADC state */
1962 ADC_STATE_CLR_SET(hadc->State,
1963 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1964 HAL_ADC_STATE_READY);
1965 }
1966 }
1967
1968 /* Process unlocked */
1969 __HAL_UNLOCK(hadc);
1970
1971 /* Return function status */
1972 return tmp_hal_status;
1973 }
1974
1975 /**
1976 * @brief Enable ADC, start conversion of regular group and transfer result through DMA.
1977 * @note Interruptions enabled in this function:
1978 * overrun (if applicable), DMA half transfer, DMA transfer complete.
1979 * Each of these interruptions has its dedicated callback function.
1980 * @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
1981 * is designed for single-ADC mode only. For multimode, the dedicated
1982 * HAL_ADCEx_MultiModeStart_DMA() function must be used.
1983 * @param hadc ADC handle
1984 * @param pData Destination Buffer address.
1985 * @param Length Number of data to be transferred from ADC peripheral to memory
1986 * @retval HAL status.
1987 */
HAL_ADC_Start_DMA(ADC_HandleTypeDef * hadc,uint32_t * pData,uint32_t Length)1988 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
1989 {
1990 HAL_StatusTypeDef tmp_hal_status;
1991 #if defined(ADC_MULTIMODE_SUPPORT)
1992 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
1993 #endif
1994
1995 /* Check the parameters */
1996 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1997
1998 /* Perform ADC enable and conversion start if no conversion is on going */
1999 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2000 {
2001 /* Process locked */
2002 __HAL_LOCK(hadc);
2003
2004 #if defined(ADC_MULTIMODE_SUPPORT)
2005 /* Ensure that multimode regular conversions are not enabled. */
2006 /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */
2007 if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
2008 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
2009 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
2010 )
2011 #endif
2012 {
2013 /* Enable the ADC peripheral */
2014 tmp_hal_status = ADC_Enable(hadc);
2015
2016 /* Start conversion if ADC is effectively enabled */
2017 if (tmp_hal_status == HAL_OK)
2018 {
2019 /* Set ADC state */
2020 /* - Clear state bitfield related to regular group conversion results */
2021 /* - Set state bitfield related to regular operation */
2022 ADC_STATE_CLR_SET(hadc->State,
2023 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
2024 HAL_ADC_STATE_REG_BUSY);
2025
2026 #if defined(ADC_MULTIMODE_SUPPORT)
2027 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
2028 - if ADC instance is master or if multimode feature is not available
2029 - if multimode setting is disabled (ADC instance slave in independent mode) */
2030 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
2031 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
2032 )
2033 {
2034 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
2035 }
2036 #endif
2037
2038 /* Check if a conversion is on going on ADC group injected */
2039 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
2040 {
2041 /* Reset ADC error code fields related to regular conversions only */
2042 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
2043 }
2044 else
2045 {
2046 /* Reset all ADC error code fields */
2047 ADC_CLEAR_ERRORCODE(hadc);
2048 }
2049
2050 /* Set the DMA transfer complete callback */
2051 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
2052
2053 /* Set the DMA half transfer complete callback */
2054 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
2055
2056 /* Set the DMA error callback */
2057 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
2058
2059
2060 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */
2061 /* ADC start (in case of SW start): */
2062
2063 /* Clear regular group conversion flag and overrun flag */
2064 /* (To ensure of no unknown state from potential previous ADC */
2065 /* operations) */
2066 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
2067
2068 /* Process unlocked */
2069 /* Unlock before starting ADC conversions: in case of potential */
2070 /* interruption, to let the process to ADC IRQ Handler. */
2071 __HAL_UNLOCK(hadc);
2072
2073 /* With DMA, overrun event is always considered as an error even if
2074 hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
2075 ADC_IT_OVR is enabled. */
2076 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
2077
2078 /* Enable ADC DMA mode */
2079 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
2080
2081 /* Start the DMA channel */
2082 tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
2083
2084 /* Enable conversion of regular group. */
2085 /* If software start has been selected, conversion starts immediately. */
2086 /* If external trigger has been selected, conversion will start at next */
2087 /* trigger event. */
2088 /* Start ADC group regular conversion */
2089 LL_ADC_REG_StartConversion(hadc->Instance);
2090 }
2091 else
2092 {
2093 /* Process unlocked */
2094 __HAL_UNLOCK(hadc);
2095 }
2096
2097 }
2098 #if defined(ADC_MULTIMODE_SUPPORT)
2099 else
2100 {
2101 tmp_hal_status = HAL_ERROR;
2102 /* Process unlocked */
2103 __HAL_UNLOCK(hadc);
2104 }
2105 #endif
2106 }
2107 else
2108 {
2109 tmp_hal_status = HAL_BUSY;
2110 }
2111
2112 /* Return function status */
2113 return tmp_hal_status;
2114 }
2115
2116 /**
2117 * @brief Stop ADC conversion of regular group (and injected group in
2118 * case of auto_injection mode), disable ADC DMA transfer, disable
2119 * ADC peripheral.
2120 * @note: ADC peripheral disable is forcing stop of potential
2121 * conversion on ADC group injected. If ADC group injected is under use, it
2122 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
2123 * @note Case of multimode enabled (when multimode feature is available):
2124 * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
2125 * For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
2126 * @param hadc ADC handle
2127 * @retval HAL status.
2128 */
HAL_ADC_Stop_DMA(ADC_HandleTypeDef * hadc)2129 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
2130 {
2131 HAL_StatusTypeDef tmp_hal_status;
2132
2133 /* Check the parameters */
2134 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2135
2136 /* Process locked */
2137 __HAL_LOCK(hadc);
2138
2139 /* 1. Stop potential ADC group regular conversion on going */
2140 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
2141
2142 /* Disable ADC peripheral if conversions are effectively stopped */
2143 if (tmp_hal_status == HAL_OK)
2144 {
2145 /* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */
2146 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
2147
2148 /* Disable the DMA channel (in case of DMA in circular mode or stop */
2149 /* while DMA transfer is on going) */
2150 if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
2151 {
2152 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
2153
2154 /* Check if DMA channel effectively disabled */
2155 if (tmp_hal_status != HAL_OK)
2156 {
2157 /* Update ADC state machine to error */
2158 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
2159 }
2160 }
2161
2162 /* Disable ADC overrun interrupt */
2163 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
2164
2165 /* 2. Disable the ADC peripheral */
2166 /* Update "tmp_hal_status" only if DMA channel disabling passed, */
2167 /* to keep in memory a potential failing status. */
2168 if (tmp_hal_status == HAL_OK)
2169 {
2170 tmp_hal_status = ADC_Disable(hadc);
2171 }
2172 else
2173 {
2174 (void)ADC_Disable(hadc);
2175 }
2176
2177 /* Check if ADC is effectively disabled */
2178 if (tmp_hal_status == HAL_OK)
2179 {
2180 /* Set ADC state */
2181 ADC_STATE_CLR_SET(hadc->State,
2182 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
2183 HAL_ADC_STATE_READY);
2184 }
2185
2186 }
2187
2188 /* Process unlocked */
2189 __HAL_UNLOCK(hadc);
2190
2191 /* Return function status */
2192 return tmp_hal_status;
2193 }
2194
2195 /**
2196 * @brief Get ADC regular group conversion result.
2197 * @note Reading register DR automatically clears ADC flag EOC
2198 * (ADC group regular end of unitary conversion).
2199 * @note This function does not clear ADC flag EOS
2200 * (ADC group regular end of sequence conversion).
2201 * Occurrence of flag EOS rising:
2202 * - If sequencer is composed of 1 rank, flag EOS is equivalent
2203 * to flag EOC.
2204 * - If sequencer is composed of several ranks, during the scan
2205 * sequence flag EOC only is raised, at the end of the scan sequence
2206 * both flags EOC and EOS are raised.
2207 * To clear this flag, either use function:
2208 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
2209 * model polling: @ref HAL_ADC_PollForConversion()
2210 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
2211 * @param hadc ADC handle
2212 * @retval ADC group regular conversion data
2213 */
HAL_ADC_GetValue(ADC_HandleTypeDef * hadc)2214 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
2215 {
2216 /* Check the parameters */
2217 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2218
2219 /* Note: EOC flag is not cleared here by software because automatically */
2220 /* cleared by hardware when reading register DR. */
2221
2222 /* Return ADC converted value */
2223 return hadc->Instance->DR;
2224 }
2225
2226 /**
2227 * @brief Handle ADC interrupt request.
2228 * @param hadc ADC handle
2229 * @retval None
2230 */
HAL_ADC_IRQHandler(ADC_HandleTypeDef * hadc)2231 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
2232 {
2233 uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
2234 uint32_t tmp_isr = hadc->Instance->ISR;
2235 uint32_t tmp_ier = hadc->Instance->IER;
2236 uint32_t tmp_adc_inj_is_trigger_source_sw_start;
2237 uint32_t tmp_adc_reg_is_trigger_source_sw_start;
2238 uint32_t tmp_cfgr;
2239 #if defined(ADC_MULTIMODE_SUPPORT)
2240 const ADC_TypeDef *tmpADC_Master;
2241 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2242 #endif
2243
2244 /* Check the parameters */
2245 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2246 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
2247
2248 /* ========== Check End of Sampling flag for ADC group regular ========== */
2249 if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
2250 {
2251 /* Update state machine on end of sampling status if not in error state */
2252 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
2253 {
2254 /* Set ADC state */
2255 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
2256 }
2257
2258 /* End Of Sampling callback */
2259 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2260 hadc->EndOfSamplingCallback(hadc);
2261 #else
2262 HAL_ADCEx_EndOfSamplingCallback(hadc);
2263 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2264
2265 /* Clear regular group conversion flag */
2266 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
2267 }
2268
2269 /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
2270 if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
2271 (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
2272 {
2273 /* Update state machine on conversion status if not in error state */
2274 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
2275 {
2276 /* Set ADC state */
2277 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
2278 }
2279
2280 /* Determine whether any further conversion upcoming on group regular */
2281 /* by external trigger, continuous mode or scan sequence on going */
2282 /* to disable interruption. */
2283 if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
2284 {
2285 /* Get relevant register CFGR in ADC instance of ADC master or slave */
2286 /* in function of multimode state (for devices with multimode */
2287 /* available). */
2288 #if defined(ADC_MULTIMODE_SUPPORT)
2289 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
2290 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
2291 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
2292 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
2293 )
2294 {
2295 /* check CONT bit directly in handle ADC CFGR register */
2296 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2297 }
2298 else
2299 {
2300 /* else need to check Master ADC CONT bit */
2301 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
2302 tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
2303 }
2304 #else
2305 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2306 #endif
2307
2308 /* Carry on if continuous mode is disabled */
2309 if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
2310 {
2311 /* If End of Sequence is reached, disable interrupts */
2312 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
2313 {
2314 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
2315 /* ADSTART==0 (no conversion on going) */
2316 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2317 {
2318 /* Disable ADC end of sequence conversion interrupt */
2319 /* Note: Overrun interrupt was enabled with EOC interrupt in */
2320 /* HAL_Start_IT(), but is not disabled here because can be used */
2321 /* by overrun IRQ process below. */
2322 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
2323
2324 /* Set ADC state */
2325 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
2326
2327 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
2328 {
2329 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
2330 }
2331 }
2332 else
2333 {
2334 /* Change ADC state to error state */
2335 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2336
2337 /* Set ADC error code to ADC peripheral internal error */
2338 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2339 }
2340 }
2341 }
2342 }
2343
2344 /* Conversion complete callback */
2345 /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */
2346 /* to determine if conversion has been triggered from EOC or EOS, */
2347 /* possibility to use: */
2348 /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
2349 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2350 hadc->ConvCpltCallback(hadc);
2351 #else
2352 HAL_ADC_ConvCpltCallback(hadc);
2353 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2354
2355 /* Clear regular group conversion flag */
2356 /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
2357 /* conversion flags clear induces the release of the preserved data.*/
2358 /* Therefore, if the preserved data value is needed, it must be */
2359 /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
2360 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
2361 }
2362
2363 /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */
2364 if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
2365 (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
2366 {
2367 /* Update state machine on conversion status if not in error state */
2368 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
2369 {
2370 /* Set ADC state */
2371 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
2372 }
2373
2374 /* Retrieve ADC configuration */
2375 tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
2376 tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
2377 /* Get relevant register CFGR in ADC instance of ADC master or slave */
2378 /* in function of multimode state (for devices with multimode */
2379 /* available). */
2380 #if defined(ADC_MULTIMODE_SUPPORT)
2381 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
2382 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
2383 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
2384 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
2385 )
2386 {
2387 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2388 }
2389 else
2390 {
2391 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
2392 tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
2393 }
2394 #else
2395 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2396 #endif
2397
2398 /* Disable interruption if no further conversion upcoming by injected */
2399 /* external trigger or by automatic injected conversion with regular */
2400 /* group having no further conversion upcoming (same conditions as */
2401 /* regular group interruption disabling above), */
2402 /* and if injected scan sequence is completed. */
2403 if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
2404 ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) &&
2405 ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
2406 (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
2407 {
2408 /* If End of Sequence is reached, disable interrupts */
2409 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
2410 {
2411 /* Particular case if injected contexts queue is enabled: */
2412 /* when the last context has been fully processed, JSQR is reset */
2413 /* by the hardware. Even if no injected conversion is planned to come */
2414 /* (queue empty, triggers are ignored), it can start again */
2415 /* immediately after setting a new context (JADSTART is still set). */
2416 /* Therefore, state of HAL ADC injected group is kept to busy. */
2417 if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
2418 {
2419 /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
2420 /* JADSTART==0 (no conversion on going) */
2421 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
2422 {
2423 /* Disable ADC end of sequence conversion interrupt */
2424 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
2425
2426 /* Set ADC state */
2427 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
2428
2429 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
2430 {
2431 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
2432 }
2433 }
2434 else
2435 {
2436 /* Update ADC state machine to error */
2437 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2438
2439 /* Set ADC error code to ADC peripheral internal error */
2440 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2441 }
2442 }
2443 }
2444 }
2445
2446 /* Injected Conversion complete callback */
2447 /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to
2448 if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
2449 if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
2450 interruption has been triggered by end of conversion or end of
2451 sequence. */
2452 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2453 hadc->InjectedConvCpltCallback(hadc);
2454 #else
2455 HAL_ADCEx_InjectedConvCpltCallback(hadc);
2456 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2457
2458 /* Clear injected group conversion flag */
2459 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
2460 }
2461
2462 /* ========== Check Analog watchdog 1 flag ========== */
2463 if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
2464 {
2465 /* Set ADC state */
2466 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
2467
2468 /* Level out of window 1 callback */
2469 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2470 hadc->LevelOutOfWindowCallback(hadc);
2471 #else
2472 HAL_ADC_LevelOutOfWindowCallback(hadc);
2473 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2474
2475 /* Clear ADC analog watchdog flag */
2476 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
2477 }
2478
2479 /* ========== Check analog watchdog 2 flag ========== */
2480 if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
2481 {
2482 /* Set ADC state */
2483 SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
2484
2485 /* Level out of window 2 callback */
2486 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2487 hadc->LevelOutOfWindow2Callback(hadc);
2488 #else
2489 HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
2490 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2491
2492 /* Clear ADC analog watchdog flag */
2493 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
2494 }
2495
2496 /* ========== Check analog watchdog 3 flag ========== */
2497 if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
2498 {
2499 /* Set ADC state */
2500 SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
2501
2502 /* Level out of window 3 callback */
2503 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2504 hadc->LevelOutOfWindow3Callback(hadc);
2505 #else
2506 HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
2507 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2508
2509 /* Clear ADC analog watchdog flag */
2510 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
2511 }
2512
2513 /* ========== Check Overrun flag ========== */
2514 if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
2515 {
2516 /* If overrun is set to overwrite previous data (default setting), */
2517 /* overrun event is not considered as an error. */
2518 /* (cf ref manual "Managing conversions without using the DMA and without */
2519 /* overrun ") */
2520 /* Exception for usage with DMA overrun event always considered as an */
2521 /* error. */
2522 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
2523 {
2524 overrun_error = 1UL;
2525 }
2526 else
2527 {
2528 /* Check DMA configuration */
2529 #if defined(ADC_MULTIMODE_SUPPORT)
2530 if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT)
2531 {
2532 /* Multimode (when feature is available) is enabled,
2533 Common Control Register MDMA bits must be checked. */
2534 if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
2535 {
2536 overrun_error = 1UL;
2537 }
2538 }
2539 else
2540 #endif
2541 {
2542 /* Multimode not set or feature not available or ADC independent */
2543 if ((hadc->Instance->CFGR & ADC_CFGR_DMAEN) != 0UL)
2544 {
2545 overrun_error = 1UL;
2546 }
2547 }
2548 }
2549
2550 if (overrun_error == 1UL)
2551 {
2552 /* Change ADC state to error state */
2553 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
2554
2555 /* Set ADC error code to overrun */
2556 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
2557
2558 /* Error callback */
2559 /* Note: In case of overrun, ADC conversion data is preserved until */
2560 /* flag OVR is reset. */
2561 /* Therefore, old ADC conversion data can be retrieved in */
2562 /* function "HAL_ADC_ErrorCallback()". */
2563 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2564 hadc->ErrorCallback(hadc);
2565 #else
2566 HAL_ADC_ErrorCallback(hadc);
2567 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2568 }
2569
2570 /* Clear ADC overrun flag */
2571 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
2572 }
2573
2574 /* ========== Check Injected context queue overflow flag ========== */
2575 if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
2576 {
2577 /* Change ADC state to overrun state */
2578 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
2579
2580 /* Set ADC error code to Injected context queue overflow */
2581 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
2582
2583 /* Clear the Injected context queue overflow flag */
2584 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
2585
2586 /* Injected context queue overflow callback */
2587 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2588 hadc->InjectedQueueOverflowCallback(hadc);
2589 #else
2590 HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
2591 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2592 }
2593
2594 }
2595
2596 /**
2597 * @brief Conversion complete callback in non-blocking mode.
2598 * @param hadc ADC handle
2599 * @retval None
2600 */
HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef * hadc)2601 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
2602 {
2603 /* Prevent unused argument(s) compilation warning */
2604 UNUSED(hadc);
2605
2606 /* NOTE : This function should not be modified. When the callback is needed,
2607 function HAL_ADC_ConvCpltCallback must be implemented in the user file.
2608 */
2609 }
2610
2611 /**
2612 * @brief Conversion DMA half-transfer callback in non-blocking mode.
2613 * @param hadc ADC handle
2614 * @retval None
2615 */
HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef * hadc)2616 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
2617 {
2618 /* Prevent unused argument(s) compilation warning */
2619 UNUSED(hadc);
2620
2621 /* NOTE : This function should not be modified. When the callback is needed,
2622 function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
2623 */
2624 }
2625
2626 /**
2627 * @brief Analog watchdog 1 callback in non-blocking mode.
2628 * @param hadc ADC handle
2629 * @retval None
2630 */
HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef * hadc)2631 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
2632 {
2633 /* Prevent unused argument(s) compilation warning */
2634 UNUSED(hadc);
2635
2636 /* NOTE : This function should not be modified. When the callback is needed,
2637 function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
2638 */
2639 }
2640
2641 /**
2642 * @brief ADC error callback in non-blocking mode
2643 * (ADC conversion with interruption or transfer by DMA).
2644 * @note In case of error due to overrun when using ADC with DMA transfer
2645 * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
2646 * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
2647 * - If needed, restart a new ADC conversion using function
2648 * "HAL_ADC_Start_DMA()"
2649 * (this function is also clearing overrun flag)
2650 * @param hadc ADC handle
2651 * @retval None
2652 */
HAL_ADC_ErrorCallback(ADC_HandleTypeDef * hadc)2653 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
2654 {
2655 /* Prevent unused argument(s) compilation warning */
2656 UNUSED(hadc);
2657
2658 /* NOTE : This function should not be modified. When the callback is needed,
2659 function HAL_ADC_ErrorCallback must be implemented in the user file.
2660 */
2661 }
2662
2663 /**
2664 * @}
2665 */
2666
2667 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
2668 * @brief Peripheral Control functions
2669 *
2670 @verbatim
2671 ===============================================================================
2672 ##### Peripheral Control functions #####
2673 ===============================================================================
2674 [..] This section provides functions allowing to:
2675 (+) Configure channels on regular group
2676 (+) Configure the analog watchdog
2677
2678 @endverbatim
2679 * @{
2680 */
2681
2682 /**
2683 * @brief Configure a channel to be assigned to ADC group regular.
2684 * @note In case of usage of internal measurement channels:
2685 * Vbat/VrefInt/TempSensor.
2686 * These internal paths can be disabled using function
2687 * HAL_ADC_DeInit().
2688 * @note Possibility to update parameters on the fly:
2689 * This function initializes channel into ADC group regular,
2690 * following calls to this function can be used to reconfigure
2691 * some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
2692 * without resetting the ADC.
2693 * The setting of these parameters is conditioned to ADC state:
2694 * Refer to comments of structure "ADC_ChannelConfTypeDef".
2695 * @param hadc ADC handle
2696 * @param sConfig Structure of ADC channel assigned to ADC group regular.
2697 * @retval HAL status
2698 */
HAL_ADC_ConfigChannel(ADC_HandleTypeDef * hadc,ADC_ChannelConfTypeDef * sConfig)2699 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
2700 {
2701 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2702 uint32_t tmpOffsetShifted;
2703 uint32_t tmp_config_internal_channel;
2704 __IO uint32_t wait_loop_index = 0;
2705 uint32_t tmp_adc_is_conversion_on_going_regular;
2706 uint32_t tmp_adc_is_conversion_on_going_injected;
2707
2708 /* Check the parameters */
2709 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2710 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
2711 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
2712 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
2713 assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
2714 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
2715
2716 /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
2717 ignored (considered as reset) */
2718 assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
2719
2720 /* Verification of channel number */
2721 if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
2722 {
2723 assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel));
2724 }
2725 else
2726 {
2727 assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel));
2728 }
2729
2730 /* Process locked */
2731 __HAL_LOCK(hadc);
2732
2733 /* Parameters update conditioned to ADC state: */
2734 /* Parameters that can be updated when ADC is disabled or enabled without */
2735 /* conversion on going on regular group: */
2736 /* - Channel number */
2737 /* - Channel rank */
2738 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2739 {
2740 #if !defined (USE_FULL_ASSERT)
2741 /* Correspondence for compatibility with legacy definition of */
2742 /* sequencer ranks in direct number format. This correspondence can */
2743 /* be done only on ranks 1 to 5 due to literal values. */
2744 /* Note: Sequencer ranks in direct number format are no more used */
2745 /* and are detected by activating USE_FULL_ASSERT feature. */
2746 if (sConfig->Rank <= 5U)
2747 {
2748 switch (sConfig->Rank)
2749 {
2750 case 2U: sConfig->Rank = ADC_REGULAR_RANK_2; break;
2751 case 3U: sConfig->Rank = ADC_REGULAR_RANK_3; break;
2752 case 4U: sConfig->Rank = ADC_REGULAR_RANK_4; break;
2753 case 5U: sConfig->Rank = ADC_REGULAR_RANK_5; break;
2754 /* case 1U */
2755 default: sConfig->Rank = ADC_REGULAR_RANK_1; break;
2756 }
2757 }
2758 #endif
2759
2760 /* Set ADC group regular sequence: channel on the selected scan sequence rank */
2761 LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
2762
2763 /* Parameters update conditioned to ADC state: */
2764 /* Parameters that can be updated when ADC is disabled or enabled without */
2765 /* conversion on going on regular group: */
2766 /* - Channel sampling time */
2767 /* - Channel offset */
2768 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
2769 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
2770 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
2771 && (tmp_adc_is_conversion_on_going_injected == 0UL)
2772 )
2773 {
2774 #if defined(ADC_SMPR1_SMPPLUS)
2775 /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
2776 if (sConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5)
2777 {
2778 /* Set sampling time of the selected ADC channel */
2779 LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
2780
2781 /* Set ADC sampling time common configuration */
2782 LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
2783 }
2784 else
2785 {
2786 /* Set sampling time of the selected ADC channel */
2787 LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
2788
2789 /* Set ADC sampling time common configuration */
2790 LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
2791 }
2792 #else
2793 /* Set sampling time of the selected ADC channel */
2794 LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
2795 #endif
2796
2797 /* Configure the offset: offset enable/disable, channel, offset value */
2798
2799 /* Shift the offset with respect to the selected ADC resolution. */
2800 /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
2801 tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
2802
2803 if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
2804 {
2805 /* Set ADC selected offset number */
2806 LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
2807
2808 }
2809 else
2810 {
2811 /* Scan each offset register to check if the selected channel is targeted. */
2812 /* If this is the case, the corresponding offset number is disabled. */
2813 if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
2814 {
2815 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
2816 }
2817 if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
2818 {
2819 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
2820 }
2821 if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
2822 {
2823 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
2824 }
2825 if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
2826 {
2827 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
2828 }
2829 }
2830 }
2831
2832 /* Parameters update conditioned to ADC state: */
2833 /* Parameters that can be updated only when ADC is disabled: */
2834 /* - Single or differential mode */
2835 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2836 {
2837 /* Set mode single-ended or differential input of the selected ADC channel */
2838 LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
2839
2840 /* Configuration of differential mode */
2841 if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
2842 {
2843 /* Set sampling time of the selected ADC channel */
2844 /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
2845 LL_ADC_SetChannelSamplingTime(hadc->Instance,
2846 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
2847 sConfig->SamplingTime);
2848 }
2849
2850 }
2851
2852 /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
2853 /* If internal channel selected, enable dedicated internal buffers and */
2854 /* paths. */
2855 /* Note: these internal measurement paths can be disabled using */
2856 /* HAL_ADC_DeInit(). */
2857
2858 if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
2859 {
2860 tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2861
2862 /* If the requested internal measurement path has already been enabled, */
2863 /* bypass the configuration processing. */
2864 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
2865 {
2866 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
2867 {
2868 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2869 LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
2870
2871 /* Delay for temperature sensor stabilization time */
2872 /* Wait loop initialization and execution */
2873 /* Note: Variable divided by 2 to compensate partially */
2874 /* CPU processing cycles, scaling in us split to not */
2875 /* exceed 32 bits register capacity and handle low frequency. */
2876 wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
2877 while (wait_loop_index != 0UL)
2878 {
2879 wait_loop_index--;
2880 }
2881 }
2882 }
2883 else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
2884 {
2885 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
2886 {
2887 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2888 LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
2889 }
2890 }
2891 else if ((sConfig->Channel == ADC_CHANNEL_VREFINT)
2892 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
2893 {
2894 if (ADC_VREFINT_INSTANCE(hadc))
2895 {
2896 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2897 LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
2898 }
2899 }
2900 else
2901 {
2902 /* nothing to do */
2903 }
2904 }
2905 }
2906
2907 /* If a conversion is on going on regular group, no update on regular */
2908 /* channel could be done on neither of the channel configuration structure */
2909 /* parameters. */
2910 else
2911 {
2912 /* Update ADC state machine to error */
2913 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2914
2915 tmp_hal_status = HAL_ERROR;
2916 }
2917
2918 /* Process unlocked */
2919 __HAL_UNLOCK(hadc);
2920
2921 /* Return function status */
2922 return tmp_hal_status;
2923 }
2924
2925 /**
2926 * @brief Configure the analog watchdog.
2927 * @note Possibility to update parameters on the fly:
2928 * This function initializes the selected analog watchdog, successive
2929 * calls to this function can be used to reconfigure some parameters
2930 * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
2931 * the ADC.
2932 * The setting of these parameters is conditioned to ADC state.
2933 * For parameters constraints, see comments of structure
2934 * "ADC_AnalogWDGConfTypeDef".
2935 * @note On this STM32 serie, analog watchdog thresholds cannot be modified
2936 * while ADC conversion is on going.
2937 * @param hadc ADC handle
2938 * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
2939 * @retval HAL status
2940 */
HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef * hadc,ADC_AnalogWDGConfTypeDef * AnalogWDGConfig)2941 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
2942 {
2943 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2944 uint32_t tmpAWDHighThresholdShifted;
2945 uint32_t tmpAWDLowThresholdShifted;
2946 uint32_t tmp_adc_is_conversion_on_going_regular;
2947 uint32_t tmp_adc_is_conversion_on_going_injected;
2948
2949 /* Check the parameters */
2950 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2951 assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
2952 assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
2953 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
2954
2955 if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
2956 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
2957 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
2958 {
2959 assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel));
2960 }
2961
2962 /* Verify thresholds range */
2963 if (hadc->Init.OversamplingMode == ENABLE)
2964 {
2965 /* Case of oversampling enabled: depending on ratio and shift configuration,
2966 analog watchdog thresholds can be higher than ADC resolution.
2967 Verify if thresholds are within maximum thresholds range. */
2968 assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold));
2969 assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold));
2970 }
2971 else
2972 {
2973 /* Verify if thresholds are within the selected ADC resolution */
2974 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
2975 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
2976 }
2977
2978 /* Process locked */
2979 __HAL_LOCK(hadc);
2980
2981 /* Parameters update conditioned to ADC state: */
2982 /* Parameters that can be updated when ADC is disabled or enabled without */
2983 /* conversion on going on ADC groups regular and injected: */
2984 /* - Analog watchdog channels */
2985 /* - Analog watchdog thresholds */
2986 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
2987 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
2988 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
2989 && (tmp_adc_is_conversion_on_going_injected == 0UL)
2990 )
2991 {
2992 /* Analog watchdog configuration */
2993 if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
2994 {
2995 /* Configuration of analog watchdog: */
2996 /* - Set the analog watchdog enable mode: one or overall group of */
2997 /* channels, on groups regular and-or injected. */
2998 switch (AnalogWDGConfig->WatchdogMode)
2999 {
3000 case ADC_ANALOGWATCHDOG_SINGLE_REG:
3001 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
3002 LL_ADC_GROUP_REGULAR));
3003 break;
3004
3005 case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
3006 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
3007 LL_ADC_GROUP_INJECTED));
3008 break;
3009
3010 case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
3011 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
3012 LL_ADC_GROUP_REGULAR_INJECTED));
3013 break;
3014
3015 case ADC_ANALOGWATCHDOG_ALL_REG:
3016 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
3017 break;
3018
3019 case ADC_ANALOGWATCHDOG_ALL_INJEC:
3020 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ);
3021 break;
3022
3023 case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
3024 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
3025 break;
3026
3027 default: /* ADC_ANALOGWATCHDOG_NONE */
3028 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
3029 break;
3030 }
3031
3032 /* Shift the offset in function of the selected ADC resolution: */
3033 /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
3034 /* are set to 0 */
3035 tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
3036 tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
3037
3038 /* Set ADC analog watchdog thresholds value of both thresholds high and low */
3039 LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, tmpAWDLowThresholdShifted);
3040
3041 /* Update state, clear previous result related to AWD1 */
3042 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
3043
3044 /* Clear flag ADC analog watchdog */
3045 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
3046 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
3047 /* (in case left enabled by previous ADC operations). */
3048 LL_ADC_ClearFlag_AWD1(hadc->Instance);
3049
3050 /* Configure ADC analog watchdog interrupt */
3051 if (AnalogWDGConfig->ITMode == ENABLE)
3052 {
3053 LL_ADC_EnableIT_AWD1(hadc->Instance);
3054 }
3055 else
3056 {
3057 LL_ADC_DisableIT_AWD1(hadc->Instance);
3058 }
3059 }
3060 /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
3061 else
3062 {
3063 switch (AnalogWDGConfig->WatchdogMode)
3064 {
3065 case ADC_ANALOGWATCHDOG_SINGLE_REG:
3066 case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
3067 case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
3068 /* Update AWD by bitfield to keep the possibility to monitor */
3069 /* several channels by successive calls of this function. */
3070 if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
3071 {
3072 SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
3073 }
3074 else
3075 {
3076 SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
3077 }
3078 break;
3079
3080 case ADC_ANALOGWATCHDOG_ALL_REG:
3081 case ADC_ANALOGWATCHDOG_ALL_INJEC:
3082 case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
3083 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
3084 break;
3085
3086 default: /* ADC_ANALOGWATCHDOG_NONE */
3087 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
3088 break;
3089 }
3090
3091 /* Shift the thresholds in function of the selected ADC resolution */
3092 /* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */
3093 tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
3094 tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
3095
3096 /* Set ADC analog watchdog thresholds value of both thresholds high and low */
3097 LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, tmpAWDLowThresholdShifted);
3098
3099 if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
3100 {
3101 /* Update state, clear previous result related to AWD2 */
3102 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
3103
3104 /* Clear flag ADC analog watchdog */
3105 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
3106 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
3107 /* (in case left enabled by previous ADC operations). */
3108 LL_ADC_ClearFlag_AWD2(hadc->Instance);
3109
3110 /* Configure ADC analog watchdog interrupt */
3111 if (AnalogWDGConfig->ITMode == ENABLE)
3112 {
3113 LL_ADC_EnableIT_AWD2(hadc->Instance);
3114 }
3115 else
3116 {
3117 LL_ADC_DisableIT_AWD2(hadc->Instance);
3118 }
3119 }
3120 /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
3121 else
3122 {
3123 /* Update state, clear previous result related to AWD3 */
3124 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
3125
3126 /* Clear flag ADC analog watchdog */
3127 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
3128 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
3129 /* (in case left enabled by previous ADC operations). */
3130 LL_ADC_ClearFlag_AWD3(hadc->Instance);
3131
3132 /* Configure ADC analog watchdog interrupt */
3133 if (AnalogWDGConfig->ITMode == ENABLE)
3134 {
3135 LL_ADC_EnableIT_AWD3(hadc->Instance);
3136 }
3137 else
3138 {
3139 LL_ADC_DisableIT_AWD3(hadc->Instance);
3140 }
3141 }
3142 }
3143
3144 }
3145 /* If a conversion is on going on ADC group regular or injected, no update */
3146 /* could be done on neither of the AWD configuration structure parameters. */
3147 else
3148 {
3149 /* Update ADC state machine to error */
3150 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
3151
3152 tmp_hal_status = HAL_ERROR;
3153 }
3154 /* Process unlocked */
3155 __HAL_UNLOCK(hadc);
3156
3157 /* Return function status */
3158 return tmp_hal_status;
3159 }
3160
3161
3162 /**
3163 * @}
3164 */
3165
3166 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
3167 * @brief ADC Peripheral State functions
3168 *
3169 @verbatim
3170 ===============================================================================
3171 ##### Peripheral state and errors functions #####
3172 ===============================================================================
3173 [..]
3174 This subsection provides functions to get in run-time the status of the
3175 peripheral.
3176 (+) Check the ADC state
3177 (+) Check the ADC error code
3178
3179 @endverbatim
3180 * @{
3181 */
3182
3183 /**
3184 * @brief Return the ADC handle state.
3185 * @note ADC state machine is managed by bitfields, ADC status must be
3186 * compared with states bits.
3187 * For example:
3188 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
3189 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
3190 * @param hadc ADC handle
3191 * @retval ADC handle state (bitfield on 32 bits)
3192 */
HAL_ADC_GetState(ADC_HandleTypeDef * hadc)3193 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
3194 {
3195 /* Check the parameters */
3196 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3197
3198 /* Return ADC handle state */
3199 return hadc->State;
3200 }
3201
3202 /**
3203 * @brief Return the ADC error code.
3204 * @param hadc ADC handle
3205 * @retval ADC error code (bitfield on 32 bits)
3206 */
HAL_ADC_GetError(ADC_HandleTypeDef * hadc)3207 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
3208 {
3209 /* Check the parameters */
3210 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3211
3212 return hadc->ErrorCode;
3213 }
3214
3215 /**
3216 * @}
3217 */
3218
3219 /**
3220 * @}
3221 */
3222
3223 /** @defgroup ADC_Private_Functions ADC Private Functions
3224 * @{
3225 */
3226
3227 /**
3228 * @brief Stop ADC conversion.
3229 * @param hadc ADC handle
3230 * @param ConversionGroup ADC group regular and/or injected.
3231 * This parameter can be one of the following values:
3232 * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type.
3233 * @arg @ref ADC_INJECTED_GROUP ADC injected conversion type.
3234 * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
3235 * @retval HAL status.
3236 */
ADC_ConversionStop(ADC_HandleTypeDef * hadc,uint32_t ConversionGroup)3237 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
3238 {
3239 uint32_t tickstart;
3240 uint32_t Conversion_Timeout_CPU_cycles = 0UL;
3241 uint32_t conversion_group_reassigned = ConversionGroup;
3242 uint32_t tmp_ADC_CR_ADSTART_JADSTART;
3243 uint32_t tmp_adc_is_conversion_on_going_regular;
3244 uint32_t tmp_adc_is_conversion_on_going_injected;
3245
3246 /* Check the parameters */
3247 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3248 assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
3249
3250 /* Verification if ADC is not already stopped (on regular and injected */
3251 /* groups) to bypass this function if not needed. */
3252 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
3253 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
3254 if ((tmp_adc_is_conversion_on_going_regular != 0UL)
3255 || (tmp_adc_is_conversion_on_going_injected != 0UL)
3256 )
3257 {
3258 /* Particular case of continuous auto-injection mode combined with */
3259 /* auto-delay mode. */
3260 /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
3261 /* injected group stop ADC_CR_JADSTP). */
3262 /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
3263 /* (see reference manual). */
3264 if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL)
3265 && (hadc->Init.ContinuousConvMode == ENABLE)
3266 && (hadc->Init.LowPowerAutoWait == ENABLE)
3267 )
3268 {
3269 /* Use stop of regular group */
3270 conversion_group_reassigned = ADC_REGULAR_GROUP;
3271
3272 /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
3273 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
3274 {
3275 if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
3276 {
3277 /* Update ADC state machine to error */
3278 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3279
3280 /* Set ADC error code to ADC peripheral internal error */
3281 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3282
3283 return HAL_ERROR;
3284 }
3285 Conversion_Timeout_CPU_cycles ++;
3286 }
3287
3288 /* Clear JEOS */
3289 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
3290 }
3291
3292 /* Stop potential conversion on going on ADC group regular */
3293 if (conversion_group_reassigned != ADC_INJECTED_GROUP)
3294 {
3295 /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
3296 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
3297 {
3298 if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
3299 {
3300 /* Stop ADC group regular conversion */
3301 LL_ADC_REG_StopConversion(hadc->Instance);
3302 }
3303 }
3304 }
3305
3306 /* Stop potential conversion on going on ADC group injected */
3307 if (conversion_group_reassigned != ADC_REGULAR_GROUP)
3308 {
3309 /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
3310 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
3311 {
3312 if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
3313 {
3314 /* Stop ADC group injected conversion */
3315 LL_ADC_INJ_StopConversion(hadc->Instance);
3316 }
3317 }
3318 }
3319
3320 /* Selection of start and stop bits with respect to the regular or injected group */
3321 switch (conversion_group_reassigned)
3322 {
3323 case ADC_REGULAR_INJECTED_GROUP:
3324 tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
3325 break;
3326 case ADC_INJECTED_GROUP:
3327 tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
3328 break;
3329 /* Case ADC_REGULAR_GROUP only*/
3330 default:
3331 tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
3332 break;
3333 }
3334
3335 /* Wait for conversion effectively stopped */
3336 tickstart = HAL_GetTick();
3337
3338 while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
3339 {
3340 if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
3341 {
3342 /* Update ADC state machine to error */
3343 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3344
3345 /* Set ADC error code to ADC peripheral internal error */
3346 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3347
3348 return HAL_ERROR;
3349 }
3350 }
3351
3352 }
3353
3354 /* Return HAL status */
3355 return HAL_OK;
3356 }
3357
3358
3359
3360 /**
3361 * @brief Enable the selected ADC.
3362 * @note Prerequisite condition to use this function: ADC must be disabled
3363 * and voltage regulator must be enabled (done into HAL_ADC_Init()).
3364 * @param hadc ADC handle
3365 * @retval HAL status.
3366 */
ADC_Enable(ADC_HandleTypeDef * hadc)3367 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
3368 {
3369 uint32_t tickstart;
3370
3371 /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
3372 /* enabling phase not yet completed: flag ADC ready not yet set). */
3373 /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
3374 /* causes: ADC clock not running, ...). */
3375 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
3376 {
3377 /* Check if conditions to enable the ADC are fulfilled */
3378 if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
3379 {
3380 /* Update ADC state machine to error */
3381 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3382
3383 /* Set ADC error code to ADC peripheral internal error */
3384 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3385
3386 return HAL_ERROR;
3387 }
3388
3389 /* Enable the ADC peripheral */
3390 LL_ADC_Enable(hadc->Instance);
3391
3392 /* Wait for ADC effectively enabled */
3393 tickstart = HAL_GetTick();
3394
3395 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
3396 {
3397 /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
3398 has been cleared (after a calibration), ADEN bit is reset by the
3399 calibration logic.
3400 The workaround is to continue setting ADEN until ADRDY is becomes 1.
3401 Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
3402 4 ADC clock cycle duration */
3403 /* Note: Test of ADC enabled required due to hardware constraint to */
3404 /* not enable ADC if already enabled. */
3405 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
3406 {
3407 LL_ADC_Enable(hadc->Instance);
3408 }
3409
3410 if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
3411 {
3412 /* Update ADC state machine to error */
3413 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3414
3415 /* Set ADC error code to ADC peripheral internal error */
3416 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3417
3418 return HAL_ERROR;
3419 }
3420 }
3421 }
3422
3423 /* Return HAL status */
3424 return HAL_OK;
3425 }
3426
3427 /**
3428 * @brief Disable the selected ADC.
3429 * @note Prerequisite condition to use this function: ADC conversions must be
3430 * stopped.
3431 * @param hadc ADC handle
3432 * @retval HAL status.
3433 */
ADC_Disable(ADC_HandleTypeDef * hadc)3434 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
3435 {
3436 uint32_t tickstart;
3437 const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
3438
3439 /* Verification if ADC is not already disabled: */
3440 /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
3441 /* disabled. */
3442 if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
3443 && (tmp_adc_is_disable_on_going == 0UL)
3444 )
3445 {
3446 /* Check if conditions to disable the ADC are fulfilled */
3447 if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
3448 {
3449 /* Disable the ADC peripheral */
3450 LL_ADC_Disable(hadc->Instance);
3451 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
3452 }
3453 else
3454 {
3455 /* Update ADC state machine to error */
3456 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3457
3458 /* Set ADC error code to ADC peripheral internal error */
3459 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3460
3461 return HAL_ERROR;
3462 }
3463
3464 /* Wait for ADC effectively disabled */
3465 /* Get tick count */
3466 tickstart = HAL_GetTick();
3467
3468 while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
3469 {
3470 if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
3471 {
3472 /* Update ADC state machine to error */
3473 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3474
3475 /* Set ADC error code to ADC peripheral internal error */
3476 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3477
3478 return HAL_ERROR;
3479 }
3480 }
3481 }
3482
3483 /* Return HAL status */
3484 return HAL_OK;
3485 }
3486
3487 /**
3488 * @brief DMA transfer complete callback.
3489 * @param hdma pointer to DMA handle.
3490 * @retval None
3491 */
ADC_DMAConvCplt(DMA_HandleTypeDef * hdma)3492 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
3493 {
3494 /* Retrieve ADC handle corresponding to current DMA handle */
3495 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3496
3497 /* Update state machine on conversion status if not in error state */
3498 if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
3499 {
3500 /* Set ADC state */
3501 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
3502
3503 /* Determine whether any further conversion upcoming on group regular */
3504 /* by external trigger, continuous mode or scan sequence on going */
3505 /* to disable interruption. */
3506 /* Is it the end of the regular sequence ? */
3507 if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
3508 {
3509 /* Are conversions software-triggered ? */
3510 if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
3511 {
3512 /* Is CONT bit set ? */
3513 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL)
3514 {
3515 /* CONT bit is not set, no more conversions expected */
3516 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
3517 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
3518 {
3519 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
3520 }
3521 }
3522 }
3523 }
3524 else
3525 {
3526 /* DMA End of Transfer interrupt was triggered but conversions sequence
3527 is not over. If DMACFG is set to 0, conversions are stopped. */
3528 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL)
3529 {
3530 /* DMACFG bit is not set, conversions are stopped. */
3531 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
3532 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
3533 {
3534 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
3535 }
3536 }
3537 }
3538
3539 /* Conversion complete callback */
3540 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3541 hadc->ConvCpltCallback(hadc);
3542 #else
3543 HAL_ADC_ConvCpltCallback(hadc);
3544 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3545 }
3546 else /* DMA and-or internal error occurred */
3547 {
3548 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
3549 {
3550 /* Call HAL ADC Error Callback function */
3551 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3552 hadc->ErrorCallback(hadc);
3553 #else
3554 HAL_ADC_ErrorCallback(hadc);
3555 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3556 }
3557 else
3558 {
3559 /* Call ADC DMA error callback */
3560 hadc->DMA_Handle->XferErrorCallback(hdma);
3561 }
3562 }
3563 }
3564
3565 /**
3566 * @brief DMA half transfer complete callback.
3567 * @param hdma pointer to DMA handle.
3568 * @retval None
3569 */
ADC_DMAHalfConvCplt(DMA_HandleTypeDef * hdma)3570 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
3571 {
3572 /* Retrieve ADC handle corresponding to current DMA handle */
3573 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3574
3575 /* Half conversion callback */
3576 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3577 hadc->ConvHalfCpltCallback(hadc);
3578 #else
3579 HAL_ADC_ConvHalfCpltCallback(hadc);
3580 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3581 }
3582
3583 /**
3584 * @brief DMA error callback.
3585 * @param hdma pointer to DMA handle.
3586 * @retval None
3587 */
ADC_DMAError(DMA_HandleTypeDef * hdma)3588 void ADC_DMAError(DMA_HandleTypeDef *hdma)
3589 {
3590 /* Retrieve ADC handle corresponding to current DMA handle */
3591 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3592
3593 /* Set ADC state */
3594 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
3595
3596 /* Set ADC error code to DMA error */
3597 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
3598
3599 /* Error callback */
3600 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3601 hadc->ErrorCallback(hadc);
3602 #else
3603 HAL_ADC_ErrorCallback(hadc);
3604 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3605 }
3606
3607 /**
3608 * @}
3609 */
3610
3611 #endif /* HAL_ADC_MODULE_ENABLED */
3612 /**
3613 * @}
3614 */
3615
3616 /**
3617 * @}
3618 */
3619
3620 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
3621