1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L4xx_LL_LPTIM_H
22 #define STM32L4xx_LL_LPTIM_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx.h"
30
31 /** @addtogroup STM32L4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (LPTIM1) || defined (LPTIM2)
36
37 /** @defgroup LPTIM_LL LPTIM
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45
46 /* Private macros ------------------------------------------------------------*/
47 #if defined(USE_FULL_LL_DRIVER)
48 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
49 * @{
50 */
51 /**
52 * @}
53 */
54 #endif /*USE_FULL_LL_DRIVER*/
55
56 /* Exported types ------------------------------------------------------------*/
57 #if defined(USE_FULL_LL_DRIVER)
58 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
59 * @{
60 */
61
62 /**
63 * @brief LPTIM Init structure definition
64 */
65 typedef struct
66 {
67 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
68 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
69
70 This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/
71
72 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
73 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
74
75 This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/
76
77 uint32_t Waveform; /*!< Specifies the waveform shape.
78 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
79
80 This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
81
82 uint32_t Polarity; /*!< Specifies waveform polarity.
83 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
84
85 This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
86 } LL_LPTIM_InitTypeDef;
87
88 /**
89 * @}
90 */
91 #endif /* USE_FULL_LL_DRIVER */
92
93 /* Exported constants --------------------------------------------------------*/
94 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
95 * @{
96 */
97
98 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
99 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
100 * @{
101 */
102 #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */
103 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
104 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
105 #define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
106 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
107 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
108 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
109 #if defined(LPTIM_RCR_REP)
110 #define LL_LPTIM_ISR_UE LPTIM_ISR_UE /*!< Update event */
111 #define LL_LPTIM_ISR_REPOK LPTIM_ISR_REPOK /*!< Repetition register update OK */
112 #endif
113 /**
114 * @}
115 */
116
117 /** @defgroup LPTIM_LL_EC_IT IT Defines
118 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
119 * @{
120 */
121 #define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match Interrupt Enable */
122 #define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match Interrupt Enable */
123 #define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger valid edge Interrupt Enable */
124 #define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK Interrupt Enable */
125 #define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK Interrupt Enable */
126 #define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP Interrupt Enable */
127 #define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down Interrupt Enable */
128 #if defined(LPTIM_RCR_REP)
129 #define LL_LPTIM_IER_UEIE LPTIM_IER_UEIE /*!< Update event Interrupt Enable */
130 #define LL_LPTIM_IER_REPOKIE LPTIM_IER_REPOKIE /*!< Repetition register update OK Interrupt Enable */
131 #endif
132 /**
133 * @}
134 */
135
136 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
137 * @{
138 */
139 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
140 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
141 /**
142 * @}
143 */
144
145 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
146 * @{
147 */
148 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
149 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
150 /**
151 * @}
152 */
153
154 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
155 * @{
156 */
157 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
158 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
159 /**
160 * @}
161 */
162
163 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
164 * @{
165 */
166 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
167 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
168 /**
169 * @}
170 */
171
172 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
173 * @{
174 */
175 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
176 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
177 /**
178 * @}
179 */
180
181 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
182 * @{
183 */
184 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
185 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
186 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
187 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
188 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
189 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
190 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
191 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
192 /**
193 * @}
194 */
195
196 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
197 * @{
198 */
199 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
200 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
201 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
202 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
203 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
204 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
205 #define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
206 #define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /*!<External input trigger is connected to COMP2 output*/
207 /**
208 * @}
209 */
210
211 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
212 * @{
213 */
214 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
215 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
216 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
217 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
218 /**
219 * @}
220 */
221
222 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
223 * @{
224 */
225 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
226 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
227 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
228 /**
229 * @}
230 */
231
232 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
233 * @{
234 */
235 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
236 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
237 /**
238 * @}
239 */
240
241 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
242 * @{
243 */
244 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
245 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
246 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
247 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
248 /**
249 * @}
250 */
251
252 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
253 * @{
254 */
255 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
256 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
257 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
258 /**
259 * @}
260 */
261
262 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
263 * @{
264 */
265 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
266 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
267 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
268 /**
269 * @}
270 */
271
272 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
273 * @{
274 */
275 #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U /*!< For LPTIM1 and LPTIM2 */
276 #define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_OR_OR_0 /*!< For LPTIM1 and LPTIM2 */
277 #define LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM2 */
278 #define LL_LPTIM_INPUT1_SRC_COMP1_COMP2 LPTIM_OR_OR /*!< For LPTIM2 */
279 /**
280 * @}
281 */
282
283 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
284 * @{
285 */
286 #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U /*!< For LPTIM1 */
287 #define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM1 */
288 /**
289 * @}
290 */
291
292 /**
293 * @}
294 */
295
296 /* Exported macro ------------------------------------------------------------*/
297 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
298 * @{
299 */
300
301 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
302 * @{
303 */
304
305 /**
306 * @brief Write a value in LPTIM register
307 * @param __INSTANCE__ LPTIM Instance
308 * @param __REG__ Register to be written
309 * @param __VALUE__ Value to be written in the register
310 * @retval None
311 */
312 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
313
314 /**
315 * @brief Read a value in LPTIM register
316 * @param __INSTANCE__ LPTIM Instance
317 * @param __REG__ Register to be read
318 * @retval Register value
319 */
320 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
321 /**
322 * @}
323 */
324
325 /**
326 * @}
327 */
328
329 /* Exported functions --------------------------------------------------------*/
330 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
331 * @{
332 */
333
334 #if defined(USE_FULL_LL_DRIVER)
335 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
336 * @{
337 */
338
339 ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
340 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
341 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
342 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
343 /**
344 * @}
345 */
346 #endif /* USE_FULL_LL_DRIVER */
347
348 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
349 * @{
350 */
351
352 /**
353 * @brief Enable the LPTIM instance
354 * @note After setting the ENABLE bit, a delay of two counter clock is needed
355 * before the LPTIM instance is actually enabled.
356 * @rmtoll CR ENABLE LL_LPTIM_Enable
357 * @param LPTIMx Low-Power Timer instance
358 * @retval None
359 */
LL_LPTIM_Enable(LPTIM_TypeDef * LPTIMx)360 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
361 {
362 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
363 }
364
365 /**
366 * @brief Indicates whether the LPTIM instance is enabled.
367 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
368 * @param LPTIMx Low-Power Timer instance
369 * @retval State of bit (1 or 0).
370 */
LL_LPTIM_IsEnabled(LPTIM_TypeDef * LPTIMx)371 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
372 {
373 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE)? 1UL : 0UL));
374 }
375
376 /**
377 * @brief Starts the LPTIM counter in the desired mode.
378 * @note LPTIM instance must be enabled before starting the counter.
379 * @note It is possible to change on the fly from One Shot mode to
380 * Continuous mode.
381 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
382 * CR SNGSTRT LL_LPTIM_StartCounter
383 * @param LPTIMx Low-Power Timer instance
384 * @param OperatingMode This parameter can be one of the following values:
385 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
386 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
387 * @retval None
388 */
LL_LPTIM_StartCounter(LPTIM_TypeDef * LPTIMx,uint32_t OperatingMode)389 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
390 {
391 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
392 }
393
394 #if defined(LPTIM_CR_RSTARE)
395 /**
396 * @brief Enable reset after read.
397 * @note After calling this function any read access to LPTIM_CNT
398 * register will asynchronously reset the LPTIM_CNT register content.
399 * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
400 * @param LPTIMx Low-Power Timer instance
401 * @retval None
402 */
LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef * LPTIMx)403 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
404 {
405 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
406 }
407
408 /**
409 * @brief Disable reset after read.
410 * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
411 * @param LPTIMx Low-Power Timer instance
412 * @retval None
413 */
LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef * LPTIMx)414 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
415 {
416 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
417 }
418
419 /**
420 * @brief Indicate whether the reset after read feature is enabled.
421 * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
422 * @param LPTIMx Low-Power Timer instance
423 * @retval State of bit (1 or 0).
424 */
LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef * LPTIMx)425 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx)
426 {
427 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE)? 1UL : 0UL));
428 }
429 #endif
430
431 #if defined(LPTIM_CR_COUNTRST)
432 /**
433 * @brief Reset of the LPTIM_CNT counter register (synchronous).
434 * @note Due to the synchronous nature of this reset, it only takes
435 * place after a synchronization delay of 3 LPTIM core clock cycles
436 * (LPTIM core clock may be different from APB clock).
437 * @note COUNTRST is automatically cleared by hardware
438 * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
439 * @param LPTIMx Low-Power Timer instance
440 * @retval None
441 */
LL_LPTIM_ResetCounter(LPTIM_TypeDef * LPTIMx)442 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
443 {
444 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
445 }
446 #endif
447
448 /**
449 * @brief Set the LPTIM registers update mode (enable/disable register preload)
450 * @note This function must be called when the LPTIM instance is disabled.
451 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
452 * @param LPTIMx Low-Power Timer instance
453 * @param UpdateMode This parameter can be one of the following values:
454 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
455 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
456 * @retval None
457 */
LL_LPTIM_SetUpdateMode(LPTIM_TypeDef * LPTIMx,uint32_t UpdateMode)458 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
459 {
460 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
461 }
462
463 /**
464 * @brief Get the LPTIM registers update mode
465 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
466 * @param LPTIMx Low-Power Timer instance
467 * @retval Returned value can be one of the following values:
468 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
469 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
470 */
LL_LPTIM_GetUpdateMode(LPTIM_TypeDef * LPTIMx)471 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
472 {
473 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
474 }
475
476 /**
477 * @brief Set the auto reload value
478 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
479 * @note After a write to the LPTIMx_ARR register a new write operation to the
480 * same register can only be performed when the previous write operation
481 * is completed. Any successive write before the ARROK flag is set, will
482 * lead to unpredictable results.
483 * @note autoreload value be strictly greater than the compare value.
484 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
485 * @param LPTIMx Low-Power Timer instance
486 * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
487 * @retval None
488 */
LL_LPTIM_SetAutoReload(LPTIM_TypeDef * LPTIMx,uint32_t AutoReload)489 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
490 {
491 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
492 }
493
494 /**
495 * @brief Get actual auto reload value
496 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
497 * @param LPTIMx Low-Power Timer instance
498 * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
499 */
LL_LPTIM_GetAutoReload(LPTIM_TypeDef * LPTIMx)500 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
501 {
502 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
503 }
504
505 #if defined(LPTIM_RCR_REP)
506 /**
507 * @brief Set the repetition value
508 * @note The LPTIMx_RCR register content must only be modified when the LPTIM is enabled
509 * @rmtoll RCR REP LL_LPTIM_SetRepetition
510 * @param LPTIMx Low-Power Timer instance
511 * @param Repetition Value between Min_Data=0x00 and Max_Data=0xFF
512 * @retval None
513 */
LL_LPTIM_SetRepetition(LPTIM_TypeDef * LPTIMx,uint32_t Repetition)514 __STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repetition)
515 {
516 MODIFY_REG(LPTIMx->RCR, LPTIM_RCR_REP, Repetition);
517 }
518
519 /**
520 * @brief Get the repetition value
521 * @rmtoll RCR REP LL_LPTIM_GetRepetition
522 * @param LPTIMx Low-Power Timer instance
523 * @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF
524 */
LL_LPTIM_GetRepetition(LPTIM_TypeDef * LPTIMx)525 __STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(LPTIM_TypeDef *LPTIMx)
526 {
527 return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP));
528 }
529 #endif
530
531 /**
532 * @brief Set the compare value
533 * @note After a write to the LPTIMx_CMP register a new write operation to the
534 * same register can only be performed when the previous write operation
535 * is completed. Any successive write before the CMPOK flag is set, will
536 * lead to unpredictable results.
537 * @rmtoll CMP CMP LL_LPTIM_SetCompare
538 * @param LPTIMx Low-Power Timer instance
539 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
540 * @retval None
541 */
LL_LPTIM_SetCompare(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)542 __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
543 {
544 MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
545 }
546
547 /**
548 * @brief Get actual compare value
549 * @rmtoll CMP CMP LL_LPTIM_GetCompare
550 * @param LPTIMx Low-Power Timer instance
551 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
552 */
LL_LPTIM_GetCompare(LPTIM_TypeDef * LPTIMx)553 __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
554 {
555 return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
556 }
557
558 /**
559 * @brief Get actual counter value
560 * @note When the LPTIM instance is running with an asynchronous clock, reading
561 * the LPTIMx_CNT register may return unreliable values. So in this case
562 * it is necessary to perform two consecutive read accesses and verify
563 * that the two returned values are identical.
564 * @rmtoll CNT CNT LL_LPTIM_GetCounter
565 * @param LPTIMx Low-Power Timer instance
566 * @retval Counter value
567 */
LL_LPTIM_GetCounter(LPTIM_TypeDef * LPTIMx)568 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
569 {
570 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
571 }
572
573 /**
574 * @brief Set the counter mode (selection of the LPTIM counter clock source).
575 * @note The counter mode can be set only when the LPTIM instance is disabled.
576 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
577 * @param LPTIMx Low-Power Timer instance
578 * @param CounterMode This parameter can be one of the following values:
579 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
580 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
581 * @retval None
582 */
LL_LPTIM_SetCounterMode(LPTIM_TypeDef * LPTIMx,uint32_t CounterMode)583 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
584 {
585 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
586 }
587
588 /**
589 * @brief Get the counter mode
590 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
591 * @param LPTIMx Low-Power Timer instance
592 * @retval Returned value can be one of the following values:
593 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
594 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
595 */
LL_LPTIM_GetCounterMode(LPTIM_TypeDef * LPTIMx)596 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
597 {
598 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
599 }
600
601 /**
602 * @brief Configure the LPTIM instance output (LPTIMx_OUT)
603 * @note This function must be called when the LPTIM instance is disabled.
604 * @note Regarding the LPTIM output polarity the change takes effect
605 * immediately, so the output default value will change immediately after
606 * the polarity is re-configured, even before the timer is enabled.
607 * @rmtoll CFGR WAVE LL_LPTIM_ConfigOutput\n
608 * CFGR WAVPOL LL_LPTIM_ConfigOutput
609 * @param LPTIMx Low-Power Timer instance
610 * @param Waveform This parameter can be one of the following values:
611 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
612 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
613 * @param Polarity This parameter can be one of the following values:
614 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
615 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
616 * @retval None
617 */
LL_LPTIM_ConfigOutput(LPTIM_TypeDef * LPTIMx,uint32_t Waveform,uint32_t Polarity)618 __STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
619 {
620 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
621 }
622
623 /**
624 * @brief Set waveform shape
625 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
626 * @param LPTIMx Low-Power Timer instance
627 * @param Waveform This parameter can be one of the following values:
628 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
629 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
630 * @retval None
631 */
LL_LPTIM_SetWaveform(LPTIM_TypeDef * LPTIMx,uint32_t Waveform)632 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
633 {
634 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
635 }
636
637 /**
638 * @brief Get actual waveform shape
639 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
640 * @param LPTIMx Low-Power Timer instance
641 * @retval Returned value can be one of the following values:
642 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
643 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
644 */
LL_LPTIM_GetWaveform(LPTIM_TypeDef * LPTIMx)645 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
646 {
647 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
648 }
649
650 /**
651 * @brief Set output polarity
652 * @rmtoll CFGR WAVPOL LL_LPTIM_SetPolarity
653 * @param LPTIMx Low-Power Timer instance
654 * @param Polarity This parameter can be one of the following values:
655 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
656 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
657 * @retval None
658 */
LL_LPTIM_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Polarity)659 __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
660 {
661 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
662 }
663
664 /**
665 * @brief Get actual output polarity
666 * @rmtoll CFGR WAVPOL LL_LPTIM_GetPolarity
667 * @param LPTIMx Low-Power Timer instance
668 * @retval Returned value can be one of the following values:
669 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
670 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
671 */
LL_LPTIM_GetPolarity(LPTIM_TypeDef * LPTIMx)672 __STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
673 {
674 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
675 }
676
677 /**
678 * @brief Set actual prescaler division ratio.
679 * @note This function must be called when the LPTIM instance is disabled.
680 * @note When the LPTIM is configured to be clocked by an internal clock source
681 * and the LPTIM counter is configured to be updated by active edges
682 * detected on the LPTIM external Input1, the internal clock provided to
683 * the LPTIM must be not be prescaled.
684 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
685 * @param LPTIMx Low-Power Timer instance
686 * @param Prescaler This parameter can be one of the following values:
687 * @arg @ref LL_LPTIM_PRESCALER_DIV1
688 * @arg @ref LL_LPTIM_PRESCALER_DIV2
689 * @arg @ref LL_LPTIM_PRESCALER_DIV4
690 * @arg @ref LL_LPTIM_PRESCALER_DIV8
691 * @arg @ref LL_LPTIM_PRESCALER_DIV16
692 * @arg @ref LL_LPTIM_PRESCALER_DIV32
693 * @arg @ref LL_LPTIM_PRESCALER_DIV64
694 * @arg @ref LL_LPTIM_PRESCALER_DIV128
695 * @retval None
696 */
LL_LPTIM_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Prescaler)697 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
698 {
699 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
700 }
701
702 /**
703 * @brief Get actual prescaler division ratio.
704 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
705 * @param LPTIMx Low-Power Timer instance
706 * @retval Returned value can be one of the following values:
707 * @arg @ref LL_LPTIM_PRESCALER_DIV1
708 * @arg @ref LL_LPTIM_PRESCALER_DIV2
709 * @arg @ref LL_LPTIM_PRESCALER_DIV4
710 * @arg @ref LL_LPTIM_PRESCALER_DIV8
711 * @arg @ref LL_LPTIM_PRESCALER_DIV16
712 * @arg @ref LL_LPTIM_PRESCALER_DIV32
713 * @arg @ref LL_LPTIM_PRESCALER_DIV64
714 * @arg @ref LL_LPTIM_PRESCALER_DIV128
715 */
LL_LPTIM_GetPrescaler(LPTIM_TypeDef * LPTIMx)716 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
717 {
718 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
719 }
720
721 /**
722 * @brief Set LPTIM input 1 source (default GPIO).
723 * @rmtoll OR OR LL_LPTIM_SetInput1Src
724 * @param LPTIMx Low-Power Timer instance
725 * @param Src This parameter can be one of the following values:
726 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
727 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
728 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP2
729 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1_COMP2
730 * @retval None
731 */
LL_LPTIM_SetInput1Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)732 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
733 {
734 MODIFY_REG(LPTIMx->OR, LPTIM_OR_OR, Src);
735 }
736
737 /**
738 * @brief Set LPTIM input 2 source (default GPIO).
739 * @rmtoll OR OR LL_LPTIM_SetInput2Src
740 * @param LPTIMx Low-Power Timer instance
741 * @param Src This parameter can be one of the following values:
742 * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
743 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP2
744 * @retval None
745 */
LL_LPTIM_SetInput2Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)746 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
747 {
748 MODIFY_REG(LPTIMx->OR, LPTIM_OR_OR, Src);
749 }
750
751 /**
752 * @}
753 */
754
755 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
756 * @{
757 */
758
759 /**
760 * @brief Enable the timeout function
761 * @note This function must be called when the LPTIM instance is disabled.
762 * @note The first trigger event will start the timer, any successive trigger
763 * event will reset the counter and the timer will restart.
764 * @note The timeout value corresponds to the compare value; if no trigger
765 * occurs within the expected time frame, the MCU is waked-up by the
766 * compare match event.
767 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
768 * @param LPTIMx Low-Power Timer instance
769 * @retval None
770 */
LL_LPTIM_EnableTimeout(LPTIM_TypeDef * LPTIMx)771 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
772 {
773 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
774 }
775
776 /**
777 * @brief Disable the timeout function
778 * @note This function must be called when the LPTIM instance is disabled.
779 * @note A trigger event arriving when the timer is already started will be
780 * ignored.
781 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
782 * @param LPTIMx Low-Power Timer instance
783 * @retval None
784 */
LL_LPTIM_DisableTimeout(LPTIM_TypeDef * LPTIMx)785 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
786 {
787 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
788 }
789
790 /**
791 * @brief Indicate whether the timeout function is enabled.
792 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
793 * @param LPTIMx Low-Power Timer instance
794 * @retval State of bit (1 or 0).
795 */
LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef * LPTIMx)796 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
797 {
798 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT)? 1UL : 0UL));
799 }
800
801 /**
802 * @brief Start the LPTIM counter
803 * @note This function must be called when the LPTIM instance is disabled.
804 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
805 * @param LPTIMx Low-Power Timer instance
806 * @retval None
807 */
LL_LPTIM_TrigSw(LPTIM_TypeDef * LPTIMx)808 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
809 {
810 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
811 }
812
813 /**
814 * @brief Configure the external trigger used as a trigger event for the LPTIM.
815 * @note This function must be called when the LPTIM instance is disabled.
816 * @note An internal clock source must be present when a digital filter is
817 * required for the trigger.
818 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
819 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
820 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
821 * @param LPTIMx Low-Power Timer instance
822 * @param Source This parameter can be one of the following values:
823 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
824 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
825 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
826 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
827 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
828 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
829 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
830 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
831 * @param Filter This parameter can be one of the following values:
832 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
833 * @arg @ref LL_LPTIM_TRIG_FILTER_2
834 * @arg @ref LL_LPTIM_TRIG_FILTER_4
835 * @arg @ref LL_LPTIM_TRIG_FILTER_8
836 * @param Polarity This parameter can be one of the following values:
837 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
838 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
839 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
840 * @retval None
841 */
LL_LPTIM_ConfigTrigger(LPTIM_TypeDef * LPTIMx,uint32_t Source,uint32_t Filter,uint32_t Polarity)842 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
843 {
844 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
845 }
846
847 /**
848 * @brief Get actual external trigger source.
849 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
850 * @param LPTIMx Low-Power Timer instance
851 * @retval Returned value can be one of the following values:
852 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
853 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
854 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
855 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
856 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
857 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
858 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
859 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
860 */
LL_LPTIM_GetTriggerSource(LPTIM_TypeDef * LPTIMx)861 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
862 {
863 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
864 }
865
866 /**
867 * @brief Get actual external trigger filter.
868 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
869 * @param LPTIMx Low-Power Timer instance
870 * @retval Returned value can be one of the following values:
871 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
872 * @arg @ref LL_LPTIM_TRIG_FILTER_2
873 * @arg @ref LL_LPTIM_TRIG_FILTER_4
874 * @arg @ref LL_LPTIM_TRIG_FILTER_8
875 */
LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef * LPTIMx)876 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
877 {
878 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
879 }
880
881 /**
882 * @brief Get actual external trigger polarity.
883 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
884 * @param LPTIMx Low-Power Timer instance
885 * @retval Returned value can be one of the following values:
886 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
887 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
888 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
889 */
LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef * LPTIMx)890 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
891 {
892 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
893 }
894
895 /**
896 * @}
897 */
898
899 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
900 * @{
901 */
902
903 /**
904 * @brief Set the source of the clock used by the LPTIM instance.
905 * @note This function must be called when the LPTIM instance is disabled.
906 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
907 * @param LPTIMx Low-Power Timer instance
908 * @param ClockSource This parameter can be one of the following values:
909 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
910 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
911 * @retval None
912 */
LL_LPTIM_SetClockSource(LPTIM_TypeDef * LPTIMx,uint32_t ClockSource)913 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
914 {
915 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
916 }
917
918 /**
919 * @brief Get actual LPTIM instance clock source.
920 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
921 * @param LPTIMx Low-Power Timer instance
922 * @retval Returned value can be one of the following values:
923 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
924 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
925 */
LL_LPTIM_GetClockSource(LPTIM_TypeDef * LPTIMx)926 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
927 {
928 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
929 }
930
931 /**
932 * @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
933 * @note This function must be called when the LPTIM instance is disabled.
934 * @note When both external clock signal edges are considered active ones,
935 * the LPTIM must also be clocked by an internal clock source with a
936 * frequency equal to at least four times the external clock frequency.
937 * @note An internal clock source must be present when a digital filter is
938 * required for external clock.
939 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
940 * CFGR CKPOL LL_LPTIM_ConfigClock
941 * @param LPTIMx Low-Power Timer instance
942 * @param ClockFilter This parameter can be one of the following values:
943 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
944 * @arg @ref LL_LPTIM_CLK_FILTER_2
945 * @arg @ref LL_LPTIM_CLK_FILTER_4
946 * @arg @ref LL_LPTIM_CLK_FILTER_8
947 * @param ClockPolarity This parameter can be one of the following values:
948 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
949 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
950 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
951 * @retval None
952 */
LL_LPTIM_ConfigClock(LPTIM_TypeDef * LPTIMx,uint32_t ClockFilter,uint32_t ClockPolarity)953 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
954 {
955 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
956 }
957
958 /**
959 * @brief Get actual clock polarity
960 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
961 * @param LPTIMx Low-Power Timer instance
962 * @retval Returned value can be one of the following values:
963 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
964 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
965 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
966 */
LL_LPTIM_GetClockPolarity(LPTIM_TypeDef * LPTIMx)967 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
968 {
969 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
970 }
971
972 /**
973 * @brief Get actual clock digital filter
974 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
975 * @param LPTIMx Low-Power Timer instance
976 * @retval Returned value can be one of the following values:
977 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
978 * @arg @ref LL_LPTIM_CLK_FILTER_2
979 * @arg @ref LL_LPTIM_CLK_FILTER_4
980 * @arg @ref LL_LPTIM_CLK_FILTER_8
981 */
LL_LPTIM_GetClockFilter(LPTIM_TypeDef * LPTIMx)982 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
983 {
984 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
985 }
986
987 /**
988 * @}
989 */
990
991 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
992 * @{
993 */
994
995 /**
996 * @brief Configure the encoder mode.
997 * @note This function must be called when the LPTIM instance is disabled.
998 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
999 * @param LPTIMx Low-Power Timer instance
1000 * @param EncoderMode This parameter can be one of the following values:
1001 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1002 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1003 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1004 * @retval None
1005 */
LL_LPTIM_SetEncoderMode(LPTIM_TypeDef * LPTIMx,uint32_t EncoderMode)1006 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
1007 {
1008 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
1009 }
1010
1011 /**
1012 * @brief Get actual encoder mode.
1013 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
1014 * @param LPTIMx Low-Power Timer instance
1015 * @retval Returned value can be one of the following values:
1016 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1017 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1018 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1019 */
LL_LPTIM_GetEncoderMode(LPTIM_TypeDef * LPTIMx)1020 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
1021 {
1022 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1023 }
1024
1025 /**
1026 * @brief Enable the encoder mode
1027 * @note This function must be called when the LPTIM instance is disabled.
1028 * @note In this mode the LPTIM instance must be clocked by an internal clock
1029 * source. Also, the prescaler division ratio must be equal to 1.
1030 * @note LPTIM instance must be configured in continuous mode prior enabling
1031 * the encoder mode.
1032 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
1033 * @param LPTIMx Low-Power Timer instance
1034 * @retval None
1035 */
LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef * LPTIMx)1036 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
1037 {
1038 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1039 }
1040
1041 /**
1042 * @brief Disable the encoder mode
1043 * @note This function must be called when the LPTIM instance is disabled.
1044 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
1045 * @param LPTIMx Low-Power Timer instance
1046 * @retval None
1047 */
LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef * LPTIMx)1048 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
1049 {
1050 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1051 }
1052
1053 /**
1054 * @brief Indicates whether the LPTIM operates in encoder mode.
1055 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
1056 * @param LPTIMx Low-Power Timer instance
1057 * @retval State of bit (1 or 0).
1058 */
LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef * LPTIMx)1059 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
1060 {
1061 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC)? 1UL : 0UL));
1062 }
1063
1064 /**
1065 * @}
1066 */
1067
1068 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
1069 * @{
1070 */
1071
1072 /**
1073 * @brief Clear the compare match flag (CMPMCF)
1074 * @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM
1075 * @param LPTIMx Low-Power Timer instance
1076 * @retval None
1077 */
LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef * LPTIMx)1078 __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
1079 {
1080 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
1081 }
1082
1083 /**
1084 * @brief Inform application whether a compare match interrupt has occurred.
1085 * @rmtoll ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
1086 * @param LPTIMx Low-Power Timer instance
1087 * @retval State of bit (1 or 0).
1088 */
LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef * LPTIMx)1089 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
1090 {
1091 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM)? 1UL : 0UL));
1092 }
1093
1094 /**
1095 * @brief Clear the autoreload match flag (ARRMCF)
1096 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
1097 * @param LPTIMx Low-Power Timer instance
1098 * @retval None
1099 */
LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef * LPTIMx)1100 __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
1101 {
1102 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
1103 }
1104
1105 /**
1106 * @brief Inform application whether a autoreload match interrupt has occurred.
1107 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
1108 * @param LPTIMx Low-Power Timer instance
1109 * @retval State of bit (1 or 0).
1110 */
LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef * LPTIMx)1111 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
1112 {
1113 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM)? 1UL : 0UL));
1114 }
1115
1116 /**
1117 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
1118 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
1119 * @param LPTIMx Low-Power Timer instance
1120 * @retval None
1121 */
LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1122 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1123 {
1124 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
1125 }
1126
1127 /**
1128 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
1129 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
1130 * @param LPTIMx Low-Power Timer instance
1131 * @retval State of bit (1 or 0).
1132 */
LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1133 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1134 {
1135 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG)? 1UL : 0UL));
1136 }
1137
1138 /**
1139 * @brief Clear the compare register update interrupt flag (CMPOKCF).
1140 * @rmtoll ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
1141 * @param LPTIMx Low-Power Timer instance
1142 * @retval None
1143 */
LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef * LPTIMx)1144 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
1145 {
1146 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
1147 }
1148
1149 /**
1150 * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated.
1151 * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
1152 * @param LPTIMx Low-Power Timer instance
1153 * @retval State of bit (1 or 0).
1154 */
LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef * LPTIMx)1155 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
1156 {
1157 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK)? 1UL : 0UL));
1158 }
1159
1160 /**
1161 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
1162 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
1163 * @param LPTIMx Low-Power Timer instance
1164 * @retval None
1165 */
LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef * LPTIMx)1166 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1167 {
1168 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
1169 }
1170
1171 /**
1172 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated.
1173 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
1174 * @param LPTIMx Low-Power Timer instance
1175 * @retval State of bit (1 or 0).
1176 */
LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef * LPTIMx)1177 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1178 {
1179 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK)? 1UL : 0UL));
1180 }
1181
1182 /**
1183 * @brief Clear the counter direction change to up interrupt flag (UPCF).
1184 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
1185 * @param LPTIMx Low-Power Timer instance
1186 * @retval None
1187 */
LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef * LPTIMx)1188 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
1189 {
1190 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
1191 }
1192
1193 /**
1194 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
1195 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
1196 * @param LPTIMx Low-Power Timer instance
1197 * @retval State of bit (1 or 0).
1198 */
LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef * LPTIMx)1199 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
1200 {
1201 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP)? 1UL : 0UL));
1202 }
1203
1204 /**
1205 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
1206 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
1207 * @param LPTIMx Low-Power Timer instance
1208 * @retval None
1209 */
LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef * LPTIMx)1210 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1211 {
1212 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
1213 }
1214
1215 /**
1216 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
1217 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
1218 * @param LPTIMx Low-Power Timer instance
1219 * @retval State of bit (1 or 0).
1220 */
LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef * LPTIMx)1221 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1222 {
1223 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN)? 1UL : 0UL));
1224 }
1225
1226 #if defined(LPTIM_RCR_REP)
1227 /**
1228 * @brief Clear the repetition register update interrupt flag (REPOKCF).
1229 * @rmtoll ICR REPOKCF LL_LPTIM_ClearFlag_REPOK
1230 * @param LPTIMx Low-Power Timer instance
1231 * @retval None
1232 */
LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef * LPTIMx)1233 __STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx)
1234 {
1235 SET_BIT(LPTIMx->ICR, LPTIM_ICR_REPOKCF);
1236 }
1237
1238 /**
1239 * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully completed; If so, a new one can be initiated.
1240 * @rmtoll ISR REPOK LL_LPTIM_IsActiveFlag_REPOK
1241 * @param LPTIMx Low-Power Timer instance
1242 * @retval State of bit (1 or 0).
1243 */
LL_LPTIM_IsActiveFlag_REPOK(LPTIM_TypeDef * LPTIMx)1244 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(LPTIM_TypeDef *LPTIMx)
1245 {
1246 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL);
1247 }
1248
1249 /**
1250 * @brief Clear the update event flag (UECF).
1251 * @rmtoll ICR UECF LL_LPTIM_ClearFlag_UE
1252 * @param LPTIMx Low-Power Timer instance
1253 * @retval None
1254 */
LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef * LPTIMx)1255 __STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx)
1256 {
1257 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UECF);
1258 }
1259
1260 /**
1261 * @brief Informs application whether the LPTIMx update event has occurred.
1262 * @rmtoll ISR UE LL_LPTIM_IsActiveFlag_UE
1263 * @param LPTIMx Low-Power Timer instance
1264 * @retval State of bit (1 or 0).
1265 */
LL_LPTIM_IsActiveFlag_UE(LPTIM_TypeDef * LPTIMx)1266 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(LPTIM_TypeDef *LPTIMx)
1267 {
1268 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL);
1269 }
1270 #endif
1271
1272 /**
1273 * @}
1274 */
1275
1276 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
1277 * @{
1278 */
1279
1280 /**
1281 * @brief Enable compare match interrupt (CMPMIE).
1282 * @rmtoll IER CMPMIE LL_LPTIM_EnableIT_CMPM
1283 * @param LPTIMx Low-Power Timer instance
1284 * @retval None
1285 */
LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef * LPTIMx)1286 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1287 {
1288 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1289 }
1290
1291 /**
1292 * @brief Disable compare match interrupt (CMPMIE).
1293 * @rmtoll IER CMPMIE LL_LPTIM_DisableIT_CMPM
1294 * @param LPTIMx Low-Power Timer instance
1295 * @retval None
1296 */
LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef * LPTIMx)1297 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1298 {
1299 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1300 }
1301
1302 /**
1303 * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled.
1304 * @rmtoll IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
1305 * @param LPTIMx Low-Power Timer instance
1306 * @retval State of bit (1 or 0).
1307 */
LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef * LPTIMx)1308 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
1309 {
1310 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE)? 1UL : 0UL));
1311 }
1312
1313 /**
1314 * @brief Enable autoreload match interrupt (ARRMIE).
1315 * @rmtoll IER ARRMIE LL_LPTIM_EnableIT_ARRM
1316 * @param LPTIMx Low-Power Timer instance
1317 * @retval None
1318 */
LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef * LPTIMx)1319 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1320 {
1321 SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1322 }
1323
1324 /**
1325 * @brief Disable autoreload match interrupt (ARRMIE).
1326 * @rmtoll IER ARRMIE LL_LPTIM_DisableIT_ARRM
1327 * @param LPTIMx Low-Power Timer instance
1328 * @retval None
1329 */
LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef * LPTIMx)1330 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1331 {
1332 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1333 }
1334
1335 /**
1336 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
1337 * @rmtoll IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
1338 * @param LPTIMx Low-Power Timer instance
1339 * @retval State of bit (1 or 0).
1340 */
LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef * LPTIMx)1341 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
1342 {
1343 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE)? 1UL : 0UL));
1344 }
1345
1346 /**
1347 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
1348 * @rmtoll IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
1349 * @param LPTIMx Low-Power Timer instance
1350 * @retval None
1351 */
LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1352 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1353 {
1354 SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1355 }
1356
1357 /**
1358 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
1359 * @rmtoll IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
1360 * @param LPTIMx Low-Power Timer instance
1361 * @retval None
1362 */
LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1363 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1364 {
1365 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1366 }
1367
1368 /**
1369 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
1370 * @rmtoll IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
1371 * @param LPTIMx Low-Power Timer instance
1372 * @retval State of bit (1 or 0).
1373 */
LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1374 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1375 {
1376 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE)? 1UL : 0UL));
1377 }
1378
1379 /**
1380 * @brief Enable compare register write completed interrupt (CMPOKIE).
1381 * @rmtoll IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
1382 * @param LPTIMx Low-Power Timer instance
1383 * @retval None
1384 */
LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef * LPTIMx)1385 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1386 {
1387 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1388 }
1389
1390 /**
1391 * @brief Disable compare register write completed interrupt (CMPOKIE).
1392 * @rmtoll IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
1393 * @param LPTIMx Low-Power Timer instance
1394 * @retval None
1395 */
LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef * LPTIMx)1396 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1397 {
1398 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1399 }
1400
1401 /**
1402 * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
1403 * @rmtoll IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
1404 * @param LPTIMx Low-Power Timer instance
1405 * @retval State of bit (1 or 0).
1406 */
LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef * LPTIMx)1407 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1408 {
1409 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE)? 1UL : 0UL));
1410 }
1411
1412 /**
1413 * @brief Enable autoreload register write completed interrupt (ARROKIE).
1414 * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
1415 * @param LPTIMx Low-Power Timer instance
1416 * @retval None
1417 */
LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef * LPTIMx)1418 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1419 {
1420 SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1421 }
1422
1423 /**
1424 * @brief Disable autoreload register write completed interrupt (ARROKIE).
1425 * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
1426 * @param LPTIMx Low-Power Timer instance
1427 * @retval None
1428 */
LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef * LPTIMx)1429 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1430 {
1431 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1432 }
1433
1434 /**
1435 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
1436 * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
1437 * @param LPTIMx Low-Power Timer instance
1438 * @retval State of bit (1 or 0).
1439 */
LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef * LPTIMx)1440 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
1441 {
1442 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE)? 1UL : 0UL));
1443 }
1444
1445 /**
1446 * @brief Enable direction change to up interrupt (UPIE).
1447 * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
1448 * @param LPTIMx Low-Power Timer instance
1449 * @retval None
1450 */
LL_LPTIM_EnableIT_UP(LPTIM_TypeDef * LPTIMx)1451 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
1452 {
1453 SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1454 }
1455
1456 /**
1457 * @brief Disable direction change to up interrupt (UPIE).
1458 * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
1459 * @param LPTIMx Low-Power Timer instance
1460 * @retval None
1461 */
LL_LPTIM_DisableIT_UP(LPTIM_TypeDef * LPTIMx)1462 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
1463 {
1464 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1465 }
1466
1467 /**
1468 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
1469 * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
1470 * @param LPTIMx Low-Power Timer instance
1471 * @retval State of bit (1 or 0).
1472 */
LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef * LPTIMx)1473 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
1474 {
1475 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE)? 1UL : 0UL));
1476 }
1477
1478 /**
1479 * @brief Enable direction change to down interrupt (DOWNIE).
1480 * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
1481 * @param LPTIMx Low-Power Timer instance
1482 * @retval None
1483 */
LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef * LPTIMx)1484 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1485 {
1486 SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1487 }
1488
1489 /**
1490 * @brief Disable direction change to down interrupt (DOWNIE).
1491 * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
1492 * @param LPTIMx Low-Power Timer instance
1493 * @retval None
1494 */
LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef * LPTIMx)1495 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1496 {
1497 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1498 }
1499
1500 /**
1501 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
1502 * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
1503 * @param LPTIMx Low-Power Timer instance
1504 * @retval State of bit (1 or 0).
1505 */
LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef * LPTIMx)1506 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
1507 {
1508 return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE)? 1UL : 0UL);
1509 }
1510
1511 #if defined(LPTIM_RCR_REP)
1512 /**
1513 * @brief Enable repetition register update successfully completed interrupt (REPOKIE).
1514 * @rmtoll IER REPOKIE LL_LPTIM_EnableIT_REPOK
1515 * @param LPTIMx Low-Power Timer instance
1516 * @retval None
1517 */
LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef * LPTIMx)1518 __STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *LPTIMx)
1519 {
1520 SET_BIT(LPTIMx->IER, LPTIM_IER_REPOKIE);
1521 }
1522
1523 /**
1524 * @brief Disable repetition register update successfully completed interrupt (REPOKIE).
1525 * @rmtoll IER REPOKIE LL_LPTIM_DisableIT_REPOK
1526 * @param LPTIMx Low-Power Timer instance
1527 * @retval None
1528 */
LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef * LPTIMx)1529 __STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx)
1530 {
1531 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_REPOKIE);
1532 }
1533
1534 /**
1535 * @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled.
1536 * @rmtoll IER REPOKIE LL_LPTIM_IsEnabledIT_REPOK
1537 * @param LPTIMx Low-Power Timer instance
1538 * @retval State of bit (1 or 0).
1539 */
LL_LPTIM_IsEnabledIT_REPOK(LPTIM_TypeDef * LPTIMx)1540 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(LPTIM_TypeDef *LPTIMx)
1541 {
1542 return ((READ_BIT(LPTIMx->IER, LPTIM_IER_REPOKIE) == (LPTIM_IER_REPOKIE)) ? 1UL : 0UL);
1543 }
1544
1545 /**
1546 * @brief Enable update event interrupt (UEIE).
1547 * @rmtoll IER UEIE LL_LPTIM_EnableIT_UE
1548 * @param LPTIMx Low-Power Timer instance
1549 * @retval None
1550 */
LL_LPTIM_EnableIT_UE(LPTIM_TypeDef * LPTIMx)1551 __STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *LPTIMx)
1552 {
1553 SET_BIT(LPTIMx->IER, LPTIM_IER_UEIE);
1554 }
1555
1556 /**
1557 * @brief Disable update event interrupt (UEIE).
1558 * @rmtoll IER UEIE LL_LPTIM_DisableIT_UE
1559 * @param LPTIMx Low-Power Timer instance
1560 * @retval None
1561 */
LL_LPTIM_DisableIT_UE(LPTIM_TypeDef * LPTIMx)1562 __STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx)
1563 {
1564 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UEIE);
1565 }
1566
1567 /**
1568 * @brief Indicates whether the update event interrupt (UEIE) is enabled.
1569 * @rmtoll IER UEIE LL_LPTIM_IsEnabledIT_UE
1570 * @param LPTIMx Low-Power Timer instance
1571 * @retval State of bit (1 or 0).
1572 */
LL_LPTIM_IsEnabledIT_UE(LPTIM_TypeDef * LPTIMx)1573 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(LPTIM_TypeDef *LPTIMx)
1574 {
1575 return ((READ_BIT(LPTIMx->IER, LPTIM_IER_UEIE) == (LPTIM_IER_UEIE)) ? 1UL : 0UL);
1576 }
1577 #endif
1578 /**
1579 * @}
1580 */
1581
1582 /**
1583 * @}
1584 */
1585
1586 /**
1587 * @}
1588 */
1589
1590 #endif /* LPTIM1 || LPTIM2 */
1591
1592 /**
1593 * @}
1594 */
1595
1596 #ifdef __cplusplus
1597 }
1598 #endif
1599
1600 #endif /* STM32L4xx_LL_LPTIM_H */
1601
1602 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1603