1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L4xx_LL_DMA_H
22 #define STM32L4xx_LL_DMA_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx.h"
30 #if defined(DMAMUX1)
31 #include "stm32l4xx_ll_dmamux.h"
32 #endif /* DMAMUX1 */
33
34 /** @addtogroup STM32L4xx_LL_Driver
35 * @{
36 */
37
38 #if defined (DMA1) || defined (DMA2)
39
40 /** @defgroup DMA_LL DMA
41 * @{
42 */
43
44 /* Private types -------------------------------------------------------------*/
45 /* Private variables ---------------------------------------------------------*/
46 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
47 * @{
48 */
49 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
50 static const uint8_t CHANNEL_OFFSET_TAB[] =
51 {
52 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
55 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
56 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
57 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
58 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
59 };
60 /**
61 * @}
62 */
63
64 /* Private constants ---------------------------------------------------------*/
65 #if defined(DMAMUX1)
66 #else
67 /** @defgroup DMA_LL_Private_Constants DMA Private Constants
68 * @{
69 */
70 /* Define used to get CSELR register offset */
71 #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
72
73 /* Defines used for the bit position in the register and perform offsets */
74 #define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << (Channel*4U))
75 /**
76 * @}
77 */
78 #endif /* DMAMUX1 */
79
80 /* Private constants ---------------------------------------------------------*/
81 /* Private macros ------------------------------------------------------------*/
82 #if defined(DMAMUX1)
83 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
84 * @{
85 */
86 /**
87 * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel
88 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
89 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
90 * @param __DMA_INSTANCE__ DMAx
91 * @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0).
92 */
93 #define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \
94 (((__DMA_INSTANCE__) == DMA1) ? 0x00000000U : LL_DMA_CHANNEL_7)
95
96 /**
97 * @}
98 */
99 #else
100 #if defined(USE_FULL_LL_DRIVER)
101 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
102 * @{
103 */
104 /**
105 * @}
106 */
107 #endif /*USE_FULL_LL_DRIVER*/
108 #endif /* DMAMUX1 */
109
110 /* Exported types ------------------------------------------------------------*/
111 #if defined(USE_FULL_LL_DRIVER)
112 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
113 * @{
114 */
115 typedef struct
116 {
117 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
118 or as Source base address in case of memory to memory transfer direction.
119
120 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
121
122 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
123 or as Destination base address in case of memory to memory transfer direction.
124
125 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
126
127 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
128 from memory to memory or from peripheral to memory.
129 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
130
131 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
132
133 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
134 This parameter can be a value of @ref DMA_LL_EC_MODE
135 @note: The circular buffer mode cannot be used if the memory to memory
136 data transfer direction is configured on the selected Channel
137
138 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
139
140 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
141 is incremented or not.
142 This parameter can be a value of @ref DMA_LL_EC_PERIPH
143
144 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
145
146 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
147 is incremented or not.
148 This parameter can be a value of @ref DMA_LL_EC_MEMORY
149
150 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
151
152 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
153 in case of memory to memory transfer direction.
154 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
155
156 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
157
158 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
159 in case of memory to memory transfer direction.
160 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
161
162 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
163
164 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
165 The data unit is equal to the source buffer configuration set in PeripheralSize
166 or MemorySize parameters depending in the transfer direction.
167 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
168
169 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
170 #if defined(DMAMUX1)
171
172 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
173 This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
174
175 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
176 #else
177
178 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
179 This parameter can be a value of @ref DMA_LL_EC_REQUEST
180
181 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
182 #endif /* DMAMUX1 */
183
184 uint32_t Priority; /*!< Specifies the channel priority level.
185 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
186
187 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
188
189 } LL_DMA_InitTypeDef;
190 /**
191 * @}
192 */
193 #endif /*USE_FULL_LL_DRIVER*/
194
195 /* Exported constants --------------------------------------------------------*/
196 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
197 * @{
198 */
199 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
200 * @brief Flags defines which can be used with LL_DMA_WriteReg function
201 * @{
202 */
203 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
204 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
205 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
206 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
207 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
208 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
209 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
210 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
211 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
212 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
213 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
214 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
215 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
216 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
217 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
218 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
219 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
220 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
221 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
222 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
223 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
224 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
225 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
226 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
227 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
228 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
229 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
230 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
231 /**
232 * @}
233 */
234
235 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
236 * @brief Flags defines which can be used with LL_DMA_ReadReg function
237 * @{
238 */
239 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
240 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
241 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
242 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
243 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
244 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
245 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
246 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
247 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
248 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
249 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
250 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
251 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
252 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
253 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
254 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
255 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
256 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
257 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
258 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
259 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
260 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
261 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
262 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
263 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
264 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
265 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
266 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
267 /**
268 * @}
269 */
270
271 /** @defgroup DMA_LL_EC_IT IT Defines
272 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
273 * @{
274 */
275 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
276 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
277 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
278 /**
279 * @}
280 */
281
282 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
283 * @{
284 */
285 #define LL_DMA_CHANNEL_1 0x00000000U /*!< DMA Channel 1 */
286 #define LL_DMA_CHANNEL_2 0x00000001U /*!< DMA Channel 2 */
287 #define LL_DMA_CHANNEL_3 0x00000002U /*!< DMA Channel 3 */
288 #define LL_DMA_CHANNEL_4 0x00000003U /*!< DMA Channel 4 */
289 #define LL_DMA_CHANNEL_5 0x00000004U /*!< DMA Channel 5 */
290 #define LL_DMA_CHANNEL_6 0x00000005U /*!< DMA Channel 6 */
291 #define LL_DMA_CHANNEL_7 0x00000006U /*!< DMA Channel 7 */
292 #if defined(USE_FULL_LL_DRIVER)
293 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
294 #endif /*USE_FULL_LL_DRIVER*/
295 /**
296 * @}
297 */
298
299 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
300 * @{
301 */
302 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
303 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
304 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
305 /**
306 * @}
307 */
308
309 /** @defgroup DMA_LL_EC_MODE Transfer mode
310 * @{
311 */
312 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
313 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
314 /**
315 * @}
316 */
317
318 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
319 * @{
320 */
321 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
322 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
323 /**
324 * @}
325 */
326
327 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
328 * @{
329 */
330 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
331 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
332 /**
333 * @}
334 */
335
336 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
337 * @{
338 */
339 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
340 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
341 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
342 /**
343 * @}
344 */
345
346 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
347 * @{
348 */
349 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
350 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
351 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
352 /**
353 * @}
354 */
355
356 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
357 * @{
358 */
359 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
360 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
361 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
362 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
363 /**
364 * @}
365 */
366
367 #if !defined (DMAMUX1)
368 /** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
369 * @{
370 */
371 #define LL_DMA_REQUEST_0 0x00000000U /*!< DMA peripheral request 0 */
372 #define LL_DMA_REQUEST_1 0x00000001U /*!< DMA peripheral request 1 */
373 #define LL_DMA_REQUEST_2 0x00000002U /*!< DMA peripheral request 2 */
374 #define LL_DMA_REQUEST_3 0x00000003U /*!< DMA peripheral request 3 */
375 #define LL_DMA_REQUEST_4 0x00000004U /*!< DMA peripheral request 4 */
376 #define LL_DMA_REQUEST_5 0x00000005U /*!< DMA peripheral request 5 */
377 #define LL_DMA_REQUEST_6 0x00000006U /*!< DMA peripheral request 6 */
378 #define LL_DMA_REQUEST_7 0x00000007U /*!< DMA peripheral request 7 */
379 /**
380 * @}
381 */
382 #endif /* !defined DMAMUX1 */
383
384 /**
385 * @}
386 */
387
388 /* Exported macro ------------------------------------------------------------*/
389 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
390 * @{
391 */
392
393 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
394 * @{
395 */
396 /**
397 * @brief Write a value in DMA register
398 * @param __INSTANCE__ DMA Instance
399 * @param __REG__ Register to be written
400 * @param __VALUE__ Value to be written in the register
401 * @retval None
402 */
403 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
404
405 /**
406 * @brief Read a value in DMA register
407 * @param __INSTANCE__ DMA Instance
408 * @param __REG__ Register to be read
409 * @retval Register value
410 */
411 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
412 /**
413 * @}
414 */
415
416 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
417 * @{
418 */
419 /**
420 * @brief Convert DMAx_Channely into DMAx
421 * @param __CHANNEL_INSTANCE__ DMAx_Channely
422 * @retval DMAx
423 */
424 #if defined(DMA2)
425 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
426 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
427 #else
428 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
429 #endif
430
431 /**
432 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
433 * @param __CHANNEL_INSTANCE__ DMAx_Channely
434 * @retval LL_DMA_CHANNEL_y
435 */
436 #if defined (DMA2)
437 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
438 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
439 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
440 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
441 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
442 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
443 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
444 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
445 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
446 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
447 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
448 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
449 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
450 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
451 LL_DMA_CHANNEL_7)
452 #else
453 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
454 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
455 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
456 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
457 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
458 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
459 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
460 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
461 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
462 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
463 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
464 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
465 LL_DMA_CHANNEL_7)
466 #endif
467 #else
468 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
469 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
470 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
471 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
472 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
473 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
474 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
475 LL_DMA_CHANNEL_7)
476 #endif
477
478 /**
479 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
480 * @param __DMA_INSTANCE__ DMAx
481 * @param __CHANNEL__ LL_DMA_CHANNEL_y
482 * @retval DMAx_Channely
483 */
484 #if defined (DMA2)
485 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
486 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
487 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
488 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
489 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
490 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
491 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
492 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
493 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
494 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
495 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
496 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
497 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
498 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
499 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
500 DMA2_Channel7)
501 #else
502 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
503 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
504 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
505 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
506 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
507 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
508 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
509 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
510 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
511 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
512 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
513 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
514 DMA1_Channel7)
515 #endif
516 #else
517 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
518 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
519 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
520 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
521 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
522 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
523 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
524 DMA1_Channel7)
525 #endif
526
527 /**
528 * @}
529 */
530
531 /**
532 * @}
533 */
534
535 /* Exported functions --------------------------------------------------------*/
536 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
537 * @{
538 */
539
540 /** @defgroup DMA_LL_EF_Configuration Configuration
541 * @{
542 */
543 /**
544 * @brief Enable DMA channel.
545 * @rmtoll CCR EN LL_DMA_EnableChannel
546 * @param DMAx DMAx Instance
547 * @param Channel This parameter can be one of the following values:
548 * @arg @ref LL_DMA_CHANNEL_1
549 * @arg @ref LL_DMA_CHANNEL_2
550 * @arg @ref LL_DMA_CHANNEL_3
551 * @arg @ref LL_DMA_CHANNEL_4
552 * @arg @ref LL_DMA_CHANNEL_5
553 * @arg @ref LL_DMA_CHANNEL_6
554 * @arg @ref LL_DMA_CHANNEL_7
555 * @retval None
556 */
LL_DMA_EnableChannel(DMA_TypeDef * DMAx,uint32_t Channel)557 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
558 {
559 uint32_t dma_base_addr = (uint32_t)DMAx;
560 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
561 }
562
563 /**
564 * @brief Disable DMA channel.
565 * @rmtoll CCR EN LL_DMA_DisableChannel
566 * @param DMAx DMAx Instance
567 * @param Channel This parameter can be one of the following values:
568 * @arg @ref LL_DMA_CHANNEL_1
569 * @arg @ref LL_DMA_CHANNEL_2
570 * @arg @ref LL_DMA_CHANNEL_3
571 * @arg @ref LL_DMA_CHANNEL_4
572 * @arg @ref LL_DMA_CHANNEL_5
573 * @arg @ref LL_DMA_CHANNEL_6
574 * @arg @ref LL_DMA_CHANNEL_7
575 * @retval None
576 */
LL_DMA_DisableChannel(DMA_TypeDef * DMAx,uint32_t Channel)577 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
578 {
579 uint32_t dma_base_addr = (uint32_t)DMAx;
580 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
581 }
582
583 /**
584 * @brief Check if DMA channel is enabled or disabled.
585 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
586 * @param DMAx DMAx Instance
587 * @param Channel This parameter can be one of the following values:
588 * @arg @ref LL_DMA_CHANNEL_1
589 * @arg @ref LL_DMA_CHANNEL_2
590 * @arg @ref LL_DMA_CHANNEL_3
591 * @arg @ref LL_DMA_CHANNEL_4
592 * @arg @ref LL_DMA_CHANNEL_5
593 * @arg @ref LL_DMA_CHANNEL_6
594 * @arg @ref LL_DMA_CHANNEL_7
595 * @retval State of bit (1 or 0).
596 */
LL_DMA_IsEnabledChannel(DMA_TypeDef * DMAx,uint32_t Channel)597 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
598 {
599 uint32_t dma_base_addr = (uint32_t)DMAx;
600 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
601 DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
602 }
603
604 /**
605 * @brief Configure all parameters link to DMA transfer.
606 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
607 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
608 * CCR CIRC LL_DMA_ConfigTransfer\n
609 * CCR PINC LL_DMA_ConfigTransfer\n
610 * CCR MINC LL_DMA_ConfigTransfer\n
611 * CCR PSIZE LL_DMA_ConfigTransfer\n
612 * CCR MSIZE LL_DMA_ConfigTransfer\n
613 * CCR PL LL_DMA_ConfigTransfer
614 * @param DMAx DMAx Instance
615 * @param Channel This parameter can be one of the following values:
616 * @arg @ref LL_DMA_CHANNEL_1
617 * @arg @ref LL_DMA_CHANNEL_2
618 * @arg @ref LL_DMA_CHANNEL_3
619 * @arg @ref LL_DMA_CHANNEL_4
620 * @arg @ref LL_DMA_CHANNEL_5
621 * @arg @ref LL_DMA_CHANNEL_6
622 * @arg @ref LL_DMA_CHANNEL_7
623 * @param Configuration This parameter must be a combination of all the following values:
624 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
625 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
626 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
627 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
628 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
629 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
630 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
631 * @retval None
632 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)633 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
634 {
635 uint32_t dma_base_addr = (uint32_t)DMAx;
636 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
637 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
638 Configuration);
639 }
640
641 /**
642 * @brief Set Data transfer direction (read from peripheral or from memory).
643 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
644 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
645 * @param DMAx DMAx Instance
646 * @param Channel This parameter can be one of the following values:
647 * @arg @ref LL_DMA_CHANNEL_1
648 * @arg @ref LL_DMA_CHANNEL_2
649 * @arg @ref LL_DMA_CHANNEL_3
650 * @arg @ref LL_DMA_CHANNEL_4
651 * @arg @ref LL_DMA_CHANNEL_5
652 * @arg @ref LL_DMA_CHANNEL_6
653 * @arg @ref LL_DMA_CHANNEL_7
654 * @param Direction This parameter can be one of the following values:
655 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
656 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
657 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
658 * @retval None
659 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)660 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
661 {
662 uint32_t dma_base_addr = (uint32_t)DMAx;
663 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
664 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
665 }
666
667 /**
668 * @brief Get Data transfer direction (read from peripheral or from memory).
669 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
670 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
671 * @param DMAx DMAx Instance
672 * @param Channel This parameter can be one of the following values:
673 * @arg @ref LL_DMA_CHANNEL_1
674 * @arg @ref LL_DMA_CHANNEL_2
675 * @arg @ref LL_DMA_CHANNEL_3
676 * @arg @ref LL_DMA_CHANNEL_4
677 * @arg @ref LL_DMA_CHANNEL_5
678 * @arg @ref LL_DMA_CHANNEL_6
679 * @arg @ref LL_DMA_CHANNEL_7
680 * @retval Returned value can be one of the following values:
681 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
682 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
683 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
684 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel)685 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
686 {
687 uint32_t dma_base_addr = (uint32_t)DMAx;
688 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
689 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
690 }
691
692 /**
693 * @brief Set DMA mode circular or normal.
694 * @note The circular buffer mode cannot be used if the memory-to-memory
695 * data transfer is configured on the selected Channel.
696 * @rmtoll CCR CIRC LL_DMA_SetMode
697 * @param DMAx DMAx Instance
698 * @param Channel This parameter can be one of the following values:
699 * @arg @ref LL_DMA_CHANNEL_1
700 * @arg @ref LL_DMA_CHANNEL_2
701 * @arg @ref LL_DMA_CHANNEL_3
702 * @arg @ref LL_DMA_CHANNEL_4
703 * @arg @ref LL_DMA_CHANNEL_5
704 * @arg @ref LL_DMA_CHANNEL_6
705 * @arg @ref LL_DMA_CHANNEL_7
706 * @param Mode This parameter can be one of the following values:
707 * @arg @ref LL_DMA_MODE_NORMAL
708 * @arg @ref LL_DMA_MODE_CIRCULAR
709 * @retval None
710 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Mode)711 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
712 {
713 uint32_t dma_base_addr = (uint32_t)DMAx;
714 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CIRC,
715 Mode);
716 }
717
718 /**
719 * @brief Get DMA mode circular or normal.
720 * @rmtoll CCR CIRC LL_DMA_GetMode
721 * @param DMAx DMAx Instance
722 * @param Channel This parameter can be one of the following values:
723 * @arg @ref LL_DMA_CHANNEL_1
724 * @arg @ref LL_DMA_CHANNEL_2
725 * @arg @ref LL_DMA_CHANNEL_3
726 * @arg @ref LL_DMA_CHANNEL_4
727 * @arg @ref LL_DMA_CHANNEL_5
728 * @arg @ref LL_DMA_CHANNEL_6
729 * @arg @ref LL_DMA_CHANNEL_7
730 * @retval Returned value can be one of the following values:
731 * @arg @ref LL_DMA_MODE_NORMAL
732 * @arg @ref LL_DMA_MODE_CIRCULAR
733 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Channel)734 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
735 {
736 uint32_t dma_base_addr = (uint32_t)DMAx;
737 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
738 DMA_CCR_CIRC));
739 }
740
741 /**
742 * @brief Set Peripheral increment mode.
743 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
744 * @param DMAx DMAx Instance
745 * @param Channel This parameter can be one of the following values:
746 * @arg @ref LL_DMA_CHANNEL_1
747 * @arg @ref LL_DMA_CHANNEL_2
748 * @arg @ref LL_DMA_CHANNEL_3
749 * @arg @ref LL_DMA_CHANNEL_4
750 * @arg @ref LL_DMA_CHANNEL_5
751 * @arg @ref LL_DMA_CHANNEL_6
752 * @arg @ref LL_DMA_CHANNEL_7
753 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
754 * @arg @ref LL_DMA_PERIPH_INCREMENT
755 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
756 * @retval None
757 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcIncMode)758 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
759 {
760 uint32_t dma_base_addr = (uint32_t)DMAx;
761 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PINC,
762 PeriphOrM2MSrcIncMode);
763 }
764
765 /**
766 * @brief Get Peripheral increment mode.
767 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
768 * @param DMAx DMAx Instance
769 * @param Channel This parameter can be one of the following values:
770 * @arg @ref LL_DMA_CHANNEL_1
771 * @arg @ref LL_DMA_CHANNEL_2
772 * @arg @ref LL_DMA_CHANNEL_3
773 * @arg @ref LL_DMA_CHANNEL_4
774 * @arg @ref LL_DMA_CHANNEL_5
775 * @arg @ref LL_DMA_CHANNEL_6
776 * @arg @ref LL_DMA_CHANNEL_7
777 * @retval Returned value can be one of the following values:
778 * @arg @ref LL_DMA_PERIPH_INCREMENT
779 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
780 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel)781 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
782 {
783 uint32_t dma_base_addr = (uint32_t)DMAx;
784 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
785 DMA_CCR_PINC));
786 }
787
788 /**
789 * @brief Set Memory increment mode.
790 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
791 * @param DMAx DMAx Instance
792 * @param Channel This parameter can be one of the following values:
793 * @arg @ref LL_DMA_CHANNEL_1
794 * @arg @ref LL_DMA_CHANNEL_2
795 * @arg @ref LL_DMA_CHANNEL_3
796 * @arg @ref LL_DMA_CHANNEL_4
797 * @arg @ref LL_DMA_CHANNEL_5
798 * @arg @ref LL_DMA_CHANNEL_6
799 * @arg @ref LL_DMA_CHANNEL_7
800 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
801 * @arg @ref LL_DMA_MEMORY_INCREMENT
802 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
803 * @retval None
804 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstIncMode)805 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
806 {
807 uint32_t dma_base_addr = (uint32_t)DMAx;
808 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MINC,
809 MemoryOrM2MDstIncMode);
810 }
811
812 /**
813 * @brief Get Memory increment mode.
814 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
815 * @param DMAx DMAx Instance
816 * @param Channel This parameter can be one of the following values:
817 * @arg @ref LL_DMA_CHANNEL_1
818 * @arg @ref LL_DMA_CHANNEL_2
819 * @arg @ref LL_DMA_CHANNEL_3
820 * @arg @ref LL_DMA_CHANNEL_4
821 * @arg @ref LL_DMA_CHANNEL_5
822 * @arg @ref LL_DMA_CHANNEL_6
823 * @arg @ref LL_DMA_CHANNEL_7
824 * @retval Returned value can be one of the following values:
825 * @arg @ref LL_DMA_MEMORY_INCREMENT
826 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
827 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel)828 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
829 {
830 uint32_t dma_base_addr = (uint32_t)DMAx;
831 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
832 DMA_CCR_MINC));
833 }
834
835 /**
836 * @brief Set Peripheral size.
837 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
838 * @param DMAx DMAx Instance
839 * @param Channel This parameter can be one of the following values:
840 * @arg @ref LL_DMA_CHANNEL_1
841 * @arg @ref LL_DMA_CHANNEL_2
842 * @arg @ref LL_DMA_CHANNEL_3
843 * @arg @ref LL_DMA_CHANNEL_4
844 * @arg @ref LL_DMA_CHANNEL_5
845 * @arg @ref LL_DMA_CHANNEL_6
846 * @arg @ref LL_DMA_CHANNEL_7
847 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
848 * @arg @ref LL_DMA_PDATAALIGN_BYTE
849 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
850 * @arg @ref LL_DMA_PDATAALIGN_WORD
851 * @retval None
852 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcDataSize)853 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
854 {
855 uint32_t dma_base_addr = (uint32_t)DMAx;
856 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PSIZE,
857 PeriphOrM2MSrcDataSize);
858 }
859
860 /**
861 * @brief Get Peripheral size.
862 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
863 * @param DMAx DMAx Instance
864 * @param Channel This parameter can be one of the following values:
865 * @arg @ref LL_DMA_CHANNEL_1
866 * @arg @ref LL_DMA_CHANNEL_2
867 * @arg @ref LL_DMA_CHANNEL_3
868 * @arg @ref LL_DMA_CHANNEL_4
869 * @arg @ref LL_DMA_CHANNEL_5
870 * @arg @ref LL_DMA_CHANNEL_6
871 * @arg @ref LL_DMA_CHANNEL_7
872 * @retval Returned value can be one of the following values:
873 * @arg @ref LL_DMA_PDATAALIGN_BYTE
874 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
875 * @arg @ref LL_DMA_PDATAALIGN_WORD
876 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel)877 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
878 {
879 uint32_t dma_base_addr = (uint32_t)DMAx;
880 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
881 DMA_CCR_PSIZE));
882 }
883
884 /**
885 * @brief Set Memory size.
886 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
887 * @param DMAx DMAx Instance
888 * @param Channel This parameter can be one of the following values:
889 * @arg @ref LL_DMA_CHANNEL_1
890 * @arg @ref LL_DMA_CHANNEL_2
891 * @arg @ref LL_DMA_CHANNEL_3
892 * @arg @ref LL_DMA_CHANNEL_4
893 * @arg @ref LL_DMA_CHANNEL_5
894 * @arg @ref LL_DMA_CHANNEL_6
895 * @arg @ref LL_DMA_CHANNEL_7
896 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
897 * @arg @ref LL_DMA_MDATAALIGN_BYTE
898 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
899 * @arg @ref LL_DMA_MDATAALIGN_WORD
900 * @retval None
901 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstDataSize)902 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
903 {
904 uint32_t dma_base_addr = (uint32_t)DMAx;
905 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MSIZE,
906 MemoryOrM2MDstDataSize);
907 }
908
909 /**
910 * @brief Get Memory size.
911 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
912 * @param DMAx DMAx Instance
913 * @param Channel This parameter can be one of the following values:
914 * @arg @ref LL_DMA_CHANNEL_1
915 * @arg @ref LL_DMA_CHANNEL_2
916 * @arg @ref LL_DMA_CHANNEL_3
917 * @arg @ref LL_DMA_CHANNEL_4
918 * @arg @ref LL_DMA_CHANNEL_5
919 * @arg @ref LL_DMA_CHANNEL_6
920 * @arg @ref LL_DMA_CHANNEL_7
921 * @retval Returned value can be one of the following values:
922 * @arg @ref LL_DMA_MDATAALIGN_BYTE
923 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
924 * @arg @ref LL_DMA_MDATAALIGN_WORD
925 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel)926 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
927 {
928 uint32_t dma_base_addr = (uint32_t)DMAx;
929 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
930 DMA_CCR_MSIZE));
931 }
932
933 /**
934 * @brief Set Channel priority level.
935 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
936 * @param DMAx DMAx Instance
937 * @param Channel This parameter can be one of the following values:
938 * @arg @ref LL_DMA_CHANNEL_1
939 * @arg @ref LL_DMA_CHANNEL_2
940 * @arg @ref LL_DMA_CHANNEL_3
941 * @arg @ref LL_DMA_CHANNEL_4
942 * @arg @ref LL_DMA_CHANNEL_5
943 * @arg @ref LL_DMA_CHANNEL_6
944 * @arg @ref LL_DMA_CHANNEL_7
945 * @param Priority This parameter can be one of the following values:
946 * @arg @ref LL_DMA_PRIORITY_LOW
947 * @arg @ref LL_DMA_PRIORITY_MEDIUM
948 * @arg @ref LL_DMA_PRIORITY_HIGH
949 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
950 * @retval None
951 */
LL_DMA_SetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)952 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
953 {
954 uint32_t dma_base_addr = (uint32_t)DMAx;
955 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PL,
956 Priority);
957 }
958
959 /**
960 * @brief Get Channel priority level.
961 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
962 * @param DMAx DMAx Instance
963 * @param Channel This parameter can be one of the following values:
964 * @arg @ref LL_DMA_CHANNEL_1
965 * @arg @ref LL_DMA_CHANNEL_2
966 * @arg @ref LL_DMA_CHANNEL_3
967 * @arg @ref LL_DMA_CHANNEL_4
968 * @arg @ref LL_DMA_CHANNEL_5
969 * @arg @ref LL_DMA_CHANNEL_6
970 * @arg @ref LL_DMA_CHANNEL_7
971 * @retval Returned value can be one of the following values:
972 * @arg @ref LL_DMA_PRIORITY_LOW
973 * @arg @ref LL_DMA_PRIORITY_MEDIUM
974 * @arg @ref LL_DMA_PRIORITY_HIGH
975 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
976 */
LL_DMA_GetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel)977 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
978 {
979 uint32_t dma_base_addr = (uint32_t)DMAx;
980 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
981 DMA_CCR_PL));
982 }
983
984 /**
985 * @brief Set Number of data to transfer.
986 * @note This action has no effect if
987 * channel is enabled.
988 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
989 * @param DMAx DMAx Instance
990 * @param Channel This parameter can be one of the following values:
991 * @arg @ref LL_DMA_CHANNEL_1
992 * @arg @ref LL_DMA_CHANNEL_2
993 * @arg @ref LL_DMA_CHANNEL_3
994 * @arg @ref LL_DMA_CHANNEL_4
995 * @arg @ref LL_DMA_CHANNEL_5
996 * @arg @ref LL_DMA_CHANNEL_6
997 * @arg @ref LL_DMA_CHANNEL_7
998 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
999 * @retval None
1000 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t NbData)1001 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
1002 {
1003 uint32_t dma_base_addr = (uint32_t)DMAx;
1004 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR,
1005 DMA_CNDTR_NDT, NbData);
1006 }
1007
1008 /**
1009 * @brief Get Number of data to transfer.
1010 * @note Once the channel is enabled, the return value indicate the
1011 * remaining bytes to be transmitted.
1012 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
1013 * @param DMAx DMAx Instance
1014 * @param Channel This parameter can be one of the following values:
1015 * @arg @ref LL_DMA_CHANNEL_1
1016 * @arg @ref LL_DMA_CHANNEL_2
1017 * @arg @ref LL_DMA_CHANNEL_3
1018 * @arg @ref LL_DMA_CHANNEL_4
1019 * @arg @ref LL_DMA_CHANNEL_5
1020 * @arg @ref LL_DMA_CHANNEL_6
1021 * @arg @ref LL_DMA_CHANNEL_7
1022 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1023 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Channel)1024 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
1025 {
1026 uint32_t dma_base_addr = (uint32_t)DMAx;
1027 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR,
1028 DMA_CNDTR_NDT));
1029 }
1030
1031 /**
1032 * @brief Configure the Source and Destination addresses.
1033 * @note This API must not be called when the DMA channel is enabled.
1034 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
1035 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
1036 * CMAR MA LL_DMA_ConfigAddresses
1037 * @param DMAx DMAx Instance
1038 * @param Channel This parameter can be one of the following values:
1039 * @arg @ref LL_DMA_CHANNEL_1
1040 * @arg @ref LL_DMA_CHANNEL_2
1041 * @arg @ref LL_DMA_CHANNEL_3
1042 * @arg @ref LL_DMA_CHANNEL_4
1043 * @arg @ref LL_DMA_CHANNEL_5
1044 * @arg @ref LL_DMA_CHANNEL_6
1045 * @arg @ref LL_DMA_CHANNEL_7
1046 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1047 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1048 * @param Direction This parameter can be one of the following values:
1049 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1050 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1051 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1052 * @retval None
1053 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)1054 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
1055 uint32_t DstAddress, uint32_t Direction)
1056 {
1057 uint32_t dma_base_addr = (uint32_t)DMAx;
1058 /* Direction Memory to Periph */
1059 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
1060 {
1061 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, SrcAddress);
1062 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, DstAddress);
1063 }
1064 /* Direction Periph to Memory and Memory to Memory */
1065 else
1066 {
1067 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, SrcAddress);
1068 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, DstAddress);
1069 }
1070 }
1071
1072 /**
1073 * @brief Set the Memory address.
1074 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1075 * @note This API must not be called when the DMA channel is enabled.
1076 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
1077 * @param DMAx DMAx Instance
1078 * @param Channel This parameter can be one of the following values:
1079 * @arg @ref LL_DMA_CHANNEL_1
1080 * @arg @ref LL_DMA_CHANNEL_2
1081 * @arg @ref LL_DMA_CHANNEL_3
1082 * @arg @ref LL_DMA_CHANNEL_4
1083 * @arg @ref LL_DMA_CHANNEL_5
1084 * @arg @ref LL_DMA_CHANNEL_6
1085 * @arg @ref LL_DMA_CHANNEL_7
1086 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1087 * @retval None
1088 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1089 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1090 {
1091 uint32_t dma_base_addr = (uint32_t)DMAx;
1092 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress);
1093 }
1094
1095 /**
1096 * @brief Set the Peripheral address.
1097 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1098 * @note This API must not be called when the DMA channel is enabled.
1099 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
1100 * @param DMAx DMAx Instance
1101 * @param Channel This parameter can be one of the following values:
1102 * @arg @ref LL_DMA_CHANNEL_1
1103 * @arg @ref LL_DMA_CHANNEL_2
1104 * @arg @ref LL_DMA_CHANNEL_3
1105 * @arg @ref LL_DMA_CHANNEL_4
1106 * @arg @ref LL_DMA_CHANNEL_5
1107 * @arg @ref LL_DMA_CHANNEL_6
1108 * @arg @ref LL_DMA_CHANNEL_7
1109 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1110 * @retval None
1111 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphAddress)1112 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
1113 {
1114 uint32_t dma_base_addr = (uint32_t)DMAx;
1115 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, PeriphAddress);
1116 }
1117
1118 /**
1119 * @brief Get Memory address.
1120 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1121 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
1122 * @param DMAx DMAx Instance
1123 * @param Channel This parameter can be one of the following values:
1124 * @arg @ref LL_DMA_CHANNEL_1
1125 * @arg @ref LL_DMA_CHANNEL_2
1126 * @arg @ref LL_DMA_CHANNEL_3
1127 * @arg @ref LL_DMA_CHANNEL_4
1128 * @arg @ref LL_DMA_CHANNEL_5
1129 * @arg @ref LL_DMA_CHANNEL_6
1130 * @arg @ref LL_DMA_CHANNEL_7
1131 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1132 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel)1133 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1134 {
1135 uint32_t dma_base_addr = (uint32_t)DMAx;
1136 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR));
1137 }
1138
1139 /**
1140 * @brief Get Peripheral address.
1141 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1142 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
1143 * @param DMAx DMAx Instance
1144 * @param Channel This parameter can be one of the following values:
1145 * @arg @ref LL_DMA_CHANNEL_1
1146 * @arg @ref LL_DMA_CHANNEL_2
1147 * @arg @ref LL_DMA_CHANNEL_3
1148 * @arg @ref LL_DMA_CHANNEL_4
1149 * @arg @ref LL_DMA_CHANNEL_5
1150 * @arg @ref LL_DMA_CHANNEL_6
1151 * @arg @ref LL_DMA_CHANNEL_7
1152 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1153 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel)1154 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1155 {
1156 uint32_t dma_base_addr = (uint32_t)DMAx;
1157 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR));
1158 }
1159
1160 /**
1161 * @brief Set the Memory to Memory Source address.
1162 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1163 * @note This API must not be called when the DMA channel is enabled.
1164 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
1165 * @param DMAx DMAx Instance
1166 * @param Channel This parameter can be one of the following values:
1167 * @arg @ref LL_DMA_CHANNEL_1
1168 * @arg @ref LL_DMA_CHANNEL_2
1169 * @arg @ref LL_DMA_CHANNEL_3
1170 * @arg @ref LL_DMA_CHANNEL_4
1171 * @arg @ref LL_DMA_CHANNEL_5
1172 * @arg @ref LL_DMA_CHANNEL_6
1173 * @arg @ref LL_DMA_CHANNEL_7
1174 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1175 * @retval None
1176 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1177 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1178 {
1179 uint32_t dma_base_addr = (uint32_t)DMAx;
1180 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, MemoryAddress);
1181 }
1182
1183 /**
1184 * @brief Set the Memory to Memory Destination address.
1185 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1186 * @note This API must not be called when the DMA channel is enabled.
1187 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
1188 * @param DMAx DMAx Instance
1189 * @param Channel This parameter can be one of the following values:
1190 * @arg @ref LL_DMA_CHANNEL_1
1191 * @arg @ref LL_DMA_CHANNEL_2
1192 * @arg @ref LL_DMA_CHANNEL_3
1193 * @arg @ref LL_DMA_CHANNEL_4
1194 * @arg @ref LL_DMA_CHANNEL_5
1195 * @arg @ref LL_DMA_CHANNEL_6
1196 * @arg @ref LL_DMA_CHANNEL_7
1197 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1198 * @retval None
1199 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1200 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1201 {
1202 uint32_t dma_base_addr = (uint32_t)DMAx;
1203 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress);
1204 }
1205
1206 /**
1207 * @brief Get the Memory to Memory Source address.
1208 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1209 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
1210 * @param DMAx DMAx Instance
1211 * @param Channel This parameter can be one of the following values:
1212 * @arg @ref LL_DMA_CHANNEL_1
1213 * @arg @ref LL_DMA_CHANNEL_2
1214 * @arg @ref LL_DMA_CHANNEL_3
1215 * @arg @ref LL_DMA_CHANNEL_4
1216 * @arg @ref LL_DMA_CHANNEL_5
1217 * @arg @ref LL_DMA_CHANNEL_6
1218 * @arg @ref LL_DMA_CHANNEL_7
1219 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1220 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel)1221 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1222 {
1223 uint32_t dma_base_addr = (uint32_t)DMAx;
1224 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR));
1225 }
1226
1227 /**
1228 * @brief Get the Memory to Memory Destination address.
1229 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1230 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
1231 * @param DMAx DMAx Instance
1232 * @param Channel This parameter can be one of the following values:
1233 * @arg @ref LL_DMA_CHANNEL_1
1234 * @arg @ref LL_DMA_CHANNEL_2
1235 * @arg @ref LL_DMA_CHANNEL_3
1236 * @arg @ref LL_DMA_CHANNEL_4
1237 * @arg @ref LL_DMA_CHANNEL_5
1238 * @arg @ref LL_DMA_CHANNEL_6
1239 * @arg @ref LL_DMA_CHANNEL_7
1240 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1241 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel)1242 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1243 {
1244 uint32_t dma_base_addr = (uint32_t)DMAx;
1245 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR));
1246 }
1247
1248 #if defined(DMAMUX1)
1249 /**
1250 * @brief Set DMA request for DMA Channels on DMAMUX Channel x.
1251 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1252 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
1253 * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
1254 * @param DMAx DMAx Instance
1255 * @param Channel This parameter can be one of the following values:
1256 * @arg @ref LL_DMA_CHANNEL_1
1257 * @arg @ref LL_DMA_CHANNEL_2
1258 * @arg @ref LL_DMA_CHANNEL_3
1259 * @arg @ref LL_DMA_CHANNEL_4
1260 * @arg @ref LL_DMA_CHANNEL_5
1261 * @arg @ref LL_DMA_CHANNEL_6
1262 * @arg @ref LL_DMA_CHANNEL_7
1263 * @param Request This parameter can be one of the following values:
1264 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
1265 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1266 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1267 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1268 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1269 * @arg @ref LL_DMAMUX_REQ_ADC1
1270 * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
1271 * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
1272 * @arg @ref LL_DMAMUX_REQ_TIM6_UP
1273 * @arg @ref LL_DMAMUX_REQ_TIM7_UP
1274 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1275 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1276 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
1277 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
1278 * @arg @ref LL_DMAMUX_REQ_SPI3_RX
1279 * @arg @ref LL_DMAMUX_REQ_SPI3_TX
1280 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1281 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1282 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
1283 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
1284 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
1285 * @arg @ref LL_DMAMUX_REQ_I2C3_TX
1286 * @arg @ref LL_DMAMUX_REQ_I2C4_RX
1287 * @arg @ref LL_DMAMUX_REQ_I2C4_TX
1288 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1289 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1290 * @arg @ref LL_DMAMUX_REQ_USART2_RX
1291 * @arg @ref LL_DMAMUX_REQ_USART2_TX
1292 * @arg @ref LL_DMAMUX_REQ_USART3_RX
1293 * @arg @ref LL_DMAMUX_REQ_USART3_TX
1294 * @arg @ref LL_DMAMUX_REQ_UART4_RX
1295 * @arg @ref LL_DMAMUX_REQ_UART4_TX
1296 * @arg @ref LL_DMAMUX_REQ_UART5_RX
1297 * @arg @ref LL_DMAMUX_REQ_UART5_TX
1298 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
1299 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
1300 * @arg @ref LL_DMAMUX_REQ_SAI1_A
1301 * @arg @ref LL_DMAMUX_REQ_SAI1_B
1302 * @arg @ref LL_DMAMUX_REQ_SAI2_A
1303 * @arg @ref LL_DMAMUX_REQ_SAI2_B
1304 * @arg @ref LL_DMAMUX_REQ_OSPI1
1305 * @arg @ref LL_DMAMUX_REQ_OSPI2
1306 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1307 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1308 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1309 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1310 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1311 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
1312 * @arg @ref LL_DMAMUX_REQ_TIM1_COM
1313 * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
1314 * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
1315 * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
1316 * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
1317 * @arg @ref LL_DMAMUX_REQ_TIM8_UP
1318 * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
1319 * @arg @ref LL_DMAMUX_REQ_TIM8_COM
1320 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
1321 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
1322 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
1323 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
1324 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
1325 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
1326 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
1327 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
1328 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
1329 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
1330 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
1331 * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
1332 * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
1333 * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
1334 * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
1335 * @arg @ref LL_DMAMUX_REQ_TIM4_UP
1336 * @arg @ref LL_DMAMUX_REQ_TIM5_CH1
1337 * @arg @ref LL_DMAMUX_REQ_TIM5_CH2
1338 * @arg @ref LL_DMAMUX_REQ_TIM5_CH3
1339 * @arg @ref LL_DMAMUX_REQ_TIM5_CH4
1340 * @arg @ref LL_DMAMUX_REQ_TIM5_UP
1341 * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG
1342 * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
1343 * @arg @ref LL_DMAMUX_REQ_TIM15_UP
1344 * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
1345 * @arg @ref LL_DMAMUX_REQ_TIM15_COM
1346 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1347 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1348 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
1349 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1350 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0
1351 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1
1352 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2
1353 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3
1354 * @arg @ref LL_DMAMUX_REQ_DCMI
1355 * @arg @ref LL_DMAMUX_REQ_AES_IN
1356 * @arg @ref LL_DMAMUX_REQ_AES_OUT
1357 * @arg @ref LL_DMAMUX_REQ_HASH_IN
1358 * @retval None
1359 */
LL_DMA_SetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Request)1360 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
1361 {
1362 uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U);
1363 MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
1364 }
1365
1366 /**
1367 * @brief Get DMA request for DMA Channels on DMAMUX Channel x.
1368 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1369 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
1370 * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
1371 * @param DMAx DMAx Instance
1372 * @param Channel This parameter can be one of the following values:
1373 * @arg @ref LL_DMA_CHANNEL_1
1374 * @arg @ref LL_DMA_CHANNEL_2
1375 * @arg @ref LL_DMA_CHANNEL_3
1376 * @arg @ref LL_DMA_CHANNEL_4
1377 * @arg @ref LL_DMA_CHANNEL_5
1378 * @arg @ref LL_DMA_CHANNEL_6
1379 * @arg @ref LL_DMA_CHANNEL_7
1380 * @retval Returned value can be one of the following values:
1381 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
1382 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1383 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1384 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1385 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1386 * @arg @ref LL_DMAMUX_REQ_ADC1
1387 * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
1388 * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
1389 * @arg @ref LL_DMAMUX_REQ_TIM6_UP
1390 * @arg @ref LL_DMAMUX_REQ_TIM7_UP
1391 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1392 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1393 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
1394 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
1395 * @arg @ref LL_DMAMUX_REQ_SPI3_RX
1396 * @arg @ref LL_DMAMUX_REQ_SPI3_TX
1397 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1398 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1399 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
1400 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
1401 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
1402 * @arg @ref LL_DMAMUX_REQ_I2C3_TX
1403 * @arg @ref LL_DMAMUX_REQ_I2C4_RX
1404 * @arg @ref LL_DMAMUX_REQ_I2C4_TX
1405 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1406 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1407 * @arg @ref LL_DMAMUX_REQ_USART2_RX
1408 * @arg @ref LL_DMAMUX_REQ_USART2_TX
1409 * @arg @ref LL_DMAMUX_REQ_USART3_RX
1410 * @arg @ref LL_DMAMUX_REQ_USART3_TX
1411 * @arg @ref LL_DMAMUX_REQ_UART4_RX
1412 * @arg @ref LL_DMAMUX_REQ_UART4_TX
1413 * @arg @ref LL_DMAMUX_REQ_UART5_RX
1414 * @arg @ref LL_DMAMUX_REQ_UART5_TX
1415 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
1416 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
1417 * @arg @ref LL_DMAMUX_REQ_SAI1_A
1418 * @arg @ref LL_DMAMUX_REQ_SAI1_B
1419 * @arg @ref LL_DMAMUX_REQ_SAI2_A
1420 * @arg @ref LL_DMAMUX_REQ_SAI2_B
1421 * @arg @ref LL_DMAMUX_REQ_OSPI1
1422 * @arg @ref LL_DMAMUX_REQ_OSPI2
1423 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1424 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1425 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1426 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1427 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1428 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
1429 * @arg @ref LL_DMAMUX_REQ_TIM1_COM
1430 * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
1431 * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
1432 * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
1433 * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
1434 * @arg @ref LL_DMAMUX_REQ_TIM8_UP
1435 * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
1436 * @arg @ref LL_DMAMUX_REQ_TIM8_COM
1437 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
1438 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
1439 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
1440 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
1441 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
1442 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
1443 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
1444 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
1445 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
1446 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
1447 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
1448 * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
1449 * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
1450 * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
1451 * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
1452 * @arg @ref LL_DMAMUX_REQ_TIM4_UP
1453 * @arg @ref LL_DMAMUX_REQ_TIM5_CH1
1454 * @arg @ref LL_DMAMUX_REQ_TIM5_CH2
1455 * @arg @ref LL_DMAMUX_REQ_TIM5_CH3
1456 * @arg @ref LL_DMAMUX_REQ_TIM5_CH4
1457 * @arg @ref LL_DMAMUX_REQ_TIM5_UP
1458 * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG
1459 * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
1460 * @arg @ref LL_DMAMUX_REQ_TIM15_UP
1461 * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
1462 * @arg @ref LL_DMAMUX_REQ_TIM15_COM
1463 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1464 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1465 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
1466 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1467 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0
1468 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1
1469 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2
1470 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3
1471 * @arg @ref LL_DMAMUX_REQ_DCMI
1472 * @arg @ref LL_DMAMUX_REQ_AES_IN
1473 * @arg @ref LL_DMAMUX_REQ_AES_OUT
1474 * @arg @ref LL_DMAMUX_REQ_HASH_IN
1475 */
LL_DMA_GetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel)1476 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
1477 {
1478 uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U);
1479 return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID));
1480 }
1481 #else
1482 /**
1483 * @brief Set DMA request for DMA instance on Channel x.
1484 * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
1485 * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
1486 * CSELR C2S LL_DMA_SetPeriphRequest\n
1487 * CSELR C3S LL_DMA_SetPeriphRequest\n
1488 * CSELR C4S LL_DMA_SetPeriphRequest\n
1489 * CSELR C5S LL_DMA_SetPeriphRequest\n
1490 * CSELR C6S LL_DMA_SetPeriphRequest\n
1491 * CSELR C7S LL_DMA_SetPeriphRequest
1492 * @param DMAx DMAx Instance
1493 * @param Channel This parameter can be one of the following values:
1494 * @arg @ref LL_DMA_CHANNEL_1
1495 * @arg @ref LL_DMA_CHANNEL_2
1496 * @arg @ref LL_DMA_CHANNEL_3
1497 * @arg @ref LL_DMA_CHANNEL_4
1498 * @arg @ref LL_DMA_CHANNEL_5
1499 * @arg @ref LL_DMA_CHANNEL_6
1500 * @arg @ref LL_DMA_CHANNEL_7
1501 * @param PeriphRequest This parameter can be one of the following values:
1502 * @arg @ref LL_DMA_REQUEST_0
1503 * @arg @ref LL_DMA_REQUEST_1
1504 * @arg @ref LL_DMA_REQUEST_2
1505 * @arg @ref LL_DMA_REQUEST_3
1506 * @arg @ref LL_DMA_REQUEST_4
1507 * @arg @ref LL_DMA_REQUEST_5
1508 * @arg @ref LL_DMA_REQUEST_6
1509 * @arg @ref LL_DMA_REQUEST_7
1510 * @retval None
1511 */
LL_DMA_SetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphRequest)1512 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
1513 {
1514 MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
1515 DMA_CSELR_C1S << ((Channel) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);
1516 }
1517
1518 /**
1519 * @brief Get DMA request for DMA instance on Channel x.
1520 * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
1521 * CSELR C2S LL_DMA_GetPeriphRequest\n
1522 * CSELR C3S LL_DMA_GetPeriphRequest\n
1523 * CSELR C4S LL_DMA_GetPeriphRequest\n
1524 * CSELR C5S LL_DMA_GetPeriphRequest\n
1525 * CSELR C6S LL_DMA_GetPeriphRequest\n
1526 * CSELR C7S LL_DMA_GetPeriphRequest
1527 * @param DMAx DMAx Instance
1528 * @param Channel This parameter can be one of the following values:
1529 * @arg @ref LL_DMA_CHANNEL_1
1530 * @arg @ref LL_DMA_CHANNEL_2
1531 * @arg @ref LL_DMA_CHANNEL_3
1532 * @arg @ref LL_DMA_CHANNEL_4
1533 * @arg @ref LL_DMA_CHANNEL_5
1534 * @arg @ref LL_DMA_CHANNEL_6
1535 * @arg @ref LL_DMA_CHANNEL_7
1536 * @retval Returned value can be one of the following values:
1537 * @arg @ref LL_DMA_REQUEST_0
1538 * @arg @ref LL_DMA_REQUEST_1
1539 * @arg @ref LL_DMA_REQUEST_2
1540 * @arg @ref LL_DMA_REQUEST_3
1541 * @arg @ref LL_DMA_REQUEST_4
1542 * @arg @ref LL_DMA_REQUEST_5
1543 * @arg @ref LL_DMA_REQUEST_6
1544 * @arg @ref LL_DMA_REQUEST_7
1545 */
LL_DMA_GetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel)1546 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
1547 {
1548 return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
1549 DMA_CSELR_C1S << ((Channel) * 4U)) >> DMA_POSITION_CSELR_CXS);
1550 }
1551 #endif /* DMAMUX1 */
1552
1553 /**
1554 * @}
1555 */
1556
1557 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1558 * @{
1559 */
1560
1561 /**
1562 * @brief Get Channel 1 global interrupt flag.
1563 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
1564 * @param DMAx DMAx Instance
1565 * @retval State of bit (1 or 0).
1566 */
LL_DMA_IsActiveFlag_GI1(DMA_TypeDef * DMAx)1567 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
1568 {
1569 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
1570 }
1571
1572 /**
1573 * @brief Get Channel 2 global interrupt flag.
1574 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
1575 * @param DMAx DMAx Instance
1576 * @retval State of bit (1 or 0).
1577 */
LL_DMA_IsActiveFlag_GI2(DMA_TypeDef * DMAx)1578 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
1579 {
1580 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
1581 }
1582
1583 /**
1584 * @brief Get Channel 3 global interrupt flag.
1585 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
1586 * @param DMAx DMAx Instance
1587 * @retval State of bit (1 or 0).
1588 */
LL_DMA_IsActiveFlag_GI3(DMA_TypeDef * DMAx)1589 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
1590 {
1591 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
1592 }
1593
1594 /**
1595 * @brief Get Channel 4 global interrupt flag.
1596 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
1597 * @param DMAx DMAx Instance
1598 * @retval State of bit (1 or 0).
1599 */
LL_DMA_IsActiveFlag_GI4(DMA_TypeDef * DMAx)1600 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
1601 {
1602 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
1603 }
1604
1605 /**
1606 * @brief Get Channel 5 global interrupt flag.
1607 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
1608 * @param DMAx DMAx Instance
1609 * @retval State of bit (1 or 0).
1610 */
LL_DMA_IsActiveFlag_GI5(DMA_TypeDef * DMAx)1611 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
1612 {
1613 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
1614 }
1615
1616 /**
1617 * @brief Get Channel 6 global interrupt flag.
1618 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
1619 * @param DMAx DMAx Instance
1620 * @retval State of bit (1 or 0).
1621 */
LL_DMA_IsActiveFlag_GI6(DMA_TypeDef * DMAx)1622 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
1623 {
1624 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
1625 }
1626
1627 /**
1628 * @brief Get Channel 7 global interrupt flag.
1629 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
1630 * @param DMAx DMAx Instance
1631 * @retval State of bit (1 or 0).
1632 */
LL_DMA_IsActiveFlag_GI7(DMA_TypeDef * DMAx)1633 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
1634 {
1635 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
1636 }
1637
1638 /**
1639 * @brief Get Channel 1 transfer complete flag.
1640 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
1641 * @param DMAx DMAx Instance
1642 * @retval State of bit (1 or 0).
1643 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)1644 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1645 {
1646 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
1647 }
1648
1649 /**
1650 * @brief Get Channel 2 transfer complete flag.
1651 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
1652 * @param DMAx DMAx Instance
1653 * @retval State of bit (1 or 0).
1654 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)1655 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1656 {
1657 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
1658 }
1659
1660 /**
1661 * @brief Get Channel 3 transfer complete flag.
1662 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
1663 * @param DMAx DMAx Instance
1664 * @retval State of bit (1 or 0).
1665 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)1666 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1667 {
1668 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
1669 }
1670
1671 /**
1672 * @brief Get Channel 4 transfer complete flag.
1673 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
1674 * @param DMAx DMAx Instance
1675 * @retval State of bit (1 or 0).
1676 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)1677 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1678 {
1679 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
1680 }
1681
1682 /**
1683 * @brief Get Channel 5 transfer complete flag.
1684 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
1685 * @param DMAx DMAx Instance
1686 * @retval State of bit (1 or 0).
1687 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)1688 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1689 {
1690 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
1691 }
1692
1693 /**
1694 * @brief Get Channel 6 transfer complete flag.
1695 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
1696 * @param DMAx DMAx Instance
1697 * @retval State of bit (1 or 0).
1698 */
LL_DMA_IsActiveFlag_TC6(DMA_TypeDef * DMAx)1699 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1700 {
1701 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
1702 }
1703
1704 /**
1705 * @brief Get Channel 7 transfer complete flag.
1706 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
1707 * @param DMAx DMAx Instance
1708 * @retval State of bit (1 or 0).
1709 */
LL_DMA_IsActiveFlag_TC7(DMA_TypeDef * DMAx)1710 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1711 {
1712 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
1713 }
1714
1715 /**
1716 * @brief Get Channel 1 half transfer flag.
1717 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
1718 * @param DMAx DMAx Instance
1719 * @retval State of bit (1 or 0).
1720 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)1721 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1722 {
1723 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
1724 }
1725
1726 /**
1727 * @brief Get Channel 2 half transfer flag.
1728 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
1729 * @param DMAx DMAx Instance
1730 * @retval State of bit (1 or 0).
1731 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)1732 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1733 {
1734 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
1735 }
1736
1737 /**
1738 * @brief Get Channel 3 half transfer flag.
1739 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
1740 * @param DMAx DMAx Instance
1741 * @retval State of bit (1 or 0).
1742 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)1743 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1744 {
1745 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
1746 }
1747
1748 /**
1749 * @brief Get Channel 4 half transfer flag.
1750 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
1751 * @param DMAx DMAx Instance
1752 * @retval State of bit (1 or 0).
1753 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)1754 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1755 {
1756 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
1757 }
1758
1759 /**
1760 * @brief Get Channel 5 half transfer flag.
1761 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
1762 * @param DMAx DMAx Instance
1763 * @retval State of bit (1 or 0).
1764 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)1765 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1766 {
1767 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
1768 }
1769
1770 /**
1771 * @brief Get Channel 6 half transfer flag.
1772 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
1773 * @param DMAx DMAx Instance
1774 * @retval State of bit (1 or 0).
1775 */
LL_DMA_IsActiveFlag_HT6(DMA_TypeDef * DMAx)1776 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1777 {
1778 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
1779 }
1780
1781 /**
1782 * @brief Get Channel 7 half transfer flag.
1783 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
1784 * @param DMAx DMAx Instance
1785 * @retval State of bit (1 or 0).
1786 */
LL_DMA_IsActiveFlag_HT7(DMA_TypeDef * DMAx)1787 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1788 {
1789 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
1790 }
1791
1792 /**
1793 * @brief Get Channel 1 transfer error flag.
1794 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
1795 * @param DMAx DMAx Instance
1796 * @retval State of bit (1 or 0).
1797 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)1798 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1799 {
1800 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
1801 }
1802
1803 /**
1804 * @brief Get Channel 2 transfer error flag.
1805 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
1806 * @param DMAx DMAx Instance
1807 * @retval State of bit (1 or 0).
1808 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)1809 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1810 {
1811 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
1812 }
1813
1814 /**
1815 * @brief Get Channel 3 transfer error flag.
1816 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
1817 * @param DMAx DMAx Instance
1818 * @retval State of bit (1 or 0).
1819 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)1820 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1821 {
1822 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
1823 }
1824
1825 /**
1826 * @brief Get Channel 4 transfer error flag.
1827 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
1828 * @param DMAx DMAx Instance
1829 * @retval State of bit (1 or 0).
1830 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)1831 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1832 {
1833 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
1834 }
1835
1836 /**
1837 * @brief Get Channel 5 transfer error flag.
1838 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
1839 * @param DMAx DMAx Instance
1840 * @retval State of bit (1 or 0).
1841 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)1842 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1843 {
1844 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
1845 }
1846
1847 /**
1848 * @brief Get Channel 6 transfer error flag.
1849 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
1850 * @param DMAx DMAx Instance
1851 * @retval State of bit (1 or 0).
1852 */
LL_DMA_IsActiveFlag_TE6(DMA_TypeDef * DMAx)1853 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1854 {
1855 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
1856 }
1857
1858 /**
1859 * @brief Get Channel 7 transfer error flag.
1860 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
1861 * @param DMAx DMAx Instance
1862 * @retval State of bit (1 or 0).
1863 */
LL_DMA_IsActiveFlag_TE7(DMA_TypeDef * DMAx)1864 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1865 {
1866 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
1867 }
1868
1869 /**
1870 * @brief Clear Channel 1 global interrupt flag.
1871 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
1872 * @param DMAx DMAx Instance
1873 * @retval None
1874 */
LL_DMA_ClearFlag_GI1(DMA_TypeDef * DMAx)1875 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
1876 {
1877 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
1878 }
1879
1880 /**
1881 * @brief Clear Channel 2 global interrupt flag.
1882 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
1883 * @param DMAx DMAx Instance
1884 * @retval None
1885 */
LL_DMA_ClearFlag_GI2(DMA_TypeDef * DMAx)1886 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
1887 {
1888 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
1889 }
1890
1891 /**
1892 * @brief Clear Channel 3 global interrupt flag.
1893 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
1894 * @param DMAx DMAx Instance
1895 * @retval None
1896 */
LL_DMA_ClearFlag_GI3(DMA_TypeDef * DMAx)1897 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
1898 {
1899 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
1900 }
1901
1902 /**
1903 * @brief Clear Channel 4 global interrupt flag.
1904 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
1905 * @param DMAx DMAx Instance
1906 * @retval None
1907 */
LL_DMA_ClearFlag_GI4(DMA_TypeDef * DMAx)1908 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
1909 {
1910 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
1911 }
1912
1913 /**
1914 * @brief Clear Channel 5 global interrupt flag.
1915 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
1916 * @param DMAx DMAx Instance
1917 * @retval None
1918 */
LL_DMA_ClearFlag_GI5(DMA_TypeDef * DMAx)1919 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
1920 {
1921 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
1922 }
1923
1924 /**
1925 * @brief Clear Channel 6 global interrupt flag.
1926 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
1927 * @param DMAx DMAx Instance
1928 * @retval None
1929 */
LL_DMA_ClearFlag_GI6(DMA_TypeDef * DMAx)1930 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
1931 {
1932 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
1933 }
1934
1935 /**
1936 * @brief Clear Channel 7 global interrupt flag.
1937 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
1938 * @param DMAx DMAx Instance
1939 * @retval None
1940 */
LL_DMA_ClearFlag_GI7(DMA_TypeDef * DMAx)1941 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
1942 {
1943 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
1944 }
1945
1946 /**
1947 * @brief Clear Channel 1 transfer complete flag.
1948 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
1949 * @param DMAx DMAx Instance
1950 * @retval None
1951 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)1952 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
1953 {
1954 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
1955 }
1956
1957 /**
1958 * @brief Clear Channel 2 transfer complete flag.
1959 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
1960 * @param DMAx DMAx Instance
1961 * @retval None
1962 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)1963 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
1964 {
1965 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
1966 }
1967
1968 /**
1969 * @brief Clear Channel 3 transfer complete flag.
1970 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
1971 * @param DMAx DMAx Instance
1972 * @retval None
1973 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)1974 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
1975 {
1976 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
1977 }
1978
1979 /**
1980 * @brief Clear Channel 4 transfer complete flag.
1981 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
1982 * @param DMAx DMAx Instance
1983 * @retval None
1984 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)1985 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
1986 {
1987 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
1988 }
1989
1990 /**
1991 * @brief Clear Channel 5 transfer complete flag.
1992 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
1993 * @param DMAx DMAx Instance
1994 * @retval None
1995 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)1996 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
1997 {
1998 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
1999 }
2000
2001 /**
2002 * @brief Clear Channel 6 transfer complete flag.
2003 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
2004 * @param DMAx DMAx Instance
2005 * @retval None
2006 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)2007 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
2008 {
2009 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
2010 }
2011
2012 /**
2013 * @brief Clear Channel 7 transfer complete flag.
2014 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
2015 * @param DMAx DMAx Instance
2016 * @retval None
2017 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)2018 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
2019 {
2020 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
2021 }
2022
2023 /**
2024 * @brief Clear Channel 1 half transfer flag.
2025 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
2026 * @param DMAx DMAx Instance
2027 * @retval None
2028 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)2029 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
2030 {
2031 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
2032 }
2033
2034 /**
2035 * @brief Clear Channel 2 half transfer flag.
2036 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
2037 * @param DMAx DMAx Instance
2038 * @retval None
2039 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)2040 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
2041 {
2042 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
2043 }
2044
2045 /**
2046 * @brief Clear Channel 3 half transfer flag.
2047 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
2048 * @param DMAx DMAx Instance
2049 * @retval None
2050 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)2051 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
2052 {
2053 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
2054 }
2055
2056 /**
2057 * @brief Clear Channel 4 half transfer flag.
2058 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
2059 * @param DMAx DMAx Instance
2060 * @retval None
2061 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)2062 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
2063 {
2064 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
2065 }
2066
2067 /**
2068 * @brief Clear Channel 5 half transfer flag.
2069 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
2070 * @param DMAx DMAx Instance
2071 * @retval None
2072 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)2073 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
2074 {
2075 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
2076 }
2077
2078 /**
2079 * @brief Clear Channel 6 half transfer flag.
2080 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
2081 * @param DMAx DMAx Instance
2082 * @retval None
2083 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)2084 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
2085 {
2086 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
2087 }
2088
2089 /**
2090 * @brief Clear Channel 7 half transfer flag.
2091 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
2092 * @param DMAx DMAx Instance
2093 * @retval None
2094 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)2095 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
2096 {
2097 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
2098 }
2099
2100 /**
2101 * @brief Clear Channel 1 transfer error flag.
2102 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
2103 * @param DMAx DMAx Instance
2104 * @retval None
2105 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)2106 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
2107 {
2108 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
2109 }
2110
2111 /**
2112 * @brief Clear Channel 2 transfer error flag.
2113 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
2114 * @param DMAx DMAx Instance
2115 * @retval None
2116 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)2117 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
2118 {
2119 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
2120 }
2121
2122 /**
2123 * @brief Clear Channel 3 transfer error flag.
2124 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
2125 * @param DMAx DMAx Instance
2126 * @retval None
2127 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)2128 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
2129 {
2130 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
2131 }
2132
2133 /**
2134 * @brief Clear Channel 4 transfer error flag.
2135 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
2136 * @param DMAx DMAx Instance
2137 * @retval None
2138 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)2139 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
2140 {
2141 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
2142 }
2143
2144 /**
2145 * @brief Clear Channel 5 transfer error flag.
2146 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
2147 * @param DMAx DMAx Instance
2148 * @retval None
2149 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)2150 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
2151 {
2152 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
2153 }
2154
2155 /**
2156 * @brief Clear Channel 6 transfer error flag.
2157 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
2158 * @param DMAx DMAx Instance
2159 * @retval None
2160 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)2161 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
2162 {
2163 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
2164 }
2165
2166 /**
2167 * @brief Clear Channel 7 transfer error flag.
2168 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
2169 * @param DMAx DMAx Instance
2170 * @retval None
2171 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)2172 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
2173 {
2174 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
2175 }
2176
2177 /**
2178 * @}
2179 */
2180
2181 /** @defgroup DMA_LL_EF_IT_Management IT_Management
2182 * @{
2183 */
2184 /**
2185 * @brief Enable Transfer complete interrupt.
2186 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
2187 * @param DMAx DMAx Instance
2188 * @param Channel This parameter can be one of the following values:
2189 * @arg @ref LL_DMA_CHANNEL_1
2190 * @arg @ref LL_DMA_CHANNEL_2
2191 * @arg @ref LL_DMA_CHANNEL_3
2192 * @arg @ref LL_DMA_CHANNEL_4
2193 * @arg @ref LL_DMA_CHANNEL_5
2194 * @arg @ref LL_DMA_CHANNEL_6
2195 * @arg @ref LL_DMA_CHANNEL_7
2196 * @retval None
2197 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2198 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2199 {
2200 uint32_t dma_base_addr = (uint32_t)DMAx;
2201 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
2202 }
2203
2204 /**
2205 * @brief Enable Half transfer interrupt.
2206 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
2207 * @param DMAx DMAx Instance
2208 * @param Channel This parameter can be one of the following values:
2209 * @arg @ref LL_DMA_CHANNEL_1
2210 * @arg @ref LL_DMA_CHANNEL_2
2211 * @arg @ref LL_DMA_CHANNEL_3
2212 * @arg @ref LL_DMA_CHANNEL_4
2213 * @arg @ref LL_DMA_CHANNEL_5
2214 * @arg @ref LL_DMA_CHANNEL_6
2215 * @arg @ref LL_DMA_CHANNEL_7
2216 * @retval None
2217 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2218 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2219 {
2220 uint32_t dma_base_addr = (uint32_t)DMAx;
2221 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
2222 }
2223
2224 /**
2225 * @brief Enable Transfer error interrupt.
2226 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
2227 * @param DMAx DMAx Instance
2228 * @param Channel This parameter can be one of the following values:
2229 * @arg @ref LL_DMA_CHANNEL_1
2230 * @arg @ref LL_DMA_CHANNEL_2
2231 * @arg @ref LL_DMA_CHANNEL_3
2232 * @arg @ref LL_DMA_CHANNEL_4
2233 * @arg @ref LL_DMA_CHANNEL_5
2234 * @arg @ref LL_DMA_CHANNEL_6
2235 * @arg @ref LL_DMA_CHANNEL_7
2236 * @retval None
2237 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2238 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2239 {
2240 uint32_t dma_base_addr = (uint32_t)DMAx;
2241 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE);
2242 }
2243
2244 /**
2245 * @brief Disable Transfer complete interrupt.
2246 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
2247 * @param DMAx DMAx Instance
2248 * @param Channel This parameter can be one of the following values:
2249 * @arg @ref LL_DMA_CHANNEL_1
2250 * @arg @ref LL_DMA_CHANNEL_2
2251 * @arg @ref LL_DMA_CHANNEL_3
2252 * @arg @ref LL_DMA_CHANNEL_4
2253 * @arg @ref LL_DMA_CHANNEL_5
2254 * @arg @ref LL_DMA_CHANNEL_6
2255 * @arg @ref LL_DMA_CHANNEL_7
2256 * @retval None
2257 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2258 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2259 {
2260 uint32_t dma_base_addr = (uint32_t)DMAx;
2261 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
2262 }
2263
2264 /**
2265 * @brief Disable Half transfer interrupt.
2266 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
2267 * @param DMAx DMAx Instance
2268 * @param Channel This parameter can be one of the following values:
2269 * @arg @ref LL_DMA_CHANNEL_1
2270 * @arg @ref LL_DMA_CHANNEL_2
2271 * @arg @ref LL_DMA_CHANNEL_3
2272 * @arg @ref LL_DMA_CHANNEL_4
2273 * @arg @ref LL_DMA_CHANNEL_5
2274 * @arg @ref LL_DMA_CHANNEL_6
2275 * @arg @ref LL_DMA_CHANNEL_7
2276 * @retval None
2277 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2278 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2279 {
2280 uint32_t dma_base_addr = (uint32_t)DMAx;
2281 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
2282 }
2283
2284 /**
2285 * @brief Disable Transfer error interrupt.
2286 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
2287 * @param DMAx DMAx Instance
2288 * @param Channel This parameter can be one of the following values:
2289 * @arg @ref LL_DMA_CHANNEL_1
2290 * @arg @ref LL_DMA_CHANNEL_2
2291 * @arg @ref LL_DMA_CHANNEL_3
2292 * @arg @ref LL_DMA_CHANNEL_4
2293 * @arg @ref LL_DMA_CHANNEL_5
2294 * @arg @ref LL_DMA_CHANNEL_6
2295 * @arg @ref LL_DMA_CHANNEL_7
2296 * @retval None
2297 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2298 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2299 {
2300 uint32_t dma_base_addr = (uint32_t)DMAx;
2301 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE);
2302 }
2303
2304 /**
2305 * @brief Check if Transfer complete Interrupt is enabled.
2306 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
2307 * @param DMAx DMAx Instance
2308 * @param Channel This parameter can be one of the following values:
2309 * @arg @ref LL_DMA_CHANNEL_1
2310 * @arg @ref LL_DMA_CHANNEL_2
2311 * @arg @ref LL_DMA_CHANNEL_3
2312 * @arg @ref LL_DMA_CHANNEL_4
2313 * @arg @ref LL_DMA_CHANNEL_5
2314 * @arg @ref LL_DMA_CHANNEL_6
2315 * @arg @ref LL_DMA_CHANNEL_7
2316 * @retval State of bit (1 or 0).
2317 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2318 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2319 {
2320 uint32_t dma_base_addr = (uint32_t)DMAx;
2321 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
2322 DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
2323 }
2324
2325 /**
2326 * @brief Check if Half transfer Interrupt is enabled.
2327 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
2328 * @param DMAx DMAx Instance
2329 * @param Channel This parameter can be one of the following values:
2330 * @arg @ref LL_DMA_CHANNEL_1
2331 * @arg @ref LL_DMA_CHANNEL_2
2332 * @arg @ref LL_DMA_CHANNEL_3
2333 * @arg @ref LL_DMA_CHANNEL_4
2334 * @arg @ref LL_DMA_CHANNEL_5
2335 * @arg @ref LL_DMA_CHANNEL_6
2336 * @arg @ref LL_DMA_CHANNEL_7
2337 * @retval State of bit (1 or 0).
2338 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2339 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2340 {
2341 uint32_t dma_base_addr = (uint32_t)DMAx;
2342 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
2343 DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
2344 }
2345
2346 /**
2347 * @brief Check if Transfer error Interrupt is enabled.
2348 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
2349 * @param DMAx DMAx Instance
2350 * @param Channel This parameter can be one of the following values:
2351 * @arg @ref LL_DMA_CHANNEL_1
2352 * @arg @ref LL_DMA_CHANNEL_2
2353 * @arg @ref LL_DMA_CHANNEL_3
2354 * @arg @ref LL_DMA_CHANNEL_4
2355 * @arg @ref LL_DMA_CHANNEL_5
2356 * @arg @ref LL_DMA_CHANNEL_6
2357 * @arg @ref LL_DMA_CHANNEL_7
2358 * @retval State of bit (1 or 0).
2359 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2360 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2361 {
2362 uint32_t dma_base_addr = (uint32_t)DMAx;
2363 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
2364 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
2365 }
2366
2367 /**
2368 * @}
2369 */
2370
2371 #if defined(USE_FULL_LL_DRIVER)
2372 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
2373 * @{
2374 */
2375 ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
2376 ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
2377 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
2378
2379 /**
2380 * @}
2381 */
2382 #endif /* USE_FULL_LL_DRIVER */
2383
2384 /**
2385 * @}
2386 */
2387
2388 /**
2389 * @}
2390 */
2391
2392 #endif /* DMA1 || DMA2 */
2393
2394 /**
2395 * @}
2396 */
2397
2398 #ifdef __cplusplus
2399 }
2400 #endif
2401
2402 #endif /* STM32L4xx_LL_DMA_H */
2403
2404 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2405