1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_crs.h
4 * @author MCD Application Team
5 * @brief Header file of CRS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L4xx_LL_CRS_H
22 #define STM32L4xx_LL_CRS_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx.h"
30
31 /** @addtogroup STM32L4xx_LL_Driver
32 * @{
33 */
34
35 #if defined(CRS)
36
37 /** @defgroup CRS_LL CRS
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45
46 /* Exported types ------------------------------------------------------------*/
47 /* Exported constants --------------------------------------------------------*/
48 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
49 * @{
50 */
51
52 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
53 * @brief Flags defines which can be used with LL_CRS_ReadReg function
54 * @{
55 */
56 #define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
57 #define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
58 #define LL_CRS_ISR_ERRF CRS_ISR_ERRF
59 #define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
60 #define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
61 #define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
62 #define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
63 /**
64 * @}
65 */
66
67 /** @defgroup CRS_LL_EC_IT IT Defines
68 * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
69 * @{
70 */
71 #define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
72 #define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
73 #define LL_CRS_CR_ERRIE CRS_CR_ERRIE
74 #define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
75 /**
76 * @}
77 */
78
79 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
80 * @{
81 */
82 #define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */
83 #define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
84 #define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
85 #define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
86 #define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
87 #define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
88 #define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
89 #define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
90 /**
91 * @}
92 */
93
94 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
95 * @{
96 */
97 #define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal soucre GPIO */
98 #define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
99 #define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
100 /**
101 * @}
102 */
103
104 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
105 * @{
106 */
107 #define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */
108 #define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
109 /**
110 * @}
111 */
112
113 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
114 * @{
115 */
116 #define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */
117 #define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
118 /**
119 * @}
120 */
121
122 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
123 * @{
124 */
125 /**
126 * @brief Reset value of the RELOAD field
127 * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
128 * and a synchronization signal frequency of 1 kHz (SOF signal from USB)
129 */
130 #define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)
131
132 /**
133 * @brief Reset value of Frequency error limit.
134 */
135 #define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)
136
137 /**
138 * @brief Reset value of the HSI48 Calibration field
139 * @note The default value is 64 for STM32L412xx/L422xx, 32 otherwise, which corresponds
140 * to the middle of the trimming interval.
141 * The trimming step is around 67 kHz between two consecutive TRIM steps.
142 * A higher TRIM value corresponds to a higher output frequency
143 */
144 #if defined (STM32L412xx) || defined (STM32L422xx)
145 #define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)64U)
146 #else
147 #define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)32U)
148 #endif
149 /**
150 * @}
151 */
152
153 /**
154 * @}
155 */
156
157 /* Exported macro ------------------------------------------------------------*/
158 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
159 * @{
160 */
161
162 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
163 * @{
164 */
165
166 /**
167 * @brief Write a value in CRS register
168 * @param __INSTANCE__ CRS Instance
169 * @param __REG__ Register to be written
170 * @param __VALUE__ Value to be written in the register
171 * @retval None
172 */
173 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
174
175 /**
176 * @brief Read a value in CRS register
177 * @param __INSTANCE__ CRS Instance
178 * @param __REG__ Register to be read
179 * @retval Register value
180 */
181 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
182 /**
183 * @}
184 */
185
186 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
187 * @{
188 */
189
190 /**
191 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
192 * @note The RELOAD value should be selected according to the ratio between
193 * the target frequency and the frequency of the synchronization source after
194 * prescaling. It is then decreased by one in order to reach the expected
195 * synchronization on the zero value. The formula is the following:
196 * RELOAD = (fTARGET / fSYNC) -1
197 * @param __FTARGET__ Target frequency (value in Hz)
198 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
199 * @retval Reload value (in Hz)
200 */
201 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
202
203 /**
204 * @}
205 */
206
207 /**
208 * @}
209 */
210
211 /* Exported functions --------------------------------------------------------*/
212 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
213 * @{
214 */
215
216 /** @defgroup CRS_LL_EF_Configuration Configuration
217 * @{
218 */
219
220 /**
221 * @brief Enable Frequency error counter
222 * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
223 * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
224 * @retval None
225 */
LL_CRS_EnableFreqErrorCounter(void)226 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
227 {
228 SET_BIT(CRS->CR, CRS_CR_CEN);
229 }
230
231 /**
232 * @brief Disable Frequency error counter
233 * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
234 * @retval None
235 */
LL_CRS_DisableFreqErrorCounter(void)236 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
237 {
238 CLEAR_BIT(CRS->CR, CRS_CR_CEN);
239 }
240
241 /**
242 * @brief Check if Frequency error counter is enabled or not
243 * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
244 * @retval State of bit (1 or 0).
245 */
LL_CRS_IsEnabledFreqErrorCounter(void)246 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
247 {
248 return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
249 }
250
251 /**
252 * @brief Enable Automatic trimming counter
253 * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
254 * @retval None
255 */
LL_CRS_EnableAutoTrimming(void)256 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
257 {
258 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
259 }
260
261 /**
262 * @brief Disable Automatic trimming counter
263 * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
264 * @retval None
265 */
LL_CRS_DisableAutoTrimming(void)266 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
267 {
268 CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
269 }
270
271 /**
272 * @brief Check if Automatic trimming is enabled or not
273 * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
274 * @retval State of bit (1 or 0).
275 */
LL_CRS_IsEnabledAutoTrimming(void)276 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
277 {
278 return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
279 }
280
281 /**
282 * @brief Set HSI48 oscillator smooth trimming
283 * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
284 * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
285 * @param Value a number between Min_Data = 0 and Max_Data = 127 for STM32L412xx/L422xx or 63 otherwise
286 * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
287 * @retval None
288 */
LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)289 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
290 {
291 MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
292 }
293
294 /**
295 * @brief Get HSI48 oscillator smooth trimming
296 * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
297 * @retval a number between Min_Data = 0 and Max_Data = 127 for STM32L412xx/L422xx or 63 otherwise
298 */
LL_CRS_GetHSI48SmoothTrimming(void)299 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
300 {
301 return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
302 }
303
304 /**
305 * @brief Set counter reload value
306 * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
307 * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
308 * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
309 * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
310 * @retval None
311 */
LL_CRS_SetReloadCounter(uint32_t Value)312 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
313 {
314 MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
315 }
316
317 /**
318 * @brief Get counter reload value
319 * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
320 * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
321 */
LL_CRS_GetReloadCounter(void)322 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
323 {
324 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
325 }
326
327 /**
328 * @brief Set frequency error limit
329 * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
330 * @param Value a number between Min_Data = 0 and Max_Data = 255
331 * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
332 * @retval None
333 */
LL_CRS_SetFreqErrorLimit(uint32_t Value)334 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
335 {
336 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
337 }
338
339 /**
340 * @brief Get frequency error limit
341 * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
342 * @retval A number between Min_Data = 0 and Max_Data = 255
343 */
LL_CRS_GetFreqErrorLimit(void)344 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
345 {
346 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
347 }
348
349 /**
350 * @brief Set division factor for SYNC signal
351 * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
352 * @param Divider This parameter can be one of the following values:
353 * @arg @ref LL_CRS_SYNC_DIV_1
354 * @arg @ref LL_CRS_SYNC_DIV_2
355 * @arg @ref LL_CRS_SYNC_DIV_4
356 * @arg @ref LL_CRS_SYNC_DIV_8
357 * @arg @ref LL_CRS_SYNC_DIV_16
358 * @arg @ref LL_CRS_SYNC_DIV_32
359 * @arg @ref LL_CRS_SYNC_DIV_64
360 * @arg @ref LL_CRS_SYNC_DIV_128
361 * @retval None
362 */
LL_CRS_SetSyncDivider(uint32_t Divider)363 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
364 {
365 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
366 }
367
368 /**
369 * @brief Get division factor for SYNC signal
370 * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
371 * @retval Returned value can be one of the following values:
372 * @arg @ref LL_CRS_SYNC_DIV_1
373 * @arg @ref LL_CRS_SYNC_DIV_2
374 * @arg @ref LL_CRS_SYNC_DIV_4
375 * @arg @ref LL_CRS_SYNC_DIV_8
376 * @arg @ref LL_CRS_SYNC_DIV_16
377 * @arg @ref LL_CRS_SYNC_DIV_32
378 * @arg @ref LL_CRS_SYNC_DIV_64
379 * @arg @ref LL_CRS_SYNC_DIV_128
380 */
LL_CRS_GetSyncDivider(void)381 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
382 {
383 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
384 }
385
386 /**
387 * @brief Set SYNC signal source
388 * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
389 * @param Source This parameter can be one of the following values:
390 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
391 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
392 * @arg @ref LL_CRS_SYNC_SOURCE_USB
393 * @retval None
394 */
LL_CRS_SetSyncSignalSource(uint32_t Source)395 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
396 {
397 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
398 }
399
400 /**
401 * @brief Get SYNC signal source
402 * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
403 * @retval Returned value can be one of the following values:
404 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
405 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
406 * @arg @ref LL_CRS_SYNC_SOURCE_USB
407 */
LL_CRS_GetSyncSignalSource(void)408 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
409 {
410 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
411 }
412
413 /**
414 * @brief Set input polarity for the SYNC signal source
415 * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
416 * @param Polarity This parameter can be one of the following values:
417 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
418 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
419 * @retval None
420 */
LL_CRS_SetSyncPolarity(uint32_t Polarity)421 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
422 {
423 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
424 }
425
426 /**
427 * @brief Get input polarity for the SYNC signal source
428 * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
429 * @retval Returned value can be one of the following values:
430 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
431 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
432 */
LL_CRS_GetSyncPolarity(void)433 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
434 {
435 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
436 }
437
438 /**
439 * @brief Configure CRS for the synchronization
440 * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
441 * CFGR RELOAD LL_CRS_ConfigSynchronization\n
442 * CFGR FELIM LL_CRS_ConfigSynchronization\n
443 * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
444 * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
445 * CFGR SYNCPOL LL_CRS_ConfigSynchronization
446 * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
447 * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
448 * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
449 * @param Settings This parameter can be a combination of the following values:
450 * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
451 * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
452 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
453 * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
454 * @retval None
455 */
LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue,uint32_t ErrorLimitValue,uint32_t ReloadValue,uint32_t Settings)456 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
457 {
458 MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
459 MODIFY_REG(CRS->CFGR,
460 CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
461 ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
462 }
463
464 /**
465 * @}
466 */
467
468 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
469 * @{
470 */
471
472 /**
473 * @brief Generate software SYNC event
474 * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
475 * @retval None
476 */
LL_CRS_GenerateEvent_SWSYNC(void)477 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
478 {
479 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
480 }
481
482 /**
483 * @brief Get the frequency error direction latched in the time of the last
484 * SYNC event
485 * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
486 * @retval Returned value can be one of the following values:
487 * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
488 * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
489 */
LL_CRS_GetFreqErrorDirection(void)490 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
491 {
492 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
493 }
494
495 /**
496 * @brief Get the frequency error counter value latched in the time of the last SYNC event
497 * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
498 * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
499 */
LL_CRS_GetFreqErrorCapture(void)500 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
501 {
502 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
503 }
504
505 /**
506 * @}
507 */
508
509 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
510 * @{
511 */
512
513 /**
514 * @brief Check if SYNC event OK signal occurred or not
515 * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
516 * @retval State of bit (1 or 0).
517 */
LL_CRS_IsActiveFlag_SYNCOK(void)518 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
519 {
520 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
521 }
522
523 /**
524 * @brief Check if SYNC warning signal occurred or not
525 * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
526 * @retval State of bit (1 or 0).
527 */
LL_CRS_IsActiveFlag_SYNCWARN(void)528 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
529 {
530 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
531 }
532
533 /**
534 * @brief Check if Synchronization or trimming error signal occurred or not
535 * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
536 * @retval State of bit (1 or 0).
537 */
LL_CRS_IsActiveFlag_ERR(void)538 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
539 {
540 return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
541 }
542
543 /**
544 * @brief Check if Expected SYNC signal occurred or not
545 * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
546 * @retval State of bit (1 or 0).
547 */
LL_CRS_IsActiveFlag_ESYNC(void)548 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
549 {
550 return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
551 }
552
553 /**
554 * @brief Check if SYNC error signal occurred or not
555 * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
556 * @retval State of bit (1 or 0).
557 */
LL_CRS_IsActiveFlag_SYNCERR(void)558 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
559 {
560 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
561 }
562
563 /**
564 * @brief Check if SYNC missed error signal occurred or not
565 * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
566 * @retval State of bit (1 or 0).
567 */
LL_CRS_IsActiveFlag_SYNCMISS(void)568 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
569 {
570 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
571 }
572
573 /**
574 * @brief Check if Trimming overflow or underflow occurred or not
575 * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
576 * @retval State of bit (1 or 0).
577 */
LL_CRS_IsActiveFlag_TRIMOVF(void)578 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
579 {
580 return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
581 }
582
583 /**
584 * @brief Clear the SYNC event OK flag
585 * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
586 * @retval None
587 */
LL_CRS_ClearFlag_SYNCOK(void)588 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
589 {
590 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
591 }
592
593 /**
594 * @brief Clear the SYNC warning flag
595 * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
596 * @retval None
597 */
LL_CRS_ClearFlag_SYNCWARN(void)598 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
599 {
600 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
601 }
602
603 /**
604 * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
605 * the ERR flag
606 * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
607 * @retval None
608 */
LL_CRS_ClearFlag_ERR(void)609 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
610 {
611 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
612 }
613
614 /**
615 * @brief Clear Expected SYNC flag
616 * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
617 * @retval None
618 */
LL_CRS_ClearFlag_ESYNC(void)619 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
620 {
621 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
622 }
623
624 /**
625 * @}
626 */
627
628 /** @defgroup CRS_LL_EF_IT_Management IT_Management
629 * @{
630 */
631
632 /**
633 * @brief Enable SYNC event OK interrupt
634 * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
635 * @retval None
636 */
LL_CRS_EnableIT_SYNCOK(void)637 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
638 {
639 SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
640 }
641
642 /**
643 * @brief Disable SYNC event OK interrupt
644 * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
645 * @retval None
646 */
LL_CRS_DisableIT_SYNCOK(void)647 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
648 {
649 CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
650 }
651
652 /**
653 * @brief Check if SYNC event OK interrupt is enabled or not
654 * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
655 * @retval State of bit (1 or 0).
656 */
LL_CRS_IsEnabledIT_SYNCOK(void)657 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
658 {
659 return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
660 }
661
662 /**
663 * @brief Enable SYNC warning interrupt
664 * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
665 * @retval None
666 */
LL_CRS_EnableIT_SYNCWARN(void)667 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
668 {
669 SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
670 }
671
672 /**
673 * @brief Disable SYNC warning interrupt
674 * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
675 * @retval None
676 */
LL_CRS_DisableIT_SYNCWARN(void)677 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
678 {
679 CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
680 }
681
682 /**
683 * @brief Check if SYNC warning interrupt is enabled or not
684 * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
685 * @retval State of bit (1 or 0).
686 */
LL_CRS_IsEnabledIT_SYNCWARN(void)687 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
688 {
689 return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
690 }
691
692 /**
693 * @brief Enable Synchronization or trimming error interrupt
694 * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
695 * @retval None
696 */
LL_CRS_EnableIT_ERR(void)697 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
698 {
699 SET_BIT(CRS->CR, CRS_CR_ERRIE);
700 }
701
702 /**
703 * @brief Disable Synchronization or trimming error interrupt
704 * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
705 * @retval None
706 */
LL_CRS_DisableIT_ERR(void)707 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
708 {
709 CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
710 }
711
712 /**
713 * @brief Check if Synchronization or trimming error interrupt is enabled or not
714 * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
715 * @retval State of bit (1 or 0).
716 */
LL_CRS_IsEnabledIT_ERR(void)717 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
718 {
719 return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
720 }
721
722 /**
723 * @brief Enable Expected SYNC interrupt
724 * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
725 * @retval None
726 */
LL_CRS_EnableIT_ESYNC(void)727 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
728 {
729 SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
730 }
731
732 /**
733 * @brief Disable Expected SYNC interrupt
734 * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
735 * @retval None
736 */
LL_CRS_DisableIT_ESYNC(void)737 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
738 {
739 CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
740 }
741
742 /**
743 * @brief Check if Expected SYNC interrupt is enabled or not
744 * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
745 * @retval State of bit (1 or 0).
746 */
LL_CRS_IsEnabledIT_ESYNC(void)747 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
748 {
749 return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
750 }
751
752 /**
753 * @}
754 */
755
756 #if defined(USE_FULL_LL_DRIVER)
757 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
758 * @{
759 */
760
761 ErrorStatus LL_CRS_DeInit(void);
762
763 /**
764 * @}
765 */
766 #endif /* USE_FULL_LL_DRIVER */
767
768 /**
769 * @}
770 */
771
772 /**
773 * @}
774 */
775
776 #endif /* defined(CRS) */
777
778 /**
779 * @}
780 */
781
782 #ifdef __cplusplus
783 }
784 #endif
785
786 #endif /* STM32L4xx_LL_CRS_H */
787
788 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
789