1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L4xx_LL_ADC_H
22 #define STM32L4xx_LL_ADC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx.h"
30
31 /** @addtogroup STM32L4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
36
37 /** @defgroup ADC_LL ADC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
46 * @{
47 */
48
49 /* Internal mask for ADC group regular sequencer: */
50 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
51 /* - sequencer register offset */
52 /* - sequencer rank bits position into the selected register */
53
54 /* Internal register offset for ADC group regular sequencer configuration */
55 /* (offset placed into a spare area of literal definition) */
56 #define ADC_SQR1_REGOFFSET (0x00000000UL)
57 #define ADC_SQR2_REGOFFSET (0x00000100UL)
58 #define ADC_SQR3_REGOFFSET (0x00000200UL)
59 #define ADC_SQR4_REGOFFSET (0x00000300UL)
60
61 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
62 #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
63 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
64
65 /* Definition of ADC group regular sequencer bits information to be inserted */
66 /* into ADC group regular sequencer ranks literals definition. */
67 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */
68 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */
69 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */
70 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */
71 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */
72 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */
73 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */
74 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */
75 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */
76 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */
77 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */
78 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */
79 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */
80 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */
81 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */
82 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */
83
84
85
86 /* Internal mask for ADC group injected sequencer: */
87 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
88 /* - data register offset */
89 /* - sequencer rank bits position into the selected register */
90
91 /* Internal register offset for ADC group injected data register */
92 /* (offset placed into a spare area of literal definition) */
93 #define ADC_JDR1_REGOFFSET (0x00000000UL)
94 #define ADC_JDR2_REGOFFSET (0x00000100UL)
95 #define ADC_JDR3_REGOFFSET (0x00000200UL)
96 #define ADC_JDR4_REGOFFSET (0x00000300UL)
97
98 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
99 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
100 #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
101
102 /* Definition of ADC group injected sequencer bits information to be inserted */
103 /* into ADC group injected sequencer ranks literals definition. */
104 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ1" position in register */
105 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (14UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ2" position in register */
106 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ3" position in register */
107 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (26UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ4" position in register */
108
109
110
111 /* Internal mask for ADC group regular trigger: */
112 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
113 /* - regular trigger source */
114 /* - regular trigger edge */
115 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
116
117 /* Mask containing trigger source masks for each of possible */
118 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
119 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
120 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
121 ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \
122 ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \
123 ((ADC_CFGR_EXTSEL) << (4U * 3UL)) )
124
125 /* Mask containing trigger edge masks for each of possible */
126 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
127 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
128 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
129 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
130 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
131 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
132
133 /* Definition of ADC group regular trigger bits information. */
134 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */
135 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */
136
137
138
139 /* Internal mask for ADC group injected trigger: */
140 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
141 /* - injected trigger source */
142 /* - injected trigger edge */
143 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
144
145 /* Mask containing trigger source masks for each of possible */
146 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
147 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
148 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
149 ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
150 ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
151 ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
152
153 /* Mask containing trigger edge masks for each of possible */
154 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
155 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
156 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
157 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
158 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
159 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
160
161 /* Definition of ADC group injected trigger bits information. */
162 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */
163 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */
164
165
166
167
168
169
170 /* Internal mask for ADC channel: */
171 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
172 /* - channel identifier defined by number */
173 /* - channel identifier defined by bitfield */
174 /* - channel differentiation between external channels (connected to */
175 /* GPIO pins) and internal channels (connected to internal paths) */
176 /* - channel sampling time defined by SMPRx register offset */
177 /* and SMPx bits positions into SMPRx register */
178 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
179 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
180 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
181 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
182 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
183 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
184
185 /* Channel differentiation between external and internal channels */
186 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
187 #define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
188 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
189
190 /* Internal register offset for ADC channel sampling time configuration */
191 /* (offset placed into a spare area of literal definition) */
192 #define ADC_SMPR1_REGOFFSET (0x00000000UL)
193 #define ADC_SMPR2_REGOFFSET (0x02000000UL)
194 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
195 #define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
196
197 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
198 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
199
200 /* Definition of channels ID number information to be inserted into */
201 /* channels literals definition. */
202 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
203 #define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
204 #define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
205 #define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
206 #define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
207 #define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
208 #define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
209 #define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
210 #define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
211 #define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
212 #define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
213 #define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
214 #define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
215 #define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
216 #define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
217 #define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
218 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
219 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
220 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
221
222 /* Definition of channels ID bitfield information to be inserted into */
223 /* channels literals definition. */
224 #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
225 #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
226 #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
227 #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
228 #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
229 #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
230 #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
231 #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
232 #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
233 #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
234 #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
235 #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
236 #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
237 #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
238 #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
239 #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
240 #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
241 #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
242 #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
243
244 /* Definition of channels sampling time information to be inserted into */
245 /* channels literals definition. */
246 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
247 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
248 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
249 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
250 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
251 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
252 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
253 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
254 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */
255 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */
256 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
257 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
258 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
259 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
260 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
261 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
262 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */
263 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */
264 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
265
266
267 /* Internal mask for ADC mode single or differential ended: */
268 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
269 /* the relevant bits for: */
270 /* (concatenation of multiple bits used in different registers) */
271 /* - ADC calibration: calibration start, calibration factor get or set */
272 /* - ADC channels: set each ADC channel ending mode */
273 #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
274 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
275 #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
276 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
277 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */
278 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */
279 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */
280
281 /* Internal mask for ADC analog watchdog: */
282 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
283 /* (concatenation of multiple bits used in different analog watchdogs, */
284 /* (feature of several watchdogs not available on all STM32 families)). */
285 /* - analog watchdog 1: monitored channel defined by number, */
286 /* selection of ADC group (ADC groups regular and-or injected). */
287 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
288 /* selection on groups. */
289
290 /* Internal register offset for ADC analog watchdog channel configuration */
291 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
292 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
293 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
294
295 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
296 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
297 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
298 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
299
300 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
301
302 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
303 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
304 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
305
306 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
307
308 /* Internal register offset for ADC analog watchdog threshold configuration */
309 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
310 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
311 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
312 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
313 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
314 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
315 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
316 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
317
318 /* Internal mask for ADC offset: */
319 /* Internal register offset for ADC offset number configuration */
320 #define ADC_OFR1_REGOFFSET (0x00000000UL)
321 #define ADC_OFR2_REGOFFSET (0x00000001UL)
322 #define ADC_OFR3_REGOFFSET (0x00000002UL)
323 #define ADC_OFR4_REGOFFSET (0x00000003UL)
324 #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
325
326
327 /* ADC registers bits positions */
328 #define ADC_CFGR_RES_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CFGR_RES" position in register */
329 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS (22UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1SGL" position in register */
330 #define ADC_CFGR_AWD1EN_BITOFFSET_POS (23UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1EN" position in register */
331 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_CFGR_JAWD1EN" position in register */
332 #define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */
333
334
335 /* ADC registers bits groups */
336 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
337
338
339 /* ADC internal channels related definitions */
340 /* Internal voltage reference VrefInt */
341 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
342 #define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
343 /* Temperature sensor */
344 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
345 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature defined by TEMPSENSOR_CAL2_TEMP (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
346 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
347 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
348 #define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
349 #else
350 #define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
351 #endif
352 #define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
353
354
355 /**
356 * @}
357 */
358
359
360 /* Private macros ------------------------------------------------------------*/
361 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
362 * @{
363 */
364
365 /**
366 * @brief Driver macro reserved for internal use: set a pointer to
367 * a register from a register basis from which an offset
368 * is applied.
369 * @param __REG__ Register basis from which the offset is applied.
370 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
371 * @retval Pointer to register address
372 */
373 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
374 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
375
376 /**
377 * @}
378 */
379
380
381 /* Exported types ------------------------------------------------------------*/
382 #if defined(USE_FULL_LL_DRIVER)
383 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
384 * @{
385 */
386
387 /**
388 * @brief Structure definition of some features of ADC common parameters
389 * and multimode
390 * (all ADC instances belonging to the same ADC common instance).
391 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
392 * is conditioned to ADC instances state (all ADC instances
393 * sharing the same ADC common instance):
394 * All ADC instances sharing the same ADC common instance must be
395 * disabled.
396 */
397 typedef struct
398 {
399 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
400 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
401 @note On this STM32 serie, if ADC group injected is used, some
402 clock ratio constraints between ADC clock and AHB clock
403 must be respected. Refer to reference manual.
404
405 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
406
407 #if defined(ADC_MULTIMODE_SUPPORT)
408 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
409 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
410
411 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
412
413 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
414 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
415
416 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
417
418 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
419 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
420
421 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
422 #endif /* ADC_MULTIMODE_SUPPORT */
423
424 } LL_ADC_CommonInitTypeDef;
425
426 /**
427 * @brief Structure definition of some features of ADC instance.
428 * @note These parameters have an impact on ADC scope: ADC instance.
429 * Affects both group regular and group injected (availability
430 * of ADC group injected depends on STM32 families).
431 * Refer to corresponding unitary functions into
432 * @ref ADC_LL_EF_Configuration_ADC_Instance .
433 * @note The setting of these parameters by function @ref LL_ADC_Init()
434 * is conditioned to ADC state:
435 * ADC instance must be disabled.
436 * This condition is applied to all ADC features, for efficiency
437 * and compatibility over all STM32 families. However, the different
438 * features can be set under different ADC state conditions
439 * (setting possible with ADC enabled without conversion on going,
440 * ADC enabled with conversion on going, ...)
441 * Each feature can be updated afterwards with a unitary function
442 * and potentially with ADC in a different state than disabled,
443 * refer to description of each function for setting
444 * conditioned to ADC state.
445 */
446 typedef struct
447 {
448 uint32_t Resolution; /*!< Set ADC resolution.
449 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
450
451 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
452
453 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
454 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
455
456 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
457
458 uint32_t LowPowerMode; /*!< Set ADC low power mode.
459 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
460
461 This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
462
463 } LL_ADC_InitTypeDef;
464
465 /**
466 * @brief Structure definition of some features of ADC group regular.
467 * @note These parameters have an impact on ADC scope: ADC group regular.
468 * Refer to corresponding unitary functions into
469 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
470 * (functions with prefix "REG").
471 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
472 * is conditioned to ADC state:
473 * ADC instance must be disabled.
474 * This condition is applied to all ADC features, for efficiency
475 * and compatibility over all STM32 families. However, the different
476 * features can be set under different ADC state conditions
477 * (setting possible with ADC enabled without conversion on going,
478 * ADC enabled with conversion on going, ...)
479 * Each feature can be updated afterwards with a unitary function
480 * and potentially with ADC in a different state than disabled,
481 * refer to description of each function for setting
482 * conditioned to ADC state.
483 */
484 typedef struct
485 {
486 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
487 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
488 @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
489 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
490 In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
491
492 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
493
494 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
495 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
496
497 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
498
499 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
500 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
501 @note This parameter has an effect only if group regular sequencer is enabled
502 (scan length of 2 ranks or more).
503
504 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
505
506 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
507 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
508 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
509
510 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
511
512 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
513 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
514
515 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
516
517 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
518 data preserved or overwritten.
519 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
520
521 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
522
523 } LL_ADC_REG_InitTypeDef;
524
525 /**
526 * @brief Structure definition of some features of ADC group injected.
527 * @note These parameters have an impact on ADC scope: ADC group injected.
528 * Refer to corresponding unitary functions into
529 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
530 * (functions with prefix "INJ").
531 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
532 * is conditioned to ADC state:
533 * ADC instance must be disabled.
534 * This condition is applied to all ADC features, for efficiency
535 * and compatibility over all STM32 families. However, the different
536 * features can be set under different ADC state conditions
537 * (setting possible with ADC enabled without conversion on going,
538 * ADC enabled with conversion on going, ...)
539 * Each feature can be updated afterwards with a unitary function
540 * and potentially with ADC in a different state than disabled,
541 * refer to description of each function for setting
542 * conditioned to ADC state.
543 */
544 typedef struct
545 {
546 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
547 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
548 @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
549 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
550 In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
551
552 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
553
554 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
555 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
556
557 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
558
559 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
560 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
561 @note This parameter has an effect only if group injected sequencer is enabled
562 (scan length of 2 ranks or more).
563
564 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
565
566 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
567 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
568 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
569
570 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
571
572 } LL_ADC_INJ_InitTypeDef;
573
574 /**
575 * @}
576 */
577 #endif /* USE_FULL_LL_DRIVER */
578
579 /* Exported constants --------------------------------------------------------*/
580 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
581 * @{
582 */
583
584 /** @defgroup ADC_LL_EC_FLAG ADC flags
585 * @brief Flags defines which can be used with LL_ADC_ReadReg function
586 * @{
587 */
588 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
589 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
590 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
591 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
592 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
593 #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
594 #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
595 #define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */
596 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
597 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
598 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
599 #if defined(ADC_MULTIMODE_SUPPORT)
600 #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
601 #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
602 #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */
603 #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */
604 #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */
605 #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */
606 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */
607 #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */
608 #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */
609 #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */
610 #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */
611 #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */
612 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */
613 #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */
614 #define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */
615 #define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */
616 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
617 #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */
618 #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */
619 #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
620 #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
621 #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
622 #endif
623 /**
624 * @}
625 */
626
627 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
628 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
629 * @{
630 */
631 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
632 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
633 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
634 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
635 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
636 #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */
637 #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */
638 #define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */
639 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
640 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
641 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
642 /**
643 * @}
644 */
645
646 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
647 * @{
648 */
649 /* List of ADC registers intended to be used (most commonly) with */
650 /* DMA transfer. */
651 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
652 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
653 #if defined(ADC_MULTIMODE_SUPPORT)
654 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
655 #endif
656 /**
657 * @}
658 */
659
660 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
661 * @{
662 */
663 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
664 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
665 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
666 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */
667 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */
668 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4 */
669 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6 */
670 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8 */
671 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10 */
672 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12 */
673 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16 */
674 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32 */
675 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64 */
676 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128 */
677 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */
678 /**
679 * @}
680 */
681
682 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
683 * @{
684 */
685 /* Note: Other measurement paths to internal channels may be available */
686 /* (connections to other peripherals). */
687 /* If they are not listed below, they do not require any specific */
688 /* path enable. In this case, Access to measurement path is done */
689 /* only by selecting the corresponding ADC internal channel. */
690 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement pathes all disabled */
691 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
692 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
693 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
694 /**
695 * @}
696 */
697
698 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
699 * @{
700 */
701 #define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
702 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
703 #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */
704 #define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */
705 /**
706 * @}
707 */
708
709 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
710 * @{
711 */
712 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
713 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
714 /**
715 * @}
716 */
717
718 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
719 * @{
720 */
721 #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
722 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
723 /**
724 * @}
725 */
726
727 /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
728 * @{
729 */
730 #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
731 #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
732 #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
733 #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
734 /**
735 * @}
736 */
737
738 /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
739 * @{
740 */
741 #define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */
742 #define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */
743 /**
744 * @}
745 */
746
747 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
748 * @{
749 */
750 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
751 #define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/
752 #define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
753 /**
754 * @}
755 */
756
757 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
758 * @{
759 */
760 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
761 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
762 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
763 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
764 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
765 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
766 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
767 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
768 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
769 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
770 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
771 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
772 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
773 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
774 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
775 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
776 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
777 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
778 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
779 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32L4, ADC channel available only on ADC instance: ADC1. */
780 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. */
781 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. */
782 #if defined(ADC1) && !defined(ADC2)
783 #define LL_ADC_CHANNEL_DAC1CH1 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
784 #define LL_ADC_CHANNEL_DAC1CH2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
785 #elif defined(ADC2)
786 #define LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
787 #define LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
788 #if defined(ADC3)
789 #define LL_ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */
790 #define LL_ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */
791 #endif
792 #endif
793 /**
794 * @}
795 */
796
797 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
798 * @{
799 */
800 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */
801 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
802 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
803 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
804 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
805 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
806 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
807 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
808 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
809 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
810 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
811 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
812 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
813 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
814 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
815 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
816 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
817 /**
818 * @}
819 */
820
821 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
822 * @{
823 */
824 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
825 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
826 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
827 /**
828 * @}
829 */
830
831 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
832 * @{
833 */
834 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */
835 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
836 /**
837 * @}
838 */
839
840 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
841 * @{
842 */
843 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
844 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
845 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
846 /**
847 * @}
848 */
849
850 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
851 /** @defgroup ADC_LL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data
852 * @{
853 */
854 #define LL_ADC_REG_DFSDM_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */
855 #define LL_ADC_REG_DFSDM_TRANSFER_ENABLE (ADC_CFGR_DFSDMCFG) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */
856 /**
857 * @}
858 */
859 #endif
860
861 #if defined(ADC_SMPR1_SMPPLUS)
862 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration
863 * @{
864 */
865 #define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL) /*!< ADC sampling time let to default settings. */
866 #define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped with selection sampling time 2.5 ADC clock cycles, whatever channels mapped on ADC groups regular or injected). */
867 /**
868 * @}
869 */
870 #endif
871
872 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
873 * @{
874 */
875 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */
876 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
877 /**
878 * @}
879 */
880
881 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
882 * @{
883 */
884 #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
885 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
886 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
887 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
888 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
889 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
890 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
891 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
892 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
893 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
894 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
895 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
896 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
897 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
898 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
899 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
900 /**
901 * @}
902 */
903
904 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
905 * @{
906 */
907 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */
908 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
909 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
910 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
911 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
912 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
913 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
914 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
915 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
916 /**
917 * @}
918 */
919
920 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
921 * @{
922 */
923 #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
924 #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
925 #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
926 #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
927 #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
928 #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
929 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
930 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
931 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
932 #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
933 #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
934 #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
935 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
936 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
937 #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
938 #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
939 /**
940 * @}
941 */
942
943 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
944 * @{
945 */
946 #define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */
947 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
948 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
949 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
950 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
951 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
952 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
953 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
954 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
955 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
956 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
957 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
958 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
959 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
960 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
961 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
962 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
963 /**
964 * @}
965 */
966
967 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
968 * @{
969 */
970 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
971 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
972 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
973 /**
974 * @}
975 */
976
977 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
978 * @{
979 */
980 #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
981 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
982 /**
983 * @}
984 */
985
986 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
987 * @{
988 */
989 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
990 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
991 #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
992 /**
993 * @}
994 */
995
996 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
997 * @{
998 */
999 #define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1000 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
1001 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
1002 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
1003 /**
1004 * @}
1005 */
1006
1007 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
1008 * @{
1009 */
1010 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */
1011 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
1012 /**
1013 * @}
1014 */
1015
1016 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
1017 * @{
1018 */
1019 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
1020 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
1021 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
1022 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
1023 /**
1024 * @}
1025 */
1026
1027 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1028 * @{
1029 */
1030 #define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */
1031 #define LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
1032 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12.5 ADC clock cycles */
1033 #define LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
1034 #define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 47.5 ADC clock cycles */
1035 #define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
1036 #define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 247.5 ADC clock cycles */
1037 #define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
1038 /**
1039 * @}
1040 */
1041
1042 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
1043 * @{
1044 */
1045 #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
1046 #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
1047 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
1048 /**
1049 * @}
1050 */
1051
1052 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
1053 * @{
1054 */
1055 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
1056 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
1057 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
1058 /**
1059 * @}
1060 */
1061
1062 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
1063 * @{
1064 */
1065 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
1066 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
1067 #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
1068 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
1069 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
1070 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
1071 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
1072 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
1073 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
1074 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
1075 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
1076 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
1077 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
1078 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
1079 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
1080 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
1081 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
1082 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
1083 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
1084 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
1085 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
1086 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
1087 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
1088 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
1089 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
1090 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
1091 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
1092 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
1093 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
1094 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
1095 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
1096 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
1097 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
1098 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
1099 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
1100 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
1101 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
1102 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
1103 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
1104 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
1105 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
1106 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
1107 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
1108 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
1109 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
1110 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
1111 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
1112 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
1113 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
1114 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
1115 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
1116 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
1117 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
1118 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
1119 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
1120 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
1121 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
1122 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
1123 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
1124 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
1125 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
1126 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
1127 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
1128 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
1129 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
1130 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
1131 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
1132 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
1133 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
1134 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
1135 #if defined(ADC1) && !defined(ADC2)
1136 #define LL_ADC_AWD_CH_DAC1CH1_REG ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group regular only */
1137 #define LL_ADC_AWD_CH_DAC1CH1_INJ ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group injected only */
1138 #define LL_ADC_AWD_CH_DAC1CH1_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by either group regular or injected */
1139 #define LL_ADC_AWD_CH_DAC1CH2_REG ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC1, converted by group regular only */
1140 #define LL_ADC_AWD_CH_DAC1CH2_INJ ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC1, converted by group injected only */
1141 #define LL_ADC_AWD_CH_DAC1CH2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC1, converted by either group regular or injected */
1142 #elif defined(ADC2)
1143 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
1144 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
1145 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
1146 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC2, converted by group regular only */
1147 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC2, converted by group injected only */
1148 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC2, converted by either group regular or injected */
1149 #if defined(ADC3)
1150 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
1151 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
1152 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
1153 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC3, converted by group regular only */
1154 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC3, converted by group injected only */
1155 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC3, converted by either group regular or injected */
1156 #endif
1157 #endif
1158 /**
1159 * @}
1160 */
1161
1162 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1163 * @{
1164 */
1165 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 ) /*!< ADC analog watchdog threshold high */
1166 #define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
1167 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
1168 /**
1169 * @}
1170 */
1171
1172 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
1173 * @{
1174 */
1175 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
1176 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
1177 #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1178 #define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */
1179 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1180 /**
1181 * @}
1182 */
1183
1184 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
1185 * @{
1186 */
1187 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
1188 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
1189 /**
1190 * @}
1191 */
1192
1193 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
1194 * @{
1195 */
1196 #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1197 #define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1198 #define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1199 #define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1200 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1201 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1202 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1203 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1204 /**
1205 * @}
1206 */
1207
1208 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
1209 * @{
1210 */
1211 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
1212 #define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
1213 #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
1214 #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
1215 #define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
1216 #define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
1217 #define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
1218 #define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
1219 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
1220 /**
1221 * @}
1222 */
1223
1224 #if defined(ADC_MULTIMODE_SUPPORT)
1225 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
1226 * @{
1227 */
1228 #define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */
1229 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
1230 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
1231 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
1232 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
1233 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
1234 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
1235 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
1236 /**
1237 * @}
1238 */
1239
1240 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
1241 * @{
1242 */
1243 #define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
1244 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */
1245 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */
1246 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */
1247 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */
1248 /**
1249 * @}
1250 */
1251
1252 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1253 * @{
1254 */
1255 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
1256 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
1257 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
1258 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
1259 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
1260 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
1261 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
1262 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
1263 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
1264 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
1265 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
1266 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
1267 /**
1268 * @}
1269 */
1270
1271 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1272 * @{
1273 */
1274 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
1275 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
1276 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
1277 /**
1278 * @}
1279 */
1280
1281 #endif /* ADC_MULTIMODE_SUPPORT */
1282
1283 /** @defgroup ADC_LL_EC_LEGACY ADC literals legacy naming
1284 * @{
1285 */
1286 #define LL_ADC_REG_TRIG_SW_START (LL_ADC_REG_TRIG_SOFTWARE)
1287 #define LL_ADC_REG_TRIG_EXT_TIM1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)
1288 #define LL_ADC_REG_TRIG_EXT_TIM1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)
1289 #define LL_ADC_REG_TRIG_EXT_TIM1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)
1290 #define LL_ADC_REG_TRIG_EXT_TIM2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)
1291 #define LL_ADC_REG_TRIG_EXT_TIM3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4)
1292 #define LL_ADC_REG_TRIG_EXT_TIM4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4)
1293
1294 #define LL_ADC_INJ_TRIG_SW_START (LL_ADC_INJ_TRIG_SOFTWARE)
1295 #define LL_ADC_INJ_TRIG_EXT_TIM1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)
1296 #define LL_ADC_INJ_TRIG_EXT_TIM2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)
1297 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)
1298 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)
1299 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)
1300 #define LL_ADC_INJ_TRIG_EXT_TIM8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)
1301
1302 #define LL_ADC_OVS_DATA_SHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)
1303 #define LL_ADC_OVS_DATA_SHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)
1304 #define LL_ADC_OVS_DATA_SHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)
1305 #define LL_ADC_OVS_DATA_SHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)
1306 #define LL_ADC_OVS_DATA_SHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)
1307 #define LL_ADC_OVS_DATA_SHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)
1308 #define LL_ADC_OVS_DATA_SHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)
1309 #define LL_ADC_OVS_DATA_SHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)
1310 #define LL_ADC_OVS_DATA_SHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)
1311
1312 /**
1313 * @}
1314 */
1315
1316
1317 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1318 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
1319 * not timeout values.
1320 * For details on delays values, refer to descriptions in source code
1321 * above each literal definition.
1322 * @{
1323 */
1324
1325 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
1326 /* not timeout values. */
1327 /* Timeout values for ADC operations are dependent to device clock */
1328 /* configuration (system clock versus ADC clock), */
1329 /* and therefore must be defined in user application. */
1330 /* Indications for estimation of ADC timeout delays, for this */
1331 /* STM32 serie: */
1332 /* - ADC calibration time: maximum delay is 112/fADC. */
1333 /* (refer to device datasheet, parameter "tCAL") */
1334 /* - ADC enable time: maximum delay is 1 conversion cycle. */
1335 /* (refer to device datasheet, parameter "tSTAB") */
1336 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
1337 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
1338 /* cycles */
1339 /* - ADC conversion time: duration depending on ADC clock and ADC */
1340 /* configuration. */
1341 /* (refer to device reference manual, section "Timing") */
1342
1343 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1344 /* Delay set to maximum value (refer to device datasheet, */
1345 /* parameter "tADCVREG_STUP"). */
1346 /* Unit: us */
1347 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1348
1349 /* Delay for internal voltage reference stabilization time. */
1350 /* Delay set to maximum value (refer to device datasheet, */
1351 /* parameter "tstart_vrefint"). */
1352 /* Unit: us */
1353 #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */
1354
1355 /* Delay for temperature sensor stabilization time. */
1356 /* Literal set to maximum value (refer to device datasheet, */
1357 /* parameter "tSTART"). */
1358 /* Unit: us */
1359 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */
1360
1361 /* Delay required between ADC end of calibration and ADC enable. */
1362 /* Note: On this STM32 serie, a minimum number of ADC clock cycles */
1363 /* are required between ADC end of calibration and ADC enable. */
1364 /* Wait time can be computed in user application by waiting for the */
1365 /* equivalent number of CPU cycles, by taking into account */
1366 /* ratio of CPU clock versus ADC clock prescalers. */
1367 /* Unit: ADC clock cycles. */
1368 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */
1369
1370 /**
1371 * @}
1372 */
1373
1374 /**
1375 * @}
1376 */
1377
1378
1379 /* Exported macro ------------------------------------------------------------*/
1380 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1381 * @{
1382 */
1383
1384 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1385 * @{
1386 */
1387
1388 /**
1389 * @brief Write a value in ADC register
1390 * @param __INSTANCE__ ADC Instance
1391 * @param __REG__ Register to be written
1392 * @param __VALUE__ Value to be written in the register
1393 * @retval None
1394 */
1395 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1396
1397 /**
1398 * @brief Read a value in ADC register
1399 * @param __INSTANCE__ ADC Instance
1400 * @param __REG__ Register to be read
1401 * @retval Register value
1402 */
1403 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1404 /**
1405 * @}
1406 */
1407
1408 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1409 * @{
1410 */
1411
1412 /**
1413 * @brief Helper macro to get ADC channel number in decimal format
1414 * from literals LL_ADC_CHANNEL_x.
1415 * @note Example:
1416 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1417 * will return decimal number "4".
1418 * @note The input can be a value from functions where a channel
1419 * number is returned, either defined with number
1420 * or with bitfield (only one bit must be set).
1421 * @param __CHANNEL__ This parameter can be one of the following values:
1422 * @arg @ref LL_ADC_CHANNEL_0
1423 * @arg @ref LL_ADC_CHANNEL_1 (7)
1424 * @arg @ref LL_ADC_CHANNEL_2 (7)
1425 * @arg @ref LL_ADC_CHANNEL_3 (7)
1426 * @arg @ref LL_ADC_CHANNEL_4 (7)
1427 * @arg @ref LL_ADC_CHANNEL_5 (7)
1428 * @arg @ref LL_ADC_CHANNEL_6
1429 * @arg @ref LL_ADC_CHANNEL_7
1430 * @arg @ref LL_ADC_CHANNEL_8
1431 * @arg @ref LL_ADC_CHANNEL_9
1432 * @arg @ref LL_ADC_CHANNEL_10
1433 * @arg @ref LL_ADC_CHANNEL_11
1434 * @arg @ref LL_ADC_CHANNEL_12
1435 * @arg @ref LL_ADC_CHANNEL_13
1436 * @arg @ref LL_ADC_CHANNEL_14
1437 * @arg @ref LL_ADC_CHANNEL_15
1438 * @arg @ref LL_ADC_CHANNEL_16
1439 * @arg @ref LL_ADC_CHANNEL_17
1440 * @arg @ref LL_ADC_CHANNEL_18
1441 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1442 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
1443 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
1444 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
1445 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
1446 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
1447 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
1448 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
1449 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
1450 *
1451 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
1452 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
1453 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
1454 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
1455 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
1456 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
1457 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
1458 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
1459 * @retval Value between Min_Data=0 and Max_Data=18
1460 */
1461 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1462 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
1463 ? ( \
1464 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1465 ) \
1466 : \
1467 ( \
1468 (uint32_t)POSITION_VAL((__CHANNEL__)) \
1469 ) \
1470 )
1471
1472 /**
1473 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1474 * from number in decimal format.
1475 * @note Example:
1476 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1477 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1478 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1479 * @retval Returned value can be one of the following values:
1480 * @arg @ref LL_ADC_CHANNEL_0
1481 * @arg @ref LL_ADC_CHANNEL_1 (7)
1482 * @arg @ref LL_ADC_CHANNEL_2 (7)
1483 * @arg @ref LL_ADC_CHANNEL_3 (7)
1484 * @arg @ref LL_ADC_CHANNEL_4 (7)
1485 * @arg @ref LL_ADC_CHANNEL_5 (7)
1486 * @arg @ref LL_ADC_CHANNEL_6
1487 * @arg @ref LL_ADC_CHANNEL_7
1488 * @arg @ref LL_ADC_CHANNEL_8
1489 * @arg @ref LL_ADC_CHANNEL_9
1490 * @arg @ref LL_ADC_CHANNEL_10
1491 * @arg @ref LL_ADC_CHANNEL_11
1492 * @arg @ref LL_ADC_CHANNEL_12
1493 * @arg @ref LL_ADC_CHANNEL_13
1494 * @arg @ref LL_ADC_CHANNEL_14
1495 * @arg @ref LL_ADC_CHANNEL_15
1496 * @arg @ref LL_ADC_CHANNEL_16
1497 * @arg @ref LL_ADC_CHANNEL_17
1498 * @arg @ref LL_ADC_CHANNEL_18
1499 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1500 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
1501 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
1502 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
1503 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
1504 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
1505 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
1506 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
1507 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
1508 *
1509 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
1510 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
1511 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
1512 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
1513 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
1514 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
1515 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
1516 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
1517 * (1, 2, 3, 4) For ADC channel read back from ADC register,
1518 * comparison with internal channel parameter to be done
1519 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1520 */
1521 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1522 (((__DECIMAL_NB__) <= 9UL) \
1523 ? ( \
1524 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1525 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1526 (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1527 ) \
1528 : \
1529 ( \
1530 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1531 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1532 (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1533 ) \
1534 )
1535
1536 /**
1537 * @brief Helper macro to determine whether the selected channel
1538 * corresponds to literal definitions of driver.
1539 * @note The different literal definitions of ADC channels are:
1540 * - ADC internal channel:
1541 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1542 * - ADC external channel (channel connected to a GPIO pin):
1543 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1544 * @note The channel parameter must be a value defined from literal
1545 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1546 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1547 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1548 * must not be a value from functions where a channel number is
1549 * returned from ADC registers,
1550 * because internal and external channels share the same channel
1551 * number in ADC registers. The differentiation is made only with
1552 * parameters definitions of driver.
1553 * @param __CHANNEL__ This parameter can be one of the following values:
1554 * @arg @ref LL_ADC_CHANNEL_0
1555 * @arg @ref LL_ADC_CHANNEL_1 (7)
1556 * @arg @ref LL_ADC_CHANNEL_2 (7)
1557 * @arg @ref LL_ADC_CHANNEL_3 (7)
1558 * @arg @ref LL_ADC_CHANNEL_4 (7)
1559 * @arg @ref LL_ADC_CHANNEL_5 (7)
1560 * @arg @ref LL_ADC_CHANNEL_6
1561 * @arg @ref LL_ADC_CHANNEL_7
1562 * @arg @ref LL_ADC_CHANNEL_8
1563 * @arg @ref LL_ADC_CHANNEL_9
1564 * @arg @ref LL_ADC_CHANNEL_10
1565 * @arg @ref LL_ADC_CHANNEL_11
1566 * @arg @ref LL_ADC_CHANNEL_12
1567 * @arg @ref LL_ADC_CHANNEL_13
1568 * @arg @ref LL_ADC_CHANNEL_14
1569 * @arg @ref LL_ADC_CHANNEL_15
1570 * @arg @ref LL_ADC_CHANNEL_16
1571 * @arg @ref LL_ADC_CHANNEL_17
1572 * @arg @ref LL_ADC_CHANNEL_18
1573 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1574 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
1575 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
1576 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
1577 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
1578 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
1579 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
1580 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
1581 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
1582 *
1583 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
1584 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
1585 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
1586 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
1587 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
1588 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
1589 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
1590 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
1591 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1592 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1593 */
1594 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1595 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1596
1597 /**
1598 * @brief Helper macro to convert a channel defined from parameter
1599 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1600 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1601 * to its equivalent parameter definition of a ADC external channel
1602 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1603 * @note The channel parameter can be, additionally to a value
1604 * defined from parameter definition of a ADC internal channel
1605 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1606 * a value defined from parameter definition of
1607 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1608 * or a value from functions where a channel number is returned
1609 * from ADC registers.
1610 * @param __CHANNEL__ This parameter can be one of the following values:
1611 * @arg @ref LL_ADC_CHANNEL_0
1612 * @arg @ref LL_ADC_CHANNEL_1 (7)
1613 * @arg @ref LL_ADC_CHANNEL_2 (7)
1614 * @arg @ref LL_ADC_CHANNEL_3 (7)
1615 * @arg @ref LL_ADC_CHANNEL_4 (7)
1616 * @arg @ref LL_ADC_CHANNEL_5 (7)
1617 * @arg @ref LL_ADC_CHANNEL_6
1618 * @arg @ref LL_ADC_CHANNEL_7
1619 * @arg @ref LL_ADC_CHANNEL_8
1620 * @arg @ref LL_ADC_CHANNEL_9
1621 * @arg @ref LL_ADC_CHANNEL_10
1622 * @arg @ref LL_ADC_CHANNEL_11
1623 * @arg @ref LL_ADC_CHANNEL_12
1624 * @arg @ref LL_ADC_CHANNEL_13
1625 * @arg @ref LL_ADC_CHANNEL_14
1626 * @arg @ref LL_ADC_CHANNEL_15
1627 * @arg @ref LL_ADC_CHANNEL_16
1628 * @arg @ref LL_ADC_CHANNEL_17
1629 * @arg @ref LL_ADC_CHANNEL_18
1630 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1631 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
1632 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
1633 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
1634 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
1635 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
1636 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
1637 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
1638 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
1639 *
1640 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
1641 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
1642 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
1643 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
1644 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
1645 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
1646 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
1647 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
1648 * @retval Returned value can be one of the following values:
1649 * @arg @ref LL_ADC_CHANNEL_0
1650 * @arg @ref LL_ADC_CHANNEL_1
1651 * @arg @ref LL_ADC_CHANNEL_2
1652 * @arg @ref LL_ADC_CHANNEL_3
1653 * @arg @ref LL_ADC_CHANNEL_4
1654 * @arg @ref LL_ADC_CHANNEL_5
1655 * @arg @ref LL_ADC_CHANNEL_6
1656 * @arg @ref LL_ADC_CHANNEL_7
1657 * @arg @ref LL_ADC_CHANNEL_8
1658 * @arg @ref LL_ADC_CHANNEL_9
1659 * @arg @ref LL_ADC_CHANNEL_10
1660 * @arg @ref LL_ADC_CHANNEL_11
1661 * @arg @ref LL_ADC_CHANNEL_12
1662 * @arg @ref LL_ADC_CHANNEL_13
1663 * @arg @ref LL_ADC_CHANNEL_14
1664 * @arg @ref LL_ADC_CHANNEL_15
1665 * @arg @ref LL_ADC_CHANNEL_16
1666 * @arg @ref LL_ADC_CHANNEL_17
1667 * @arg @ref LL_ADC_CHANNEL_18
1668 */
1669 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1670 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1671
1672 /**
1673 * @brief Helper macro to determine whether the internal channel
1674 * selected is available on the ADC instance selected.
1675 * @note The channel parameter must be a value defined from parameter
1676 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1677 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1678 * must not be a value defined from parameter definition of
1679 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1680 * or a value from functions where a channel number is
1681 * returned from ADC registers,
1682 * because internal and external channels share the same channel
1683 * number in ADC registers. The differentiation is made only with
1684 * parameters definitions of driver.
1685 * @param __ADC_INSTANCE__ ADC instance
1686 * @param __CHANNEL__ This parameter can be one of the following values:
1687 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1688 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
1689 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
1690 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
1691 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
1692 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
1693 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
1694 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
1695 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
1696 *
1697 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
1698 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
1699 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
1700 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
1701 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
1702 * (6) On STM32L4, parameter available on devices with several ADC instances.
1703 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1704 * Value "1" if the internal channel selected is available on the ADC instance selected.
1705 */
1706 #if defined (ADC1) && defined (ADC2) && defined (ADC3)
1707 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1708 (((__ADC_INSTANCE__) == ADC1) \
1709 ? ( \
1710 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1711 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1712 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1713 ) \
1714 : \
1715 ((__ADC_INSTANCE__) == ADC2) \
1716 ? ( \
1717 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1718 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
1719 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
1720 ) \
1721 : \
1722 ((__ADC_INSTANCE__) == ADC3) \
1723 ? ( \
1724 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1725 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1726 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1727 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC3) || \
1728 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC3) \
1729 ) \
1730 : \
1731 (0UL) \
1732 )
1733 #elif defined (ADC1) && defined (ADC2)
1734 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1735 (((__ADC_INSTANCE__) == ADC1) \
1736 ? ( \
1737 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1738 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1739 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1740 ) \
1741 : \
1742 ((__ADC_INSTANCE__) == ADC2) \
1743 ? ( \
1744 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1745 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
1746 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
1747 ) \
1748 : \
1749 (0UL) \
1750 )
1751 #elif defined (ADC1)
1752 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1753 ( \
1754 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1755 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1756 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1757 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1) || \
1758 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2) \
1759 )
1760 #endif
1761
1762 /**
1763 * @brief Helper macro to define ADC analog watchdog parameter:
1764 * define a single channel to monitor with analog watchdog
1765 * from sequencer channel and groups definition.
1766 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1767 * Example:
1768 * LL_ADC_SetAnalogWDMonitChannels(
1769 * ADC1, LL_ADC_AWD1,
1770 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1771 * @param __CHANNEL__ This parameter can be one of the following values:
1772 * @arg @ref LL_ADC_CHANNEL_0
1773 * @arg @ref LL_ADC_CHANNEL_1 (7)
1774 * @arg @ref LL_ADC_CHANNEL_2 (7)
1775 * @arg @ref LL_ADC_CHANNEL_3 (7)
1776 * @arg @ref LL_ADC_CHANNEL_4 (7)
1777 * @arg @ref LL_ADC_CHANNEL_5 (7)
1778 * @arg @ref LL_ADC_CHANNEL_6
1779 * @arg @ref LL_ADC_CHANNEL_7
1780 * @arg @ref LL_ADC_CHANNEL_8
1781 * @arg @ref LL_ADC_CHANNEL_9
1782 * @arg @ref LL_ADC_CHANNEL_10
1783 * @arg @ref LL_ADC_CHANNEL_11
1784 * @arg @ref LL_ADC_CHANNEL_12
1785 * @arg @ref LL_ADC_CHANNEL_13
1786 * @arg @ref LL_ADC_CHANNEL_14
1787 * @arg @ref LL_ADC_CHANNEL_15
1788 * @arg @ref LL_ADC_CHANNEL_16
1789 * @arg @ref LL_ADC_CHANNEL_17
1790 * @arg @ref LL_ADC_CHANNEL_18
1791 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1792 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
1793 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
1794 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
1795 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
1796 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
1797 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
1798 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
1799 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
1800 *
1801 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
1802 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
1803 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
1804 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
1805 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
1806 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
1807 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
1808 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
1809 * (1, 2, 3, 4) For ADC channel read back from ADC register,
1810 * comparison with internal channel parameter to be done
1811 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1812 * @param __GROUP__ This parameter can be one of the following values:
1813 * @arg @ref LL_ADC_GROUP_REGULAR
1814 * @arg @ref LL_ADC_GROUP_INJECTED
1815 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
1816 * @retval Returned value can be one of the following values:
1817 * @arg @ref LL_ADC_AWD_DISABLE
1818 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
1819 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
1820 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
1821 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
1822 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
1823 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
1824 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
1825 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
1826 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
1827 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
1828 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
1829 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
1830 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
1831 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
1832 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
1833 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
1834 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
1835 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
1836 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
1837 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
1838 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
1839 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
1840 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
1841 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
1842 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
1843 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
1844 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
1845 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
1846 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
1847 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
1848 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
1849 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
1850 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
1851 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
1852 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
1853 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
1854 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
1855 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
1856 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
1857 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
1858 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
1859 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
1860 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
1861 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
1862 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
1863 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
1864 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
1865 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
1866 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
1867 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
1868 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
1869 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
1870 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
1871 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
1872 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
1873 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
1874 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
1875 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
1876 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
1877 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
1878 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
1879 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
1880 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
1881 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(4)
1882 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(4)
1883 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (4)
1884 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(4)
1885 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(4)
1886 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (4)
1887 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG (0)(2)(5)
1888 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_INJ (0)(2)(5)
1889 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG_INJ (2)(5)
1890 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG (0)(2)(5)
1891 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_INJ (0)(2)(5)
1892 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG_INJ (2)(5)
1893 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)(6)
1894 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)(6)
1895 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)(6)
1896 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)(6)
1897 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)(6)
1898 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)(6)
1899 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG (0)(3)(6)
1900 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ (0)(3)(6)
1901 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ (3)(6)
1902 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG (0)(3)(6)
1903 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ (0)(3)(6)
1904 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ (3)(6)
1905 *
1906 * (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\n
1907 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
1908 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
1909 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
1910 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
1911 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
1912 * (6) On STM32L4, parameter available on devices with several ADC instances.
1913 */
1914 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1915 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
1916 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
1917 : \
1918 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
1919 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
1920 : \
1921 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
1922 )
1923
1924 /**
1925 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1926 * or low in function of ADC resolution, when ADC resolution is
1927 * different of 12 bits.
1928 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
1929 * or @ref LL_ADC_SetAnalogWDThresholds().
1930 * Example, with a ADC resolution of 8 bits, to set the value of
1931 * analog watchdog threshold high (on 8 bits):
1932 * LL_ADC_SetAnalogWDThresholds
1933 * (< ADCx param >,
1934 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1935 * );
1936 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1937 * @arg @ref LL_ADC_RESOLUTION_12B
1938 * @arg @ref LL_ADC_RESOLUTION_10B
1939 * @arg @ref LL_ADC_RESOLUTION_8B
1940 * @arg @ref LL_ADC_RESOLUTION_6B
1941 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1942 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1943 */
1944 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1945 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
1946
1947 /**
1948 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1949 * or low in function of ADC resolution, when ADC resolution is
1950 * different of 12 bits.
1951 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1952 * Example, with a ADC resolution of 8 bits, to get the value of
1953 * analog watchdog threshold high (on 8 bits):
1954 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1955 * (LL_ADC_RESOLUTION_8B,
1956 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1957 * );
1958 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1959 * @arg @ref LL_ADC_RESOLUTION_12B
1960 * @arg @ref LL_ADC_RESOLUTION_10B
1961 * @arg @ref LL_ADC_RESOLUTION_8B
1962 * @arg @ref LL_ADC_RESOLUTION_6B
1963 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1964 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1965 */
1966 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1967 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
1968
1969 /**
1970 * @brief Helper macro to get the ADC analog watchdog threshold high
1971 * or low from raw value containing both thresholds concatenated.
1972 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1973 * Example, to get analog watchdog threshold high from the register raw value:
1974 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
1975 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
1976 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
1977 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
1978 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1979 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1980 */
1981 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
1982 (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)
1983
1984 /**
1985 * @brief Helper macro to set the ADC calibration value with both single ended
1986 * and differential modes calibration factors concatenated.
1987 * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
1988 * Example, to set calibration factors single ended to 0x55
1989 * and differential ended to 0x2A:
1990 * LL_ADC_SetCalibrationFactor(
1991 * ADC1,
1992 * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
1993 * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
1994 * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
1995 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1996 */
1997 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
1998 (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
1999
2000 #if defined(ADC_MULTIMODE_SUPPORT)
2001 /**
2002 * @brief Helper macro to get the ADC multimode conversion data of ADC master
2003 * or ADC slave from raw value with both ADC conversion data concatenated.
2004 * @note This macro is intended to be used when multimode transfer by DMA
2005 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
2006 * In this case the transferred data need to processed with this macro
2007 * to separate the conversion data of ADC master and ADC slave.
2008 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
2009 * @arg @ref LL_ADC_MULTI_MASTER
2010 * @arg @ref LL_ADC_MULTI_SLAVE
2011 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
2012 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2013 */
2014 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
2015 (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
2016 #endif
2017
2018 #if defined(ADC_MULTIMODE_SUPPORT)
2019 /**
2020 * @brief Helper macro to select, from a ADC instance, to which ADC instance
2021 * it has a dependence in multimode (ADC master of the corresponding
2022 * ADC common instance).
2023 * @note In case of device with multimode available and a mix of
2024 * ADC instances compliant and not compliant with multimode feature,
2025 * ADC instances not compliant with multimode feature are
2026 * considered as master instances (do not depend to
2027 * any other ADC instance).
2028 * @param __ADCx__ ADC instance
2029 * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
2030 */
2031 #if defined(ADC2)
2032 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2033 ( ( ((__ADCx__) == ADC2) \
2034 )? \
2035 (ADC1) \
2036 : \
2037 (__ADCx__) \
2038 )
2039 #else
2040 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2041 (__ADCx__)
2042 #endif
2043 #endif
2044
2045 /**
2046 * @brief Helper macro to select the ADC common instance
2047 * to which is belonging the selected ADC instance.
2048 * @note ADC common register instance can be used for:
2049 * - Set parameters common to several ADC instances
2050 * - Multimode (for devices with several ADC instances)
2051 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2052 * @param __ADCx__ ADC instance
2053 * @retval ADC common register instance
2054 */
2055 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
2056 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2057 (ADC123_COMMON)
2058 #elif defined(ADC1) && defined(ADC2)
2059 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2060 (ADC12_COMMON)
2061 #else
2062 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2063 (ADC1_COMMON)
2064 #endif
2065
2066 /**
2067 * @brief Helper macro to check if all ADC instances sharing the same
2068 * ADC common instance are disabled.
2069 * @note This check is required by functions with setting conditioned to
2070 * ADC state:
2071 * All ADC instances of the ADC common group must be disabled.
2072 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2073 * @note On devices with only 1 ADC common instance, parameter of this macro
2074 * is useless and can be ignored (parameter kept for compatibility
2075 * with devices featuring several ADC common instances).
2076 * @param __ADCXY_COMMON__ ADC common instance
2077 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2078 * @retval Value "0" if all ADC instances sharing the same ADC common instance
2079 * are disabled.
2080 * Value "1" if at least one ADC instance sharing the same ADC common instance
2081 * is enabled.
2082 */
2083 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
2084 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2085 (LL_ADC_IsEnabled(ADC1) | \
2086 LL_ADC_IsEnabled(ADC2) | \
2087 LL_ADC_IsEnabled(ADC3) )
2088 #elif defined(ADC1) && defined(ADC2)
2089 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2090 (LL_ADC_IsEnabled(ADC1) | \
2091 LL_ADC_IsEnabled(ADC2) )
2092 #else
2093 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2094 (LL_ADC_IsEnabled(ADC1))
2095 #endif
2096
2097 /**
2098 * @brief Helper macro to define the ADC conversion data full-scale digital
2099 * value corresponding to the selected ADC resolution.
2100 * @note ADC conversion data full-scale corresponds to voltage range
2101 * determined by analog voltage references Vref+ and Vref-
2102 * (refer to reference manual).
2103 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2104 * @arg @ref LL_ADC_RESOLUTION_12B
2105 * @arg @ref LL_ADC_RESOLUTION_10B
2106 * @arg @ref LL_ADC_RESOLUTION_8B
2107 * @arg @ref LL_ADC_RESOLUTION_6B
2108 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
2109 */
2110 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2111 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
2112
2113 /**
2114 * @brief Helper macro to convert the ADC conversion data from
2115 * a resolution to another resolution.
2116 * @param __DATA__ ADC conversion data to be converted
2117 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
2118 * This parameter can be one of the following values:
2119 * @arg @ref LL_ADC_RESOLUTION_12B
2120 * @arg @ref LL_ADC_RESOLUTION_10B
2121 * @arg @ref LL_ADC_RESOLUTION_8B
2122 * @arg @ref LL_ADC_RESOLUTION_6B
2123 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
2124 * This parameter can be one of the following values:
2125 * @arg @ref LL_ADC_RESOLUTION_12B
2126 * @arg @ref LL_ADC_RESOLUTION_10B
2127 * @arg @ref LL_ADC_RESOLUTION_8B
2128 * @arg @ref LL_ADC_RESOLUTION_6B
2129 * @retval ADC conversion data to the requested resolution
2130 */
2131 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2132 __ADC_RESOLUTION_CURRENT__,\
2133 __ADC_RESOLUTION_TARGET__) \
2134 (((__DATA__) \
2135 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2136 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2137 )
2138
2139 /**
2140 * @brief Helper macro to calculate the voltage (unit: mVolt)
2141 * corresponding to a ADC conversion data (unit: digital value).
2142 * @note Analog reference voltage (Vref+) must be either known from
2143 * user board environment or can be calculated using ADC measurement
2144 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2145 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2146 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
2147 * (unit: digital value).
2148 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2149 * @arg @ref LL_ADC_RESOLUTION_12B
2150 * @arg @ref LL_ADC_RESOLUTION_10B
2151 * @arg @ref LL_ADC_RESOLUTION_8B
2152 * @arg @ref LL_ADC_RESOLUTION_6B
2153 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2154 */
2155 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2156 __ADC_DATA__,\
2157 __ADC_RESOLUTION__) \
2158 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
2159 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2160 )
2161
2162 /* Legacy define */
2163 #define __LL_ADC_CALC_DATA_VOLTAGE() __LL_ADC_CALC_DATA_TO_VOLTAGE()
2164
2165 /**
2166 * @brief Helper macro to calculate analog reference voltage (Vref+)
2167 * (unit: mVolt) from ADC conversion data of internal voltage
2168 * reference VrefInt.
2169 * @note Computation is using VrefInt calibration value
2170 * stored in system memory for each device during production.
2171 * @note This voltage depends on user board environment: voltage level
2172 * connected to pin Vref+.
2173 * On devices with small package, the pin Vref+ is not present
2174 * and internally bonded to pin Vdda.
2175 * @note On this STM32 serie, calibration data of internal voltage reference
2176 * VrefInt corresponds to a resolution of 12 bits,
2177 * this is the recommended ADC resolution to convert voltage of
2178 * internal voltage reference VrefInt.
2179 * Otherwise, this macro performs the processing to scale
2180 * ADC conversion data to 12 bits.
2181 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
2182 * of internal voltage reference VrefInt (unit: digital value).
2183 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2184 * @arg @ref LL_ADC_RESOLUTION_12B
2185 * @arg @ref LL_ADC_RESOLUTION_10B
2186 * @arg @ref LL_ADC_RESOLUTION_8B
2187 * @arg @ref LL_ADC_RESOLUTION_6B
2188 * @retval Analog reference voltage (unit: mV)
2189 */
2190 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
2191 __ADC_RESOLUTION__) \
2192 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
2193 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
2194 (__ADC_RESOLUTION__), \
2195 LL_ADC_RESOLUTION_12B))
2196
2197 /**
2198 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2199 * from ADC conversion data of internal temperature sensor.
2200 * @note Computation is using temperature sensor calibration values
2201 * stored in system memory for each device during production.
2202 * @note Calculation formula:
2203 * Temperature = ((TS_ADC_DATA - TS_CAL1)
2204 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
2205 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
2206 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2207 * Avg_Slope = (TS_CAL2 - TS_CAL1)
2208 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
2209 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
2210 * TEMP_DEGC_CAL1 (calibrated in factory)
2211 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
2212 * TEMP_DEGC_CAL2 (calibrated in factory)
2213 * Caution: Calculation relevancy under reserve that calibration
2214 * parameters are correct (address and data).
2215 * To calculate temperature using temperature sensor
2216 * datasheet typical values (generic values less, therefore
2217 * less accurate than calibrated values),
2218 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
2219 * @note As calculation input, the analog reference voltage (Vref+) must be
2220 * defined as it impacts the ADC LSB equivalent voltage.
2221 * @note Analog reference voltage (Vref+) must be either known from
2222 * user board environment or can be calculated using ADC measurement
2223 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2224 * @note On this STM32 serie, calibration data of temperature sensor
2225 * corresponds to a resolution of 12 bits,
2226 * this is the recommended ADC resolution to convert voltage of
2227 * temperature sensor.
2228 * Otherwise, this macro performs the processing to scale
2229 * ADC conversion data to 12 bits.
2230 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2231 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
2232 * temperature sensor (unit: digital value).
2233 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
2234 * sensor voltage has been measured.
2235 * This parameter can be one of the following values:
2236 * @arg @ref LL_ADC_RESOLUTION_12B
2237 * @arg @ref LL_ADC_RESOLUTION_10B
2238 * @arg @ref LL_ADC_RESOLUTION_8B
2239 * @arg @ref LL_ADC_RESOLUTION_6B
2240 * @retval Temperature (unit: degree Celsius)
2241 */
2242 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
2243 __TEMPSENSOR_ADC_DATA__,\
2244 __ADC_RESOLUTION__) \
2245 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
2246 (__ADC_RESOLUTION__), \
2247 LL_ADC_RESOLUTION_12B) \
2248 * (__VREFANALOG_VOLTAGE__)) \
2249 / TEMPSENSOR_CAL_VREFANALOG) \
2250 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
2251 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
2252 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
2253 ) + TEMPSENSOR_CAL1_TEMP \
2254 )
2255
2256 /**
2257 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2258 * from ADC conversion data of internal temperature sensor.
2259 * @note Computation is using temperature sensor typical values
2260 * (refer to device datasheet).
2261 * @note Calculation formula:
2262 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
2263 * / Avg_Slope + CALx_TEMP
2264 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2265 * (unit: digital value)
2266 * Avg_Slope = temperature sensor slope
2267 * (unit: uV/Degree Celsius)
2268 * TS_TYP_CALx_VOLT = temperature sensor digital value at
2269 * temperature CALx_TEMP (unit: mV)
2270 * Caution: Calculation relevancy under reserve the temperature sensor
2271 * of the current device has characteristics in line with
2272 * datasheet typical values.
2273 * If temperature sensor calibration values are available on
2274 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
2275 * temperature calculation will be more accurate using
2276 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
2277 * @note As calculation input, the analog reference voltage (Vref+) must be
2278 * defined as it impacts the ADC LSB equivalent voltage.
2279 * @note Analog reference voltage (Vref+) must be either known from
2280 * user board environment or can be calculated using ADC measurement
2281 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2282 * @note ADC measurement data must correspond to a resolution of 12 bits
2283 * (full scale digital value 4095). If not the case, the data must be
2284 * preliminarily rescaled to an equivalent resolution of 12 bits.
2285 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
2286 * On STM32L4, refer to device datasheet parameter "Avg_Slope".
2287 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
2288 * On STM32L4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
2289 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
2290 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
2291 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
2292 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
2293 * This parameter can be one of the following values:
2294 * @arg @ref LL_ADC_RESOLUTION_12B
2295 * @arg @ref LL_ADC_RESOLUTION_10B
2296 * @arg @ref LL_ADC_RESOLUTION_8B
2297 * @arg @ref LL_ADC_RESOLUTION_6B
2298 * @retval Temperature (unit: degree Celsius)
2299 */
2300 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
2301 __TEMPSENSOR_TYP_CALX_V__,\
2302 __TEMPSENSOR_CALX_TEMP__,\
2303 __VREFANALOG_VOLTAGE__,\
2304 __TEMPSENSOR_ADC_DATA__,\
2305 __ADC_RESOLUTION__) \
2306 ((( ( \
2307 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
2308 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
2309 * 1000UL) \
2310 - \
2311 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
2312 * 1000UL) \
2313 ) \
2314 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
2315 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
2316 )
2317
2318 /**
2319 * @}
2320 */
2321
2322 /**
2323 * @}
2324 */
2325
2326
2327 /* Exported functions --------------------------------------------------------*/
2328 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
2329 * @{
2330 */
2331
2332 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
2333 * @{
2334 */
2335 /* Note: LL ADC functions to set DMA transfer are located into sections of */
2336 /* configuration of ADC instance, groups and multimode (if available): */
2337 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
2338
2339 /**
2340 * @brief Function to help to configure DMA transfer from ADC: retrieve the
2341 * ADC register address from ADC instance and a list of ADC registers
2342 * intended to be used (most commonly) with DMA transfer.
2343 * @note These ADC registers are data registers:
2344 * when ADC conversion data is available in ADC data registers,
2345 * ADC generates a DMA transfer request.
2346 * @note This macro is intended to be used with LL DMA driver, refer to
2347 * function "LL_DMA_ConfigAddresses()".
2348 * Example:
2349 * LL_DMA_ConfigAddresses(DMA1,
2350 * LL_DMA_CHANNEL_1,
2351 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
2352 * (uint32_t)&< array or variable >,
2353 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
2354 * @note For devices with several ADC: in multimode, some devices
2355 * use a different data register outside of ADC instance scope
2356 * (common data register). This macro manages this register difference,
2357 * only ADC instance has to be set as parameter.
2358 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
2359 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
2360 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
2361 * @param ADCx ADC instance
2362 * @param Register This parameter can be one of the following values:
2363 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
2364 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
2365 *
2366 * (1) Available on devices with several ADC instances.
2367 * @retval ADC register address
2368 */
2369 #if defined(ADC_MULTIMODE_SUPPORT)
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)2370 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
2371 {
2372 register uint32_t data_reg_addr;
2373
2374 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
2375 {
2376 /* Retrieve address of register DR */
2377 data_reg_addr = (uint32_t) &(ADCx->DR);
2378 }
2379 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
2380 {
2381 /* Retrieve address of register CDR */
2382 data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
2383 }
2384
2385 return data_reg_addr;
2386 }
2387 #else
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)2388 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
2389 {
2390 /* Prevent unused argument(s) compilation warning */
2391 (void)(Register);
2392
2393 /* Retrieve address of register DR */
2394 return (uint32_t) &(ADCx->DR);
2395 }
2396 #endif
2397
2398 /**
2399 * @}
2400 */
2401
2402 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
2403 * @{
2404 */
2405
2406 /**
2407 * @brief Set parameter common to several ADC: Clock source and prescaler.
2408 * @note On this STM32 serie, if ADC group injected is used, some
2409 * clock ratio constraints between ADC clock and AHB clock
2410 * must be respected.
2411 * Refer to reference manual.
2412 * @note On this STM32 serie, setting of this feature is conditioned to
2413 * ADC state:
2414 * All ADC instances of the ADC common group must be disabled.
2415 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2416 * ADC instance or by using helper macro helper macro
2417 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2418 * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
2419 * CCR PRESC LL_ADC_SetCommonClock
2420 * @param ADCxy_COMMON ADC common instance
2421 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2422 * @param CommonClock This parameter can be one of the following values:
2423 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2424 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2425 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2426 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2427 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2428 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2429 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
2430 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
2431 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
2432 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
2433 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
2434 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
2435 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
2436 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
2437 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
2438 * @retval None
2439 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)2440 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
2441 {
2442 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
2443 }
2444
2445 /**
2446 * @brief Get parameter common to several ADC: Clock source and prescaler.
2447 * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
2448 * CCR PRESC LL_ADC_GetCommonClock
2449 * @param ADCxy_COMMON ADC common instance
2450 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2451 * @retval Returned value can be one of the following values:
2452 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2453 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2454 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2455 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2456 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2457 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2458 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
2459 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
2460 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
2461 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
2462 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
2463 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
2464 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
2465 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
2466 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
2467 */
LL_ADC_GetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON)2468 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
2469 {
2470 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
2471 }
2472
2473 /**
2474 * @brief Set parameter common to several ADC: measurement path to
2475 * internal channels (VrefInt, temperature sensor, ...).
2476 * Configure all paths (overwrite current configuration).
2477 * @note One or several values can be selected.
2478 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2479 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2480 * The values not selected are removed from configuration.
2481 * @note Stabilization time of measurement path to internal channel:
2482 * After enabling internal paths, before starting ADC conversion,
2483 * a delay is required for internal voltage reference and
2484 * temperature sensor stabilization time.
2485 * Refer to device datasheet.
2486 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2487 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
2488 * @note ADC internal channel sampling time constraint:
2489 * For ADC conversion of internal channels,
2490 * a sampling time minimum value is required.
2491 * Refer to device datasheet.
2492 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
2493 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
2494 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
2495 * @param ADCxy_COMMON ADC common instance
2496 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2497 * @param PathInternal This parameter can be a combination of the following values:
2498 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2499 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2500 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2501 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2502 * @retval None
2503 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2504 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2505 {
2506 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
2507 }
2508
2509 /**
2510 * @brief Set parameter common to several ADC: measurement path to
2511 * internal channels (VrefInt, temperature sensor, ...).
2512 * Add paths to the current configuration.
2513 * @note One or several values can be selected.
2514 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2515 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2516 * @note Stabilization time of measurement path to internal channel:
2517 * After enabling internal paths, before starting ADC conversion,
2518 * a delay is required for internal voltage reference and
2519 * temperature sensor stabilization time.
2520 * Refer to device datasheet.
2521 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2522 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
2523 * @note ADC internal channel sampling time constraint:
2524 * For ADC conversion of internal channels,
2525 * a sampling time minimum value is required.
2526 * Refer to device datasheet.
2527 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
2528 * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n
2529 * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd
2530 * @param ADCxy_COMMON ADC common instance
2531 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2532 * @param PathInternal This parameter can be a combination of the following values:
2533 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2534 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2535 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2536 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2537 * @retval None
2538 */
LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2539 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2540 {
2541 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
2542 }
2543
2544 /**
2545 * @brief Set parameter common to several ADC: measurement path to
2546 * internal channels (VrefInt, temperature sensor, ...).
2547 * Remove paths to the current configuration.
2548 * @note One or several values can be selected.
2549 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2550 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2551 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
2552 * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n
2553 * CCR VBATEN LL_ADC_SetCommonPathInternalChRem
2554 * @param ADCxy_COMMON ADC common instance
2555 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2556 * @param PathInternal This parameter can be a combination of the following values:
2557 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2558 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2559 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2560 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2561 * @retval None
2562 */
LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2563 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2564 {
2565 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
2566 }
2567
2568 /**
2569 * @brief Get parameter common to several ADC: measurement path to internal
2570 * channels (VrefInt, temperature sensor, ...).
2571 * @note One or several values can be selected.
2572 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2573 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2574 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
2575 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
2576 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
2577 * @param ADCxy_COMMON ADC common instance
2578 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2579 * @retval Returned value can be a combination of the following values:
2580 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2581 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2582 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2583 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2584 */
LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON)2585 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
2586 {
2587 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
2588 }
2589
2590 /**
2591 * @}
2592 */
2593
2594 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
2595 * @{
2596 */
2597
2598 /**
2599 * @brief Set ADC calibration factor in the mode single-ended
2600 * or differential (for devices with differential mode available).
2601 * @note This function is intended to set calibration parameters
2602 * without having to perform a new calibration using
2603 * @ref LL_ADC_StartCalibration().
2604 * @note For devices with differential mode available:
2605 * Calibration of offset is specific to each of
2606 * single-ended and differential modes
2607 * (calibration factor must be specified for each of these
2608 * differential modes, if used afterwards and if the application
2609 * requires their calibration).
2610 * @note In case of setting calibration factors of both modes single ended
2611 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
2612 * both calibration factors must be concatenated.
2613 * To perform this processing, use helper macro
2614 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
2615 * @note On this STM32 serie, setting of this feature is conditioned to
2616 * ADC state:
2617 * ADC must be enabled, without calibration on going, without conversion
2618 * on going on group regular.
2619 * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
2620 * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
2621 * @param ADCx ADC instance
2622 * @param SingleDiff This parameter can be one of the following values:
2623 * @arg @ref LL_ADC_SINGLE_ENDED
2624 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
2625 * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
2626 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
2627 * @retval None
2628 */
LL_ADC_SetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff,uint32_t CalibrationFactor)2629 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
2630 {
2631 MODIFY_REG(ADCx->CALFACT,
2632 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
2633 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
2634 }
2635
2636 /**
2637 * @brief Get ADC calibration factor in the mode single-ended
2638 * or differential (for devices with differential mode available).
2639 * @note Calibration factors are set by hardware after performing
2640 * a calibration run using function @ref LL_ADC_StartCalibration().
2641 * @note For devices with differential mode available:
2642 * Calibration of offset is specific to each of
2643 * single-ended and differential modes
2644 * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
2645 * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
2646 * @param ADCx ADC instance
2647 * @param SingleDiff This parameter can be one of the following values:
2648 * @arg @ref LL_ADC_SINGLE_ENDED
2649 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
2650 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
2651 */
LL_ADC_GetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff)2652 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
2653 {
2654 /* Retrieve bits with position in register depending on parameter */
2655 /* "SingleDiff". */
2656 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
2657 /* containing other bits reserved for other purpose. */
2658 return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
2659 }
2660
2661 /**
2662 * @brief Set ADC resolution.
2663 * Refer to reference manual for alignments formats
2664 * dependencies to ADC resolutions.
2665 * @note On this STM32 serie, setting of this feature is conditioned to
2666 * ADC state:
2667 * ADC must be disabled or enabled without conversion on going
2668 * on either groups regular or injected.
2669 * @rmtoll CFGR RES LL_ADC_SetResolution
2670 * @param ADCx ADC instance
2671 * @param Resolution This parameter can be one of the following values:
2672 * @arg @ref LL_ADC_RESOLUTION_12B
2673 * @arg @ref LL_ADC_RESOLUTION_10B
2674 * @arg @ref LL_ADC_RESOLUTION_8B
2675 * @arg @ref LL_ADC_RESOLUTION_6B
2676 * @retval None
2677 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)2678 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2679 {
2680 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
2681 }
2682
2683 /**
2684 * @brief Get ADC resolution.
2685 * Refer to reference manual for alignments formats
2686 * dependencies to ADC resolutions.
2687 * @rmtoll CFGR RES LL_ADC_GetResolution
2688 * @param ADCx ADC instance
2689 * @retval Returned value can be one of the following values:
2690 * @arg @ref LL_ADC_RESOLUTION_12B
2691 * @arg @ref LL_ADC_RESOLUTION_10B
2692 * @arg @ref LL_ADC_RESOLUTION_8B
2693 * @arg @ref LL_ADC_RESOLUTION_6B
2694 */
LL_ADC_GetResolution(ADC_TypeDef * ADCx)2695 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
2696 {
2697 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
2698 }
2699
2700 /**
2701 * @brief Set ADC conversion data alignment.
2702 * @note Refer to reference manual for alignments formats
2703 * dependencies to ADC resolutions.
2704 * @note On this STM32 serie, setting of this feature is conditioned to
2705 * ADC state:
2706 * ADC must be disabled or enabled without conversion on going
2707 * on either groups regular or injected.
2708 * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment
2709 * @param ADCx ADC instance
2710 * @param DataAlignment This parameter can be one of the following values:
2711 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2712 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2713 * @retval None
2714 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)2715 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
2716 {
2717 MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
2718 }
2719
2720 /**
2721 * @brief Get ADC conversion data alignment.
2722 * @note Refer to reference manual for alignments formats
2723 * dependencies to ADC resolutions.
2724 * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment
2725 * @param ADCx ADC instance
2726 * @retval Returned value can be one of the following values:
2727 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2728 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2729 */
LL_ADC_GetDataAlignment(ADC_TypeDef * ADCx)2730 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
2731 {
2732 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
2733 }
2734
2735 /**
2736 * @brief Set ADC low power mode.
2737 * @note Description of ADC low power modes:
2738 * - ADC low power mode "auto wait": Dynamic low power mode,
2739 * ADC conversions occurrences are limited to the minimum necessary
2740 * in order to reduce power consumption.
2741 * New ADC conversion starts only when the previous
2742 * unitary conversion data (for ADC group regular)
2743 * or previous sequence conversions data (for ADC group injected)
2744 * has been retrieved by user software.
2745 * In the meantime, ADC remains idle: does not performs any
2746 * other conversion.
2747 * This mode allows to automatically adapt the ADC conversions
2748 * triggers to the speed of the software that reads the data.
2749 * Moreover, this avoids risk of overrun for low frequency
2750 * applications.
2751 * How to use this low power mode:
2752 * - Do not use with interruption or DMA since these modes
2753 * have to clear immediately the EOC flag to free the
2754 * IRQ vector sequencer.
2755 * - Do use with polling: 1. Start conversion,
2756 * 2. Later on, when conversion data is needed: poll for end of
2757 * conversion to ensure that conversion is completed and
2758 * retrieve ADC conversion data. This will trig another
2759 * ADC conversion start.
2760 * - ADC low power mode "auto power-off" (feature available on
2761 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2762 * the ADC automatically powers-off after a conversion and
2763 * automatically wakes up when a new conversion is triggered
2764 * (with startup time between trigger and start of sampling).
2765 * This feature can be combined with low power mode "auto wait".
2766 * @note With ADC low power mode "auto wait", the ADC conversion data read
2767 * is corresponding to previous ADC conversion start, independently
2768 * of delay during which ADC was idle.
2769 * Therefore, the ADC conversion data may be outdated: does not
2770 * correspond to the current voltage level on the selected
2771 * ADC channel.
2772 * @note On this STM32 serie, setting of this feature is conditioned to
2773 * ADC state:
2774 * ADC must be disabled or enabled without conversion on going
2775 * on either groups regular or injected.
2776 * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
2777 * @param ADCx ADC instance
2778 * @param LowPowerMode This parameter can be one of the following values:
2779 * @arg @ref LL_ADC_LP_MODE_NONE
2780 * @arg @ref LL_ADC_LP_AUTOWAIT
2781 * @retval None
2782 */
LL_ADC_SetLowPowerMode(ADC_TypeDef * ADCx,uint32_t LowPowerMode)2783 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
2784 {
2785 MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
2786 }
2787
2788 /**
2789 * @brief Get ADC low power mode:
2790 * @note Description of ADC low power modes:
2791 * - ADC low power mode "auto wait": Dynamic low power mode,
2792 * ADC conversions occurrences are limited to the minimum necessary
2793 * in order to reduce power consumption.
2794 * New ADC conversion starts only when the previous
2795 * unitary conversion data (for ADC group regular)
2796 * or previous sequence conversions data (for ADC group injected)
2797 * has been retrieved by user software.
2798 * In the meantime, ADC remains idle: does not performs any
2799 * other conversion.
2800 * This mode allows to automatically adapt the ADC conversions
2801 * triggers to the speed of the software that reads the data.
2802 * Moreover, this avoids risk of overrun for low frequency
2803 * applications.
2804 * How to use this low power mode:
2805 * - Do not use with interruption or DMA since these modes
2806 * have to clear immediately the EOC flag to free the
2807 * IRQ vector sequencer.
2808 * - Do use with polling: 1. Start conversion,
2809 * 2. Later on, when conversion data is needed: poll for end of
2810 * conversion to ensure that conversion is completed and
2811 * retrieve ADC conversion data. This will trig another
2812 * ADC conversion start.
2813 * - ADC low power mode "auto power-off" (feature available on
2814 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2815 * the ADC automatically powers-off after a conversion and
2816 * automatically wakes up when a new conversion is triggered
2817 * (with startup time between trigger and start of sampling).
2818 * This feature can be combined with low power mode "auto wait".
2819 * @note With ADC low power mode "auto wait", the ADC conversion data read
2820 * is corresponding to previous ADC conversion start, independently
2821 * of delay during which ADC was idle.
2822 * Therefore, the ADC conversion data may be outdated: does not
2823 * correspond to the current voltage level on the selected
2824 * ADC channel.
2825 * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
2826 * @param ADCx ADC instance
2827 * @retval Returned value can be one of the following values:
2828 * @arg @ref LL_ADC_LP_MODE_NONE
2829 * @arg @ref LL_ADC_LP_AUTOWAIT
2830 */
LL_ADC_GetLowPowerMode(ADC_TypeDef * ADCx)2831 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
2832 {
2833 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
2834 }
2835
2836 /**
2837 * @brief Set ADC selected offset number 1, 2, 3 or 4.
2838 * @note This function set the 2 items of offset configuration:
2839 * - ADC channel to which the offset programmed will be applied
2840 * (independently of channel mapped on ADC group regular
2841 * or group injected)
2842 * - Offset level (offset to be subtracted from the raw
2843 * converted data).
2844 * @note Caution: Offset format is dependent to ADC resolution:
2845 * offset has to be left-aligned on bit 11, the LSB (right bits)
2846 * are set to 0.
2847 * @note This function enables the offset, by default. It can be forced
2848 * to disable state using function LL_ADC_SetOffsetState().
2849 * @note If a channel is mapped on several offsets numbers, only the offset
2850 * with the lowest value is considered for the subtraction.
2851 * @note On this STM32 serie, setting of this feature is conditioned to
2852 * ADC state:
2853 * ADC must be disabled or enabled without conversion on going
2854 * on either groups regular or injected.
2855 * @note On STM32L4, some fast channels are available: fast analog inputs
2856 * coming from GPIO pads (ADC_IN1..5).
2857 * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
2858 * OFR1 OFFSET1 LL_ADC_SetOffset\n
2859 * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
2860 * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
2861 * OFR2 OFFSET2 LL_ADC_SetOffset\n
2862 * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
2863 * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
2864 * OFR3 OFFSET3 LL_ADC_SetOffset\n
2865 * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
2866 * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
2867 * OFR4 OFFSET4 LL_ADC_SetOffset\n
2868 * OFR4 OFFSET4_EN LL_ADC_SetOffset
2869 * @param ADCx ADC instance
2870 * @param Offsety This parameter can be one of the following values:
2871 * @arg @ref LL_ADC_OFFSET_1
2872 * @arg @ref LL_ADC_OFFSET_2
2873 * @arg @ref LL_ADC_OFFSET_3
2874 * @arg @ref LL_ADC_OFFSET_4
2875 * @param Channel This parameter can be one of the following values:
2876 * @arg @ref LL_ADC_CHANNEL_0
2877 * @arg @ref LL_ADC_CHANNEL_1 (7)
2878 * @arg @ref LL_ADC_CHANNEL_2 (7)
2879 * @arg @ref LL_ADC_CHANNEL_3 (7)
2880 * @arg @ref LL_ADC_CHANNEL_4 (7)
2881 * @arg @ref LL_ADC_CHANNEL_5 (7)
2882 * @arg @ref LL_ADC_CHANNEL_6
2883 * @arg @ref LL_ADC_CHANNEL_7
2884 * @arg @ref LL_ADC_CHANNEL_8
2885 * @arg @ref LL_ADC_CHANNEL_9
2886 * @arg @ref LL_ADC_CHANNEL_10
2887 * @arg @ref LL_ADC_CHANNEL_11
2888 * @arg @ref LL_ADC_CHANNEL_12
2889 * @arg @ref LL_ADC_CHANNEL_13
2890 * @arg @ref LL_ADC_CHANNEL_14
2891 * @arg @ref LL_ADC_CHANNEL_15
2892 * @arg @ref LL_ADC_CHANNEL_16
2893 * @arg @ref LL_ADC_CHANNEL_17
2894 * @arg @ref LL_ADC_CHANNEL_18
2895 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2896 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
2897 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
2898 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
2899 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
2900 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
2901 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
2902 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
2903 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
2904 *
2905 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
2906 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
2907 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
2908 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
2909 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
2910 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
2911 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
2912 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
2913 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
2914 * @retval None
2915 */
LL_ADC_SetOffset(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t Channel,uint32_t OffsetLevel)2916 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
2917 {
2918 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
2919
2920 MODIFY_REG(*preg,
2921 ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
2922 ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
2923 }
2924
2925 /**
2926 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
2927 * Channel to which the offset programmed will be applied
2928 * (independently of channel mapped on ADC group regular
2929 * or group injected)
2930 * @note Usage of the returned channel number:
2931 * - To reinject this channel into another function LL_ADC_xxx:
2932 * the returned channel number is only partly formatted on definition
2933 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2934 * with parts of literals LL_ADC_CHANNEL_x or using
2935 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2936 * Then the selected literal LL_ADC_CHANNEL_x can be used
2937 * as parameter for another function.
2938 * - To get the channel number in decimal format:
2939 * process the returned value with the helper macro
2940 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2941 * @note On STM32L4, some fast channels are available: fast analog inputs
2942 * coming from GPIO pads (ADC_IN1..5).
2943 * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
2944 * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
2945 * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
2946 * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
2947 * @param ADCx ADC instance
2948 * @param Offsety This parameter can be one of the following values:
2949 * @arg @ref LL_ADC_OFFSET_1
2950 * @arg @ref LL_ADC_OFFSET_2
2951 * @arg @ref LL_ADC_OFFSET_3
2952 * @arg @ref LL_ADC_OFFSET_4
2953 * @retval Returned value can be one of the following values:
2954 * @arg @ref LL_ADC_CHANNEL_0
2955 * @arg @ref LL_ADC_CHANNEL_1 (7)
2956 * @arg @ref LL_ADC_CHANNEL_2 (7)
2957 * @arg @ref LL_ADC_CHANNEL_3 (7)
2958 * @arg @ref LL_ADC_CHANNEL_4 (7)
2959 * @arg @ref LL_ADC_CHANNEL_5 (7)
2960 * @arg @ref LL_ADC_CHANNEL_6
2961 * @arg @ref LL_ADC_CHANNEL_7
2962 * @arg @ref LL_ADC_CHANNEL_8
2963 * @arg @ref LL_ADC_CHANNEL_9
2964 * @arg @ref LL_ADC_CHANNEL_10
2965 * @arg @ref LL_ADC_CHANNEL_11
2966 * @arg @ref LL_ADC_CHANNEL_12
2967 * @arg @ref LL_ADC_CHANNEL_13
2968 * @arg @ref LL_ADC_CHANNEL_14
2969 * @arg @ref LL_ADC_CHANNEL_15
2970 * @arg @ref LL_ADC_CHANNEL_16
2971 * @arg @ref LL_ADC_CHANNEL_17
2972 * @arg @ref LL_ADC_CHANNEL_18
2973 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2974 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
2975 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
2976 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
2977 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
2978 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
2979 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
2980 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
2981 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
2982 *
2983 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
2984 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
2985 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
2986 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
2987 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
2988 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
2989 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
2990 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
2991 * (1, 2, 3, 4) For ADC channel read back from ADC register,
2992 * comparison with internal channel parameter to be done
2993 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2994 */
LL_ADC_GetOffsetChannel(ADC_TypeDef * ADCx,uint32_t Offsety)2995 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
2996 {
2997 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
2998
2999 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
3000 }
3001
3002 /**
3003 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3004 * Offset level (offset to be subtracted from the raw
3005 * converted data).
3006 * @note Caution: Offset format is dependent to ADC resolution:
3007 * offset has to be left-aligned on bit 11, the LSB (right bits)
3008 * are set to 0.
3009 * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
3010 * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
3011 * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
3012 * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
3013 * @param ADCx ADC instance
3014 * @param Offsety This parameter can be one of the following values:
3015 * @arg @ref LL_ADC_OFFSET_1
3016 * @arg @ref LL_ADC_OFFSET_2
3017 * @arg @ref LL_ADC_OFFSET_3
3018 * @arg @ref LL_ADC_OFFSET_4
3019 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3020 */
LL_ADC_GetOffsetLevel(ADC_TypeDef * ADCx,uint32_t Offsety)3021 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
3022 {
3023 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3024
3025 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
3026 }
3027
3028 /**
3029 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
3030 * force offset state disable or enable
3031 * without modifying offset channel or offset value.
3032 * @note This function should be needed only in case of offset to be
3033 * enabled-disabled dynamically, and should not be needed in other cases:
3034 * function LL_ADC_SetOffset() automatically enables the offset.
3035 * @note On this STM32 serie, setting of this feature is conditioned to
3036 * ADC state:
3037 * ADC must be disabled or enabled without conversion on going
3038 * on either groups regular or injected.
3039 * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
3040 * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
3041 * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
3042 * OFR4 OFFSET4_EN LL_ADC_SetOffsetState
3043 * @param ADCx ADC instance
3044 * @param Offsety This parameter can be one of the following values:
3045 * @arg @ref LL_ADC_OFFSET_1
3046 * @arg @ref LL_ADC_OFFSET_2
3047 * @arg @ref LL_ADC_OFFSET_3
3048 * @arg @ref LL_ADC_OFFSET_4
3049 * @param OffsetState This parameter can be one of the following values:
3050 * @arg @ref LL_ADC_OFFSET_DISABLE
3051 * @arg @ref LL_ADC_OFFSET_ENABLE
3052 * @retval None
3053 */
LL_ADC_SetOffsetState(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetState)3054 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
3055 {
3056 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3057
3058 MODIFY_REG(*preg,
3059 ADC_OFR1_OFFSET1_EN,
3060 OffsetState);
3061 }
3062
3063 /**
3064 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3065 * offset state disabled or enabled.
3066 * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
3067 * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
3068 * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
3069 * OFR4 OFFSET4_EN LL_ADC_GetOffsetState
3070 * @param ADCx ADC instance
3071 * @param Offsety This parameter can be one of the following values:
3072 * @arg @ref LL_ADC_OFFSET_1
3073 * @arg @ref LL_ADC_OFFSET_2
3074 * @arg @ref LL_ADC_OFFSET_3
3075 * @arg @ref LL_ADC_OFFSET_4
3076 * @retval Returned value can be one of the following values:
3077 * @arg @ref LL_ADC_OFFSET_DISABLE
3078 * @arg @ref LL_ADC_OFFSET_ENABLE
3079 */
LL_ADC_GetOffsetState(ADC_TypeDef * ADCx,uint32_t Offsety)3080 __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
3081 {
3082 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3083
3084 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
3085 }
3086
3087 #if defined(ADC_SMPR1_SMPPLUS)
3088 /**
3089 * @brief Set ADC sampling time common configuration impacting
3090 * settings of sampling time channel wise.
3091 * @note On this STM32 serie, setting of this feature is conditioned to
3092 * ADC state:
3093 * ADC must be disabled or enabled without conversion on going
3094 * on either groups regular or injected.
3095 * @rmtoll SMPR1 SMPPLUS LL_ADC_SetSamplingTimeCommonConfig
3096 * @param ADCx ADC instance
3097 * @param SamplingTimeCommonConfig This parameter can be one of the following values:
3098 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
3099 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
3100 * @retval None
3101 */
LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef * ADCx,uint32_t SamplingTimeCommonConfig)3102 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
3103 {
3104 MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
3105 }
3106
3107 /**
3108 * @brief Get ADC sampling time common configuration impacting
3109 * settings of sampling time channel wise.
3110 * @rmtoll SMPR1 SMPPLUS LL_ADC_GetSamplingTimeCommonConfig
3111 * @param ADCx ADC instance
3112 * @retval Returned value can be one of the following values:
3113 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
3114 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
3115 */
LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef * ADCx)3116 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx)
3117 {
3118 return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS));
3119 }
3120 #endif /* ADC_SMPR1_SMPPLUS */
3121
3122 /**
3123 * @}
3124 */
3125
3126 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
3127 * @{
3128 */
3129
3130 /**
3131 * @brief Set ADC group regular conversion trigger source:
3132 * internal (SW start) or from external peripheral (timer event,
3133 * external interrupt line).
3134 * @note On this STM32 serie, setting trigger source to external trigger
3135 * also set trigger polarity to rising edge
3136 * (default setting for compatibility with some ADC on other
3137 * STM32 families having this setting set by HW default value).
3138 * In case of need to modify trigger edge, use
3139 * function @ref LL_ADC_REG_SetTriggerEdge().
3140 * @note Availability of parameters of trigger sources from timer
3141 * depends on timers availability on the selected device.
3142 * @note On this STM32 serie, setting of this feature is conditioned to
3143 * ADC state:
3144 * ADC must be disabled or enabled without conversion on going
3145 * on group regular.
3146 * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
3147 * CFGR EXTEN LL_ADC_REG_SetTriggerSource
3148 * @param ADCx ADC instance
3149 * @param TriggerSource This parameter can be one of the following values:
3150 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3151 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3152 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3153 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
3154 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
3155 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3156 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3157 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3158 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3159 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
3160 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3161 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
3162 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3163 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3164 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3165 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3166 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3167 * @retval None
3168 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)3169 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3170 {
3171 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
3172 }
3173
3174 /**
3175 * @brief Get ADC group regular conversion trigger source:
3176 * internal (SW start) or from external peripheral (timer event,
3177 * external interrupt line).
3178 * @note To determine whether group regular trigger source is
3179 * internal (SW start) or external, without detail
3180 * of which peripheral is selected as external trigger,
3181 * (equivalent to
3182 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
3183 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
3184 * @note Availability of parameters of trigger sources from timer
3185 * depends on timers availability on the selected device.
3186 * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
3187 * CFGR EXTEN LL_ADC_REG_GetTriggerSource
3188 * @param ADCx ADC instance
3189 * @retval Returned value can be one of the following values:
3190 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3191 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3192 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3193 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
3194 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
3195 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3196 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3197 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3198 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3199 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
3200 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3201 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
3202 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3203 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3204 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3205 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3206 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3207 */
LL_ADC_REG_GetTriggerSource(ADC_TypeDef * ADCx)3208 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
3209 {
3210 register __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
3211
3212 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3213 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
3214 register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3215
3216 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
3217 /* to match with triggers literals definition. */
3218 return ((TriggerSource
3219 & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
3220 | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
3221 );
3222 }
3223
3224 /**
3225 * @brief Get ADC group regular conversion trigger source internal (SW start)
3226 * or external.
3227 * @note In case of group regular trigger source set to external trigger,
3228 * to determine which peripheral is selected as external trigger,
3229 * use function @ref LL_ADC_REG_GetTriggerSource().
3230 * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
3231 * @param ADCx ADC instance
3232 * @retval Value "0" if trigger source external trigger
3233 * Value "1" if trigger source SW start.
3234 */
LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)3235 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
3236 {
3237 return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
3238 }
3239
3240 /**
3241 * @brief Set ADC group regular conversion trigger polarity.
3242 * @note Applicable only for trigger source set to external trigger.
3243 * @note On this STM32 serie, setting of this feature is conditioned to
3244 * ADC state:
3245 * ADC must be disabled or enabled without conversion on going
3246 * on group regular.
3247 * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
3248 * @param ADCx ADC instance
3249 * @param ExternalTriggerEdge This parameter can be one of the following values:
3250 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3251 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3252 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3253 * @retval None
3254 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)3255 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3256 {
3257 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
3258 }
3259
3260 /**
3261 * @brief Get ADC group regular conversion trigger polarity.
3262 * @note Applicable only for trigger source set to external trigger.
3263 * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
3264 * @param ADCx ADC instance
3265 * @retval Returned value can be one of the following values:
3266 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3267 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3268 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3269 */
LL_ADC_REG_GetTriggerEdge(ADC_TypeDef * ADCx)3270 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
3271 {
3272 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
3273 }
3274
3275 /**
3276 * @brief Set ADC group regular sequencer length and scan direction.
3277 * @note Description of ADC group regular sequencer features:
3278 * - For devices with sequencer fully configurable
3279 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3280 * sequencer length and each rank affectation to a channel
3281 * are configurable.
3282 * This function performs configuration of:
3283 * - Sequence length: Number of ranks in the scan sequence.
3284 * - Sequence direction: Unless specified in parameters, sequencer
3285 * scan direction is forward (from rank 1 to rank n).
3286 * Sequencer ranks are selected using
3287 * function "LL_ADC_REG_SetSequencerRanks()".
3288 * - For devices with sequencer not fully configurable
3289 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3290 * sequencer length and each rank affectation to a channel
3291 * are defined by channel number.
3292 * This function performs configuration of:
3293 * - Sequence length: Number of ranks in the scan sequence is
3294 * defined by number of channels set in the sequence,
3295 * rank of each channel is fixed by channel HW number.
3296 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3297 * - Sequence direction: Unless specified in parameters, sequencer
3298 * scan direction is forward (from lowest channel number to
3299 * highest channel number).
3300 * Sequencer ranks are selected using
3301 * function "LL_ADC_REG_SetSequencerChannels()".
3302 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3303 * ADC conversion on only 1 channel.
3304 * @note On this STM32 serie, setting of this feature is conditioned to
3305 * ADC state:
3306 * ADC must be disabled or enabled without conversion on going
3307 * on group regular.
3308 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
3309 * @param ADCx ADC instance
3310 * @param SequencerNbRanks This parameter can be one of the following values:
3311 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3312 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3313 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3314 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3315 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3316 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3317 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3318 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3319 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
3320 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
3321 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
3322 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
3323 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
3324 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
3325 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
3326 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
3327 * @retval None
3328 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)3329 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
3330 {
3331 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
3332 }
3333
3334 /**
3335 * @brief Get ADC group regular sequencer length and scan direction.
3336 * @note Description of ADC group regular sequencer features:
3337 * - For devices with sequencer fully configurable
3338 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3339 * sequencer length and each rank affectation to a channel
3340 * are configurable.
3341 * This function retrieves:
3342 * - Sequence length: Number of ranks in the scan sequence.
3343 * - Sequence direction: Unless specified in parameters, sequencer
3344 * scan direction is forward (from rank 1 to rank n).
3345 * Sequencer ranks are selected using
3346 * function "LL_ADC_REG_SetSequencerRanks()".
3347 * - For devices with sequencer not fully configurable
3348 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3349 * sequencer length and each rank affectation to a channel
3350 * are defined by channel number.
3351 * This function retrieves:
3352 * - Sequence length: Number of ranks in the scan sequence is
3353 * defined by number of channels set in the sequence,
3354 * rank of each channel is fixed by channel HW number.
3355 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3356 * - Sequence direction: Unless specified in parameters, sequencer
3357 * scan direction is forward (from lowest channel number to
3358 * highest channel number).
3359 * Sequencer ranks are selected using
3360 * function "LL_ADC_REG_SetSequencerChannels()".
3361 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3362 * ADC conversion on only 1 channel.
3363 * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
3364 * @param ADCx ADC instance
3365 * @retval Returned value can be one of the following values:
3366 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3367 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3368 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3369 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3370 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3371 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3372 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3373 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3374 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
3375 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
3376 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
3377 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
3378 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
3379 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
3380 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
3381 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
3382 */
LL_ADC_REG_GetSequencerLength(ADC_TypeDef * ADCx)3383 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
3384 {
3385 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
3386 }
3387
3388 /**
3389 * @brief Set ADC group regular sequencer discontinuous mode:
3390 * sequence subdivided and scan conversions interrupted every selected
3391 * number of ranks.
3392 * @note It is not possible to enable both ADC group regular
3393 * continuous mode and sequencer discontinuous mode.
3394 * @note It is not possible to enable both ADC auto-injected mode
3395 * and ADC group regular sequencer discontinuous mode.
3396 * @note On this STM32 serie, setting of this feature is conditioned to
3397 * ADC state:
3398 * ADC must be disabled or enabled without conversion on going
3399 * on group regular.
3400 * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
3401 * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
3402 * @param ADCx ADC instance
3403 * @param SeqDiscont This parameter can be one of the following values:
3404 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3405 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3406 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
3407 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
3408 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
3409 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
3410 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
3411 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
3412 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
3413 * @retval None
3414 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)3415 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
3416 {
3417 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
3418 }
3419
3420 /**
3421 * @brief Get ADC group regular sequencer discontinuous mode:
3422 * sequence subdivided and scan conversions interrupted every selected
3423 * number of ranks.
3424 * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
3425 * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
3426 * @param ADCx ADC instance
3427 * @retval Returned value can be one of the following values:
3428 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3429 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3430 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
3431 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
3432 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
3433 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
3434 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
3435 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
3436 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
3437 */
LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef * ADCx)3438 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
3439 {
3440 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
3441 }
3442
3443 /**
3444 * @brief Set ADC group regular sequence: channel on the selected
3445 * scan sequence rank.
3446 * @note This function performs configuration of:
3447 * - Channels ordering into each rank of scan sequence:
3448 * whatever channel can be placed into whatever rank.
3449 * @note On this STM32 serie, ADC group regular sequencer is
3450 * fully configurable: sequencer length and each rank
3451 * affectation to a channel are configurable.
3452 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3453 * @note Depending on devices and packages, some channels may not be available.
3454 * Refer to device datasheet for channels availability.
3455 * @note On this STM32 serie, to measure internal channels (VrefInt,
3456 * TempSensor, ...), measurement paths to internal channels must be
3457 * enabled separately.
3458 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3459 * @note On this STM32 serie, setting of this feature is conditioned to
3460 * ADC state:
3461 * ADC must be disabled or enabled without conversion on going
3462 * on group regular.
3463 * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
3464 * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
3465 * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
3466 * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
3467 * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
3468 * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
3469 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
3470 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
3471 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
3472 * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
3473 * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
3474 * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
3475 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
3476 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
3477 * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
3478 * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
3479 * @param ADCx ADC instance
3480 * @param Rank This parameter can be one of the following values:
3481 * @arg @ref LL_ADC_REG_RANK_1
3482 * @arg @ref LL_ADC_REG_RANK_2
3483 * @arg @ref LL_ADC_REG_RANK_3
3484 * @arg @ref LL_ADC_REG_RANK_4
3485 * @arg @ref LL_ADC_REG_RANK_5
3486 * @arg @ref LL_ADC_REG_RANK_6
3487 * @arg @ref LL_ADC_REG_RANK_7
3488 * @arg @ref LL_ADC_REG_RANK_8
3489 * @arg @ref LL_ADC_REG_RANK_9
3490 * @arg @ref LL_ADC_REG_RANK_10
3491 * @arg @ref LL_ADC_REG_RANK_11
3492 * @arg @ref LL_ADC_REG_RANK_12
3493 * @arg @ref LL_ADC_REG_RANK_13
3494 * @arg @ref LL_ADC_REG_RANK_14
3495 * @arg @ref LL_ADC_REG_RANK_15
3496 * @arg @ref LL_ADC_REG_RANK_16
3497 * @param Channel This parameter can be one of the following values:
3498 * @arg @ref LL_ADC_CHANNEL_0
3499 * @arg @ref LL_ADC_CHANNEL_1 (7)
3500 * @arg @ref LL_ADC_CHANNEL_2 (7)
3501 * @arg @ref LL_ADC_CHANNEL_3 (7)
3502 * @arg @ref LL_ADC_CHANNEL_4 (7)
3503 * @arg @ref LL_ADC_CHANNEL_5 (7)
3504 * @arg @ref LL_ADC_CHANNEL_6
3505 * @arg @ref LL_ADC_CHANNEL_7
3506 * @arg @ref LL_ADC_CHANNEL_8
3507 * @arg @ref LL_ADC_CHANNEL_9
3508 * @arg @ref LL_ADC_CHANNEL_10
3509 * @arg @ref LL_ADC_CHANNEL_11
3510 * @arg @ref LL_ADC_CHANNEL_12
3511 * @arg @ref LL_ADC_CHANNEL_13
3512 * @arg @ref LL_ADC_CHANNEL_14
3513 * @arg @ref LL_ADC_CHANNEL_15
3514 * @arg @ref LL_ADC_CHANNEL_16
3515 * @arg @ref LL_ADC_CHANNEL_17
3516 * @arg @ref LL_ADC_CHANNEL_18
3517 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3518 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
3519 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
3520 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
3521 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
3522 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
3523 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
3524 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
3525 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
3526 *
3527 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
3528 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
3529 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
3530 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
3531 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
3532 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
3533 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
3534 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
3535 * @retval None
3536 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)3537 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
3538 {
3539 /* Set bits with content of parameter "Channel" with bits position */
3540 /* in register and register position depending on parameter "Rank". */
3541 /* Parameters "Rank" and "Channel" are used with masks because containing */
3542 /* other bits reserved for other purpose. */
3543 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
3544
3545 MODIFY_REG(*preg,
3546 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
3547 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
3548 }
3549
3550 /**
3551 * @brief Get ADC group regular sequence: channel on the selected
3552 * scan sequence rank.
3553 * @note On this STM32 serie, ADC group regular sequencer is
3554 * fully configurable: sequencer length and each rank
3555 * affectation to a channel are configurable.
3556 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3557 * @note Depending on devices and packages, some channels may not be available.
3558 * Refer to device datasheet for channels availability.
3559 * @note Usage of the returned channel number:
3560 * - To reinject this channel into another function LL_ADC_xxx:
3561 * the returned channel number is only partly formatted on definition
3562 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3563 * with parts of literals LL_ADC_CHANNEL_x or using
3564 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3565 * Then the selected literal LL_ADC_CHANNEL_x can be used
3566 * as parameter for another function.
3567 * - To get the channel number in decimal format:
3568 * process the returned value with the helper macro
3569 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3570 * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
3571 * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
3572 * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
3573 * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
3574 * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
3575 * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
3576 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
3577 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
3578 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
3579 * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
3580 * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
3581 * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
3582 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
3583 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
3584 * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
3585 * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
3586 * @param ADCx ADC instance
3587 * @param Rank This parameter can be one of the following values:
3588 * @arg @ref LL_ADC_REG_RANK_1
3589 * @arg @ref LL_ADC_REG_RANK_2
3590 * @arg @ref LL_ADC_REG_RANK_3
3591 * @arg @ref LL_ADC_REG_RANK_4
3592 * @arg @ref LL_ADC_REG_RANK_5
3593 * @arg @ref LL_ADC_REG_RANK_6
3594 * @arg @ref LL_ADC_REG_RANK_7
3595 * @arg @ref LL_ADC_REG_RANK_8
3596 * @arg @ref LL_ADC_REG_RANK_9
3597 * @arg @ref LL_ADC_REG_RANK_10
3598 * @arg @ref LL_ADC_REG_RANK_11
3599 * @arg @ref LL_ADC_REG_RANK_12
3600 * @arg @ref LL_ADC_REG_RANK_13
3601 * @arg @ref LL_ADC_REG_RANK_14
3602 * @arg @ref LL_ADC_REG_RANK_15
3603 * @arg @ref LL_ADC_REG_RANK_16
3604 * @retval Returned value can be one of the following values:
3605 * @arg @ref LL_ADC_CHANNEL_0
3606 * @arg @ref LL_ADC_CHANNEL_1 (7)
3607 * @arg @ref LL_ADC_CHANNEL_2 (7)
3608 * @arg @ref LL_ADC_CHANNEL_3 (7)
3609 * @arg @ref LL_ADC_CHANNEL_4 (7)
3610 * @arg @ref LL_ADC_CHANNEL_5 (7)
3611 * @arg @ref LL_ADC_CHANNEL_6
3612 * @arg @ref LL_ADC_CHANNEL_7
3613 * @arg @ref LL_ADC_CHANNEL_8
3614 * @arg @ref LL_ADC_CHANNEL_9
3615 * @arg @ref LL_ADC_CHANNEL_10
3616 * @arg @ref LL_ADC_CHANNEL_11
3617 * @arg @ref LL_ADC_CHANNEL_12
3618 * @arg @ref LL_ADC_CHANNEL_13
3619 * @arg @ref LL_ADC_CHANNEL_14
3620 * @arg @ref LL_ADC_CHANNEL_15
3621 * @arg @ref LL_ADC_CHANNEL_16
3622 * @arg @ref LL_ADC_CHANNEL_17
3623 * @arg @ref LL_ADC_CHANNEL_18
3624 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3625 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
3626 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
3627 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
3628 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
3629 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
3630 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
3631 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
3632 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
3633 *
3634 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
3635 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
3636 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
3637 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
3638 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
3639 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
3640 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
3641 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
3642 * (1, 2, 3, 4) For ADC channel read back from ADC register,
3643 * comparison with internal channel parameter to be done
3644 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3645 */
LL_ADC_REG_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)3646 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
3647 {
3648 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
3649
3650 return (uint32_t)((READ_BIT(*preg,
3651 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
3652 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
3653 );
3654 }
3655
3656 /**
3657 * @brief Set ADC continuous conversion mode on ADC group regular.
3658 * @note Description of ADC continuous conversion mode:
3659 * - single mode: one conversion per trigger
3660 * - continuous mode: after the first trigger, following
3661 * conversions launched successively automatically.
3662 * @note It is not possible to enable both ADC group regular
3663 * continuous mode and sequencer discontinuous mode.
3664 * @note On this STM32 serie, setting of this feature is conditioned to
3665 * ADC state:
3666 * ADC must be disabled or enabled without conversion on going
3667 * on group regular.
3668 * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
3669 * @param ADCx ADC instance
3670 * @param Continuous This parameter can be one of the following values:
3671 * @arg @ref LL_ADC_REG_CONV_SINGLE
3672 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3673 * @retval None
3674 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)3675 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
3676 {
3677 MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
3678 }
3679
3680 /**
3681 * @brief Get ADC continuous conversion mode on ADC group regular.
3682 * @note Description of ADC continuous conversion mode:
3683 * - single mode: one conversion per trigger
3684 * - continuous mode: after the first trigger, following
3685 * conversions launched successively automatically.
3686 * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
3687 * @param ADCx ADC instance
3688 * @retval Returned value can be one of the following values:
3689 * @arg @ref LL_ADC_REG_CONV_SINGLE
3690 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3691 */
LL_ADC_REG_GetContinuousMode(ADC_TypeDef * ADCx)3692 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
3693 {
3694 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
3695 }
3696
3697 /**
3698 * @brief Set ADC group regular conversion data transfer: no transfer or
3699 * transfer by DMA, and DMA requests mode.
3700 * @note If transfer by DMA selected, specifies the DMA requests
3701 * mode:
3702 * - Limited mode (One shot mode): DMA transfer requests are stopped
3703 * when number of DMA data transfers (number of
3704 * ADC conversions) is reached.
3705 * This ADC mode is intended to be used with DMA mode non-circular.
3706 * - Unlimited mode: DMA transfer requests are unlimited,
3707 * whatever number of DMA data transfers (number of
3708 * ADC conversions).
3709 * This ADC mode is intended to be used with DMA mode circular.
3710 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3711 * mode non-circular:
3712 * when DMA transfers size will be reached, DMA will stop transfers of
3713 * ADC conversions data ADC will raise an overrun error
3714 * (overrun flag and interruption if enabled).
3715 * @note For devices with several ADC instances: ADC multimode DMA
3716 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
3717 * @note To configure DMA source address (peripheral address),
3718 * use function @ref LL_ADC_DMA_GetRegAddr().
3719 * @note On this STM32 serie, setting of this feature is conditioned to
3720 * ADC state:
3721 * ADC must be disabled or enabled without conversion on going
3722 * on either groups regular or injected.
3723 * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
3724 * CFGR DMACFG LL_ADC_REG_SetDMATransfer
3725 * @param ADCx ADC instance
3726 * @param DMATransfer This parameter can be one of the following values:
3727 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3728 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3729 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3730 * @retval None
3731 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)3732 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
3733 {
3734 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
3735 }
3736
3737 /**
3738 * @brief Get ADC group regular conversion data transfer: no transfer or
3739 * transfer by DMA, and DMA requests mode.
3740 * @note If transfer by DMA selected, specifies the DMA requests
3741 * mode:
3742 * - Limited mode (One shot mode): DMA transfer requests are stopped
3743 * when number of DMA data transfers (number of
3744 * ADC conversions) is reached.
3745 * This ADC mode is intended to be used with DMA mode non-circular.
3746 * - Unlimited mode: DMA transfer requests are unlimited,
3747 * whatever number of DMA data transfers (number of
3748 * ADC conversions).
3749 * This ADC mode is intended to be used with DMA mode circular.
3750 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3751 * mode non-circular:
3752 * when DMA transfers size will be reached, DMA will stop transfers of
3753 * ADC conversions data ADC will raise an overrun error
3754 * (overrun flag and interruption if enabled).
3755 * @note For devices with several ADC instances: ADC multimode DMA
3756 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
3757 * @note To configure DMA source address (peripheral address),
3758 * use function @ref LL_ADC_DMA_GetRegAddr().
3759 * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
3760 * CFGR DMACFG LL_ADC_REG_GetDMATransfer
3761 * @param ADCx ADC instance
3762 * @retval Returned value can be one of the following values:
3763 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3764 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3765 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3766 */
LL_ADC_REG_GetDMATransfer(ADC_TypeDef * ADCx)3767 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
3768 {
3769 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
3770 }
3771
3772 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
3773 /**
3774 * @brief Set ADC group regular conversion data transfer to DFSDM.
3775 * @note DFSDM transfer cannot be used if DMA transfer is enabled.
3776 * @note To configure DFSDM source address (peripheral address),
3777 * use the same function as for DMA transfer:
3778 * function @ref LL_ADC_DMA_GetRegAddr().
3779 * @note On this STM32 serie, setting of this feature is conditioned to
3780 * ADC state:
3781 * ADC must be disabled or enabled without conversion on going
3782 * on either groups regular or injected.
3783 * @rmtoll CFGR DFSDMCFG LL_ADC_REG_GetDFSDMTransfer
3784 * @param ADCx ADC instance
3785 * @param DFSDMTransfer This parameter can be one of the following values:
3786 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_NONE
3787 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_ENABLE
3788 * @retval None
3789 */
LL_ADC_REG_SetDFSDMTransfer(ADC_TypeDef * ADCx,uint32_t DFSDMTransfer)3790 __STATIC_INLINE void LL_ADC_REG_SetDFSDMTransfer(ADC_TypeDef *ADCx, uint32_t DFSDMTransfer)
3791 {
3792 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DFSDMCFG, DFSDMTransfer);
3793 }
3794
3795 /**
3796 * @brief Get ADC group regular conversion data transfer to DFSDM.
3797 * @rmtoll CFGR DFSDMCFG LL_ADC_REG_GetDFSDMTransfer
3798 * @param ADCx ADC instance
3799 * @retval Returned value can be one of the following values:
3800 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_NONE
3801 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_ENABLE
3802 */
LL_ADC_REG_GetDFSDMTransfer(ADC_TypeDef * ADCx)3803 __STATIC_INLINE uint32_t LL_ADC_REG_GetDFSDMTransfer(ADC_TypeDef *ADCx)
3804 {
3805 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DFSDMCFG));
3806 }
3807 #endif
3808
3809 /**
3810 * @brief Set ADC group regular behavior in case of overrun:
3811 * data preserved or overwritten.
3812 * @note Compatibility with devices without feature overrun:
3813 * other devices without this feature have a behavior
3814 * equivalent to data overwritten.
3815 * The default setting of overrun is data preserved.
3816 * Therefore, for compatibility with all devices, parameter
3817 * overrun should be set to data overwritten.
3818 * @note On this STM32 serie, setting of this feature is conditioned to
3819 * ADC state:
3820 * ADC must be disabled or enabled without conversion on going
3821 * on group regular.
3822 * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
3823 * @param ADCx ADC instance
3824 * @param Overrun This parameter can be one of the following values:
3825 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3826 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3827 * @retval None
3828 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)3829 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
3830 {
3831 MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
3832 }
3833
3834 /**
3835 * @brief Get ADC group regular behavior in case of overrun:
3836 * data preserved or overwritten.
3837 * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
3838 * @param ADCx ADC instance
3839 * @retval Returned value can be one of the following values:
3840 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3841 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3842 */
LL_ADC_REG_GetOverrun(ADC_TypeDef * ADCx)3843 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
3844 {
3845 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
3846 }
3847
3848 /**
3849 * @}
3850 */
3851
3852 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
3853 * @{
3854 */
3855
3856 /**
3857 * @brief Set ADC group injected conversion trigger source:
3858 * internal (SW start) or from external peripheral (timer event,
3859 * external interrupt line).
3860 * @note On this STM32 serie, setting trigger source to external trigger
3861 * also set trigger polarity to rising edge
3862 * (default setting for compatibility with some ADC on other
3863 * STM32 families having this setting set by HW default value).
3864 * In case of need to modify trigger edge, use
3865 * function @ref LL_ADC_INJ_SetTriggerEdge().
3866 * @note Availability of parameters of trigger sources from timer
3867 * depends on timers availability on the selected device.
3868 * @note On this STM32 serie, setting of this feature is conditioned to
3869 * ADC state:
3870 * ADC must not be disabled. Can be enabled with or without conversion
3871 * on going on either groups regular or injected.
3872 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
3873 * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
3874 * @param ADCx ADC instance
3875 * @param TriggerSource This parameter can be one of the following values:
3876 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
3877 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
3878 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
3879 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
3880 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
3881 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
3882 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
3883 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
3884 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
3885 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
3886 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
3887 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
3888 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
3889 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
3890 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
3891 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
3892 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
3893 * @retval None
3894 */
LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)3895 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3896 {
3897 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
3898 }
3899
3900 /**
3901 * @brief Get ADC group injected conversion trigger source:
3902 * internal (SW start) or from external peripheral (timer event,
3903 * external interrupt line).
3904 * @note To determine whether group injected trigger source is
3905 * internal (SW start) or external, without detail
3906 * of which peripheral is selected as external trigger,
3907 * (equivalent to
3908 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
3909 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
3910 * @note Availability of parameters of trigger sources from timer
3911 * depends on timers availability on the selected device.
3912 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
3913 * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
3914 * @param ADCx ADC instance
3915 * @retval Returned value can be one of the following values:
3916 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
3917 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
3918 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
3919 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
3920 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
3921 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
3922 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
3923 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
3924 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
3925 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
3926 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
3927 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
3928 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
3929 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
3930 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
3931 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
3932 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
3933 */
LL_ADC_INJ_GetTriggerSource(ADC_TypeDef * ADCx)3934 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
3935 {
3936 register __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
3937
3938 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3939 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
3940 register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3941
3942 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
3943 /* to match with triggers literals definition. */
3944 return ((TriggerSource
3945 & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
3946 | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
3947 );
3948 }
3949
3950 /**
3951 * @brief Get ADC group injected conversion trigger source internal (SW start)
3952 or external
3953 * @note In case of group injected trigger source set to external trigger,
3954 * to determine which peripheral is selected as external trigger,
3955 * use function @ref LL_ADC_INJ_GetTriggerSource.
3956 * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
3957 * @param ADCx ADC instance
3958 * @retval Value "0" if trigger source external trigger
3959 * Value "1" if trigger source SW start.
3960 */
LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)3961 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
3962 {
3963 return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
3964 }
3965
3966 /**
3967 * @brief Set ADC group injected conversion trigger polarity.
3968 * Applicable only for trigger source set to external trigger.
3969 * @note On this STM32 serie, setting of this feature is conditioned to
3970 * ADC state:
3971 * ADC must not be disabled. Can be enabled with or without conversion
3972 * on going on either groups regular or injected.
3973 * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
3974 * @param ADCx ADC instance
3975 * @param ExternalTriggerEdge This parameter can be one of the following values:
3976 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
3977 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
3978 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
3979 * @retval None
3980 */
LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)3981 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3982 {
3983 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
3984 }
3985
3986 /**
3987 * @brief Get ADC group injected conversion trigger polarity.
3988 * Applicable only for trigger source set to external trigger.
3989 * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
3990 * @param ADCx ADC instance
3991 * @retval Returned value can be one of the following values:
3992 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
3993 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
3994 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
3995 */
LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef * ADCx)3996 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
3997 {
3998 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
3999 }
4000
4001 /**
4002 * @brief Set ADC group injected sequencer length and scan direction.
4003 * @note This function performs configuration of:
4004 * - Sequence length: Number of ranks in the scan sequence.
4005 * - Sequence direction: Unless specified in parameters, sequencer
4006 * scan direction is forward (from rank 1 to rank n).
4007 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4008 * ADC conversion on only 1 channel.
4009 * @note On this STM32 serie, setting of this feature is conditioned to
4010 * ADC state:
4011 * ADC must not be disabled. Can be enabled with or without conversion
4012 * on going on either groups regular or injected.
4013 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
4014 * @param ADCx ADC instance
4015 * @param SequencerNbRanks This parameter can be one of the following values:
4016 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4017 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4018 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4019 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4020 * @retval None
4021 */
LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)4022 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4023 {
4024 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
4025 }
4026
4027 /**
4028 * @brief Get ADC group injected sequencer length and scan direction.
4029 * @note This function retrieves:
4030 * - Sequence length: Number of ranks in the scan sequence.
4031 * - Sequence direction: Unless specified in parameters, sequencer
4032 * scan direction is forward (from rank 1 to rank n).
4033 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4034 * ADC conversion on only 1 channel.
4035 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
4036 * @param ADCx ADC instance
4037 * @retval Returned value can be one of the following values:
4038 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4039 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4040 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4041 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4042 */
LL_ADC_INJ_GetSequencerLength(ADC_TypeDef * ADCx)4043 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
4044 {
4045 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
4046 }
4047
4048 /**
4049 * @brief Set ADC group injected sequencer discontinuous mode:
4050 * sequence subdivided and scan conversions interrupted every selected
4051 * number of ranks.
4052 * @note It is not possible to enable both ADC group injected
4053 * auto-injected mode and sequencer discontinuous mode.
4054 * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
4055 * @param ADCx ADC instance
4056 * @param SeqDiscont This parameter can be one of the following values:
4057 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4058 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4059 * @retval None
4060 */
LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)4061 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4062 {
4063 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
4064 }
4065
4066 /**
4067 * @brief Get ADC group injected sequencer discontinuous mode:
4068 * sequence subdivided and scan conversions interrupted every selected
4069 * number of ranks.
4070 * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
4071 * @param ADCx ADC instance
4072 * @retval Returned value can be one of the following values:
4073 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4074 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4075 */
LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef * ADCx)4076 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
4077 {
4078 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
4079 }
4080
4081 /**
4082 * @brief Set ADC group injected sequence: channel on the selected
4083 * sequence rank.
4084 * @note Depending on devices and packages, some channels may not be available.
4085 * Refer to device datasheet for channels availability.
4086 * @note On this STM32 serie, to measure internal channels (VrefInt,
4087 * TempSensor, ...), measurement paths to internal channels must be
4088 * enabled separately.
4089 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4090 * @note On STM32L4, some fast channels are available: fast analog inputs
4091 * coming from GPIO pads (ADC_IN1..5).
4092 * @note On this STM32 serie, setting of this feature is conditioned to
4093 * ADC state:
4094 * ADC must not be disabled. Can be enabled with or without conversion
4095 * on going on either groups regular or injected.
4096 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
4097 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
4098 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
4099 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
4100 * @param ADCx ADC instance
4101 * @param Rank This parameter can be one of the following values:
4102 * @arg @ref LL_ADC_INJ_RANK_1
4103 * @arg @ref LL_ADC_INJ_RANK_2
4104 * @arg @ref LL_ADC_INJ_RANK_3
4105 * @arg @ref LL_ADC_INJ_RANK_4
4106 * @param Channel This parameter can be one of the following values:
4107 * @arg @ref LL_ADC_CHANNEL_0
4108 * @arg @ref LL_ADC_CHANNEL_1 (7)
4109 * @arg @ref LL_ADC_CHANNEL_2 (7)
4110 * @arg @ref LL_ADC_CHANNEL_3 (7)
4111 * @arg @ref LL_ADC_CHANNEL_4 (7)
4112 * @arg @ref LL_ADC_CHANNEL_5 (7)
4113 * @arg @ref LL_ADC_CHANNEL_6
4114 * @arg @ref LL_ADC_CHANNEL_7
4115 * @arg @ref LL_ADC_CHANNEL_8
4116 * @arg @ref LL_ADC_CHANNEL_9
4117 * @arg @ref LL_ADC_CHANNEL_10
4118 * @arg @ref LL_ADC_CHANNEL_11
4119 * @arg @ref LL_ADC_CHANNEL_12
4120 * @arg @ref LL_ADC_CHANNEL_13
4121 * @arg @ref LL_ADC_CHANNEL_14
4122 * @arg @ref LL_ADC_CHANNEL_15
4123 * @arg @ref LL_ADC_CHANNEL_16
4124 * @arg @ref LL_ADC_CHANNEL_17
4125 * @arg @ref LL_ADC_CHANNEL_18
4126 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4127 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4128 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4129 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4130 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4131 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4132 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4133 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4134 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4135 *
4136 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4137 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4138 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4139 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4140 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4141 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4142 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4143 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4144 * @retval None
4145 */
LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)4146 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4147 {
4148 /* Set bits with content of parameter "Channel" with bits position */
4149 /* in register depending on parameter "Rank". */
4150 /* Parameters "Rank" and "Channel" are used with masks because containing */
4151 /* other bits reserved for other purpose. */
4152 MODIFY_REG(ADCx->JSQR,
4153 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
4154 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
4155 }
4156
4157 /**
4158 * @brief Get ADC group injected sequence: channel on the selected
4159 * sequence rank.
4160 * @note Depending on devices and packages, some channels may not be available.
4161 * Refer to device datasheet for channels availability.
4162 * @note Usage of the returned channel number:
4163 * - To reinject this channel into another function LL_ADC_xxx:
4164 * the returned channel number is only partly formatted on definition
4165 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4166 * with parts of literals LL_ADC_CHANNEL_x or using
4167 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4168 * Then the selected literal LL_ADC_CHANNEL_x can be used
4169 * as parameter for another function.
4170 * - To get the channel number in decimal format:
4171 * process the returned value with the helper macro
4172 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4173 * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
4174 * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
4175 * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
4176 * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
4177 * @param ADCx ADC instance
4178 * @param Rank This parameter can be one of the following values:
4179 * @arg @ref LL_ADC_INJ_RANK_1
4180 * @arg @ref LL_ADC_INJ_RANK_2
4181 * @arg @ref LL_ADC_INJ_RANK_3
4182 * @arg @ref LL_ADC_INJ_RANK_4
4183 * @retval Returned value can be one of the following values:
4184 * @arg @ref LL_ADC_CHANNEL_0
4185 * @arg @ref LL_ADC_CHANNEL_1 (7)
4186 * @arg @ref LL_ADC_CHANNEL_2 (7)
4187 * @arg @ref LL_ADC_CHANNEL_3 (7)
4188 * @arg @ref LL_ADC_CHANNEL_4 (7)
4189 * @arg @ref LL_ADC_CHANNEL_5 (7)
4190 * @arg @ref LL_ADC_CHANNEL_6
4191 * @arg @ref LL_ADC_CHANNEL_7
4192 * @arg @ref LL_ADC_CHANNEL_8
4193 * @arg @ref LL_ADC_CHANNEL_9
4194 * @arg @ref LL_ADC_CHANNEL_10
4195 * @arg @ref LL_ADC_CHANNEL_11
4196 * @arg @ref LL_ADC_CHANNEL_12
4197 * @arg @ref LL_ADC_CHANNEL_13
4198 * @arg @ref LL_ADC_CHANNEL_14
4199 * @arg @ref LL_ADC_CHANNEL_15
4200 * @arg @ref LL_ADC_CHANNEL_16
4201 * @arg @ref LL_ADC_CHANNEL_17
4202 * @arg @ref LL_ADC_CHANNEL_18
4203 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4204 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4205 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4206 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4207 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4208 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4209 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4210 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4211 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4212 *
4213 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4214 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4215 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4216 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4217 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4218 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4219 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4220 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
4221 * (1, 2, 3, 4) For ADC channel read back from ADC register,
4222 * comparison with internal channel parameter to be done
4223 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4224 */
LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)4225 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
4226 {
4227 return (uint32_t)((READ_BIT(ADCx->JSQR,
4228 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
4229 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4230 );
4231 }
4232
4233 /**
4234 * @brief Set ADC group injected conversion trigger:
4235 * independent or from ADC group regular.
4236 * @note This mode can be used to extend number of data registers
4237 * updated after one ADC conversion trigger and with data
4238 * permanently kept (not erased by successive conversions of scan of
4239 * ADC sequencer ranks), up to 5 data registers:
4240 * 1 data register on ADC group regular, 4 data registers
4241 * on ADC group injected.
4242 * @note If ADC group injected injected trigger source is set to an
4243 * external trigger, this feature must be must be set to
4244 * independent trigger.
4245 * ADC group injected automatic trigger is compliant only with
4246 * group injected trigger source set to SW start, without any
4247 * further action on ADC group injected conversion start or stop:
4248 * in this case, ADC group injected is controlled only
4249 * from ADC group regular.
4250 * @note It is not possible to enable both ADC group injected
4251 * auto-injected mode and sequencer discontinuous mode.
4252 * @note On this STM32 serie, setting of this feature is conditioned to
4253 * ADC state:
4254 * ADC must be disabled or enabled without conversion on going
4255 * on either groups regular or injected.
4256 * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
4257 * @param ADCx ADC instance
4258 * @param TrigAuto This parameter can be one of the following values:
4259 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4260 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4261 * @retval None
4262 */
LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)4263 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
4264 {
4265 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
4266 }
4267
4268 /**
4269 * @brief Get ADC group injected conversion trigger:
4270 * independent or from ADC group regular.
4271 * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
4272 * @param ADCx ADC instance
4273 * @retval Returned value can be one of the following values:
4274 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4275 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4276 */
LL_ADC_INJ_GetTrigAuto(ADC_TypeDef * ADCx)4277 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
4278 {
4279 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
4280 }
4281
4282 /**
4283 * @brief Set ADC group injected contexts queue mode.
4284 * @note A context is a setting of group injected sequencer:
4285 * - group injected trigger
4286 * - sequencer length
4287 * - sequencer ranks
4288 * If contexts queue is disabled:
4289 * - only 1 sequence can be configured
4290 * and is active perpetually.
4291 * If contexts queue is enabled:
4292 * - up to 2 contexts can be queued
4293 * and are checked in and out as a FIFO stack (first-in, first-out).
4294 * - If a new context is set when queues is full, error is triggered
4295 * by interruption "Injected Queue Overflow".
4296 * - Two behaviors are possible when all contexts have been processed:
4297 * the contexts queue can maintain the last context active perpetually
4298 * or can be empty and injected group triggers are disabled.
4299 * - Triggers can be only external (not internal SW start)
4300 * - Caution: The sequence must be fully configured in one time
4301 * (one write of register JSQR makes a check-in of a new context
4302 * into the queue).
4303 * Therefore functions to set separately injected trigger and
4304 * sequencer channels cannot be used, register JSQR must be set
4305 * using function @ref LL_ADC_INJ_ConfigQueueContext().
4306 * @note This parameter can be modified only when no conversion is on going
4307 * on either groups regular or injected.
4308 * @note A modification of the context mode (bit JQDIS) causes the contexts
4309 * queue to be flushed and the register JSQR is cleared.
4310 * @note On this STM32 serie, setting of this feature is conditioned to
4311 * ADC state:
4312 * ADC must be disabled or enabled without conversion on going
4313 * on either groups regular or injected.
4314 * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n
4315 * CFGR JQDIS LL_ADC_INJ_SetQueueMode
4316 * @param ADCx ADC instance
4317 * @param QueueMode This parameter can be one of the following values:
4318 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
4319 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
4320 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
4321 * @retval None
4322 */
LL_ADC_INJ_SetQueueMode(ADC_TypeDef * ADCx,uint32_t QueueMode)4323 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
4324 {
4325 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
4326 }
4327
4328 /**
4329 * @brief Get ADC group injected context queue mode.
4330 * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n
4331 * CFGR JQDIS LL_ADC_INJ_GetQueueMode
4332 * @param ADCx ADC instance
4333 * @retval Returned value can be one of the following values:
4334 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
4335 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
4336 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
4337 */
LL_ADC_INJ_GetQueueMode(ADC_TypeDef * ADCx)4338 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
4339 {
4340 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
4341 }
4342
4343 /**
4344 * @brief Set one context on ADC group injected that will be checked in
4345 * contexts queue.
4346 * @note A context is a setting of group injected sequencer:
4347 * - group injected trigger
4348 * - sequencer length
4349 * - sequencer ranks
4350 * This function is intended to be used when contexts queue is enabled,
4351 * because the sequence must be fully configured in one time
4352 * (functions to set separately injected trigger and sequencer channels
4353 * cannot be used):
4354 * Refer to function @ref LL_ADC_INJ_SetQueueMode().
4355 * @note In the contexts queue, only the active context can be read.
4356 * The parameters of this function can be read using functions:
4357 * @arg @ref LL_ADC_INJ_GetTriggerSource()
4358 * @arg @ref LL_ADC_INJ_GetTriggerEdge()
4359 * @arg @ref LL_ADC_INJ_GetSequencerRanks()
4360 * @note On this STM32 serie, to measure internal channels (VrefInt,
4361 * TempSensor, ...), measurement paths to internal channels must be
4362 * enabled separately.
4363 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4364 * @note On STM32L4, some fast channels are available: fast analog inputs
4365 * coming from GPIO pads (ADC_IN1..5).
4366 * @note On this STM32 serie, setting of this feature is conditioned to
4367 * ADC state:
4368 * ADC must not be disabled. Can be enabled with or without conversion
4369 * on going on either groups regular or injected.
4370 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
4371 * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
4372 * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
4373 * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
4374 * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
4375 * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
4376 * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
4377 * @param ADCx ADC instance
4378 * @param TriggerSource This parameter can be one of the following values:
4379 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4380 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4381 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4382 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4383 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4384 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4385 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4386 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
4387 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
4388 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
4389 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4390 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4391 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
4392 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4393 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4394 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4395 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4396 * @param ExternalTriggerEdge This parameter can be one of the following values:
4397 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4398 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4399 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4400 *
4401 * Note: This parameter is discarded in case of SW start:
4402 * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
4403 * @param SequencerNbRanks This parameter can be one of the following values:
4404 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4405 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4406 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4407 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4408 * @param Rank1_Channel This parameter can be one of the following values:
4409 * @arg @ref LL_ADC_CHANNEL_0
4410 * @arg @ref LL_ADC_CHANNEL_1 (7)
4411 * @arg @ref LL_ADC_CHANNEL_2 (7)
4412 * @arg @ref LL_ADC_CHANNEL_3 (7)
4413 * @arg @ref LL_ADC_CHANNEL_4 (7)
4414 * @arg @ref LL_ADC_CHANNEL_5 (7)
4415 * @arg @ref LL_ADC_CHANNEL_6
4416 * @arg @ref LL_ADC_CHANNEL_7
4417 * @arg @ref LL_ADC_CHANNEL_8
4418 * @arg @ref LL_ADC_CHANNEL_9
4419 * @arg @ref LL_ADC_CHANNEL_10
4420 * @arg @ref LL_ADC_CHANNEL_11
4421 * @arg @ref LL_ADC_CHANNEL_12
4422 * @arg @ref LL_ADC_CHANNEL_13
4423 * @arg @ref LL_ADC_CHANNEL_14
4424 * @arg @ref LL_ADC_CHANNEL_15
4425 * @arg @ref LL_ADC_CHANNEL_16
4426 * @arg @ref LL_ADC_CHANNEL_17
4427 * @arg @ref LL_ADC_CHANNEL_18
4428 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4429 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4430 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4431 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4432 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4433 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4434 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4435 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4436 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4437 *
4438 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4439 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4440 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4441 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4442 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4443 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4444 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4445 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4446 * @param Rank2_Channel This parameter can be one of the following values:
4447 * @arg @ref LL_ADC_CHANNEL_0
4448 * @arg @ref LL_ADC_CHANNEL_1 (7)
4449 * @arg @ref LL_ADC_CHANNEL_2 (7)
4450 * @arg @ref LL_ADC_CHANNEL_3 (7)
4451 * @arg @ref LL_ADC_CHANNEL_4 (7)
4452 * @arg @ref LL_ADC_CHANNEL_5 (7)
4453 * @arg @ref LL_ADC_CHANNEL_6
4454 * @arg @ref LL_ADC_CHANNEL_7
4455 * @arg @ref LL_ADC_CHANNEL_8
4456 * @arg @ref LL_ADC_CHANNEL_9
4457 * @arg @ref LL_ADC_CHANNEL_10
4458 * @arg @ref LL_ADC_CHANNEL_11
4459 * @arg @ref LL_ADC_CHANNEL_12
4460 * @arg @ref LL_ADC_CHANNEL_13
4461 * @arg @ref LL_ADC_CHANNEL_14
4462 * @arg @ref LL_ADC_CHANNEL_15
4463 * @arg @ref LL_ADC_CHANNEL_16
4464 * @arg @ref LL_ADC_CHANNEL_17
4465 * @arg @ref LL_ADC_CHANNEL_18
4466 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4467 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4468 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4469 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4470 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4471 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4472 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4473 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4474 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4475 *
4476 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4477 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4478 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4479 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4480 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4481 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4482 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4483 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4484 * @param Rank3_Channel This parameter can be one of the following values:
4485 * @arg @ref LL_ADC_CHANNEL_0
4486 * @arg @ref LL_ADC_CHANNEL_1 (7)
4487 * @arg @ref LL_ADC_CHANNEL_2 (7)
4488 * @arg @ref LL_ADC_CHANNEL_3 (7)
4489 * @arg @ref LL_ADC_CHANNEL_4 (7)
4490 * @arg @ref LL_ADC_CHANNEL_5 (7)
4491 * @arg @ref LL_ADC_CHANNEL_6
4492 * @arg @ref LL_ADC_CHANNEL_7
4493 * @arg @ref LL_ADC_CHANNEL_8
4494 * @arg @ref LL_ADC_CHANNEL_9
4495 * @arg @ref LL_ADC_CHANNEL_10
4496 * @arg @ref LL_ADC_CHANNEL_11
4497 * @arg @ref LL_ADC_CHANNEL_12
4498 * @arg @ref LL_ADC_CHANNEL_13
4499 * @arg @ref LL_ADC_CHANNEL_14
4500 * @arg @ref LL_ADC_CHANNEL_15
4501 * @arg @ref LL_ADC_CHANNEL_16
4502 * @arg @ref LL_ADC_CHANNEL_17
4503 * @arg @ref LL_ADC_CHANNEL_18
4504 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4505 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4506 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4507 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4508 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4509 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4510 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4511 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4512 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4513 *
4514 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4515 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4516 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4517 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4518 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4519 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4520 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4521 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4522 * @param Rank4_Channel This parameter can be one of the following values:
4523 * @arg @ref LL_ADC_CHANNEL_0
4524 * @arg @ref LL_ADC_CHANNEL_1 (7)
4525 * @arg @ref LL_ADC_CHANNEL_2 (7)
4526 * @arg @ref LL_ADC_CHANNEL_3 (7)
4527 * @arg @ref LL_ADC_CHANNEL_4 (7)
4528 * @arg @ref LL_ADC_CHANNEL_5 (7)
4529 * @arg @ref LL_ADC_CHANNEL_6
4530 * @arg @ref LL_ADC_CHANNEL_7
4531 * @arg @ref LL_ADC_CHANNEL_8
4532 * @arg @ref LL_ADC_CHANNEL_9
4533 * @arg @ref LL_ADC_CHANNEL_10
4534 * @arg @ref LL_ADC_CHANNEL_11
4535 * @arg @ref LL_ADC_CHANNEL_12
4536 * @arg @ref LL_ADC_CHANNEL_13
4537 * @arg @ref LL_ADC_CHANNEL_14
4538 * @arg @ref LL_ADC_CHANNEL_15
4539 * @arg @ref LL_ADC_CHANNEL_16
4540 * @arg @ref LL_ADC_CHANNEL_17
4541 * @arg @ref LL_ADC_CHANNEL_18
4542 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4543 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4544 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4545 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4546 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4547 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4548 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4549 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4550 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4551 *
4552 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4553 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4554 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4555 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4556 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4557 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4558 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4559 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4560 * @retval None
4561 */
LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef * ADCx,uint32_t TriggerSource,uint32_t ExternalTriggerEdge,uint32_t SequencerNbRanks,uint32_t Rank1_Channel,uint32_t Rank2_Channel,uint32_t Rank3_Channel,uint32_t Rank4_Channel)4562 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
4563 uint32_t TriggerSource,
4564 uint32_t ExternalTriggerEdge,
4565 uint32_t SequencerNbRanks,
4566 uint32_t Rank1_Channel,
4567 uint32_t Rank2_Channel,
4568 uint32_t Rank3_Channel,
4569 uint32_t Rank4_Channel)
4570 {
4571 /* Set bits with content of parameter "Rankx_Channel" with bits position */
4572 /* in register depending on literal "LL_ADC_INJ_RANK_x". */
4573 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
4574 /* because containing other bits reserved for other purpose. */
4575 /* If parameter "TriggerSource" is set to SW start, then parameter */
4576 /* "ExternalTriggerEdge" is discarded. */
4577 register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
4578 MODIFY_REG(ADCx->JSQR,
4579 ADC_JSQR_JEXTSEL |
4580 ADC_JSQR_JEXTEN |
4581 ADC_JSQR_JSQ4 |
4582 ADC_JSQR_JSQ3 |
4583 ADC_JSQR_JSQ2 |
4584 ADC_JSQR_JSQ1 |
4585 ADC_JSQR_JL,
4586 (TriggerSource & ADC_JSQR_JEXTSEL) |
4587 (ExternalTriggerEdge * (is_trigger_not_sw)) |
4588 (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
4589 (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
4590 (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
4591 (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
4592 SequencerNbRanks
4593 );
4594 }
4595
4596 /**
4597 * @}
4598 */
4599
4600 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
4601 * @{
4602 */
4603
4604 /**
4605 * @brief Set sampling time of the selected ADC channel
4606 * Unit: ADC clock cycles.
4607 * @note On this device, sampling time is on channel scope: independently
4608 * of channel mapped on ADC group regular or injected.
4609 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
4610 * converted:
4611 * sampling time constraints must be respected (sampling time can be
4612 * adjusted in function of ADC clock frequency and sampling time
4613 * setting).
4614 * Refer to device datasheet for timings values (parameters TS_vrefint,
4615 * TS_temp, ...).
4616 * @note Conversion time is the addition of sampling time and processing time.
4617 * On this STM32 serie, ADC processing time is:
4618 * - 12.5 ADC clock cycles at ADC resolution 12 bits
4619 * - 10.5 ADC clock cycles at ADC resolution 10 bits
4620 * - 8.5 ADC clock cycles at ADC resolution 8 bits
4621 * - 6.5 ADC clock cycles at ADC resolution 6 bits
4622 * @note In case of ADC conversion of internal channel (VrefInt,
4623 * temperature sensor, ...), a sampling time minimum value
4624 * is required.
4625 * Refer to device datasheet.
4626 * @note On this STM32 serie, setting of this feature is conditioned to
4627 * ADC state:
4628 * ADC must be disabled or enabled without conversion on going
4629 * on either groups regular or injected.
4630 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
4631 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
4632 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
4633 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
4634 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
4635 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
4636 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
4637 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
4638 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
4639 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
4640 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
4641 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
4642 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
4643 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
4644 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
4645 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
4646 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
4647 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
4648 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
4649 * @param ADCx ADC instance
4650 * @param Channel This parameter can be one of the following values:
4651 * @arg @ref LL_ADC_CHANNEL_0
4652 * @arg @ref LL_ADC_CHANNEL_1 (7)
4653 * @arg @ref LL_ADC_CHANNEL_2 (7)
4654 * @arg @ref LL_ADC_CHANNEL_3 (7)
4655 * @arg @ref LL_ADC_CHANNEL_4 (7)
4656 * @arg @ref LL_ADC_CHANNEL_5 (7)
4657 * @arg @ref LL_ADC_CHANNEL_6
4658 * @arg @ref LL_ADC_CHANNEL_7
4659 * @arg @ref LL_ADC_CHANNEL_8
4660 * @arg @ref LL_ADC_CHANNEL_9
4661 * @arg @ref LL_ADC_CHANNEL_10
4662 * @arg @ref LL_ADC_CHANNEL_11
4663 * @arg @ref LL_ADC_CHANNEL_12
4664 * @arg @ref LL_ADC_CHANNEL_13
4665 * @arg @ref LL_ADC_CHANNEL_14
4666 * @arg @ref LL_ADC_CHANNEL_15
4667 * @arg @ref LL_ADC_CHANNEL_16
4668 * @arg @ref LL_ADC_CHANNEL_17
4669 * @arg @ref LL_ADC_CHANNEL_18
4670 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4671 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4672 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4673 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4674 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4675 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4676 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4677 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4678 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4679 *
4680 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4681 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4682 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4683 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4684 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4685 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4686 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4687 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4688 * @param SamplingTime This parameter can be one of the following values:
4689 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
4690 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
4691 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
4692 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
4693 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
4694 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
4695 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
4696 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
4697 *
4698 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
4699 * can be replaced by 3.5 ADC clock cycles.
4700 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
4701 * @retval None
4702 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)4703 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
4704 {
4705 /* Set bits with content of parameter "SamplingTime" with bits position */
4706 /* in register and register position depending on parameter "Channel". */
4707 /* Parameter "Channel" is used with masks because containing */
4708 /* other bits reserved for other purpose. */
4709 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
4710
4711 MODIFY_REG(*preg,
4712 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
4713 SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
4714 }
4715
4716 /**
4717 * @brief Get sampling time of the selected ADC channel
4718 * Unit: ADC clock cycles.
4719 * @note On this device, sampling time is on channel scope: independently
4720 * of channel mapped on ADC group regular or injected.
4721 * @note Conversion time is the addition of sampling time and processing time.
4722 * On this STM32 serie, ADC processing time is:
4723 * - 12.5 ADC clock cycles at ADC resolution 12 bits
4724 * - 10.5 ADC clock cycles at ADC resolution 10 bits
4725 * - 8.5 ADC clock cycles at ADC resolution 8 bits
4726 * - 6.5 ADC clock cycles at ADC resolution 6 bits
4727 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
4728 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
4729 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
4730 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
4731 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
4732 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
4733 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
4734 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
4735 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
4736 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
4737 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
4738 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
4739 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
4740 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
4741 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
4742 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
4743 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
4744 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
4745 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
4746 * @param ADCx ADC instance
4747 * @param Channel This parameter can be one of the following values:
4748 * @arg @ref LL_ADC_CHANNEL_0
4749 * @arg @ref LL_ADC_CHANNEL_1 (7)
4750 * @arg @ref LL_ADC_CHANNEL_2 (7)
4751 * @arg @ref LL_ADC_CHANNEL_3 (7)
4752 * @arg @ref LL_ADC_CHANNEL_4 (7)
4753 * @arg @ref LL_ADC_CHANNEL_5 (7)
4754 * @arg @ref LL_ADC_CHANNEL_6
4755 * @arg @ref LL_ADC_CHANNEL_7
4756 * @arg @ref LL_ADC_CHANNEL_8
4757 * @arg @ref LL_ADC_CHANNEL_9
4758 * @arg @ref LL_ADC_CHANNEL_10
4759 * @arg @ref LL_ADC_CHANNEL_11
4760 * @arg @ref LL_ADC_CHANNEL_12
4761 * @arg @ref LL_ADC_CHANNEL_13
4762 * @arg @ref LL_ADC_CHANNEL_14
4763 * @arg @ref LL_ADC_CHANNEL_15
4764 * @arg @ref LL_ADC_CHANNEL_16
4765 * @arg @ref LL_ADC_CHANNEL_17
4766 * @arg @ref LL_ADC_CHANNEL_18
4767 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4768 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4769 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4770 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4771 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4772 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4773 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4774 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4775 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4776 *
4777 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4778 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4779 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4780 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4781 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4782 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4783 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4784 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4785 * @retval Returned value can be one of the following values:
4786 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
4787 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
4788 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
4789 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
4790 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
4791 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
4792 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
4793 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
4794 *
4795 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
4796 * can be replaced by 3.5 ADC clock cycles.
4797 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
4798 */
LL_ADC_GetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel)4799 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
4800 {
4801 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
4802
4803 return (uint32_t)(READ_BIT(*preg,
4804 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
4805 >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
4806 );
4807 }
4808
4809 /**
4810 * @brief Set mode single-ended or differential input of the selected
4811 * ADC channel.
4812 * @note Channel ending is on channel scope: independently of channel mapped
4813 * on ADC group regular or injected.
4814 * In differential mode: Differential measurement is carried out
4815 * between the selected channel 'i' (positive input) and
4816 * channel 'i+1' (negative input). Only channel 'i' has to be
4817 * configured, channel 'i+1' is configured automatically.
4818 * @note Refer to Reference Manual to ensure the selected channel is
4819 * available in differential mode.
4820 * For example, internal channels (VrefInt, TempSensor, ...) are
4821 * not available in differential mode.
4822 * @note When configuring a channel 'i' in differential mode,
4823 * the channel 'i+1' is not usable separately.
4824 * @note On STM32L4, channels 16, 17, 18 of ADC1, ADC2, ADC3 (if available)
4825 * are internally fixed to single-ended inputs configuration.
4826 * @note For ADC channels configured in differential mode, both inputs
4827 * should be biased at (Vref+)/2 +/-200mV.
4828 * (Vref+ is the analog voltage reference)
4829 * @note On this STM32 serie, setting of this feature is conditioned to
4830 * ADC state:
4831 * ADC must be ADC disabled.
4832 * @note One or several values can be selected.
4833 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
4834 * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
4835 * @param ADCx ADC instance
4836 * @param Channel This parameter can be one of the following values:
4837 * @arg @ref LL_ADC_CHANNEL_1
4838 * @arg @ref LL_ADC_CHANNEL_2
4839 * @arg @ref LL_ADC_CHANNEL_3
4840 * @arg @ref LL_ADC_CHANNEL_4
4841 * @arg @ref LL_ADC_CHANNEL_5
4842 * @arg @ref LL_ADC_CHANNEL_6
4843 * @arg @ref LL_ADC_CHANNEL_7
4844 * @arg @ref LL_ADC_CHANNEL_8
4845 * @arg @ref LL_ADC_CHANNEL_9
4846 * @arg @ref LL_ADC_CHANNEL_10
4847 * @arg @ref LL_ADC_CHANNEL_11
4848 * @arg @ref LL_ADC_CHANNEL_12
4849 * @arg @ref LL_ADC_CHANNEL_13
4850 * @arg @ref LL_ADC_CHANNEL_14
4851 * @arg @ref LL_ADC_CHANNEL_15
4852 * @param SingleDiff This parameter can be a combination of the following values:
4853 * @arg @ref LL_ADC_SINGLE_ENDED
4854 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
4855 * @retval None
4856 */
LL_ADC_SetChannelSingleDiff(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SingleDiff)4857 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
4858 {
4859 /* Bits of channels in single or differential mode are set only for */
4860 /* differential mode (for single mode, mask of bits allowed to be set is */
4861 /* shifted out of range of bits of channels in single or differential mode. */
4862 MODIFY_REG(ADCx->DIFSEL,
4863 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
4864 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
4865 }
4866
4867 /**
4868 * @brief Get mode single-ended or differential input of the selected
4869 * ADC channel.
4870 * @note When configuring a channel 'i' in differential mode,
4871 * the channel 'i+1' is not usable separately.
4872 * Therefore, to ensure a channel is configured in single-ended mode,
4873 * the configuration of channel itself and the channel 'i-1' must be
4874 * read back (to ensure that the selected channel channel has not been
4875 * configured in differential mode by the previous channel).
4876 * @note Refer to Reference Manual to ensure the selected channel is
4877 * available in differential mode.
4878 * For example, internal channels (VrefInt, TempSensor, ...) are
4879 * not available in differential mode.
4880 * @note When configuring a channel 'i' in differential mode,
4881 * the channel 'i+1' is not usable separately.
4882 * @note On STM32L4, channels 16, 17, 18 of ADC1, ADC2, ADC3 (if available)
4883 * are internally fixed to single-ended inputs configuration.
4884 * @note One or several values can be selected. In this case, the value
4885 * returned is null if all channels are in single ended-mode.
4886 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
4887 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
4888 * @param ADCx ADC instance
4889 * @param Channel This parameter can be a combination of the following values:
4890 * @arg @ref LL_ADC_CHANNEL_1
4891 * @arg @ref LL_ADC_CHANNEL_2
4892 * @arg @ref LL_ADC_CHANNEL_3
4893 * @arg @ref LL_ADC_CHANNEL_4
4894 * @arg @ref LL_ADC_CHANNEL_5
4895 * @arg @ref LL_ADC_CHANNEL_6
4896 * @arg @ref LL_ADC_CHANNEL_7
4897 * @arg @ref LL_ADC_CHANNEL_8
4898 * @arg @ref LL_ADC_CHANNEL_9
4899 * @arg @ref LL_ADC_CHANNEL_10
4900 * @arg @ref LL_ADC_CHANNEL_11
4901 * @arg @ref LL_ADC_CHANNEL_12
4902 * @arg @ref LL_ADC_CHANNEL_13
4903 * @arg @ref LL_ADC_CHANNEL_14
4904 * @arg @ref LL_ADC_CHANNEL_15
4905 * @retval 0: channel in single-ended mode, else: channel in differential mode
4906 */
LL_ADC_GetChannelSingleDiff(ADC_TypeDef * ADCx,uint32_t Channel)4907 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
4908 {
4909 return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
4910 }
4911
4912 /**
4913 * @}
4914 */
4915
4916 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
4917 * @{
4918 */
4919
4920 /**
4921 * @brief Set ADC analog watchdog monitored channels:
4922 * a single channel, multiple channels or all channels,
4923 * on ADC groups regular and-or injected.
4924 * @note Once monitored channels are selected, analog watchdog
4925 * is enabled.
4926 * @note In case of need to define a single channel to monitor
4927 * with analog watchdog from sequencer channel definition,
4928 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
4929 * @note On this STM32 serie, there are 2 kinds of analog watchdog
4930 * instance:
4931 * - AWD standard (instance AWD1):
4932 * - channels monitored: can monitor 1 channel or all channels.
4933 * - groups monitored: ADC groups regular and-or injected.
4934 * - resolution: resolution is not limited (corresponds to
4935 * ADC resolution configured).
4936 * - AWD flexible (instances AWD2, AWD3):
4937 * - channels monitored: flexible on channels monitored, selection is
4938 * channel wise, from from 1 to all channels.
4939 * Specificity of this analog watchdog: Multiple channels can
4940 * be selected. For example:
4941 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
4942 * - groups monitored: not selection possible (monitoring on both
4943 * groups regular and injected).
4944 * Channels selected are monitored on groups regular and injected:
4945 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
4946 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
4947 * - resolution: resolution is limited to 8 bits: if ADC resolution is
4948 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
4949 * the 2 LSB are ignored.
4950 * @note On this STM32 serie, setting of this feature is conditioned to
4951 * ADC state:
4952 * ADC must be disabled or enabled without conversion on going
4953 * on either groups regular or injected.
4954 * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
4955 * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
4956 * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
4957 * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
4958 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
4959 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
4960 * @param ADCx ADC instance
4961 * @param AWDy This parameter can be one of the following values:
4962 * @arg @ref LL_ADC_AWD1
4963 * @arg @ref LL_ADC_AWD2
4964 * @arg @ref LL_ADC_AWD3
4965 * @param AWDChannelGroup This parameter can be one of the following values:
4966 * @arg @ref LL_ADC_AWD_DISABLE
4967 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
4968 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
4969 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
4970 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
4971 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
4972 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
4973 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
4974 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
4975 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
4976 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
4977 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
4978 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
4979 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
4980 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
4981 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
4982 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
4983 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
4984 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
4985 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
4986 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
4987 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
4988 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
4989 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
4990 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
4991 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
4992 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
4993 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
4994 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
4995 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
4996 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
4997 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
4998 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
4999 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5000 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5001 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5002 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5003 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5004 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5005 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5006 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5007 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5008 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5009 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5010 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5011 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5012 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5013 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5014 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5015 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5016 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5017 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5018 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5019 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5020 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5021 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5022 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5023 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5024 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5025 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5026 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5027 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
5028 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
5029 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
5030 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(4)
5031 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(4)
5032 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (4)
5033 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(4)
5034 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(4)
5035 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (4)
5036 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG (0)(2)(5)
5037 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_INJ (0)(2)(5)
5038 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG_INJ (2)(5)
5039 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG (0)(2)(5)
5040 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_INJ (0)(2)(5)
5041 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG_INJ (2)(5)
5042 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)(6)
5043 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)(6)
5044 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)(6)
5045 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)(6)
5046 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)(6)
5047 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)(6)
5048 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG (0)(3)(6)
5049 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ (0)(3)(6)
5050 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ (3)(6)
5051 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG (0)(3)(6)
5052 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ (0)(3)(6)
5053 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ (3)(6)
5054 *
5055 * (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\n
5056 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
5057 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
5058 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
5059 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
5060 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
5061 * (6) On STM32L4, parameter available on devices with several ADC instances.
5062 * @retval None
5063 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)5064 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
5065 {
5066 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
5067 /* in register and register position depending on parameter "AWDy". */
5068 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
5069 /* containing other bits reserved for other purpose. */
5070 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5071 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5072
5073 MODIFY_REG(*preg,
5074 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
5075 AWDChannelGroup & AWDy);
5076 }
5077
5078 /**
5079 * @brief Get ADC analog watchdog monitored channel.
5080 * @note Usage of the returned channel number:
5081 * - To reinject this channel into another function LL_ADC_xxx:
5082 * the returned channel number is only partly formatted on definition
5083 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
5084 * with parts of literals LL_ADC_CHANNEL_x or using
5085 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5086 * Then the selected literal LL_ADC_CHANNEL_x can be used
5087 * as parameter for another function.
5088 * - To get the channel number in decimal format:
5089 * process the returned value with the helper macro
5090 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5091 * Applicable only when the analog watchdog is set to monitor
5092 * one channel.
5093 * @note On this STM32 serie, there are 2 kinds of analog watchdog
5094 * instance:
5095 * - AWD standard (instance AWD1):
5096 * - channels monitored: can monitor 1 channel or all channels.
5097 * - groups monitored: ADC groups regular and-or injected.
5098 * - resolution: resolution is not limited (corresponds to
5099 * ADC resolution configured).
5100 * - AWD flexible (instances AWD2, AWD3):
5101 * - channels monitored: flexible on channels monitored, selection is
5102 * channel wise, from from 1 to all channels.
5103 * Specificity of this analog watchdog: Multiple channels can
5104 * be selected. For example:
5105 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5106 * - groups monitored: not selection possible (monitoring on both
5107 * groups regular and injected).
5108 * Channels selected are monitored on groups regular and injected:
5109 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5110 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5111 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5112 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5113 * the 2 LSB are ignored.
5114 * @note On this STM32 serie, setting of this feature is conditioned to
5115 * ADC state:
5116 * ADC must be disabled or enabled without conversion on going
5117 * on either groups regular or injected.
5118 * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
5119 * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
5120 * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5121 * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5122 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
5123 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
5124 * @param ADCx ADC instance
5125 * @param AWDy This parameter can be one of the following values:
5126 * @arg @ref LL_ADC_AWD1
5127 * @arg @ref LL_ADC_AWD2 (1)
5128 * @arg @ref LL_ADC_AWD3 (1)
5129 *
5130 * (1) On this AWD number, monitored channel can be retrieved
5131 * if only 1 channel is programmed (or none or all channels).
5132 * This function cannot retrieve monitored channel if
5133 * multiple channels are programmed simultaneously
5134 * by bitfield.
5135 * @retval Returned value can be one of the following values:
5136 * @arg @ref LL_ADC_AWD_DISABLE
5137 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5138 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5139 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5140 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5141 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5142 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5143 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5144 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5145 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5146 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5147 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5148 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5149 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5150 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5151 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5152 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5153 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5154 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5155 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5156 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5157 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5158 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5159 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5160 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5161 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5162 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5163 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5164 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5165 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5166 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5167 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5168 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5169 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5170 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5171 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5172 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5173 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5174 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5175 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5176 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5177 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5178 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5179 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5180 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5181 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5182 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5183 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5184 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5185 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5186 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5187 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5188 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5189 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5190 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5191 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5192 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5193 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5194 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5195 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5196 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5197 *
5198 * (0) On STM32L4, parameter available only on analog watchdog number: AWD1.
5199 */
LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy)5200 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
5201 {
5202 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5203 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5204
5205 register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
5206
5207 /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
5208 /* (parameter value LL_ADC_AWD_DISABLE). */
5209 /* Else, the selected AWD is enabled and is monitoring a group of channels */
5210 /* or a single channel. */
5211 if (AnalogWDMonitChannels != 0UL)
5212 {
5213 if (AWDy == LL_ADC_AWD1)
5214 {
5215 if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)
5216 {
5217 /* AWD monitoring a group of channels */
5218 AnalogWDMonitChannels = ((AnalogWDMonitChannels
5219 | (ADC_AWD_CR23_CHANNEL_MASK)
5220 )
5221 & (~(ADC_CFGR_AWD1CH))
5222 );
5223 }
5224 else
5225 {
5226 /* AWD monitoring a single channel */
5227 AnalogWDMonitChannels = (AnalogWDMonitChannels
5228 | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))
5229 );
5230 }
5231 }
5232 else
5233 {
5234 if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
5235 {
5236 /* AWD monitoring a group of channels */
5237 AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK
5238 | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
5239 );
5240 }
5241 else
5242 {
5243 /* AWD monitoring a single channel */
5244 /* AWD monitoring a group of channels */
5245 AnalogWDMonitChannels = (AnalogWDMonitChannels
5246 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
5247 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)
5248 );
5249 }
5250 }
5251 }
5252
5253 return AnalogWDMonitChannels;
5254 }
5255
5256 /**
5257 * @brief Set ADC analog watchdog thresholds value of both thresholds
5258 * high and low.
5259 * @note If value of only one threshold high or low must be set,
5260 * use function @ref LL_ADC_SetAnalogWDThresholds().
5261 * @note In case of ADC resolution different of 12 bits,
5262 * analog watchdog thresholds data require a specific shift.
5263 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5264 * @note On this STM32 serie, there are 2 kinds of analog watchdog
5265 * instance:
5266 * - AWD standard (instance AWD1):
5267 * - channels monitored: can monitor 1 channel or all channels.
5268 * - groups monitored: ADC groups regular and-or injected.
5269 * - resolution: resolution is not limited (corresponds to
5270 * ADC resolution configured).
5271 * - AWD flexible (instances AWD2, AWD3):
5272 * - channels monitored: flexible on channels monitored, selection is
5273 * channel wise, from from 1 to all channels.
5274 * Specificity of this analog watchdog: Multiple channels can
5275 * be selected. For example:
5276 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5277 * - groups monitored: not selection possible (monitoring on both
5278 * groups regular and injected).
5279 * Channels selected are monitored on groups regular and injected:
5280 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5281 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5282 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5283 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5284 * the 2 LSB are ignored.
5285 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
5286 * impacted: the comparison of analog watchdog thresholds is done on
5287 * oversampling final computation (after ratio and shift application):
5288 * ADC data register bitfield [15:4] (12 most significant bits).
5289 * @note On this STM32 serie, setting of this feature is conditioned to
5290 * ADC state:
5291 * ADC must be disabled or enabled without conversion on going
5292 * on either groups regular or injected.
5293 * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
5294 * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
5295 * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
5296 * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
5297 * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
5298 * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
5299 * @param ADCx ADC instance
5300 * @param AWDy This parameter can be one of the following values:
5301 * @arg @ref LL_ADC_AWD1
5302 * @arg @ref LL_ADC_AWD2
5303 * @arg @ref LL_ADC_AWD3
5304 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
5305 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
5306 * @retval None
5307 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)5308 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
5309 uint32_t AWDThresholdLowValue)
5310 {
5311 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
5312 /* position in register and register position depending on parameter */
5313 /* "AWDy". */
5314 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
5315 /* containing other bits reserved for other purpose. */
5316 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
5317
5318 MODIFY_REG(*preg,
5319 ADC_TR1_HT1 | ADC_TR1_LT1,
5320 (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
5321 }
5322
5323 /**
5324 * @brief Set ADC analog watchdog threshold value of threshold
5325 * high or low.
5326 * @note If values of both thresholds high or low must be set,
5327 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
5328 * @note In case of ADC resolution different of 12 bits,
5329 * analog watchdog thresholds data require a specific shift.
5330 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5331 * @note On this STM32 serie, there are 2 kinds of analog watchdog
5332 * instance:
5333 * - AWD standard (instance AWD1):
5334 * - channels monitored: can monitor 1 channel or all channels.
5335 * - groups monitored: ADC groups regular and-or injected.
5336 * - resolution: resolution is not limited (corresponds to
5337 * ADC resolution configured).
5338 * - AWD flexible (instances AWD2, AWD3):
5339 * - channels monitored: flexible on channels monitored, selection is
5340 * channel wise, from from 1 to all channels.
5341 * Specificity of this analog watchdog: Multiple channels can
5342 * be selected. For example:
5343 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5344 * - groups monitored: not selection possible (monitoring on both
5345 * groups regular and injected).
5346 * Channels selected are monitored on groups regular and injected:
5347 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5348 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5349 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5350 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5351 * the 2 LSB are ignored.
5352 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
5353 * impacted: the comparison of analog watchdog thresholds is done on
5354 * oversampling final computation (after ratio and shift application):
5355 * ADC data register bitfield [15:4] (12 most significant bits).
5356 * @note On this STM32 serie, setting of this feature is conditioned to
5357 * ADC state:
5358 * ADC must be disabled or enabled without conversion on going
5359 * on either ADC groups regular or injected.
5360 * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
5361 * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
5362 * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
5363 * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
5364 * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
5365 * TR3 LT3 LL_ADC_SetAnalogWDThresholds
5366 * @param ADCx ADC instance
5367 * @param AWDy This parameter can be one of the following values:
5368 * @arg @ref LL_ADC_AWD1
5369 * @arg @ref LL_ADC_AWD2
5370 * @arg @ref LL_ADC_AWD3
5371 * @param AWDThresholdsHighLow This parameter can be one of the following values:
5372 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
5373 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
5374 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
5375 * @retval None
5376 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)5377 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
5378 uint32_t AWDThresholdValue)
5379 {
5380 /* Set bits with content of parameter "AWDThresholdValue" with bits */
5381 /* position in register and register position depending on parameters */
5382 /* "AWDThresholdsHighLow" and "AWDy". */
5383 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
5384 /* containing other bits reserved for other purpose. */
5385 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
5386
5387 MODIFY_REG(*preg,
5388 AWDThresholdsHighLow,
5389 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
5390 }
5391
5392 /**
5393 * @brief Get ADC analog watchdog threshold value of threshold high,
5394 * threshold low or raw data with ADC thresholds high and low
5395 * concatenated.
5396 * @note If raw data with ADC thresholds high and low is retrieved,
5397 * the data of each threshold high or low can be isolated
5398 * using helper macro:
5399 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
5400 * @note In case of ADC resolution different of 12 bits,
5401 * analog watchdog thresholds data require a specific shift.
5402 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
5403 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
5404 * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
5405 * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
5406 * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
5407 * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
5408 * TR3 LT3 LL_ADC_GetAnalogWDThresholds
5409 * @param ADCx ADC instance
5410 * @param AWDy This parameter can be one of the following values:
5411 * @arg @ref LL_ADC_AWD1
5412 * @arg @ref LL_ADC_AWD2
5413 * @arg @ref LL_ADC_AWD3
5414 * @param AWDThresholdsHighLow This parameter can be one of the following values:
5415 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
5416 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
5417 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
5418 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
5419 */
LL_ADC_GetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)5420 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
5421 {
5422 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
5423
5424 return (uint32_t)(READ_BIT(*preg,
5425 (AWDThresholdsHighLow | ADC_TR1_LT1))
5426 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1))
5427 );
5428 }
5429
5430 /**
5431 * @}
5432 */
5433
5434 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
5435 * @{
5436 */
5437
5438 /**
5439 * @brief Set ADC oversampling scope: ADC groups regular and-or injected
5440 * (availability of ADC group injected depends on STM32 families).
5441 * @note If both groups regular and injected are selected,
5442 * specify behavior of ADC group injected interrupting
5443 * group regular: when ADC group injected is triggered,
5444 * the oversampling on ADC group regular is either
5445 * temporary stopped and continued, or resumed from start
5446 * (oversampler buffer reset).
5447 * @note On this STM32 serie, setting of this feature is conditioned to
5448 * ADC state:
5449 * ADC must be disabled or enabled without conversion on going
5450 * on either groups regular or injected.
5451 * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
5452 * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
5453 * CFGR2 ROVSM LL_ADC_SetOverSamplingScope
5454 * @param ADCx ADC instance
5455 * @param OvsScope This parameter can be one of the following values:
5456 * @arg @ref LL_ADC_OVS_DISABLE
5457 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
5458 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
5459 * @arg @ref LL_ADC_OVS_GRP_INJECTED
5460 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
5461 * @retval None
5462 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)5463 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
5464 {
5465 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
5466 }
5467
5468 /**
5469 * @brief Get ADC oversampling scope: ADC groups regular and-or injected
5470 * (availability of ADC group injected depends on STM32 families).
5471 * @note If both groups regular and injected are selected,
5472 * specify behavior of ADC group injected interrupting
5473 * group regular: when ADC group injected is triggered,
5474 * the oversampling on ADC group regular is either
5475 * temporary stopped and continued, or resumed from start
5476 * (oversampler buffer reset).
5477 * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
5478 * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
5479 * CFGR2 ROVSM LL_ADC_GetOverSamplingScope
5480 * @param ADCx ADC instance
5481 * @retval Returned value can be one of the following values:
5482 * @arg @ref LL_ADC_OVS_DISABLE
5483 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
5484 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
5485 * @arg @ref LL_ADC_OVS_GRP_INJECTED
5486 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
5487 */
LL_ADC_GetOverSamplingScope(ADC_TypeDef * ADCx)5488 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
5489 {
5490 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
5491 }
5492
5493 /**
5494 * @brief Set ADC oversampling discontinuous mode (triggered mode)
5495 * on the selected ADC group.
5496 * @note Number of oversampled conversions are done either in:
5497 * - continuous mode (all conversions of oversampling ratio
5498 * are done from 1 trigger)
5499 * - discontinuous mode (each conversion of oversampling ratio
5500 * needs a trigger)
5501 * @note On this STM32 serie, setting of this feature is conditioned to
5502 * ADC state:
5503 * ADC must be disabled or enabled without conversion on going
5504 * on group regular.
5505 * @note On this STM32 serie, oversampling discontinuous mode
5506 * (triggered mode) can be used only when oversampling is
5507 * set on group regular only and in resumed mode.
5508 * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
5509 * @param ADCx ADC instance
5510 * @param OverSamplingDiscont This parameter can be one of the following values:
5511 * @arg @ref LL_ADC_OVS_REG_CONT
5512 * @arg @ref LL_ADC_OVS_REG_DISCONT
5513 * @retval None
5514 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)5515 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
5516 {
5517 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
5518 }
5519
5520 /**
5521 * @brief Get ADC oversampling discontinuous mode (triggered mode)
5522 * on the selected ADC group.
5523 * @note Number of oversampled conversions are done either in:
5524 * - continuous mode (all conversions of oversampling ratio
5525 * are done from 1 trigger)
5526 * - discontinuous mode (each conversion of oversampling ratio
5527 * needs a trigger)
5528 * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
5529 * @param ADCx ADC instance
5530 * @retval Returned value can be one of the following values:
5531 * @arg @ref LL_ADC_OVS_REG_CONT
5532 * @arg @ref LL_ADC_OVS_REG_DISCONT
5533 */
LL_ADC_GetOverSamplingDiscont(ADC_TypeDef * ADCx)5534 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
5535 {
5536 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
5537 }
5538
5539 /**
5540 * @brief Set ADC oversampling
5541 * (impacting both ADC groups regular and injected)
5542 * @note This function set the 2 items of oversampling configuration:
5543 * - ratio
5544 * - shift
5545 * @note On this STM32 serie, setting of this feature is conditioned to
5546 * ADC state:
5547 * ADC must be disabled or enabled without conversion on going
5548 * on either groups regular or injected.
5549 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
5550 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
5551 * @param ADCx ADC instance
5552 * @param Ratio This parameter can be one of the following values:
5553 * @arg @ref LL_ADC_OVS_RATIO_2
5554 * @arg @ref LL_ADC_OVS_RATIO_4
5555 * @arg @ref LL_ADC_OVS_RATIO_8
5556 * @arg @ref LL_ADC_OVS_RATIO_16
5557 * @arg @ref LL_ADC_OVS_RATIO_32
5558 * @arg @ref LL_ADC_OVS_RATIO_64
5559 * @arg @ref LL_ADC_OVS_RATIO_128
5560 * @arg @ref LL_ADC_OVS_RATIO_256
5561 * @param Shift This parameter can be one of the following values:
5562 * @arg @ref LL_ADC_OVS_SHIFT_NONE
5563 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
5564 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
5565 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
5566 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
5567 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
5568 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
5569 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
5570 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
5571 * @retval None
5572 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)5573 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
5574 {
5575 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
5576 }
5577
5578 /**
5579 * @brief Get ADC oversampling ratio
5580 * (impacting both ADC groups regular and injected)
5581 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
5582 * @param ADCx ADC instance
5583 * @retval Ratio This parameter can be one of the following values:
5584 * @arg @ref LL_ADC_OVS_RATIO_2
5585 * @arg @ref LL_ADC_OVS_RATIO_4
5586 * @arg @ref LL_ADC_OVS_RATIO_8
5587 * @arg @ref LL_ADC_OVS_RATIO_16
5588 * @arg @ref LL_ADC_OVS_RATIO_32
5589 * @arg @ref LL_ADC_OVS_RATIO_64
5590 * @arg @ref LL_ADC_OVS_RATIO_128
5591 * @arg @ref LL_ADC_OVS_RATIO_256
5592 */
LL_ADC_GetOverSamplingRatio(ADC_TypeDef * ADCx)5593 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
5594 {
5595 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
5596 }
5597
5598 /**
5599 * @brief Get ADC oversampling shift
5600 * (impacting both ADC groups regular and injected)
5601 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
5602 * @param ADCx ADC instance
5603 * @retval Shift This parameter can be one of the following values:
5604 * @arg @ref LL_ADC_OVS_SHIFT_NONE
5605 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
5606 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
5607 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
5608 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
5609 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
5610 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
5611 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
5612 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
5613 */
LL_ADC_GetOverSamplingShift(ADC_TypeDef * ADCx)5614 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
5615 {
5616 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
5617 }
5618
5619 /**
5620 * @}
5621 */
5622
5623 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
5624 * @{
5625 */
5626
5627 #if defined(ADC_MULTIMODE_SUPPORT)
5628 /**
5629 * @brief Set ADC multimode configuration to operate in independent mode
5630 * or multimode (for devices with several ADC instances).
5631 * @note If multimode configuration: the selected ADC instance is
5632 * either master or slave depending on hardware.
5633 * Refer to reference manual.
5634 * @note On this STM32 serie, setting of this feature is conditioned to
5635 * ADC state:
5636 * All ADC instances of the ADC common group must be disabled.
5637 * This check can be done with function @ref LL_ADC_IsEnabled() for each
5638 * ADC instance or by using helper macro
5639 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
5640 * @rmtoll CCR DUAL LL_ADC_SetMultimode
5641 * @param ADCxy_COMMON ADC common instance
5642 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5643 * @param Multimode This parameter can be one of the following values:
5644 * @arg @ref LL_ADC_MULTI_INDEPENDENT
5645 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
5646 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
5647 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
5648 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
5649 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
5650 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
5651 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
5652 * @retval None
5653 */
LL_ADC_SetMultimode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t Multimode)5654 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
5655 {
5656 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
5657 }
5658
5659 /**
5660 * @brief Get ADC multimode configuration to operate in independent mode
5661 * or multimode (for devices with several ADC instances).
5662 * @note If multimode configuration: the selected ADC instance is
5663 * either master or slave depending on hardware.
5664 * Refer to reference manual.
5665 * @rmtoll CCR DUAL LL_ADC_GetMultimode
5666 * @param ADCxy_COMMON ADC common instance
5667 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5668 * @retval Returned value can be one of the following values:
5669 * @arg @ref LL_ADC_MULTI_INDEPENDENT
5670 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
5671 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
5672 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
5673 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
5674 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
5675 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
5676 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
5677 */
LL_ADC_GetMultimode(ADC_Common_TypeDef * ADCxy_COMMON)5678 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
5679 {
5680 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
5681 }
5682
5683 /**
5684 * @brief Set ADC multimode conversion data transfer: no transfer
5685 * or transfer by DMA.
5686 * @note If ADC multimode transfer by DMA is not selected:
5687 * each ADC uses its own DMA channel, with its individual
5688 * DMA transfer settings.
5689 * If ADC multimode transfer by DMA is selected:
5690 * One DMA channel is used for both ADC (DMA of ADC master)
5691 * Specifies the DMA requests mode:
5692 * - Limited mode (One shot mode): DMA transfer requests are stopped
5693 * when number of DMA data transfers (number of
5694 * ADC conversions) is reached.
5695 * This ADC mode is intended to be used with DMA mode non-circular.
5696 * - Unlimited mode: DMA transfer requests are unlimited,
5697 * whatever number of DMA data transfers (number of
5698 * ADC conversions).
5699 * This ADC mode is intended to be used with DMA mode circular.
5700 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
5701 * mode non-circular:
5702 * when DMA transfers size will be reached, DMA will stop transfers of
5703 * ADC conversions data ADC will raise an overrun error
5704 * (overrun flag and interruption if enabled).
5705 * @note How to retrieve multimode conversion data:
5706 * Whatever multimode transfer by DMA setting: using function
5707 * @ref LL_ADC_REG_ReadMultiConversionData32().
5708 * If ADC multimode transfer by DMA is selected: conversion data
5709 * is a raw data with ADC master and slave concatenated.
5710 * A macro is available to get the conversion data of
5711 * ADC master or ADC slave: see helper macro
5712 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
5713 * @note On this STM32 serie, setting of this feature is conditioned to
5714 * ADC state:
5715 * All ADC instances of the ADC common group must be disabled
5716 * or enabled without conversion on going on group regular.
5717 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
5718 * CCR DMACFG LL_ADC_SetMultiDMATransfer
5719 * @param ADCxy_COMMON ADC common instance
5720 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5721 * @param MultiDMATransfer This parameter can be one of the following values:
5722 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
5723 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
5724 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
5725 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
5726 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
5727 * @retval None
5728 */
LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiDMATransfer)5729 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
5730 {
5731 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
5732 }
5733
5734 /**
5735 * @brief Get ADC multimode conversion data transfer: no transfer
5736 * or transfer by DMA.
5737 * @note If ADC multimode transfer by DMA is not selected:
5738 * each ADC uses its own DMA channel, with its individual
5739 * DMA transfer settings.
5740 * If ADC multimode transfer by DMA is selected:
5741 * One DMA channel is used for both ADC (DMA of ADC master)
5742 * Specifies the DMA requests mode:
5743 * - Limited mode (One shot mode): DMA transfer requests are stopped
5744 * when number of DMA data transfers (number of
5745 * ADC conversions) is reached.
5746 * This ADC mode is intended to be used with DMA mode non-circular.
5747 * - Unlimited mode: DMA transfer requests are unlimited,
5748 * whatever number of DMA data transfers (number of
5749 * ADC conversions).
5750 * This ADC mode is intended to be used with DMA mode circular.
5751 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
5752 * mode non-circular:
5753 * when DMA transfers size will be reached, DMA will stop transfers of
5754 * ADC conversions data ADC will raise an overrun error
5755 * (overrun flag and interruption if enabled).
5756 * @note How to retrieve multimode conversion data:
5757 * Whatever multimode transfer by DMA setting: using function
5758 * @ref LL_ADC_REG_ReadMultiConversionData32().
5759 * If ADC multimode transfer by DMA is selected: conversion data
5760 * is a raw data with ADC master and slave concatenated.
5761 * A macro is available to get the conversion data of
5762 * ADC master or ADC slave: see helper macro
5763 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
5764 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
5765 * CCR DMACFG LL_ADC_GetMultiDMATransfer
5766 * @param ADCxy_COMMON ADC common instance
5767 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5768 * @retval Returned value can be one of the following values:
5769 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
5770 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
5771 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
5772 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
5773 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
5774 */
LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON)5775 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
5776 {
5777 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
5778 }
5779
5780 /**
5781 * @brief Set ADC multimode delay between 2 sampling phases.
5782 * @note The sampling delay range depends on ADC resolution:
5783 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
5784 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
5785 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
5786 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
5787 * @note On this STM32 serie, setting of this feature is conditioned to
5788 * ADC state:
5789 * All ADC instances of the ADC common group must be disabled.
5790 * This check can be done with function @ref LL_ADC_IsEnabled() for each
5791 * ADC instance or by using helper macro helper macro
5792 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
5793 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
5794 * @param ADCxy_COMMON ADC common instance
5795 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5796 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
5797 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
5798 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
5799 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
5800 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
5801 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
5802 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
5803 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
5804 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
5805 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
5806 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
5807 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
5808 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
5809 *
5810 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
5811 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
5812 * (3) Parameter available only if ADC resolution is 12 bits.
5813 * @retval None
5814 */
LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiTwoSamplingDelay)5815 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
5816 {
5817 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
5818 }
5819
5820 /**
5821 * @brief Get ADC multimode delay between 2 sampling phases.
5822 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
5823 * @param ADCxy_COMMON ADC common instance
5824 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5825 * @retval Returned value can be one of the following values:
5826 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
5827 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
5828 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
5829 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
5830 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
5831 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
5832 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
5833 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
5834 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
5835 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
5836 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
5837 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
5838 *
5839 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
5840 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
5841 * (3) Parameter available only if ADC resolution is 12 bits.
5842 */
LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON)5843 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
5844 {
5845 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
5846 }
5847 #endif /* ADC_MULTIMODE_SUPPORT */
5848
5849 /**
5850 * @}
5851 */
5852 /** @defgroup ADC_LL_EF_Configuration_Leg_Functions Configuration of ADC alternate functions name
5853 * @{
5854 */
5855 /* Old functions name kept for legacy purpose, to be replaced by the */
5856 /* current functions name. */
LL_ADC_REG_SetTrigSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)5857 __STATIC_INLINE void LL_ADC_REG_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
5858 {
5859 LL_ADC_REG_SetTriggerSource(ADCx, TriggerSource);
5860 }
LL_ADC_INJ_SetTrigSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)5861 __STATIC_INLINE void LL_ADC_INJ_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
5862 {
5863 LL_ADC_INJ_SetTriggerSource(ADCx, TriggerSource);
5864 }
5865
5866 /**
5867 * @}
5868 */
5869
5870 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
5871 * @{
5872 */
5873
5874 /**
5875 * @brief Put ADC instance in deep power down state.
5876 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
5877 * state, the internal analog calibration is lost. After exiting from
5878 * deep power down, calibration must be relaunched or calibration factor
5879 * (preliminarily saved) must be set back into calibration register.
5880 * @note On this STM32 serie, setting of this feature is conditioned to
5881 * ADC state:
5882 * ADC must be ADC disabled.
5883 * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
5884 * @param ADCx ADC instance
5885 * @retval None
5886 */
LL_ADC_EnableDeepPowerDown(ADC_TypeDef * ADCx)5887 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
5888 {
5889 /* Note: Write register with some additional bits forced to state reset */
5890 /* instead of modifying only the selected bit for this function, */
5891 /* to not interfere with bits with HW property "rs". */
5892 MODIFY_REG(ADCx->CR,
5893 ADC_CR_BITS_PROPERTY_RS,
5894 ADC_CR_DEEPPWD);
5895 }
5896
5897 /**
5898 * @brief Disable ADC deep power down mode.
5899 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
5900 * state, the internal analog calibration is lost. After exiting from
5901 * deep power down, calibration must be relaunched or calibration factor
5902 * (preliminarily saved) must be set back into calibration register.
5903 * @note On this STM32 serie, setting of this feature is conditioned to
5904 * ADC state:
5905 * ADC must be ADC disabled.
5906 * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
5907 * @param ADCx ADC instance
5908 * @retval None
5909 */
LL_ADC_DisableDeepPowerDown(ADC_TypeDef * ADCx)5910 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
5911 {
5912 /* Note: Write register with some additional bits forced to state reset */
5913 /* instead of modifying only the selected bit for this function, */
5914 /* to not interfere with bits with HW property "rs". */
5915 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
5916 }
5917
5918 /**
5919 * @brief Get the selected ADC instance deep power down state.
5920 * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
5921 * @param ADCx ADC instance
5922 * @retval 0: deep power down is disabled, 1: deep power down is enabled.
5923 */
LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef * ADCx)5924 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
5925 {
5926 return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
5927 }
5928
5929 /**
5930 * @brief Enable ADC instance internal voltage regulator.
5931 * @note On this STM32 serie, after ADC internal voltage regulator enable,
5932 * a delay for ADC internal voltage regulator stabilization
5933 * is required before performing a ADC calibration or ADC enable.
5934 * Refer to device datasheet, parameter tADCVREG_STUP.
5935 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
5936 * @note On this STM32 serie, setting of this feature is conditioned to
5937 * ADC state:
5938 * ADC must be ADC disabled.
5939 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
5940 * @param ADCx ADC instance
5941 * @retval None
5942 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)5943 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
5944 {
5945 /* Note: Write register with some additional bits forced to state reset */
5946 /* instead of modifying only the selected bit for this function, */
5947 /* to not interfere with bits with HW property "rs". */
5948 MODIFY_REG(ADCx->CR,
5949 ADC_CR_BITS_PROPERTY_RS,
5950 ADC_CR_ADVREGEN);
5951 }
5952
5953 /**
5954 * @brief Disable ADC internal voltage regulator.
5955 * @note On this STM32 serie, setting of this feature is conditioned to
5956 * ADC state:
5957 * ADC must be ADC disabled.
5958 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
5959 * @param ADCx ADC instance
5960 * @retval None
5961 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)5962 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
5963 {
5964 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
5965 }
5966
5967 /**
5968 * @brief Get the selected ADC instance internal voltage regulator state.
5969 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
5970 * @param ADCx ADC instance
5971 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
5972 */
LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef * ADCx)5973 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
5974 {
5975 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
5976 }
5977
5978 /**
5979 * @brief Enable the selected ADC instance.
5980 * @note On this STM32 serie, after ADC enable, a delay for
5981 * ADC internal analog stabilization is required before performing a
5982 * ADC conversion start.
5983 * Refer to device datasheet, parameter tSTAB.
5984 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
5985 * is enabled and when conversion clock is active.
5986 * (not only core clock: this ADC has a dual clock domain)
5987 * @note On this STM32 serie, setting of this feature is conditioned to
5988 * ADC state:
5989 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
5990 * @rmtoll CR ADEN LL_ADC_Enable
5991 * @param ADCx ADC instance
5992 * @retval None
5993 */
LL_ADC_Enable(ADC_TypeDef * ADCx)5994 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
5995 {
5996 /* Note: Write register with some additional bits forced to state reset */
5997 /* instead of modifying only the selected bit for this function, */
5998 /* to not interfere with bits with HW property "rs". */
5999 MODIFY_REG(ADCx->CR,
6000 ADC_CR_BITS_PROPERTY_RS,
6001 ADC_CR_ADEN);
6002 }
6003
6004 /**
6005 * @brief Disable the selected ADC instance.
6006 * @note On this STM32 serie, setting of this feature is conditioned to
6007 * ADC state:
6008 * ADC must be not disabled. Must be enabled without conversion on going
6009 * on either groups regular or injected.
6010 * @rmtoll CR ADDIS LL_ADC_Disable
6011 * @param ADCx ADC instance
6012 * @retval None
6013 */
LL_ADC_Disable(ADC_TypeDef * ADCx)6014 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
6015 {
6016 /* Note: Write register with some additional bits forced to state reset */
6017 /* instead of modifying only the selected bit for this function, */
6018 /* to not interfere with bits with HW property "rs". */
6019 MODIFY_REG(ADCx->CR,
6020 ADC_CR_BITS_PROPERTY_RS,
6021 ADC_CR_ADDIS);
6022 }
6023
6024 /**
6025 * @brief Get the selected ADC instance enable state.
6026 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6027 * is enabled and when conversion clock is active.
6028 * (not only core clock: this ADC has a dual clock domain)
6029 * @rmtoll CR ADEN LL_ADC_IsEnabled
6030 * @param ADCx ADC instance
6031 * @retval 0: ADC is disabled, 1: ADC is enabled.
6032 */
LL_ADC_IsEnabled(ADC_TypeDef * ADCx)6033 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
6034 {
6035 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
6036 }
6037
6038 /**
6039 * @brief Get the selected ADC instance disable state.
6040 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
6041 * @param ADCx ADC instance
6042 * @retval 0: no ADC disable command on going.
6043 */
LL_ADC_IsDisableOngoing(ADC_TypeDef * ADCx)6044 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
6045 {
6046 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
6047 }
6048
6049 /**
6050 * @brief Start ADC calibration in the mode single-ended
6051 * or differential (for devices with differential mode available).
6052 * @note On this STM32 serie, a minimum number of ADC clock cycles
6053 * are required between ADC end of calibration and ADC enable.
6054 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
6055 * @note For devices with differential mode available:
6056 * Calibration of offset is specific to each of
6057 * single-ended and differential modes
6058 * (calibration run must be performed for each of these
6059 * differential modes, if used afterwards and if the application
6060 * requires their calibration).
6061 * @note On this STM32 serie, setting of this feature is conditioned to
6062 * ADC state:
6063 * ADC must be ADC disabled.
6064 * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
6065 * CR ADCALDIF LL_ADC_StartCalibration
6066 * @param ADCx ADC instance
6067 * @param SingleDiff This parameter can be one of the following values:
6068 * @arg @ref LL_ADC_SINGLE_ENDED
6069 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
6070 * @retval None
6071 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx,uint32_t SingleDiff)6072 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
6073 {
6074 /* Note: Write register with some additional bits forced to state reset */
6075 /* instead of modifying only the selected bit for this function, */
6076 /* to not interfere with bits with HW property "rs". */
6077 MODIFY_REG(ADCx->CR,
6078 ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
6079 ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
6080 }
6081
6082 /**
6083 * @brief Get ADC calibration state.
6084 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
6085 * @param ADCx ADC instance
6086 * @retval 0: calibration complete, 1: calibration in progress.
6087 */
LL_ADC_IsCalibrationOnGoing(ADC_TypeDef * ADCx)6088 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
6089 {
6090 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
6091 }
6092
6093 /**
6094 * @}
6095 */
6096
6097 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
6098 * @{
6099 */
6100
6101 /**
6102 * @brief Start ADC group regular conversion.
6103 * @note On this STM32 serie, this function is relevant for both
6104 * internal trigger (SW start) and external trigger:
6105 * - If ADC trigger has been set to software start, ADC conversion
6106 * starts immediately.
6107 * - If ADC trigger has been set to external trigger, ADC conversion
6108 * will start at next trigger event (on the selected trigger edge)
6109 * following the ADC start conversion command.
6110 * @note On this STM32 serie, setting of this feature is conditioned to
6111 * ADC state:
6112 * ADC must be enabled without conversion on going on group regular,
6113 * without conversion stop command on going on group regular,
6114 * without ADC disable command on going.
6115 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
6116 * @param ADCx ADC instance
6117 * @retval None
6118 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)6119 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
6120 {
6121 /* Note: Write register with some additional bits forced to state reset */
6122 /* instead of modifying only the selected bit for this function, */
6123 /* to not interfere with bits with HW property "rs". */
6124 MODIFY_REG(ADCx->CR,
6125 ADC_CR_BITS_PROPERTY_RS,
6126 ADC_CR_ADSTART);
6127 }
6128
6129 /**
6130 * @brief Stop ADC group regular conversion.
6131 * @note On this STM32 serie, setting of this feature is conditioned to
6132 * ADC state:
6133 * ADC must be enabled with conversion on going on group regular,
6134 * without ADC disable command on going.
6135 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
6136 * @param ADCx ADC instance
6137 * @retval None
6138 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)6139 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
6140 {
6141 /* Note: Write register with some additional bits forced to state reset */
6142 /* instead of modifying only the selected bit for this function, */
6143 /* to not interfere with bits with HW property "rs". */
6144 MODIFY_REG(ADCx->CR,
6145 ADC_CR_BITS_PROPERTY_RS,
6146 ADC_CR_ADSTP);
6147 }
6148
6149 /**
6150 * @brief Get ADC group regular conversion state.
6151 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
6152 * @param ADCx ADC instance
6153 * @retval 0: no conversion is on going on ADC group regular.
6154 */
LL_ADC_REG_IsConversionOngoing(ADC_TypeDef * ADCx)6155 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
6156 {
6157 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
6158 }
6159
6160 /**
6161 * @brief Get ADC group regular command of conversion stop state
6162 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
6163 * @param ADCx ADC instance
6164 * @retval 0: no command of conversion stop is on going on ADC group regular.
6165 */
LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef * ADCx)6166 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
6167 {
6168 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
6169 }
6170
6171 /**
6172 * @brief Get ADC group regular conversion data, range fit for
6173 * all ADC configurations: all ADC resolutions and
6174 * all oversampling increased data width (for devices
6175 * with feature oversampling).
6176 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
6177 * @param ADCx ADC instance
6178 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6179 */
LL_ADC_REG_ReadConversionData32(ADC_TypeDef * ADCx)6180 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
6181 {
6182 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6183 }
6184
6185 /**
6186 * @brief Get ADC group regular conversion data, range fit for
6187 * ADC resolution 12 bits.
6188 * @note For devices with feature oversampling: Oversampling
6189 * can increase data width, function for extended range
6190 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6191 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
6192 * @param ADCx ADC instance
6193 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6194 */
LL_ADC_REG_ReadConversionData12(ADC_TypeDef * ADCx)6195 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
6196 {
6197 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6198 }
6199
6200 /**
6201 * @brief Get ADC group regular conversion data, range fit for
6202 * ADC resolution 10 bits.
6203 * @note For devices with feature oversampling: Oversampling
6204 * can increase data width, function for extended range
6205 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6206 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
6207 * @param ADCx ADC instance
6208 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
6209 */
LL_ADC_REG_ReadConversionData10(ADC_TypeDef * ADCx)6210 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
6211 {
6212 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6213 }
6214
6215 /**
6216 * @brief Get ADC group regular conversion data, range fit for
6217 * ADC resolution 8 bits.
6218 * @note For devices with feature oversampling: Oversampling
6219 * can increase data width, function for extended range
6220 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6221 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
6222 * @param ADCx ADC instance
6223 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
6224 */
LL_ADC_REG_ReadConversionData8(ADC_TypeDef * ADCx)6225 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
6226 {
6227 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6228 }
6229
6230 /**
6231 * @brief Get ADC group regular conversion data, range fit for
6232 * ADC resolution 6 bits.
6233 * @note For devices with feature oversampling: Oversampling
6234 * can increase data width, function for extended range
6235 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6236 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
6237 * @param ADCx ADC instance
6238 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
6239 */
LL_ADC_REG_ReadConversionData6(ADC_TypeDef * ADCx)6240 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
6241 {
6242 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6243 }
6244
6245 #if defined(ADC_MULTIMODE_SUPPORT)
6246 /**
6247 * @brief Get ADC multimode conversion data of ADC master, ADC slave
6248 * or raw data with ADC master and slave concatenated.
6249 * @note If raw data with ADC master and slave concatenated is retrieved,
6250 * a macro is available to get the conversion data of
6251 * ADC master or ADC slave: see helper macro
6252 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6253 * (however this macro is mainly intended for multimode
6254 * transfer by DMA, because this function can do the same
6255 * by getting multimode conversion data of ADC master or ADC slave
6256 * separately).
6257 * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
6258 * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
6259 * @param ADCxy_COMMON ADC common instance
6260 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6261 * @param ConversionData This parameter can be one of the following values:
6262 * @arg @ref LL_ADC_MULTI_MASTER
6263 * @arg @ref LL_ADC_MULTI_SLAVE
6264 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
6265 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6266 */
LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t ConversionData)6267 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
6268 {
6269 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
6270 ConversionData)
6271 >> (POSITION_VAL(ConversionData) & 0x1FUL)
6272 );
6273 }
6274 #endif /* ADC_MULTIMODE_SUPPORT */
6275
6276 /**
6277 * @}
6278 */
6279
6280 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
6281 * @{
6282 */
6283
6284 /**
6285 * @brief Start ADC group injected conversion.
6286 * @note On this STM32 serie, this function is relevant for both
6287 * internal trigger (SW start) and external trigger:
6288 * - If ADC trigger has been set to software start, ADC conversion
6289 * starts immediately.
6290 * - If ADC trigger has been set to external trigger, ADC conversion
6291 * will start at next trigger event (on the selected trigger edge)
6292 * following the ADC start conversion command.
6293 * @note On this STM32 serie, setting of this feature is conditioned to
6294 * ADC state:
6295 * ADC must be enabled without conversion on going on group injected,
6296 * without conversion stop command on going on group injected,
6297 * without ADC disable command on going.
6298 * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
6299 * @param ADCx ADC instance
6300 * @retval None
6301 */
LL_ADC_INJ_StartConversion(ADC_TypeDef * ADCx)6302 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
6303 {
6304 /* Note: Write register with some additional bits forced to state reset */
6305 /* instead of modifying only the selected bit for this function, */
6306 /* to not interfere with bits with HW property "rs". */
6307 MODIFY_REG(ADCx->CR,
6308 ADC_CR_BITS_PROPERTY_RS,
6309 ADC_CR_JADSTART);
6310 }
6311
6312 /**
6313 * @brief Stop ADC group injected conversion.
6314 * @note On this STM32 serie, setting of this feature is conditioned to
6315 * ADC state:
6316 * ADC must be enabled with conversion on going on group injected,
6317 * without ADC disable command on going.
6318 * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
6319 * @param ADCx ADC instance
6320 * @retval None
6321 */
LL_ADC_INJ_StopConversion(ADC_TypeDef * ADCx)6322 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
6323 {
6324 /* Note: Write register with some additional bits forced to state reset */
6325 /* instead of modifying only the selected bit for this function, */
6326 /* to not interfere with bits with HW property "rs". */
6327 MODIFY_REG(ADCx->CR,
6328 ADC_CR_BITS_PROPERTY_RS,
6329 ADC_CR_JADSTP);
6330 }
6331
6332 /**
6333 * @brief Get ADC group injected conversion state.
6334 * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
6335 * @param ADCx ADC instance
6336 * @retval 0: no conversion is on going on ADC group injected.
6337 */
LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef * ADCx)6338 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
6339 {
6340 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
6341 }
6342
6343 /**
6344 * @brief Get ADC group injected command of conversion stop state
6345 * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
6346 * @param ADCx ADC instance
6347 * @retval 0: no command of conversion stop is on going on ADC group injected.
6348 */
LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef * ADCx)6349 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
6350 {
6351 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
6352 }
6353
6354 /**
6355 * @brief Get ADC group injected conversion data, range fit for
6356 * all ADC configurations: all ADC resolutions and
6357 * all oversampling increased data width (for devices
6358 * with feature oversampling).
6359 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
6360 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
6361 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
6362 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
6363 * @param ADCx ADC instance
6364 * @param Rank This parameter can be one of the following values:
6365 * @arg @ref LL_ADC_INJ_RANK_1
6366 * @arg @ref LL_ADC_INJ_RANK_2
6367 * @arg @ref LL_ADC_INJ_RANK_3
6368 * @arg @ref LL_ADC_INJ_RANK_4
6369 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6370 */
LL_ADC_INJ_ReadConversionData32(ADC_TypeDef * ADCx,uint32_t Rank)6371 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
6372 {
6373 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6374
6375 return (uint32_t)(READ_BIT(*preg,
6376 ADC_JDR1_JDATA)
6377 );
6378 }
6379
6380 /**
6381 * @brief Get ADC group injected conversion data, range fit for
6382 * ADC resolution 12 bits.
6383 * @note For devices with feature oversampling: Oversampling
6384 * can increase data width, function for extended range
6385 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6386 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
6387 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
6388 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
6389 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
6390 * @param ADCx ADC instance
6391 * @param Rank This parameter can be one of the following values:
6392 * @arg @ref LL_ADC_INJ_RANK_1
6393 * @arg @ref LL_ADC_INJ_RANK_2
6394 * @arg @ref LL_ADC_INJ_RANK_3
6395 * @arg @ref LL_ADC_INJ_RANK_4
6396 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6397 */
LL_ADC_INJ_ReadConversionData12(ADC_TypeDef * ADCx,uint32_t Rank)6398 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
6399 {
6400 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6401
6402 return (uint16_t)(READ_BIT(*preg,
6403 ADC_JDR1_JDATA)
6404 );
6405 }
6406
6407 /**
6408 * @brief Get ADC group injected conversion data, range fit for
6409 * ADC resolution 10 bits.
6410 * @note For devices with feature oversampling: Oversampling
6411 * can increase data width, function for extended range
6412 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6413 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
6414 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
6415 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
6416 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
6417 * @param ADCx ADC instance
6418 * @param Rank This parameter can be one of the following values:
6419 * @arg @ref LL_ADC_INJ_RANK_1
6420 * @arg @ref LL_ADC_INJ_RANK_2
6421 * @arg @ref LL_ADC_INJ_RANK_3
6422 * @arg @ref LL_ADC_INJ_RANK_4
6423 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
6424 */
LL_ADC_INJ_ReadConversionData10(ADC_TypeDef * ADCx,uint32_t Rank)6425 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
6426 {
6427 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6428
6429 return (uint16_t)(READ_BIT(*preg,
6430 ADC_JDR1_JDATA)
6431 );
6432 }
6433
6434 /**
6435 * @brief Get ADC group injected conversion data, range fit for
6436 * ADC resolution 8 bits.
6437 * @note For devices with feature oversampling: Oversampling
6438 * can increase data width, function for extended range
6439 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6440 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
6441 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
6442 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
6443 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
6444 * @param ADCx ADC instance
6445 * @param Rank This parameter can be one of the following values:
6446 * @arg @ref LL_ADC_INJ_RANK_1
6447 * @arg @ref LL_ADC_INJ_RANK_2
6448 * @arg @ref LL_ADC_INJ_RANK_3
6449 * @arg @ref LL_ADC_INJ_RANK_4
6450 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
6451 */
LL_ADC_INJ_ReadConversionData8(ADC_TypeDef * ADCx,uint32_t Rank)6452 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
6453 {
6454 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6455
6456 return (uint8_t)(READ_BIT(*preg,
6457 ADC_JDR1_JDATA)
6458 );
6459 }
6460
6461 /**
6462 * @brief Get ADC group injected conversion data, range fit for
6463 * ADC resolution 6 bits.
6464 * @note For devices with feature oversampling: Oversampling
6465 * can increase data width, function for extended range
6466 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6467 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
6468 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
6469 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
6470 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
6471 * @param ADCx ADC instance
6472 * @param Rank This parameter can be one of the following values:
6473 * @arg @ref LL_ADC_INJ_RANK_1
6474 * @arg @ref LL_ADC_INJ_RANK_2
6475 * @arg @ref LL_ADC_INJ_RANK_3
6476 * @arg @ref LL_ADC_INJ_RANK_4
6477 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
6478 */
LL_ADC_INJ_ReadConversionData6(ADC_TypeDef * ADCx,uint32_t Rank)6479 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
6480 {
6481 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6482
6483 return (uint8_t)(READ_BIT(*preg,
6484 ADC_JDR1_JDATA)
6485 );
6486 }
6487
6488 /**
6489 * @}
6490 */
6491
6492 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
6493 * @{
6494 */
6495
6496 /**
6497 * @brief Get flag ADC ready.
6498 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6499 * is enabled and when conversion clock is active.
6500 * (not only core clock: this ADC has a dual clock domain)
6501 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
6502 * @param ADCx ADC instance
6503 * @retval State of bit (1 or 0).
6504 */
LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef * ADCx)6505 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
6506 {
6507 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
6508 }
6509
6510 /**
6511 * @brief Get flag ADC group regular end of unitary conversion.
6512 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
6513 * @param ADCx ADC instance
6514 * @retval State of bit (1 or 0).
6515 */
LL_ADC_IsActiveFlag_EOC(ADC_TypeDef * ADCx)6516 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
6517 {
6518 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
6519 }
6520
6521 /**
6522 * @brief Get flag ADC group regular end of sequence conversions.
6523 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
6524 * @param ADCx ADC instance
6525 * @retval State of bit (1 or 0).
6526 */
LL_ADC_IsActiveFlag_EOS(ADC_TypeDef * ADCx)6527 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
6528 {
6529 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
6530 }
6531
6532 /**
6533 * @brief Get flag ADC group regular overrun.
6534 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
6535 * @param ADCx ADC instance
6536 * @retval State of bit (1 or 0).
6537 */
LL_ADC_IsActiveFlag_OVR(ADC_TypeDef * ADCx)6538 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
6539 {
6540 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
6541 }
6542
6543 /**
6544 * @brief Get flag ADC group regular end of sampling phase.
6545 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
6546 * @param ADCx ADC instance
6547 * @retval State of bit (1 or 0).
6548 */
LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef * ADCx)6549 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
6550 {
6551 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
6552 }
6553
6554 /**
6555 * @brief Get flag ADC group injected end of unitary conversion.
6556 * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
6557 * @param ADCx ADC instance
6558 * @retval State of bit (1 or 0).
6559 */
LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef * ADCx)6560 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
6561 {
6562 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
6563 }
6564
6565 /**
6566 * @brief Get flag ADC group injected end of sequence conversions.
6567 * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
6568 * @param ADCx ADC instance
6569 * @retval State of bit (1 or 0).
6570 */
LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef * ADCx)6571 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
6572 {
6573 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
6574 }
6575
6576 /**
6577 * @brief Get flag ADC group injected contexts queue overflow.
6578 * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
6579 * @param ADCx ADC instance
6580 * @retval State of bit (1 or 0).
6581 */
LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef * ADCx)6582 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
6583 {
6584 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
6585 }
6586
6587 /**
6588 * @brief Get flag ADC analog watchdog 1 flag
6589 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
6590 * @param ADCx ADC instance
6591 * @retval State of bit (1 or 0).
6592 */
LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef * ADCx)6593 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
6594 {
6595 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
6596 }
6597
6598 /**
6599 * @brief Get flag ADC analog watchdog 2.
6600 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
6601 * @param ADCx ADC instance
6602 * @retval State of bit (1 or 0).
6603 */
LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef * ADCx)6604 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
6605 {
6606 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
6607 }
6608
6609 /**
6610 * @brief Get flag ADC analog watchdog 3.
6611 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
6612 * @param ADCx ADC instance
6613 * @retval State of bit (1 or 0).
6614 */
LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef * ADCx)6615 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
6616 {
6617 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
6618 }
6619
6620 /**
6621 * @brief Clear flag ADC ready.
6622 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6623 * is enabled and when conversion clock is active.
6624 * (not only core clock: this ADC has a dual clock domain)
6625 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
6626 * @param ADCx ADC instance
6627 * @retval None
6628 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)6629 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
6630 {
6631 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
6632 }
6633
6634 /**
6635 * @brief Clear flag ADC group regular end of unitary conversion.
6636 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
6637 * @param ADCx ADC instance
6638 * @retval None
6639 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)6640 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
6641 {
6642 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
6643 }
6644
6645 /**
6646 * @brief Clear flag ADC group regular end of sequence conversions.
6647 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
6648 * @param ADCx ADC instance
6649 * @retval None
6650 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)6651 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
6652 {
6653 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
6654 }
6655
6656 /**
6657 * @brief Clear flag ADC group regular overrun.
6658 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
6659 * @param ADCx ADC instance
6660 * @retval None
6661 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)6662 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
6663 {
6664 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
6665 }
6666
6667 /**
6668 * @brief Clear flag ADC group regular end of sampling phase.
6669 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
6670 * @param ADCx ADC instance
6671 * @retval None
6672 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)6673 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
6674 {
6675 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
6676 }
6677
6678 /**
6679 * @brief Clear flag ADC group injected end of unitary conversion.
6680 * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
6681 * @param ADCx ADC instance
6682 * @retval None
6683 */
LL_ADC_ClearFlag_JEOC(ADC_TypeDef * ADCx)6684 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
6685 {
6686 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
6687 }
6688
6689 /**
6690 * @brief Clear flag ADC group injected end of sequence conversions.
6691 * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
6692 * @param ADCx ADC instance
6693 * @retval None
6694 */
LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)6695 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
6696 {
6697 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
6698 }
6699
6700 /**
6701 * @brief Clear flag ADC group injected contexts queue overflow.
6702 * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
6703 * @param ADCx ADC instance
6704 * @retval None
6705 */
LL_ADC_ClearFlag_JQOVF(ADC_TypeDef * ADCx)6706 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
6707 {
6708 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
6709 }
6710
6711 /**
6712 * @brief Clear flag ADC analog watchdog 1.
6713 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
6714 * @param ADCx ADC instance
6715 * @retval None
6716 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)6717 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
6718 {
6719 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
6720 }
6721
6722 /**
6723 * @brief Clear flag ADC analog watchdog 2.
6724 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
6725 * @param ADCx ADC instance
6726 * @retval None
6727 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)6728 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
6729 {
6730 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
6731 }
6732
6733 /**
6734 * @brief Clear flag ADC analog watchdog 3.
6735 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
6736 * @param ADCx ADC instance
6737 * @retval None
6738 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)6739 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
6740 {
6741 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
6742 }
6743
6744 #if defined(ADC_MULTIMODE_SUPPORT)
6745 /**
6746 * @brief Get flag multimode ADC ready of the ADC master.
6747 * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
6748 * @param ADCxy_COMMON ADC common instance
6749 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6750 * @retval State of bit (1 or 0).
6751 */
LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef * ADCxy_COMMON)6752 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
6753 {
6754 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
6755 }
6756
6757 /**
6758 * @brief Get flag multimode ADC ready of the ADC slave.
6759 * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
6760 * @param ADCxy_COMMON ADC common instance
6761 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6762 * @retval State of bit (1 or 0).
6763 */
LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef * ADCxy_COMMON)6764 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
6765 {
6766 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
6767 }
6768
6769 /**
6770 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
6771 * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
6772 * @param ADCxy_COMMON ADC common instance
6773 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6774 * @retval State of bit (1 or 0).
6775 */
LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef * ADCxy_COMMON)6776 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
6777 {
6778 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
6779 }
6780
6781 /**
6782 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
6783 * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
6784 * @param ADCxy_COMMON ADC common instance
6785 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6786 * @retval State of bit (1 or 0).
6787 */
LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef * ADCxy_COMMON)6788 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
6789 {
6790 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
6791 }
6792
6793 /**
6794 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
6795 * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
6796 * @param ADCxy_COMMON ADC common instance
6797 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6798 * @retval State of bit (1 or 0).
6799 */
LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef * ADCxy_COMMON)6800 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
6801 {
6802 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
6803 }
6804
6805 /**
6806 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
6807 * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
6808 * @param ADCxy_COMMON ADC common instance
6809 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6810 * @retval State of bit (1 or 0).
6811 */
LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef * ADCxy_COMMON)6812 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
6813 {
6814 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
6815 }
6816
6817 /**
6818 * @brief Get flag multimode ADC group regular overrun of the ADC master.
6819 * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
6820 * @param ADCxy_COMMON ADC common instance
6821 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6822 * @retval State of bit (1 or 0).
6823 */
LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef * ADCxy_COMMON)6824 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
6825 {
6826 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
6827 }
6828
6829 /**
6830 * @brief Get flag multimode ADC group regular overrun of the ADC slave.
6831 * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
6832 * @param ADCxy_COMMON ADC common instance
6833 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6834 * @retval State of bit (1 or 0).
6835 */
LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef * ADCxy_COMMON)6836 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
6837 {
6838 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
6839 }
6840
6841 /**
6842 * @brief Get flag multimode ADC group regular end of sampling of the ADC master.
6843 * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
6844 * @param ADCxy_COMMON ADC common instance
6845 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6846 * @retval State of bit (1 or 0).
6847 */
LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef * ADCxy_COMMON)6848 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
6849 {
6850 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
6851 }
6852
6853 /**
6854 * @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
6855 * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
6856 * @param ADCxy_COMMON ADC common instance
6857 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6858 * @retval State of bit (1 or 0).
6859 */
LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef * ADCxy_COMMON)6860 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
6861 {
6862 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
6863 }
6864
6865 /**
6866 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
6867 * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
6868 * @param ADCxy_COMMON ADC common instance
6869 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6870 * @retval State of bit (1 or 0).
6871 */
LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef * ADCxy_COMMON)6872 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
6873 {
6874 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
6875 }
6876
6877 /**
6878 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
6879 * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
6880 * @param ADCxy_COMMON ADC common instance
6881 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6882 * @retval State of bit (1 or 0).
6883 */
LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef * ADCxy_COMMON)6884 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
6885 {
6886 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
6887 }
6888
6889 /**
6890 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
6891 * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
6892 * @param ADCxy_COMMON ADC common instance
6893 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6894 * @retval State of bit (1 or 0).
6895 */
LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)6896 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
6897 {
6898 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
6899 }
6900
6901 /**
6902 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
6903 * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
6904 * @param ADCxy_COMMON ADC common instance
6905 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6906 * @retval State of bit (1 or 0).
6907 */
LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)6908 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
6909 {
6910 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
6911 }
6912
6913 /**
6914 * @brief Get flag multimode ADC group injected context queue overflow of the ADC master.
6915 * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
6916 * @param ADCxy_COMMON ADC common instance
6917 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6918 * @retval State of bit (1 or 0).
6919 */
LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef * ADCxy_COMMON)6920 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
6921 {
6922 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
6923 }
6924
6925 /**
6926 * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.
6927 * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
6928 * @param ADCxy_COMMON ADC common instance
6929 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6930 * @retval State of bit (1 or 0).
6931 */
LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef * ADCxy_COMMON)6932 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
6933 {
6934 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
6935 }
6936
6937 /**
6938 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
6939 * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
6940 * @param ADCxy_COMMON ADC common instance
6941 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6942 * @retval State of bit (1 or 0).
6943 */
LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)6944 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
6945 {
6946 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
6947 }
6948
6949 /**
6950 * @brief Get flag multimode analog watchdog 1 of the ADC slave.
6951 * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
6952 * @param ADCxy_COMMON ADC common instance
6953 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6954 * @retval State of bit (1 or 0).
6955 */
LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)6956 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
6957 {
6958 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
6959 }
6960
6961 /**
6962 * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
6963 * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
6964 * @param ADCxy_COMMON ADC common instance
6965 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6966 * @retval State of bit (1 or 0).
6967 */
LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef * ADCxy_COMMON)6968 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
6969 {
6970 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
6971 }
6972
6973 /**
6974 * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
6975 * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
6976 * @param ADCxy_COMMON ADC common instance
6977 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6978 * @retval State of bit (1 or 0).
6979 */
LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef * ADCxy_COMMON)6980 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
6981 {
6982 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
6983 }
6984
6985 /**
6986 * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
6987 * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
6988 * @param ADCxy_COMMON ADC common instance
6989 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6990 * @retval State of bit (1 or 0).
6991 */
LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef * ADCxy_COMMON)6992 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
6993 {
6994 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
6995 }
6996
6997 /**
6998 * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
6999 * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
7000 * @param ADCxy_COMMON ADC common instance
7001 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7002 * @retval State of bit (1 or 0).
7003 */
LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef * ADCxy_COMMON)7004 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
7005 {
7006 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
7007 }
7008 #endif /* ADC_MULTIMODE_SUPPORT */
7009
7010 /**
7011 * @}
7012 */
7013
7014 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
7015 * @{
7016 */
7017
7018 /**
7019 * @brief Enable ADC ready.
7020 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
7021 * @param ADCx ADC instance
7022 * @retval None
7023 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)7024 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
7025 {
7026 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7027 }
7028
7029 /**
7030 * @brief Enable interruption ADC group regular end of unitary conversion.
7031 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
7032 * @param ADCx ADC instance
7033 * @retval None
7034 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)7035 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
7036 {
7037 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
7038 }
7039
7040 /**
7041 * @brief Enable interruption ADC group regular end of sequence conversions.
7042 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
7043 * @param ADCx ADC instance
7044 * @retval None
7045 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)7046 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
7047 {
7048 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
7049 }
7050
7051 /**
7052 * @brief Enable ADC group regular interruption overrun.
7053 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
7054 * @param ADCx ADC instance
7055 * @retval None
7056 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)7057 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
7058 {
7059 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
7060 }
7061
7062 /**
7063 * @brief Enable interruption ADC group regular end of sampling.
7064 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
7065 * @param ADCx ADC instance
7066 * @retval None
7067 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)7068 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
7069 {
7070 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7071 }
7072
7073 /**
7074 * @brief Enable interruption ADC group injected end of unitary conversion.
7075 * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
7076 * @param ADCx ADC instance
7077 * @retval None
7078 */
LL_ADC_EnableIT_JEOC(ADC_TypeDef * ADCx)7079 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
7080 {
7081 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7082 }
7083
7084 /**
7085 * @brief Enable interruption ADC group injected end of sequence conversions.
7086 * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
7087 * @param ADCx ADC instance
7088 * @retval None
7089 */
LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)7090 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
7091 {
7092 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7093 }
7094
7095 /**
7096 * @brief Enable interruption ADC group injected context queue overflow.
7097 * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
7098 * @param ADCx ADC instance
7099 * @retval None
7100 */
LL_ADC_EnableIT_JQOVF(ADC_TypeDef * ADCx)7101 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
7102 {
7103 SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7104 }
7105
7106 /**
7107 * @brief Enable interruption ADC analog watchdog 1.
7108 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
7109 * @param ADCx ADC instance
7110 * @retval None
7111 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)7112 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
7113 {
7114 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7115 }
7116
7117 /**
7118 * @brief Enable interruption ADC analog watchdog 2.
7119 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
7120 * @param ADCx ADC instance
7121 * @retval None
7122 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)7123 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
7124 {
7125 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7126 }
7127
7128 /**
7129 * @brief Enable interruption ADC analog watchdog 3.
7130 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
7131 * @param ADCx ADC instance
7132 * @retval None
7133 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)7134 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
7135 {
7136 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7137 }
7138
7139 /**
7140 * @brief Disable interruption ADC ready.
7141 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
7142 * @param ADCx ADC instance
7143 * @retval None
7144 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)7145 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
7146 {
7147 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7148 }
7149
7150 /**
7151 * @brief Disable interruption ADC group regular end of unitary conversion.
7152 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
7153 * @param ADCx ADC instance
7154 * @retval None
7155 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)7156 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
7157 {
7158 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
7159 }
7160
7161 /**
7162 * @brief Disable interruption ADC group regular end of sequence conversions.
7163 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
7164 * @param ADCx ADC instance
7165 * @retval None
7166 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)7167 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
7168 {
7169 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
7170 }
7171
7172 /**
7173 * @brief Disable interruption ADC group regular overrun.
7174 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
7175 * @param ADCx ADC instance
7176 * @retval None
7177 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)7178 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
7179 {
7180 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
7181 }
7182
7183 /**
7184 * @brief Disable interruption ADC group regular end of sampling.
7185 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
7186 * @param ADCx ADC instance
7187 * @retval None
7188 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)7189 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
7190 {
7191 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7192 }
7193
7194 /**
7195 * @brief Disable interruption ADC group regular end of unitary conversion.
7196 * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
7197 * @param ADCx ADC instance
7198 * @retval None
7199 */
LL_ADC_DisableIT_JEOC(ADC_TypeDef * ADCx)7200 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
7201 {
7202 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7203 }
7204
7205 /**
7206 * @brief Disable interruption ADC group injected end of sequence conversions.
7207 * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
7208 * @param ADCx ADC instance
7209 * @retval None
7210 */
LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)7211 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
7212 {
7213 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7214 }
7215
7216 /**
7217 * @brief Disable interruption ADC group injected context queue overflow.
7218 * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
7219 * @param ADCx ADC instance
7220 * @retval None
7221 */
LL_ADC_DisableIT_JQOVF(ADC_TypeDef * ADCx)7222 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
7223 {
7224 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7225 }
7226
7227 /**
7228 * @brief Disable interruption ADC analog watchdog 1.
7229 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
7230 * @param ADCx ADC instance
7231 * @retval None
7232 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)7233 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
7234 {
7235 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7236 }
7237
7238 /**
7239 * @brief Disable interruption ADC analog watchdog 2.
7240 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
7241 * @param ADCx ADC instance
7242 * @retval None
7243 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)7244 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
7245 {
7246 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7247 }
7248
7249 /**
7250 * @brief Disable interruption ADC analog watchdog 3.
7251 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
7252 * @param ADCx ADC instance
7253 * @retval None
7254 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)7255 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
7256 {
7257 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7258 }
7259
7260 /**
7261 * @brief Get state of interruption ADC ready
7262 * (0: interrupt disabled, 1: interrupt enabled).
7263 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
7264 * @param ADCx ADC instance
7265 * @retval State of bit (1 or 0).
7266 */
LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef * ADCx)7267 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
7268 {
7269 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
7270 }
7271
7272 /**
7273 * @brief Get state of interruption ADC group regular end of unitary conversion
7274 * (0: interrupt disabled, 1: interrupt enabled).
7275 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
7276 * @param ADCx ADC instance
7277 * @retval State of bit (1 or 0).
7278 */
LL_ADC_IsEnabledIT_EOC(ADC_TypeDef * ADCx)7279 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
7280 {
7281 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
7282 }
7283
7284 /**
7285 * @brief Get state of interruption ADC group regular end of sequence conversions
7286 * (0: interrupt disabled, 1: interrupt enabled).
7287 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
7288 * @param ADCx ADC instance
7289 * @retval State of bit (1 or 0).
7290 */
LL_ADC_IsEnabledIT_EOS(ADC_TypeDef * ADCx)7291 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
7292 {
7293 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
7294 }
7295
7296 /**
7297 * @brief Get state of interruption ADC group regular overrun
7298 * (0: interrupt disabled, 1: interrupt enabled).
7299 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
7300 * @param ADCx ADC instance
7301 * @retval State of bit (1 or 0).
7302 */
LL_ADC_IsEnabledIT_OVR(ADC_TypeDef * ADCx)7303 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
7304 {
7305 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
7306 }
7307
7308 /**
7309 * @brief Get state of interruption ADC group regular end of sampling
7310 * (0: interrupt disabled, 1: interrupt enabled).
7311 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
7312 * @param ADCx ADC instance
7313 * @retval State of bit (1 or 0).
7314 */
LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef * ADCx)7315 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
7316 {
7317 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
7318 }
7319
7320 /**
7321 * @brief Get state of interruption ADC group injected end of unitary conversion
7322 * (0: interrupt disabled, 1: interrupt enabled).
7323 * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
7324 * @param ADCx ADC instance
7325 * @retval State of bit (1 or 0).
7326 */
LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef * ADCx)7327 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
7328 {
7329 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
7330 }
7331
7332 /**
7333 * @brief Get state of interruption ADC group injected end of sequence conversions
7334 * (0: interrupt disabled, 1: interrupt enabled).
7335 * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
7336 * @param ADCx ADC instance
7337 * @retval State of bit (1 or 0).
7338 */
LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef * ADCx)7339 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
7340 {
7341 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
7342 }
7343
7344 /**
7345 * @brief Get state of interruption ADC group injected context queue overflow interrupt state
7346 * (0: interrupt disabled, 1: interrupt enabled).
7347 * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
7348 * @param ADCx ADC instance
7349 * @retval State of bit (1 or 0).
7350 */
LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef * ADCx)7351 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
7352 {
7353 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
7354 }
7355
7356 /**
7357 * @brief Get state of interruption ADC analog watchdog 1
7358 * (0: interrupt disabled, 1: interrupt enabled).
7359 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
7360 * @param ADCx ADC instance
7361 * @retval State of bit (1 or 0).
7362 */
LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef * ADCx)7363 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
7364 {
7365 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
7366 }
7367
7368 /**
7369 * @brief Get state of interruption Get ADC analog watchdog 2
7370 * (0: interrupt disabled, 1: interrupt enabled).
7371 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
7372 * @param ADCx ADC instance
7373 * @retval State of bit (1 or 0).
7374 */
LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef * ADCx)7375 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
7376 {
7377 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
7378 }
7379
7380 /**
7381 * @brief Get state of interruption Get ADC analog watchdog 3
7382 * (0: interrupt disabled, 1: interrupt enabled).
7383 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
7384 * @param ADCx ADC instance
7385 * @retval State of bit (1 or 0).
7386 */
LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef * ADCx)7387 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
7388 {
7389 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
7390 }
7391
7392 /**
7393 * @}
7394 */
7395
7396 #if defined(USE_FULL_LL_DRIVER)
7397 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
7398 * @{
7399 */
7400
7401 /* Initialization of some features of ADC common parameters and multimode */
7402 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
7403 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
7404 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
7405
7406 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
7407 /* (availability of ADC group injected depends on STM32 families) */
7408 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
7409
7410 /* Initialization of some features of ADC instance */
7411 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
7412 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
7413
7414 /* Initialization of some features of ADC instance and ADC group regular */
7415 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
7416 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
7417
7418 /* Initialization of some features of ADC instance and ADC group injected */
7419 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
7420 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
7421
7422 /**
7423 * @}
7424 */
7425 #endif /* USE_FULL_LL_DRIVER */
7426
7427 /**
7428 * @}
7429 */
7430
7431 /**
7432 * @}
7433 */
7434
7435 #endif /* ADC1 || ADC2 || ADC3 */
7436
7437 /**
7438 * @}
7439 */
7440
7441 #ifdef __cplusplus
7442 }
7443 #endif
7444
7445 #endif /* STM32L4xx_LL_ADC_H */
7446
7447 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
7448